2 * QEMU model of the CFU Configuration Unit.
4 * Copyright (C) 2023, Advanced Micro Devices, Inc.
6 * Written by Edgar E. Iglesias <edgar.iglesias@gmail.com>,
7 * Sai Pavan Boddu <sai.pavan.boddu@amd.com>,
8 * Francisco Iglesias <francisco.iglesias@amd.com>
10 * SPDX-License-Identifier: GPL-2.0-or-later
13 #include "qemu/osdep.h"
14 #include "hw/sysbus.h"
15 #include "hw/register.h"
17 #include "qemu/bitops.h"
19 #include "qemu/units.h"
20 #include "migration/vmstate.h"
21 #include "hw/qdev-properties.h"
22 #include "hw/qdev-properties-system.h"
23 #include "hw/misc/xlnx-versal-cfu.h"
25 #ifndef XLNX_VERSAL_CFU_APB_ERR_DEBUG
26 #define XLNX_VERSAL_CFU_APB_ERR_DEBUG 0
29 #define KEYHOLE_STREAM_4K (4 * KiB)
30 #define KEYHOLE_STREAM_256K (256 * KiB)
31 #define CFRAME_BROADCAST_ROW 0x1F
33 bool update_wfifo(hwaddr addr
, uint64_t value
,
34 uint32_t *wfifo
, uint32_t *wfifo_ret
)
36 unsigned int idx
= extract32(addr
, 2, 2);
41 memcpy(wfifo_ret
, wfifo
, WFIFO_SZ
* sizeof(uint32_t));
42 memset(wfifo
, 0, WFIFO_SZ
* sizeof(uint32_t));
49 static void cfu_imr_update_irq(XlnxVersalCFUAPB
*s
)
51 bool pending
= s
->regs
[R_CFU_ISR
] & ~s
->regs
[R_CFU_IMR
];
52 qemu_set_irq(s
->irq_cfu_imr
, pending
);
55 static void cfu_isr_postw(RegisterInfo
*reg
, uint64_t val64
)
57 XlnxVersalCFUAPB
*s
= XLNX_VERSAL_CFU_APB(reg
->opaque
);
58 cfu_imr_update_irq(s
);
61 static uint64_t cfu_ier_prew(RegisterInfo
*reg
, uint64_t val64
)
63 XlnxVersalCFUAPB
*s
= XLNX_VERSAL_CFU_APB(reg
->opaque
);
66 s
->regs
[R_CFU_IMR
] &= ~val
;
67 cfu_imr_update_irq(s
);
71 static uint64_t cfu_idr_prew(RegisterInfo
*reg
, uint64_t val64
)
73 XlnxVersalCFUAPB
*s
= XLNX_VERSAL_CFU_APB(reg
->opaque
);
76 s
->regs
[R_CFU_IMR
] |= val
;
77 cfu_imr_update_irq(s
);
81 static uint64_t cfu_itr_prew(RegisterInfo
*reg
, uint64_t val64
)
83 XlnxVersalCFUAPB
*s
= XLNX_VERSAL_CFU_APB(reg
->opaque
);
86 s
->regs
[R_CFU_ISR
] |= val
;
87 cfu_imr_update_irq(s
);
91 static void cfu_fgcr_postw(RegisterInfo
*reg
, uint64_t val64
)
93 XlnxVersalCFUAPB
*s
= XLNX_VERSAL_CFU_APB(reg
->opaque
);
94 uint32_t val
= (uint32_t)val64
;
96 /* Do a scan. It always looks good. */
97 if (FIELD_EX32(val
, CFU_FGCR
, SC_HBC_TRIGGER
)) {
98 ARRAY_FIELD_DP32(s
->regs
, CFU_STATUS
, SCAN_CLEAR_PASS
, 1);
99 ARRAY_FIELD_DP32(s
->regs
, CFU_STATUS
, SCAN_CLEAR_DONE
, 1);
103 static const RegisterAccessInfo cfu_apb_regs_info
[] = {
104 { .name
= "CFU_ISR", .addr
= A_CFU_ISR
,
107 .post_write
= cfu_isr_postw
,
108 },{ .name
= "CFU_IMR", .addr
= A_CFU_IMR
,
112 },{ .name
= "CFU_IER", .addr
= A_CFU_IER
,
114 .pre_write
= cfu_ier_prew
,
115 },{ .name
= "CFU_IDR", .addr
= A_CFU_IDR
,
117 .pre_write
= cfu_idr_prew
,
118 },{ .name
= "CFU_ITR", .addr
= A_CFU_ITR
,
120 .pre_write
= cfu_itr_prew
,
121 },{ .name
= "CFU_PROTECT", .addr
= A_CFU_PROTECT
,
123 },{ .name
= "CFU_FGCR", .addr
= A_CFU_FGCR
,
125 .post_write
= cfu_fgcr_postw
,
126 },{ .name
= "CFU_CTL", .addr
= A_CFU_CTL
,
128 },{ .name
= "CFU_CRAM_RW", .addr
= A_CFU_CRAM_RW
,
131 },{ .name
= "CFU_MASK", .addr
= A_CFU_MASK
,
132 },{ .name
= "CFU_CRC_EXPECT", .addr
= A_CFU_CRC_EXPECT
,
133 },{ .name
= "CFU_CFRAME_LEFT_T0", .addr
= A_CFU_CFRAME_LEFT_T0
,
135 },{ .name
= "CFU_CFRAME_LEFT_T1", .addr
= A_CFU_CFRAME_LEFT_T1
,
137 },{ .name
= "CFU_CFRAME_LEFT_T2", .addr
= A_CFU_CFRAME_LEFT_T2
,
139 },{ .name
= "CFU_ROW_RANGE", .addr
= A_CFU_ROW_RANGE
,
142 },{ .name
= "CFU_STATUS", .addr
= A_CFU_STATUS
,
145 },{ .name
= "CFU_INTERNAL_STATUS", .addr
= A_CFU_INTERNAL_STATUS
,
148 },{ .name
= "CFU_QWORD_CNT", .addr
= A_CFU_QWORD_CNT
,
150 },{ .name
= "CFU_CRC_LIVE", .addr
= A_CFU_CRC_LIVE
,
152 },{ .name
= "CFU_PENDING_READ_CNT", .addr
= A_CFU_PENDING_READ_CNT
,
155 },{ .name
= "CFU_FDRI_CNT", .addr
= A_CFU_FDRI_CNT
,
157 },{ .name
= "CFU_ECO1", .addr
= A_CFU_ECO1
,
158 },{ .name
= "CFU_ECO2", .addr
= A_CFU_ECO2
,
162 static void cfu_apb_reset(DeviceState
*dev
)
164 XlnxVersalCFUAPB
*s
= XLNX_VERSAL_CFU_APB(dev
);
167 for (i
= 0; i
< ARRAY_SIZE(s
->regs_info
); ++i
) {
168 register_reset(&s
->regs_info
[i
]);
170 memset(s
->wfifo
, 0, WFIFO_SZ
* sizeof(uint32_t));
172 s
->regs
[R_CFU_STATUS
] |= R_CFU_STATUS_HC_COMPLETE_MASK
;
173 cfu_imr_update_irq(s
);
176 static const MemoryRegionOps cfu_apb_ops
= {
177 .read
= register_read_memory
,
178 .write
= register_write_memory
,
179 .endianness
= DEVICE_LITTLE_ENDIAN
,
181 .min_access_size
= 4,
182 .max_access_size
= 4,
186 static void cfu_transfer_cfi_packet(XlnxVersalCFUAPB
*s
, uint8_t row_addr
,
189 if (row_addr
== CFRAME_BROADCAST_ROW
) {
190 for (int i
= 0; i
< ARRAY_SIZE(s
->cfg
.cframe
); i
++) {
191 if (s
->cfg
.cframe
[i
]) {
192 xlnx_cfi_transfer_packet(s
->cfg
.cframe
[i
], pkt
);
196 assert(row_addr
< ARRAY_SIZE(s
->cfg
.cframe
));
198 if (s
->cfg
.cframe
[row_addr
]) {
199 xlnx_cfi_transfer_packet(s
->cfg
.cframe
[row_addr
], pkt
);
204 static uint64_t cfu_stream_read(void *opaque
, hwaddr addr
, unsigned size
)
206 qemu_log_mask(LOG_GUEST_ERROR
, "%s: Unsupported read from addr=%"
207 HWADDR_PRIx
"\n", __func__
, addr
);
211 static void cfu_stream_write(void *opaque
, hwaddr addr
, uint64_t value
,
214 XlnxVersalCFUAPB
*s
= XLNX_VERSAL_CFU_APB(opaque
);
215 uint32_t wfifo
[WFIFO_SZ
];
217 if (update_wfifo(addr
, value
, s
->wfifo
, wfifo
)) {
218 uint8_t packet_type
, row_addr
, reg_addr
;
220 packet_type
= extract32(wfifo
[0], 24, 8);
221 row_addr
= extract32(wfifo
[0], 16, 5);
222 reg_addr
= extract32(wfifo
[0], 8, 6);
224 /* Compressed bitstreams are not supported yet. */
225 if (ARRAY_FIELD_EX32(s
->regs
, CFU_CTL
, DECOMPRESS
) == 0) {
226 if (s
->regs
[R_CFU_FDRI_CNT
]) {
227 XlnxCfiPacket pkt
= {
228 .reg_addr
= CFRAME_FDRI
,
235 cfu_transfer_cfi_packet(s
, s
->fdri_row_addr
, &pkt
);
237 s
->regs
[R_CFU_FDRI_CNT
]--;
239 } else if (packet_type
== PACKET_TYPE_CFU
&&
240 reg_addr
== CFRAME_FDRI
) {
242 /* Load R_CFU_FDRI_CNT, must be multiple of 25 */
243 s
->regs
[R_CFU_FDRI_CNT
] = wfifo
[1];
245 /* Store target row_addr */
246 s
->fdri_row_addr
= row_addr
;
248 if (wfifo
[1] % 25 != 0) {
249 qemu_log_mask(LOG_GUEST_ERROR
,
250 "CFU FDRI_CNT is not loaded with "
251 "a multiple of 25 value\n");
254 } else if (packet_type
== PACKET_TYPE_CFRAME
) {
255 XlnxCfiPacket pkt
= {
256 .reg_addr
= reg_addr
,
261 cfu_transfer_cfi_packet(s
, row_addr
, &pkt
);
267 static const MemoryRegionOps cfu_stream_ops
= {
268 .read
= cfu_stream_read
,
269 .write
= cfu_stream_write
,
270 .endianness
= DEVICE_LITTLE_ENDIAN
,
272 .min_access_size
= 4,
273 .max_access_size
= 8,
277 static void cfu_apb_init(Object
*obj
)
279 XlnxVersalCFUAPB
*s
= XLNX_VERSAL_CFU_APB(obj
);
280 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
281 RegisterInfoArray
*reg_array
;
285 memory_region_init(&s
->iomem
, obj
, TYPE_XLNX_VERSAL_CFU_APB
, R_MAX
* 4);
287 register_init_block32(DEVICE(obj
), cfu_apb_regs_info
,
288 ARRAY_SIZE(cfu_apb_regs_info
),
289 s
->regs_info
, s
->regs
,
291 XLNX_VERSAL_CFU_APB_ERR_DEBUG
,
293 memory_region_add_subregion(&s
->iomem
,
296 sysbus_init_mmio(sbd
, &s
->iomem
);
297 for (i
= 0; i
< NUM_STREAM
; i
++) {
298 name
= g_strdup_printf(TYPE_XLNX_VERSAL_CFU_APB
"-stream%d", i
);
299 memory_region_init_io(&s
->iomem_stream
[i
], obj
, &cfu_stream_ops
, s
,
300 name
, i
== 0 ? KEYHOLE_STREAM_4K
:
301 KEYHOLE_STREAM_256K
);
302 sysbus_init_mmio(sbd
, &s
->iomem_stream
[i
]);
305 sysbus_init_irq(sbd
, &s
->irq_cfu_imr
);
308 static Property cfu_props
[] = {
309 DEFINE_PROP_LINK("cframe0", XlnxVersalCFUAPB
, cfg
.cframe
[0],
310 TYPE_XLNX_CFI_IF
, XlnxCfiIf
*),
311 DEFINE_PROP_LINK("cframe1", XlnxVersalCFUAPB
, cfg
.cframe
[1],
312 TYPE_XLNX_CFI_IF
, XlnxCfiIf
*),
313 DEFINE_PROP_LINK("cframe2", XlnxVersalCFUAPB
, cfg
.cframe
[2],
314 TYPE_XLNX_CFI_IF
, XlnxCfiIf
*),
315 DEFINE_PROP_LINK("cframe3", XlnxVersalCFUAPB
, cfg
.cframe
[3],
316 TYPE_XLNX_CFI_IF
, XlnxCfiIf
*),
317 DEFINE_PROP_LINK("cframe4", XlnxVersalCFUAPB
, cfg
.cframe
[4],
318 TYPE_XLNX_CFI_IF
, XlnxCfiIf
*),
319 DEFINE_PROP_LINK("cframe5", XlnxVersalCFUAPB
, cfg
.cframe
[5],
320 TYPE_XLNX_CFI_IF
, XlnxCfiIf
*),
321 DEFINE_PROP_LINK("cframe6", XlnxVersalCFUAPB
, cfg
.cframe
[6],
322 TYPE_XLNX_CFI_IF
, XlnxCfiIf
*),
323 DEFINE_PROP_LINK("cframe7", XlnxVersalCFUAPB
, cfg
.cframe
[7],
324 TYPE_XLNX_CFI_IF
, XlnxCfiIf
*),
325 DEFINE_PROP_LINK("cframe8", XlnxVersalCFUAPB
, cfg
.cframe
[8],
326 TYPE_XLNX_CFI_IF
, XlnxCfiIf
*),
327 DEFINE_PROP_LINK("cframe9", XlnxVersalCFUAPB
, cfg
.cframe
[9],
328 TYPE_XLNX_CFI_IF
, XlnxCfiIf
*),
329 DEFINE_PROP_LINK("cframe10", XlnxVersalCFUAPB
, cfg
.cframe
[10],
330 TYPE_XLNX_CFI_IF
, XlnxCfiIf
*),
331 DEFINE_PROP_LINK("cframe11", XlnxVersalCFUAPB
, cfg
.cframe
[11],
332 TYPE_XLNX_CFI_IF
, XlnxCfiIf
*),
333 DEFINE_PROP_LINK("cframe12", XlnxVersalCFUAPB
, cfg
.cframe
[12],
334 TYPE_XLNX_CFI_IF
, XlnxCfiIf
*),
335 DEFINE_PROP_LINK("cframe13", XlnxVersalCFUAPB
, cfg
.cframe
[13],
336 TYPE_XLNX_CFI_IF
, XlnxCfiIf
*),
337 DEFINE_PROP_LINK("cframe14", XlnxVersalCFUAPB
, cfg
.cframe
[14],
338 TYPE_XLNX_CFI_IF
, XlnxCfiIf
*),
339 DEFINE_PROP_END_OF_LIST(),
342 static const VMStateDescription vmstate_cfu_apb
= {
343 .name
= TYPE_XLNX_VERSAL_CFU_APB
,
345 .minimum_version_id
= 1,
346 .fields
= (VMStateField
[]) {
347 VMSTATE_UINT32_ARRAY(wfifo
, XlnxVersalCFUAPB
, 4),
348 VMSTATE_UINT32_ARRAY(regs
, XlnxVersalCFUAPB
, R_MAX
),
349 VMSTATE_UINT8(fdri_row_addr
, XlnxVersalCFUAPB
),
350 VMSTATE_END_OF_LIST(),
354 static void cfu_apb_class_init(ObjectClass
*klass
, void *data
)
356 DeviceClass
*dc
= DEVICE_CLASS(klass
);
358 dc
->reset
= cfu_apb_reset
;
359 dc
->vmsd
= &vmstate_cfu_apb
;
360 device_class_set_props(dc
, cfu_props
);
363 static const TypeInfo cfu_apb_info
= {
364 .name
= TYPE_XLNX_VERSAL_CFU_APB
,
365 .parent
= TYPE_SYS_BUS_DEVICE
,
366 .instance_size
= sizeof(XlnxVersalCFUAPB
),
367 .class_init
= cfu_apb_class_init
,
368 .instance_init
= cfu_apb_init
,
369 .interfaces
= (InterfaceInfo
[]) {
370 { TYPE_XLNX_CFI_IF
},
375 static void cfu_apb_register_types(void)
377 type_register_static(&cfu_apb_info
);
380 type_init(cfu_apb_register_types
)