hw/misc/zynq-xadc.c

   1 /*
   2  * ADC registers for Xilinx Zynq Platform
   3  *
   4  * Copyright (c) 2015 Guenter Roeck
   5  * Based on hw/misc/zynq_slcr.c, written by Michal Simek
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; either version
  10  * 2 of the License, or (at your option) any later version.
  11  *
  12  * You should have received a copy of the GNU General Public License along
  13  * with this program; if not, see <http://www.gnu.org/licenses/>.
  14  */
  15
  16 #include "qemu/osdep.h"
  17 #include "hw/hw.h"
  18 #include "hw/irq.h"
  19 #include "hw/misc/zynq-xadc.h"
  20 #include "migration/vmstate.h"
  21 #include "qemu/timer.h"
  22 #include "sysemu/sysemu.h"
  23 #include "qemu/log.h"
  24 #include "qemu/module.h"
  25
  26 enum {
  27     CFG                = 0x000 / 4,
  28     INT_STS,
  29     INT_MASK,
  30     MSTS,
  31     CMDFIFO,
  32     RDFIFO,
  33     MCTL,
  34 };
  35
  36 #define CFG_ENABLE              BIT(31)
  37 #define CFG_CFIFOTH_SHIFT       20
  38 #define CFG_CFIFOTH_LENGTH      4
  39 #define CFG_DFIFOTH_SHIFT       16
  40 #define CFG_DFIFOTH_LENGTH      4
  41 #define CFG_WEDGE               BIT(13)
  42 #define CFG_REDGE               BIT(12)
  43 #define CFG_TCKRATE_SHIFT       8
  44 #define CFG_TCKRATE_LENGTH      2
  45
  46 #define CFG_TCKRATE_DIV(x)      (0x1 << (x - 1))
  47
  48 #define CFG_IGAP_SHIFT          0
  49 #define CFG_IGAP_LENGTH         5
  50
  51 #define INT_CFIFO_LTH           BIT(9)
  52 #define INT_DFIFO_GTH           BIT(8)
  53 #define INT_OT                  BIT(7)
  54 #define INT_ALM_SHIFT           0
  55 #define INT_ALM_LENGTH          7
  56 #define INT_ALM_MASK            (((1 << INT_ALM_LENGTH) - 1) << INT_ALM_SHIFT)
  57
  58 #define INT_ALL (INT_CFIFO_LTH | INT_DFIFO_GTH | INT_OT | INT_ALM_MASK)
  59
  60 #define MSTS_CFIFO_LVL_SHIFT    16
  61 #define MSTS_CFIFO_LVL_LENGTH   4
  62 #define MSTS_DFIFO_LVL_SHIFT    12
  63 #define MSTS_DFIFO_LVL_LENGTH   4
  64 #define MSTS_CFIFOF             BIT(11)
  65 #define MSTS_CFIFOE             BIT(10)
  66 #define MSTS_DFIFOF             BIT(9)
  67 #define MSTS_DFIFOE             BIT(8)
  68 #define MSTS_OT                 BIT(7)
  69 #define MSTS_ALM_SHIFT          0
  70 #define MSTS_ALM_LENGTH         7
  71
  72 #define MCTL_RESET              BIT(4)
  73
  74 #define CMD_NOP                 0x00
  75 #define CMD_READ                0x01
  76 #define CMD_WRITE               0x02
  77
  78 static void zynq_xadc_update_ints(ZynqXADCState *s)
  79 {
  80
  81     /* We are fast, commands are actioned instantly so the CFIFO is always
  82      * empty (and below threshold).
  83      */
  84     s->regs[INT_STS] |= INT_CFIFO_LTH;
  85
  86     if (s->xadc_dfifo_entries >
  87         extract32(s->regs[CFG], CFG_DFIFOTH_SHIFT, CFG_DFIFOTH_LENGTH)) {
  88         s->regs[INT_STS] |= INT_DFIFO_GTH;
  89     }
  90
  91     qemu_set_irq(s->qemu_irq, !!(s->regs[INT_STS] & ~s->regs[INT_MASK]));
  92 }
  93
  94 static void zynq_xadc_reset(DeviceState *d)
  95 {
  96     ZynqXADCState *s = ZYNQ_XADC(d);
  97
  98     s->regs[CFG] = 0x14 << CFG_IGAP_SHIFT |
  99                    CFG_TCKRATE_DIV(4) << CFG_TCKRATE_SHIFT | CFG_REDGE;
 100     s->regs[INT_STS] = INT_CFIFO_LTH;
 101     s->regs[INT_MASK] = 0xffffffff;
 102     s->regs[CMDFIFO] = 0;
 103     s->regs[RDFIFO] = 0;
 104     s->regs[MCTL] = MCTL_RESET;
 105
 106     memset(s->xadc_regs, 0, sizeof(s->xadc_regs));
 107     memset(s->xadc_dfifo, 0, sizeof(s->xadc_dfifo));
 108     s->xadc_dfifo_entries = 0;
 109
 110     zynq_xadc_update_ints(s);
 111 }
 112
 113 static uint16_t xadc_pop_dfifo(ZynqXADCState *s)
 114 {
 115     uint16_t rv = s->xadc_dfifo[0];
 116     int i;
 117
 118     if (s->xadc_dfifo_entries > 0) {
 119         s->xadc_dfifo_entries--;
 120     }
 121     for (i = 0; i < s->xadc_dfifo_entries; i++) {
 122         s->xadc_dfifo[i] = s->xadc_dfifo[i + 1];
 123     }
 124     s->xadc_dfifo[s->xadc_dfifo_entries] = 0;
 125     zynq_xadc_update_ints(s);
 126     return rv;
 127 }
 128
 129 static void xadc_push_dfifo(ZynqXADCState *s, uint16_t regval)
 130 {
 131     if (s->xadc_dfifo_entries < ZYNQ_XADC_FIFO_DEPTH) {
 132         s->xadc_dfifo[s->xadc_dfifo_entries++] = s->xadc_read_reg_previous;
 133     }
 134     s->xadc_read_reg_previous = regval;
 135     zynq_xadc_update_ints(s);
 136 }
 137
 138 static bool zynq_xadc_check_offset(hwaddr offset, bool rnw)
 139 {
 140     switch (offset) {
 141     case CFG:
 142     case INT_MASK:
 143     case INT_STS:
 144     case MCTL:
 145         return true;
 146     case RDFIFO:
 147     case MSTS:
 148         return rnw;     /* read only */
 149     case CMDFIFO:
 150         return !rnw;    /* write only */
 151     default:
 152         return false;
 153     }
 154 }
 155
 156 static uint64_t zynq_xadc_read(void *opaque, hwaddr offset, unsigned size)
 157 {
 158     ZynqXADCState *s = opaque;
 159     int reg = offset / 4;
 160     uint32_t rv = 0;
 161
 162     if (!zynq_xadc_check_offset(reg, true)) {
 163         qemu_log_mask(LOG_GUEST_ERROR, "zynq_xadc: Invalid read access to "
 164                       "addr %" HWADDR_PRIx "\n", offset);
 165         return 0;
 166     }
 167
 168     switch (reg) {
 169     case CFG:
 170     case INT_MASK:
 171     case INT_STS:
 172     case MCTL:
 173         rv = s->regs[reg];
 174         break;
 175     case MSTS:
 176         rv = MSTS_CFIFOE;
 177         rv |= s->xadc_dfifo_entries << MSTS_DFIFO_LVL_SHIFT;
 178         if (!s->xadc_dfifo_entries) {
 179             rv |= MSTS_DFIFOE;
 180         } else if (s->xadc_dfifo_entries == ZYNQ_XADC_FIFO_DEPTH) {
 181             rv |= MSTS_DFIFOF;
 182         }
 183         break;
 184     case RDFIFO:
 185         rv = xadc_pop_dfifo(s);
 186         break;
 187     }
 188     return rv;
 189 }
 190
 191 static void zynq_xadc_write(void *opaque, hwaddr offset, uint64_t val,
 192                             unsigned size)
 193 {
 194     ZynqXADCState *s = (ZynqXADCState *)opaque;
 195     int reg = offset / 4;
 196     int xadc_reg;
 197     int xadc_cmd;
 198     int xadc_data;
 199
 200     if (!zynq_xadc_check_offset(reg, false)) {
 201         qemu_log_mask(LOG_GUEST_ERROR, "zynq_xadc: Invalid write access "
 202                       "to addr %" HWADDR_PRIx "\n", offset);
 203         return;
 204     }
 205
 206     switch (reg) {
 207     case CFG:
 208         s->regs[CFG] = val;
 209         break;
 210     case INT_STS:
 211         s->regs[INT_STS] &= ~val;
 212         break;
 213     case INT_MASK:
 214         s->regs[INT_MASK] = val & INT_ALL;
 215         break;
 216     case CMDFIFO:
 217         xadc_cmd  = extract32(val, 26,  4);
 218         xadc_reg  = extract32(val, 16, 10);
 219         xadc_data = extract32(val,  0, 16);
 220
 221         if (s->regs[MCTL] & MCTL_RESET) {
 222             qemu_log_mask(LOG_GUEST_ERROR, "zynq_xadc: Sending command "
 223                           "while comm channel held in reset: %" PRIx32 "\n",
 224                           (uint32_t) val);
 225             break;
 226         }
 227
 228         if (xadc_reg >= ZYNQ_XADC_NUM_ADC_REGS && xadc_cmd != CMD_NOP) {
 229             qemu_log_mask(LOG_GUEST_ERROR, "read/write op to invalid xadc "
 230                           "reg 0x%x\n", xadc_reg);
 231             break;
 232         }
 233
 234         switch (xadc_cmd) {
 235         case CMD_READ:
 236             xadc_push_dfifo(s, s->xadc_regs[xadc_reg]);
 237             break;
 238         case CMD_WRITE:
 239             s->xadc_regs[xadc_reg] = xadc_data;
 240             /* fallthrough */
 241         case CMD_NOP:
 242             xadc_push_dfifo(s, 0);
 243             break;
 244         }
 245         break;
 246     case MCTL:
 247         s->regs[MCTL] = val & 0x00fffeff;
 248         break;
 249     }
 250     zynq_xadc_update_ints(s);
 251 }
 252
 253 static const MemoryRegionOps xadc_ops = {
 254     .read = zynq_xadc_read,
 255     .write = zynq_xadc_write,
 256     .endianness = DEVICE_NATIVE_ENDIAN,
 257 };
 258
 259 static void zynq_xadc_init(Object *obj)
 260 {
 261     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 262     ZynqXADCState *s = ZYNQ_XADC(obj);
 263
 264     memory_region_init_io(&s->iomem, obj, &xadc_ops, s, "zynq-xadc",
 265                           ZYNQ_XADC_MMIO_SIZE);
 266     sysbus_init_mmio(sbd, &s->iomem);
 267     sysbus_init_irq(sbd, &s->qemu_irq);
 268 }
 269
 270 static const VMStateDescription vmstate_zynq_xadc = {
 271     .name = "zynq-xadc",
 272     .version_id = 1,
 273     .minimum_version_id = 1,
 274     .fields = (VMStateField[]) {
 275         VMSTATE_UINT32_ARRAY(regs, ZynqXADCState, ZYNQ_XADC_NUM_IO_REGS),
 276         VMSTATE_UINT16_ARRAY(xadc_regs, ZynqXADCState,
 277                              ZYNQ_XADC_NUM_ADC_REGS),
 278         VMSTATE_UINT16_ARRAY(xadc_dfifo, ZynqXADCState,
 279                              ZYNQ_XADC_FIFO_DEPTH),
 280         VMSTATE_UINT16(xadc_read_reg_previous, ZynqXADCState),
 281         VMSTATE_UINT16(xadc_dfifo_entries, ZynqXADCState),
 282         VMSTATE_END_OF_LIST()
 283     }
 284 };
 285
 286 static void zynq_xadc_class_init(ObjectClass *klass, void *data)
 287 {
 288     DeviceClass *dc = DEVICE_CLASS(klass);
 289
 290     dc->vmsd = &vmstate_zynq_xadc;
 291     dc->reset = zynq_xadc_reset;
 292 }
 293
 294 static const TypeInfo zynq_xadc_info = {
 295     .class_init = zynq_xadc_class_init,
 296     .name  = TYPE_ZYNQ_XADC,
 297     .parent = TYPE_SYS_BUS_DEVICE,
 298     .instance_size  = sizeof(ZynqXADCState),
 299     .instance_init = zynq_xadc_init,
 300 };
 301
 302 static void zynq_xadc_register_types(void)
 303 {
 304     type_register_static(&zynq_xadc_info);
 305 }
 306
 307 type_init(zynq_xadc_register_types)