2 * Status and system control registers for Xilinx Zynq Platform
4 * Copyright (c) 2011 Michal Simek <monstr@monstr.eu>
5 * Copyright (c) 2012 PetaLogix Pty Ltd.
6 * Based on hw/arm_sysctl.c, written by Paul Brook
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 #include "qemu/osdep.h"
19 #include "qemu/timer.h"
20 #include "hw/sysbus.h"
21 #include "sysemu/sysemu.h"
23 #include "qemu/module.h"
25 #ifndef ZYNQ_SLCR_ERR_DEBUG
26 #define ZYNQ_SLCR_ERR_DEBUG 0
29 #define DB_PRINT(...) do { \
30 if (ZYNQ_SLCR_ERR_DEBUG) { \
31 fprintf(stderr, ": %s: ", __func__); \
32 fprintf(stderr, ## __VA_ARGS__); \
36 #define XILINX_LOCK_KEY 0x767b
37 #define XILINX_UNLOCK_KEY 0xdf0d
39 #define R_PSS_RST_CTRL_SOFT_RST 0x1
47 ARM_PLL_CTRL
= 0x100 / 4,
55 ARM_CLK_CTRL
= 0x120 / 4,
76 #define FPGA_CTRL_REGS(n, start) \
77 FPGA ## n ## _CLK_CTRL = (start) / 4, \
78 FPGA ## n ## _THR_CTRL, \
79 FPGA ## n ## _THR_CNT, \
80 FPGA ## n ## _THR_STA,
81 FPGA_CTRL_REGS(0, 0x170)
82 FPGA_CTRL_REGS(1, 0x180)
83 FPGA_CTRL_REGS(2, 0x190)
84 FPGA_CTRL_REGS(3, 0x1a0)
86 BANDGAP_TRIP
= 0x1b8 / 4,
87 PLL_PREDIVISOR
= 0x1c0 / 4,
90 PSS_RST_CTRL
= 0x200 / 4,
105 FPGA_RST_CTRL
= 0x240 / 4,
108 RS_AWDT_CTRL
= 0x24c / 4,
111 REBOOT_STATUS
= 0x258 / 4,
114 APU_CTRL
= 0x300 / 4,
117 TZ_DMA_NS
= 0x440 / 4,
121 PSS_IDCODE
= 0x530 / 4,
123 DDR_URGENT
= 0x600 / 4,
124 DDR_CAL_START
= 0x60c / 4,
125 DDR_REF_START
= 0x614 / 4,
131 #define MIO_LENGTH 54
133 MIO_LOOPBACK
= 0x804 / 4,
137 SD0_WP_CD_SEL
= 0x830 / 4,
140 LVL_SHFTR_EN
= 0x900 / 4,
147 DMAC_RAM
= 0xa50 / 4,
157 DEVCI_RAM
= 0xaa0 / 4,
161 GPIOB_CTRL
= 0xb00 / 4,
165 GPIOB_CFG_HSTL
= 0xb14 / 4,
166 GPIOB_DRVR_BIAS_CTRL
,
169 #define DDRIOB_LENGTH 14
172 #define ZYNQ_SLCR_MMIO_SIZE 0x1000
173 #define ZYNQ_SLCR_NUM_REGS (ZYNQ_SLCR_MMIO_SIZE / 4)
175 #define TYPE_ZYNQ_SLCR "xilinx,zynq_slcr"
176 #define ZYNQ_SLCR(obj) OBJECT_CHECK(ZynqSLCRState, (obj), TYPE_ZYNQ_SLCR)
178 typedef struct ZynqSLCRState
{
179 SysBusDevice parent_obj
;
183 uint32_t regs
[ZYNQ_SLCR_NUM_REGS
];
186 static void zynq_slcr_reset(DeviceState
*d
)
188 ZynqSLCRState
*s
= ZYNQ_SLCR(d
);
193 s
->regs
[LOCKSTA
] = 1;
195 s
->regs
[ARM_PLL_CTRL
] = 0x0001A008;
196 s
->regs
[DDR_PLL_CTRL
] = 0x0001A008;
197 s
->regs
[IO_PLL_CTRL
] = 0x0001A008;
198 s
->regs
[PLL_STATUS
] = 0x0000003F;
199 s
->regs
[ARM_PLL_CFG
] = 0x00014000;
200 s
->regs
[DDR_PLL_CFG
] = 0x00014000;
201 s
->regs
[IO_PLL_CFG
] = 0x00014000;
204 s
->regs
[ARM_CLK_CTRL
] = 0x1F000400;
205 s
->regs
[DDR_CLK_CTRL
] = 0x18400003;
206 s
->regs
[DCI_CLK_CTRL
] = 0x01E03201;
207 s
->regs
[APER_CLK_CTRL
] = 0x01FFCCCD;
208 s
->regs
[USB0_CLK_CTRL
] = s
->regs
[USB1_CLK_CTRL
] = 0x00101941;
209 s
->regs
[GEM0_RCLK_CTRL
] = s
->regs
[GEM1_RCLK_CTRL
] = 0x00000001;
210 s
->regs
[GEM0_CLK_CTRL
] = s
->regs
[GEM1_CLK_CTRL
] = 0x00003C01;
211 s
->regs
[SMC_CLK_CTRL
] = 0x00003C01;
212 s
->regs
[LQSPI_CLK_CTRL
] = 0x00002821;
213 s
->regs
[SDIO_CLK_CTRL
] = 0x00001E03;
214 s
->regs
[UART_CLK_CTRL
] = 0x00003F03;
215 s
->regs
[SPI_CLK_CTRL
] = 0x00003F03;
216 s
->regs
[CAN_CLK_CTRL
] = 0x00501903;
217 s
->regs
[DBG_CLK_CTRL
] = 0x00000F03;
218 s
->regs
[PCAP_CLK_CTRL
] = 0x00000F01;
221 s
->regs
[FPGA0_CLK_CTRL
] = s
->regs
[FPGA1_CLK_CTRL
] = s
->regs
[FPGA2_CLK_CTRL
]
222 = s
->regs
[FPGA3_CLK_CTRL
] = 0x00101800;
223 s
->regs
[FPGA0_THR_STA
] = s
->regs
[FPGA1_THR_STA
] = s
->regs
[FPGA2_THR_STA
]
224 = s
->regs
[FPGA3_THR_STA
] = 0x00010000;
227 s
->regs
[BANDGAP_TRIP
] = 0x0000001F;
228 s
->regs
[PLL_PREDIVISOR
] = 0x00000001;
229 s
->regs
[CLK_621_TRUE
] = 0x00000001;
232 s
->regs
[FPGA_RST_CTRL
] = 0x01F33F0F;
233 s
->regs
[RST_REASON
] = 0x00000040;
235 s
->regs
[BOOT_MODE
] = 0x00000001;
238 for (i
= 0; i
< 54; i
++) {
239 s
->regs
[MIO
+ i
] = 0x00001601;
241 for (i
= 2; i
<= 8; i
++) {
242 s
->regs
[MIO
+ i
] = 0x00000601;
245 s
->regs
[MIO_MST_TRI0
] = s
->regs
[MIO_MST_TRI1
] = 0xFFFFFFFF;
247 s
->regs
[CPU_RAM
+ 0] = s
->regs
[CPU_RAM
+ 1] = s
->regs
[CPU_RAM
+ 3]
248 = s
->regs
[CPU_RAM
+ 4] = s
->regs
[CPU_RAM
+ 7]
250 s
->regs
[CPU_RAM
+ 2] = s
->regs
[CPU_RAM
+ 5] = 0x01010101;
251 s
->regs
[CPU_RAM
+ 6] = 0x00000001;
253 s
->regs
[IOU
+ 0] = s
->regs
[IOU
+ 1] = s
->regs
[IOU
+ 2] = s
->regs
[IOU
+ 3]
255 s
->regs
[IOU
+ 4] = s
->regs
[IOU
+ 5] = 0x00090909;
256 s
->regs
[IOU
+ 6] = 0x00000909;
258 s
->regs
[DMAC_RAM
] = 0x00000009;
260 s
->regs
[AFI0
+ 0] = s
->regs
[AFI0
+ 1] = 0x09090909;
261 s
->regs
[AFI1
+ 0] = s
->regs
[AFI1
+ 1] = 0x09090909;
262 s
->regs
[AFI2
+ 0] = s
->regs
[AFI2
+ 1] = 0x09090909;
263 s
->regs
[AFI3
+ 0] = s
->regs
[AFI3
+ 1] = 0x09090909;
264 s
->regs
[AFI0
+ 2] = s
->regs
[AFI1
+ 2] = s
->regs
[AFI2
+ 2]
265 = s
->regs
[AFI3
+ 2] = 0x00000909;
267 s
->regs
[OCM
+ 0] = 0x01010101;
268 s
->regs
[OCM
+ 1] = s
->regs
[OCM
+ 2] = 0x09090909;
270 s
->regs
[DEVCI_RAM
] = 0x00000909;
271 s
->regs
[CSG_RAM
] = 0x00000001;
273 s
->regs
[DDRIOB
+ 0] = s
->regs
[DDRIOB
+ 1] = s
->regs
[DDRIOB
+ 2]
274 = s
->regs
[DDRIOB
+ 3] = 0x00000e00;
275 s
->regs
[DDRIOB
+ 4] = s
->regs
[DDRIOB
+ 5] = s
->regs
[DDRIOB
+ 6]
277 s
->regs
[DDRIOB
+ 12] = 0x00000021;
281 static bool zynq_slcr_check_offset(hwaddr offset
, bool rnw
)
288 return !rnw
; /* Write only */
299 return rnw
;/* read only */
301 case ARM_PLL_CTRL
... IO_PLL_CTRL
:
302 case ARM_PLL_CFG
... IO_PLL_CFG
:
303 case ARM_CLK_CTRL
... TOPSW_CLK_CTRL
:
304 case FPGA0_CLK_CTRL
... FPGA0_THR_CNT
:
305 case FPGA1_CLK_CTRL
... FPGA1_THR_CNT
:
306 case FPGA2_CLK_CTRL
... FPGA2_THR_CNT
:
307 case FPGA3_CLK_CTRL
... FPGA3_THR_CNT
:
311 case PSS_RST_CTRL
... A9_CPU_RST_CTRL
:
317 case TZ_DMA_NS
... TZ_DMA_PERIPH_NS
:
320 case MIO
... MIO
+ MIO_LENGTH
- 1:
321 case MIO_LOOPBACK
... MIO_MST_TRI1
:
329 case AFI0
... AFI3
+ AFI_LENGTH
- 1:
333 case GPIOB_CTRL
... GPIOB_CFG_CMOS33
:
335 case GPIOB_DRVR_BIAS_CTRL
:
336 case DDRIOB
... DDRIOB
+ DDRIOB_LENGTH
- 1:
343 static uint64_t zynq_slcr_read(void *opaque
, hwaddr offset
,
346 ZynqSLCRState
*s
= opaque
;
348 uint32_t ret
= s
->regs
[offset
];
350 if (!zynq_slcr_check_offset(offset
, true)) {
351 qemu_log_mask(LOG_GUEST_ERROR
, "zynq_slcr: Invalid read access to "
352 " addr %" HWADDR_PRIx
"\n", offset
* 4);
355 DB_PRINT("addr: %08" HWADDR_PRIx
" data: %08" PRIx32
"\n", offset
* 4, ret
);
359 static void zynq_slcr_write(void *opaque
, hwaddr offset
,
360 uint64_t val
, unsigned size
)
362 ZynqSLCRState
*s
= (ZynqSLCRState
*)opaque
;
365 DB_PRINT("addr: %08" HWADDR_PRIx
" data: %08" PRIx64
"\n", offset
* 4, val
);
367 if (!zynq_slcr_check_offset(offset
, false)) {
368 qemu_log_mask(LOG_GUEST_ERROR
, "zynq_slcr: Invalid write access to "
369 "addr %" HWADDR_PRIx
"\n", offset
* 4);
375 s
->regs
[SCL
] = val
& 0x1;
378 if ((val
& 0xFFFF) == XILINX_LOCK_KEY
) {
379 DB_PRINT("XILINX LOCK 0xF8000000 + 0x%x <= 0x%x\n", (int)offset
,
380 (unsigned)val
& 0xFFFF);
381 s
->regs
[LOCKSTA
] = 1;
383 DB_PRINT("WRONG XILINX LOCK KEY 0xF8000000 + 0x%x <= 0x%x\n",
384 (int)offset
, (unsigned)val
& 0xFFFF);
388 if ((val
& 0xFFFF) == XILINX_UNLOCK_KEY
) {
389 DB_PRINT("XILINX UNLOCK 0xF8000000 + 0x%x <= 0x%x\n", (int)offset
,
390 (unsigned)val
& 0xFFFF);
391 s
->regs
[LOCKSTA
] = 0;
393 DB_PRINT("WRONG XILINX UNLOCK KEY 0xF8000000 + 0x%x <= 0x%x\n",
394 (int)offset
, (unsigned)val
& 0xFFFF);
399 if (s
->regs
[LOCKSTA
]) {
400 qemu_log_mask(LOG_GUEST_ERROR
,
401 "SCLR registers are locked. Unlock them first\n");
404 s
->regs
[offset
] = val
;
408 if (val
& R_PSS_RST_CTRL_SOFT_RST
) {
409 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
415 static const MemoryRegionOps slcr_ops
= {
416 .read
= zynq_slcr_read
,
417 .write
= zynq_slcr_write
,
418 .endianness
= DEVICE_NATIVE_ENDIAN
,
421 static void zynq_slcr_init(Object
*obj
)
423 ZynqSLCRState
*s
= ZYNQ_SLCR(obj
);
425 memory_region_init_io(&s
->iomem
, obj
, &slcr_ops
, s
, "slcr",
426 ZYNQ_SLCR_MMIO_SIZE
);
427 sysbus_init_mmio(SYS_BUS_DEVICE(obj
), &s
->iomem
);
430 static const VMStateDescription vmstate_zynq_slcr
= {
433 .minimum_version_id
= 2,
434 .fields
= (VMStateField
[]) {
435 VMSTATE_UINT32_ARRAY(regs
, ZynqSLCRState
, ZYNQ_SLCR_NUM_REGS
),
436 VMSTATE_END_OF_LIST()
440 static void zynq_slcr_class_init(ObjectClass
*klass
, void *data
)
442 DeviceClass
*dc
= DEVICE_CLASS(klass
);
444 dc
->vmsd
= &vmstate_zynq_slcr
;
445 dc
->reset
= zynq_slcr_reset
;
448 static const TypeInfo zynq_slcr_info
= {
449 .class_init
= zynq_slcr_class_init
,
450 .name
= TYPE_ZYNQ_SLCR
,
451 .parent
= TYPE_SYS_BUS_DEVICE
,
452 .instance_size
= sizeof(ZynqSLCRState
),
453 .instance_init
= zynq_slcr_init
,
456 static void zynq_slcr_register_types(void)
458 type_register_static(&zynq_slcr_info
);
461 type_init(zynq_slcr_register_types
)