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1 /*
2 * Marvell MV88W8618 / Freecom MusicPal emulation.
3 *
4 * Copyright (c) 2008 Jan Kiszka
5 *
6 * This code is licensed under the GNU GPL v2.
7 */
8
9 #include "sysbus.h"
10 #include "arm-misc.h"
11 #include "devices.h"
12 #include "net.h"
13 #include "sysemu.h"
14 #include "boards.h"
15 #include "pc.h"
16 #include "qemu-timer.h"
17 #include "ptimer.h"
18 #include "block.h"
19 #include "flash.h"
20 #include "console.h"
21 #include "i2c.h"
22 #include "blockdev.h"
23 #include "exec-memory.h"
24
25 #define MP_MISC_BASE 0x80002000
26 #define MP_MISC_SIZE 0x00001000
27
28 #define MP_ETH_BASE 0x80008000
29 #define MP_ETH_SIZE 0x00001000
30
31 #define MP_WLAN_BASE 0x8000C000
32 #define MP_WLAN_SIZE 0x00000800
33
34 #define MP_UART1_BASE 0x8000C840
35 #define MP_UART2_BASE 0x8000C940
36
37 #define MP_GPIO_BASE 0x8000D000
38 #define MP_GPIO_SIZE 0x00001000
39
40 #define MP_FLASHCFG_BASE 0x90006000
41 #define MP_FLASHCFG_SIZE 0x00001000
42
43 #define MP_AUDIO_BASE 0x90007000
44
45 #define MP_PIC_BASE 0x90008000
46 #define MP_PIC_SIZE 0x00001000
47
48 #define MP_PIT_BASE 0x90009000
49 #define MP_PIT_SIZE 0x00001000
50
51 #define MP_LCD_BASE 0x9000c000
52 #define MP_LCD_SIZE 0x00001000
53
54 #define MP_SRAM_BASE 0xC0000000
55 #define MP_SRAM_SIZE 0x00020000
56
57 #define MP_RAM_DEFAULT_SIZE 32*1024*1024
58 #define MP_FLASH_SIZE_MAX 32*1024*1024
59
60 #define MP_TIMER1_IRQ 4
61 #define MP_TIMER2_IRQ 5
62 #define MP_TIMER3_IRQ 6
63 #define MP_TIMER4_IRQ 7
64 #define MP_EHCI_IRQ 8
65 #define MP_ETH_IRQ 9
66 #define MP_UART1_IRQ 11
67 #define MP_UART2_IRQ 11
68 #define MP_GPIO_IRQ 12
69 #define MP_RTC_IRQ 28
70 #define MP_AUDIO_IRQ 30
71
72 /* Wolfson 8750 I2C address */
73 #define MP_WM_ADDR 0x1A
74
75 /* Ethernet register offsets */
76 #define MP_ETH_SMIR 0x010
77 #define MP_ETH_PCXR 0x408
78 #define MP_ETH_SDCMR 0x448
79 #define MP_ETH_ICR 0x450
80 #define MP_ETH_IMR 0x458
81 #define MP_ETH_FRDP0 0x480
82 #define MP_ETH_FRDP1 0x484
83 #define MP_ETH_FRDP2 0x488
84 #define MP_ETH_FRDP3 0x48C
85 #define MP_ETH_CRDP0 0x4A0
86 #define MP_ETH_CRDP1 0x4A4
87 #define MP_ETH_CRDP2 0x4A8
88 #define MP_ETH_CRDP3 0x4AC
89 #define MP_ETH_CTDP0 0x4E0
90 #define MP_ETH_CTDP1 0x4E4
91 #define MP_ETH_CTDP2 0x4E8
92 #define MP_ETH_CTDP3 0x4EC
93
94 /* MII PHY access */
95 #define MP_ETH_SMIR_DATA 0x0000FFFF
96 #define MP_ETH_SMIR_ADDR 0x03FF0000
97 #define MP_ETH_SMIR_OPCODE (1 << 26) /* Read value */
98 #define MP_ETH_SMIR_RDVALID (1 << 27)
99
100 /* PHY registers */
101 #define MP_ETH_PHY1_BMSR 0x00210000
102 #define MP_ETH_PHY1_PHYSID1 0x00410000
103 #define MP_ETH_PHY1_PHYSID2 0x00610000
104
105 #define MP_PHY_BMSR_LINK 0x0004
106 #define MP_PHY_BMSR_AUTONEG 0x0008
107
108 #define MP_PHY_88E3015 0x01410E20
109
110 /* TX descriptor status */
111 #define MP_ETH_TX_OWN (1 << 31)
112
113 /* RX descriptor status */
114 #define MP_ETH_RX_OWN (1 << 31)
115
116 /* Interrupt cause/mask bits */
117 #define MP_ETH_IRQ_RX_BIT 0
118 #define MP_ETH_IRQ_RX (1 << MP_ETH_IRQ_RX_BIT)
119 #define MP_ETH_IRQ_TXHI_BIT 2
120 #define MP_ETH_IRQ_TXLO_BIT 3
121
122 /* Port config bits */
123 #define MP_ETH_PCXR_2BSM_BIT 28 /* 2-byte incoming suffix */
124
125 /* SDMA command bits */
126 #define MP_ETH_CMD_TXHI (1 << 23)
127 #define MP_ETH_CMD_TXLO (1 << 22)
128
129 typedef struct mv88w8618_tx_desc {
130 uint32_t cmdstat;
131 uint16_t res;
132 uint16_t bytes;
133 uint32_t buffer;
134 uint32_t next;
135 } mv88w8618_tx_desc;
136
137 typedef struct mv88w8618_rx_desc {
138 uint32_t cmdstat;
139 uint16_t bytes;
140 uint16_t buffer_size;
141 uint32_t buffer;
142 uint32_t next;
143 } mv88w8618_rx_desc;
144
145 typedef struct mv88w8618_eth_state {
146 SysBusDevice busdev;
147 MemoryRegion iomem;
148 qemu_irq irq;
149 uint32_t smir;
150 uint32_t icr;
151 uint32_t imr;
152 int mmio_index;
153 uint32_t vlan_header;
154 uint32_t tx_queue[2];
155 uint32_t rx_queue[4];
156 uint32_t frx_queue[4];
157 uint32_t cur_rx[4];
158 NICState *nic;
159 NICConf conf;
160 } mv88w8618_eth_state;
161
162 static void eth_rx_desc_put(uint32_t addr, mv88w8618_rx_desc *desc)
163 {
164 cpu_to_le32s(&desc->cmdstat);
165 cpu_to_le16s(&desc->bytes);
166 cpu_to_le16s(&desc->buffer_size);
167 cpu_to_le32s(&desc->buffer);
168 cpu_to_le32s(&desc->next);
169 cpu_physical_memory_write(addr, (void *)desc, sizeof(*desc));
170 }
171
172 static void eth_rx_desc_get(uint32_t addr, mv88w8618_rx_desc *desc)
173 {
174 cpu_physical_memory_read(addr, (void *)desc, sizeof(*desc));
175 le32_to_cpus(&desc->cmdstat);
176 le16_to_cpus(&desc->bytes);
177 le16_to_cpus(&desc->buffer_size);
178 le32_to_cpus(&desc->buffer);
179 le32_to_cpus(&desc->next);
180 }
181
182 static int eth_can_receive(VLANClientState *nc)
183 {
184 return 1;
185 }
186
187 static ssize_t eth_receive(VLANClientState *nc, const uint8_t *buf, size_t size)
188 {
189 mv88w8618_eth_state *s = DO_UPCAST(NICState, nc, nc)->opaque;
190 uint32_t desc_addr;
191 mv88w8618_rx_desc desc;
192 int i;
193
194 for (i = 0; i < 4; i++) {
195 desc_addr = s->cur_rx[i];
196 if (!desc_addr) {
197 continue;
198 }
199 do {
200 eth_rx_desc_get(desc_addr, &desc);
201 if ((desc.cmdstat & MP_ETH_RX_OWN) && desc.buffer_size >= size) {
202 cpu_physical_memory_write(desc.buffer + s->vlan_header,
203 buf, size);
204 desc.bytes = size + s->vlan_header;
205 desc.cmdstat &= ~MP_ETH_RX_OWN;
206 s->cur_rx[i] = desc.next;
207
208 s->icr |= MP_ETH_IRQ_RX;
209 if (s->icr & s->imr) {
210 qemu_irq_raise(s->irq);
211 }
212 eth_rx_desc_put(desc_addr, &desc);
213 return size;
214 }
215 desc_addr = desc.next;
216 } while (desc_addr != s->rx_queue[i]);
217 }
218 return size;
219 }
220
221 static void eth_tx_desc_put(uint32_t addr, mv88w8618_tx_desc *desc)
222 {
223 cpu_to_le32s(&desc->cmdstat);
224 cpu_to_le16s(&desc->res);
225 cpu_to_le16s(&desc->bytes);
226 cpu_to_le32s(&desc->buffer);
227 cpu_to_le32s(&desc->next);
228 cpu_physical_memory_write(addr, (void *)desc, sizeof(*desc));
229 }
230
231 static void eth_tx_desc_get(uint32_t addr, mv88w8618_tx_desc *desc)
232 {
233 cpu_physical_memory_read(addr, (void *)desc, sizeof(*desc));
234 le32_to_cpus(&desc->cmdstat);
235 le16_to_cpus(&desc->res);
236 le16_to_cpus(&desc->bytes);
237 le32_to_cpus(&desc->buffer);
238 le32_to_cpus(&desc->next);
239 }
240
241 static void eth_send(mv88w8618_eth_state *s, int queue_index)
242 {
243 uint32_t desc_addr = s->tx_queue[queue_index];
244 mv88w8618_tx_desc desc;
245 uint32_t next_desc;
246 uint8_t buf[2048];
247 int len;
248
249 do {
250 eth_tx_desc_get(desc_addr, &desc);
251 next_desc = desc.next;
252 if (desc.cmdstat & MP_ETH_TX_OWN) {
253 len = desc.bytes;
254 if (len < 2048) {
255 cpu_physical_memory_read(desc.buffer, buf, len);
256 qemu_send_packet(&s->nic->nc, buf, len);
257 }
258 desc.cmdstat &= ~MP_ETH_TX_OWN;
259 s->icr |= 1 << (MP_ETH_IRQ_TXLO_BIT - queue_index);
260 eth_tx_desc_put(desc_addr, &desc);
261 }
262 desc_addr = next_desc;
263 } while (desc_addr != s->tx_queue[queue_index]);
264 }
265
266 static uint64_t mv88w8618_eth_read(void *opaque, target_phys_addr_t offset,
267 unsigned size)
268 {
269 mv88w8618_eth_state *s = opaque;
270
271 switch (offset) {
272 case MP_ETH_SMIR:
273 if (s->smir & MP_ETH_SMIR_OPCODE) {
274 switch (s->smir & MP_ETH_SMIR_ADDR) {
275 case MP_ETH_PHY1_BMSR:
276 return MP_PHY_BMSR_LINK | MP_PHY_BMSR_AUTONEG |
277 MP_ETH_SMIR_RDVALID;
278 case MP_ETH_PHY1_PHYSID1:
279 return (MP_PHY_88E3015 >> 16) | MP_ETH_SMIR_RDVALID;
280 case MP_ETH_PHY1_PHYSID2:
281 return (MP_PHY_88E3015 & 0xFFFF) | MP_ETH_SMIR_RDVALID;
282 default:
283 return MP_ETH_SMIR_RDVALID;
284 }
285 }
286 return 0;
287
288 case MP_ETH_ICR:
289 return s->icr;
290
291 case MP_ETH_IMR:
292 return s->imr;
293
294 case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
295 return s->frx_queue[(offset - MP_ETH_FRDP0)/4];
296
297 case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
298 return s->rx_queue[(offset - MP_ETH_CRDP0)/4];
299
300 case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
301 return s->tx_queue[(offset - MP_ETH_CTDP0)/4];
302
303 default:
304 return 0;
305 }
306 }
307
308 static void mv88w8618_eth_write(void *opaque, target_phys_addr_t offset,
309 uint64_t value, unsigned size)
310 {
311 mv88w8618_eth_state *s = opaque;
312
313 switch (offset) {
314 case MP_ETH_SMIR:
315 s->smir = value;
316 break;
317
318 case MP_ETH_PCXR:
319 s->vlan_header = ((value >> MP_ETH_PCXR_2BSM_BIT) & 1) * 2;
320 break;
321
322 case MP_ETH_SDCMR:
323 if (value & MP_ETH_CMD_TXHI) {
324 eth_send(s, 1);
325 }
326 if (value & MP_ETH_CMD_TXLO) {
327 eth_send(s, 0);
328 }
329 if (value & (MP_ETH_CMD_TXHI | MP_ETH_CMD_TXLO) && s->icr & s->imr) {
330 qemu_irq_raise(s->irq);
331 }
332 break;
333
334 case MP_ETH_ICR:
335 s->icr &= value;
336 break;
337
338 case MP_ETH_IMR:
339 s->imr = value;
340 if (s->icr & s->imr) {
341 qemu_irq_raise(s->irq);
342 }
343 break;
344
345 case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
346 s->frx_queue[(offset - MP_ETH_FRDP0)/4] = value;
347 break;
348
349 case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
350 s->rx_queue[(offset - MP_ETH_CRDP0)/4] =
351 s->cur_rx[(offset - MP_ETH_CRDP0)/4] = value;
352 break;
353
354 case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
355 s->tx_queue[(offset - MP_ETH_CTDP0)/4] = value;
356 break;
357 }
358 }
359
360 static const MemoryRegionOps mv88w8618_eth_ops = {
361 .read = mv88w8618_eth_read,
362 .write = mv88w8618_eth_write,
363 .endianness = DEVICE_NATIVE_ENDIAN,
364 };
365
366 static void eth_cleanup(VLANClientState *nc)
367 {
368 mv88w8618_eth_state *s = DO_UPCAST(NICState, nc, nc)->opaque;
369
370 s->nic = NULL;
371 }
372
373 static NetClientInfo net_mv88w8618_info = {
374 .type = NET_CLIENT_TYPE_NIC,
375 .size = sizeof(NICState),
376 .can_receive = eth_can_receive,
377 .receive = eth_receive,
378 .cleanup = eth_cleanup,
379 };
380
381 static int mv88w8618_eth_init(SysBusDevice *dev)
382 {
383 mv88w8618_eth_state *s = FROM_SYSBUS(mv88w8618_eth_state, dev);
384
385 sysbus_init_irq(dev, &s->irq);
386 s->nic = qemu_new_nic(&net_mv88w8618_info, &s->conf,
387 dev->qdev.info->name, dev->qdev.id, s);
388 memory_region_init_io(&s->iomem, &mv88w8618_eth_ops, s, "mv88w8618-eth",
389 MP_ETH_SIZE);
390 sysbus_init_mmio(dev, &s->iomem);
391 return 0;
392 }
393
394 static const VMStateDescription mv88w8618_eth_vmsd = {
395 .name = "mv88w8618_eth",
396 .version_id = 1,
397 .minimum_version_id = 1,
398 .minimum_version_id_old = 1,
399 .fields = (VMStateField[]) {
400 VMSTATE_UINT32(smir, mv88w8618_eth_state),
401 VMSTATE_UINT32(icr, mv88w8618_eth_state),
402 VMSTATE_UINT32(imr, mv88w8618_eth_state),
403 VMSTATE_UINT32(vlan_header, mv88w8618_eth_state),
404 VMSTATE_UINT32_ARRAY(tx_queue, mv88w8618_eth_state, 2),
405 VMSTATE_UINT32_ARRAY(rx_queue, mv88w8618_eth_state, 4),
406 VMSTATE_UINT32_ARRAY(frx_queue, mv88w8618_eth_state, 4),
407 VMSTATE_UINT32_ARRAY(cur_rx, mv88w8618_eth_state, 4),
408 VMSTATE_END_OF_LIST()
409 }
410 };
411
412 static SysBusDeviceInfo mv88w8618_eth_info = {
413 .init = mv88w8618_eth_init,
414 .qdev.name = "mv88w8618_eth",
415 .qdev.size = sizeof(mv88w8618_eth_state),
416 .qdev.vmsd = &mv88w8618_eth_vmsd,
417 .qdev.props = (Property[]) {
418 DEFINE_NIC_PROPERTIES(mv88w8618_eth_state, conf),
419 DEFINE_PROP_END_OF_LIST(),
420 },
421 };
422
423 /* LCD register offsets */
424 #define MP_LCD_IRQCTRL 0x180
425 #define MP_LCD_IRQSTAT 0x184
426 #define MP_LCD_SPICTRL 0x1ac
427 #define MP_LCD_INST 0x1bc
428 #define MP_LCD_DATA 0x1c0
429
430 /* Mode magics */
431 #define MP_LCD_SPI_DATA 0x00100011
432 #define MP_LCD_SPI_CMD 0x00104011
433 #define MP_LCD_SPI_INVALID 0x00000000
434
435 /* Commmands */
436 #define MP_LCD_INST_SETPAGE0 0xB0
437 /* ... */
438 #define MP_LCD_INST_SETPAGE7 0xB7
439
440 #define MP_LCD_TEXTCOLOR 0xe0e0ff /* RRGGBB */
441
442 typedef struct musicpal_lcd_state {
443 SysBusDevice busdev;
444 MemoryRegion iomem;
445 uint32_t brightness;
446 uint32_t mode;
447 uint32_t irqctrl;
448 uint32_t page;
449 uint32_t page_off;
450 DisplayState *ds;
451 uint8_t video_ram[128*64/8];
452 } musicpal_lcd_state;
453
454 static uint8_t scale_lcd_color(musicpal_lcd_state *s, uint8_t col)
455 {
456 switch (s->brightness) {
457 case 7:
458 return col;
459 case 0:
460 return 0;
461 default:
462 return (col * s->brightness) / 7;
463 }
464 }
465
466 #define SET_LCD_PIXEL(depth, type) \
467 static inline void glue(set_lcd_pixel, depth) \
468 (musicpal_lcd_state *s, int x, int y, type col) \
469 { \
470 int dx, dy; \
471 type *pixel = &((type *) ds_get_data(s->ds))[(y * 128 * 3 + x) * 3]; \
472 \
473 for (dy = 0; dy < 3; dy++, pixel += 127 * 3) \
474 for (dx = 0; dx < 3; dx++, pixel++) \
475 *pixel = col; \
476 }
477 SET_LCD_PIXEL(8, uint8_t)
478 SET_LCD_PIXEL(16, uint16_t)
479 SET_LCD_PIXEL(32, uint32_t)
480
481 #include "pixel_ops.h"
482
483 static void lcd_refresh(void *opaque)
484 {
485 musicpal_lcd_state *s = opaque;
486 int x, y, col;
487
488 switch (ds_get_bits_per_pixel(s->ds)) {
489 case 0:
490 return;
491 #define LCD_REFRESH(depth, func) \
492 case depth: \
493 col = func(scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 16) & 0xff), \
494 scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 8) & 0xff), \
495 scale_lcd_color(s, MP_LCD_TEXTCOLOR & 0xff)); \
496 for (x = 0; x < 128; x++) { \
497 for (y = 0; y < 64; y++) { \
498 if (s->video_ram[x + (y/8)*128] & (1 << (y % 8))) { \
499 glue(set_lcd_pixel, depth)(s, x, y, col); \
500 } else { \
501 glue(set_lcd_pixel, depth)(s, x, y, 0); \
502 } \
503 } \
504 } \
505 break;
506 LCD_REFRESH(8, rgb_to_pixel8)
507 LCD_REFRESH(16, rgb_to_pixel16)
508 LCD_REFRESH(32, (is_surface_bgr(s->ds->surface) ?
509 rgb_to_pixel32bgr : rgb_to_pixel32))
510 default:
511 hw_error("unsupported colour depth %i\n",
512 ds_get_bits_per_pixel(s->ds));
513 }
514
515 dpy_update(s->ds, 0, 0, 128*3, 64*3);
516 }
517
518 static void lcd_invalidate(void *opaque)
519 {
520 }
521
522 static void musicpal_lcd_gpio_brigthness_in(void *opaque, int irq, int level)
523 {
524 musicpal_lcd_state *s = opaque;
525 s->brightness &= ~(1 << irq);
526 s->brightness |= level << irq;
527 }
528
529 static uint64_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset,
530 unsigned size)
531 {
532 musicpal_lcd_state *s = opaque;
533
534 switch (offset) {
535 case MP_LCD_IRQCTRL:
536 return s->irqctrl;
537
538 default:
539 return 0;
540 }
541 }
542
543 static void musicpal_lcd_write(void *opaque, target_phys_addr_t offset,
544 uint64_t value, unsigned size)
545 {
546 musicpal_lcd_state *s = opaque;
547
548 switch (offset) {
549 case MP_LCD_IRQCTRL:
550 s->irqctrl = value;
551 break;
552
553 case MP_LCD_SPICTRL:
554 if (value == MP_LCD_SPI_DATA || value == MP_LCD_SPI_CMD) {
555 s->mode = value;
556 } else {
557 s->mode = MP_LCD_SPI_INVALID;
558 }
559 break;
560
561 case MP_LCD_INST:
562 if (value >= MP_LCD_INST_SETPAGE0 && value <= MP_LCD_INST_SETPAGE7) {
563 s->page = value - MP_LCD_INST_SETPAGE0;
564 s->page_off = 0;
565 }
566 break;
567
568 case MP_LCD_DATA:
569 if (s->mode == MP_LCD_SPI_CMD) {
570 if (value >= MP_LCD_INST_SETPAGE0 &&
571 value <= MP_LCD_INST_SETPAGE7) {
572 s->page = value - MP_LCD_INST_SETPAGE0;
573 s->page_off = 0;
574 }
575 } else if (s->mode == MP_LCD_SPI_DATA) {
576 s->video_ram[s->page*128 + s->page_off] = value;
577 s->page_off = (s->page_off + 1) & 127;
578 }
579 break;
580 }
581 }
582
583 static const MemoryRegionOps musicpal_lcd_ops = {
584 .read = musicpal_lcd_read,
585 .write = musicpal_lcd_write,
586 .endianness = DEVICE_NATIVE_ENDIAN,
587 };
588
589 static int musicpal_lcd_init(SysBusDevice *dev)
590 {
591 musicpal_lcd_state *s = FROM_SYSBUS(musicpal_lcd_state, dev);
592
593 s->brightness = 7;
594
595 memory_region_init_io(&s->iomem, &musicpal_lcd_ops, s,
596 "musicpal-lcd", MP_LCD_SIZE);
597 sysbus_init_mmio(dev, &s->iomem);
598
599 s->ds = graphic_console_init(lcd_refresh, lcd_invalidate,
600 NULL, NULL, s);
601 qemu_console_resize(s->ds, 128*3, 64*3);
602
603 qdev_init_gpio_in(&dev->qdev, musicpal_lcd_gpio_brigthness_in, 3);
604
605 return 0;
606 }
607
608 static const VMStateDescription musicpal_lcd_vmsd = {
609 .name = "musicpal_lcd",
610 .version_id = 1,
611 .minimum_version_id = 1,
612 .minimum_version_id_old = 1,
613 .fields = (VMStateField[]) {
614 VMSTATE_UINT32(brightness, musicpal_lcd_state),
615 VMSTATE_UINT32(mode, musicpal_lcd_state),
616 VMSTATE_UINT32(irqctrl, musicpal_lcd_state),
617 VMSTATE_UINT32(page, musicpal_lcd_state),
618 VMSTATE_UINT32(page_off, musicpal_lcd_state),
619 VMSTATE_BUFFER(video_ram, musicpal_lcd_state),
620 VMSTATE_END_OF_LIST()
621 }
622 };
623
624 static SysBusDeviceInfo musicpal_lcd_info = {
625 .init = musicpal_lcd_init,
626 .qdev.name = "musicpal_lcd",
627 .qdev.size = sizeof(musicpal_lcd_state),
628 .qdev.vmsd = &musicpal_lcd_vmsd,
629 };
630
631 /* PIC register offsets */
632 #define MP_PIC_STATUS 0x00
633 #define MP_PIC_ENABLE_SET 0x08
634 #define MP_PIC_ENABLE_CLR 0x0C
635
636 typedef struct mv88w8618_pic_state
637 {
638 SysBusDevice busdev;
639 MemoryRegion iomem;
640 uint32_t level;
641 uint32_t enabled;
642 qemu_irq parent_irq;
643 } mv88w8618_pic_state;
644
645 static void mv88w8618_pic_update(mv88w8618_pic_state *s)
646 {
647 qemu_set_irq(s->parent_irq, (s->level & s->enabled));
648 }
649
650 static void mv88w8618_pic_set_irq(void *opaque, int irq, int level)
651 {
652 mv88w8618_pic_state *s = opaque;
653
654 if (level) {
655 s->level |= 1 << irq;
656 } else {
657 s->level &= ~(1 << irq);
658 }
659 mv88w8618_pic_update(s);
660 }
661
662 static uint64_t mv88w8618_pic_read(void *opaque, target_phys_addr_t offset,
663 unsigned size)
664 {
665 mv88w8618_pic_state *s = opaque;
666
667 switch (offset) {
668 case MP_PIC_STATUS:
669 return s->level & s->enabled;
670
671 default:
672 return 0;
673 }
674 }
675
676 static void mv88w8618_pic_write(void *opaque, target_phys_addr_t offset,
677 uint64_t value, unsigned size)
678 {
679 mv88w8618_pic_state *s = opaque;
680
681 switch (offset) {
682 case MP_PIC_ENABLE_SET:
683 s->enabled |= value;
684 break;
685
686 case MP_PIC_ENABLE_CLR:
687 s->enabled &= ~value;
688 s->level &= ~value;
689 break;
690 }
691 mv88w8618_pic_update(s);
692 }
693
694 static void mv88w8618_pic_reset(DeviceState *d)
695 {
696 mv88w8618_pic_state *s = FROM_SYSBUS(mv88w8618_pic_state,
697 sysbus_from_qdev(d));
698
699 s->level = 0;
700 s->enabled = 0;
701 }
702
703 static const MemoryRegionOps mv88w8618_pic_ops = {
704 .read = mv88w8618_pic_read,
705 .write = mv88w8618_pic_write,
706 .endianness = DEVICE_NATIVE_ENDIAN,
707 };
708
709 static int mv88w8618_pic_init(SysBusDevice *dev)
710 {
711 mv88w8618_pic_state *s = FROM_SYSBUS(mv88w8618_pic_state, dev);
712
713 qdev_init_gpio_in(&dev->qdev, mv88w8618_pic_set_irq, 32);
714 sysbus_init_irq(dev, &s->parent_irq);
715 memory_region_init_io(&s->iomem, &mv88w8618_pic_ops, s,
716 "musicpal-pic", MP_PIC_SIZE);
717 sysbus_init_mmio(dev, &s->iomem);
718 return 0;
719 }
720
721 static const VMStateDescription mv88w8618_pic_vmsd = {
722 .name = "mv88w8618_pic",
723 .version_id = 1,
724 .minimum_version_id = 1,
725 .minimum_version_id_old = 1,
726 .fields = (VMStateField[]) {
727 VMSTATE_UINT32(level, mv88w8618_pic_state),
728 VMSTATE_UINT32(enabled, mv88w8618_pic_state),
729 VMSTATE_END_OF_LIST()
730 }
731 };
732
733 static SysBusDeviceInfo mv88w8618_pic_info = {
734 .init = mv88w8618_pic_init,
735 .qdev.name = "mv88w8618_pic",
736 .qdev.size = sizeof(mv88w8618_pic_state),
737 .qdev.reset = mv88w8618_pic_reset,
738 .qdev.vmsd = &mv88w8618_pic_vmsd,
739 };
740
741 /* PIT register offsets */
742 #define MP_PIT_TIMER1_LENGTH 0x00
743 /* ... */
744 #define MP_PIT_TIMER4_LENGTH 0x0C
745 #define MP_PIT_CONTROL 0x10
746 #define MP_PIT_TIMER1_VALUE 0x14
747 /* ... */
748 #define MP_PIT_TIMER4_VALUE 0x20
749 #define MP_BOARD_RESET 0x34
750
751 /* Magic board reset value (probably some watchdog behind it) */
752 #define MP_BOARD_RESET_MAGIC 0x10000
753
754 typedef struct mv88w8618_timer_state {
755 ptimer_state *ptimer;
756 uint32_t limit;
757 int freq;
758 qemu_irq irq;
759 } mv88w8618_timer_state;
760
761 typedef struct mv88w8618_pit_state {
762 SysBusDevice busdev;
763 MemoryRegion iomem;
764 mv88w8618_timer_state timer[4];
765 } mv88w8618_pit_state;
766
767 static void mv88w8618_timer_tick(void *opaque)
768 {
769 mv88w8618_timer_state *s = opaque;
770
771 qemu_irq_raise(s->irq);
772 }
773
774 static void mv88w8618_timer_init(SysBusDevice *dev, mv88w8618_timer_state *s,
775 uint32_t freq)
776 {
777 QEMUBH *bh;
778
779 sysbus_init_irq(dev, &s->irq);
780 s->freq = freq;
781
782 bh = qemu_bh_new(mv88w8618_timer_tick, s);
783 s->ptimer = ptimer_init(bh);
784 }
785
786 static uint64_t mv88w8618_pit_read(void *opaque, target_phys_addr_t offset,
787 unsigned size)
788 {
789 mv88w8618_pit_state *s = opaque;
790 mv88w8618_timer_state *t;
791
792 switch (offset) {
793 case MP_PIT_TIMER1_VALUE ... MP_PIT_TIMER4_VALUE:
794 t = &s->timer[(offset-MP_PIT_TIMER1_VALUE) >> 2];
795 return ptimer_get_count(t->ptimer);
796
797 default:
798 return 0;
799 }
800 }
801
802 static void mv88w8618_pit_write(void *opaque, target_phys_addr_t offset,
803 uint64_t value, unsigned size)
804 {
805 mv88w8618_pit_state *s = opaque;
806 mv88w8618_timer_state *t;
807 int i;
808
809 switch (offset) {
810 case MP_PIT_TIMER1_LENGTH ... MP_PIT_TIMER4_LENGTH:
811 t = &s->timer[offset >> 2];
812 t->limit = value;
813 if (t->limit > 0) {
814 ptimer_set_limit(t->ptimer, t->limit, 1);
815 } else {
816 ptimer_stop(t->ptimer);
817 }
818 break;
819
820 case MP_PIT_CONTROL:
821 for (i = 0; i < 4; i++) {
822 t = &s->timer[i];
823 if (value & 0xf && t->limit > 0) {
824 ptimer_set_limit(t->ptimer, t->limit, 0);
825 ptimer_set_freq(t->ptimer, t->freq);
826 ptimer_run(t->ptimer, 0);
827 } else {
828 ptimer_stop(t->ptimer);
829 }
830 value >>= 4;
831 }
832 break;
833
834 case MP_BOARD_RESET:
835 if (value == MP_BOARD_RESET_MAGIC) {
836 qemu_system_reset_request();
837 }
838 break;
839 }
840 }
841
842 static void mv88w8618_pit_reset(DeviceState *d)
843 {
844 mv88w8618_pit_state *s = FROM_SYSBUS(mv88w8618_pit_state,
845 sysbus_from_qdev(d));
846 int i;
847
848 for (i = 0; i < 4; i++) {
849 ptimer_stop(s->timer[i].ptimer);
850 s->timer[i].limit = 0;
851 }
852 }
853
854 static const MemoryRegionOps mv88w8618_pit_ops = {
855 .read = mv88w8618_pit_read,
856 .write = mv88w8618_pit_write,
857 .endianness = DEVICE_NATIVE_ENDIAN,
858 };
859
860 static int mv88w8618_pit_init(SysBusDevice *dev)
861 {
862 mv88w8618_pit_state *s = FROM_SYSBUS(mv88w8618_pit_state, dev);
863 int i;
864
865 /* Letting them all run at 1 MHz is likely just a pragmatic
866 * simplification. */
867 for (i = 0; i < 4; i++) {
868 mv88w8618_timer_init(dev, &s->timer[i], 1000000);
869 }
870
871 memory_region_init_io(&s->iomem, &mv88w8618_pit_ops, s,
872 "musicpal-pit", MP_PIT_SIZE);
873 sysbus_init_mmio(dev, &s->iomem);
874 return 0;
875 }
876
877 static const VMStateDescription mv88w8618_timer_vmsd = {
878 .name = "timer",
879 .version_id = 1,
880 .minimum_version_id = 1,
881 .minimum_version_id_old = 1,
882 .fields = (VMStateField[]) {
883 VMSTATE_PTIMER(ptimer, mv88w8618_timer_state),
884 VMSTATE_UINT32(limit, mv88w8618_timer_state),
885 VMSTATE_END_OF_LIST()
886 }
887 };
888
889 static const VMStateDescription mv88w8618_pit_vmsd = {
890 .name = "mv88w8618_pit",
891 .version_id = 1,
892 .minimum_version_id = 1,
893 .minimum_version_id_old = 1,
894 .fields = (VMStateField[]) {
895 VMSTATE_STRUCT_ARRAY(timer, mv88w8618_pit_state, 4, 1,
896 mv88w8618_timer_vmsd, mv88w8618_timer_state),
897 VMSTATE_END_OF_LIST()
898 }
899 };
900
901 static SysBusDeviceInfo mv88w8618_pit_info = {
902 .init = mv88w8618_pit_init,
903 .qdev.name = "mv88w8618_pit",
904 .qdev.size = sizeof(mv88w8618_pit_state),
905 .qdev.reset = mv88w8618_pit_reset,
906 .qdev.vmsd = &mv88w8618_pit_vmsd,
907 };
908
909 /* Flash config register offsets */
910 #define MP_FLASHCFG_CFGR0 0x04
911
912 typedef struct mv88w8618_flashcfg_state {
913 SysBusDevice busdev;
914 MemoryRegion iomem;
915 uint32_t cfgr0;
916 } mv88w8618_flashcfg_state;
917
918 static uint64_t mv88w8618_flashcfg_read(void *opaque,
919 target_phys_addr_t offset,
920 unsigned size)
921 {
922 mv88w8618_flashcfg_state *s = opaque;
923
924 switch (offset) {
925 case MP_FLASHCFG_CFGR0:
926 return s->cfgr0;
927
928 default:
929 return 0;
930 }
931 }
932
933 static void mv88w8618_flashcfg_write(void *opaque, target_phys_addr_t offset,
934 uint64_t value, unsigned size)
935 {
936 mv88w8618_flashcfg_state *s = opaque;
937
938 switch (offset) {
939 case MP_FLASHCFG_CFGR0:
940 s->cfgr0 = value;
941 break;
942 }
943 }
944
945 static const MemoryRegionOps mv88w8618_flashcfg_ops = {
946 .read = mv88w8618_flashcfg_read,
947 .write = mv88w8618_flashcfg_write,
948 .endianness = DEVICE_NATIVE_ENDIAN,
949 };
950
951 static int mv88w8618_flashcfg_init(SysBusDevice *dev)
952 {
953 mv88w8618_flashcfg_state *s = FROM_SYSBUS(mv88w8618_flashcfg_state, dev);
954
955 s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */
956 memory_region_init_io(&s->iomem, &mv88w8618_flashcfg_ops, s,
957 "musicpal-flashcfg", MP_FLASHCFG_SIZE);
958 sysbus_init_mmio(dev, &s->iomem);
959 return 0;
960 }
961
962 static const VMStateDescription mv88w8618_flashcfg_vmsd = {
963 .name = "mv88w8618_flashcfg",
964 .version_id = 1,
965 .minimum_version_id = 1,
966 .minimum_version_id_old = 1,
967 .fields = (VMStateField[]) {
968 VMSTATE_UINT32(cfgr0, mv88w8618_flashcfg_state),
969 VMSTATE_END_OF_LIST()
970 }
971 };
972
973 static SysBusDeviceInfo mv88w8618_flashcfg_info = {
974 .init = mv88w8618_flashcfg_init,
975 .qdev.name = "mv88w8618_flashcfg",
976 .qdev.size = sizeof(mv88w8618_flashcfg_state),
977 .qdev.vmsd = &mv88w8618_flashcfg_vmsd,
978 };
979
980 /* Misc register offsets */
981 #define MP_MISC_BOARD_REVISION 0x18
982
983 #define MP_BOARD_REVISION 0x31
984
985 static uint64_t musicpal_misc_read(void *opaque, target_phys_addr_t offset,
986 unsigned size)
987 {
988 switch (offset) {
989 case MP_MISC_BOARD_REVISION:
990 return MP_BOARD_REVISION;
991
992 default:
993 return 0;
994 }
995 }
996
997 static void musicpal_misc_write(void *opaque, target_phys_addr_t offset,
998 uint64_t value, unsigned size)
999 {
1000 }
1001
1002 static const MemoryRegionOps musicpal_misc_ops = {
1003 .read = musicpal_misc_read,
1004 .write = musicpal_misc_write,
1005 .endianness = DEVICE_NATIVE_ENDIAN,
1006 };
1007
1008 static void musicpal_misc_init(SysBusDevice *dev)
1009 {
1010 MemoryRegion *iomem = g_new(MemoryRegion, 1);
1011
1012 memory_region_init_io(iomem, &musicpal_misc_ops, NULL,
1013 "musicpal-misc", MP_MISC_SIZE);
1014 sysbus_add_memory(dev, MP_MISC_BASE, iomem);
1015 }
1016
1017 /* WLAN register offsets */
1018 #define MP_WLAN_MAGIC1 0x11c
1019 #define MP_WLAN_MAGIC2 0x124
1020
1021 static uint64_t mv88w8618_wlan_read(void *opaque, target_phys_addr_t offset,
1022 unsigned size)
1023 {
1024 switch (offset) {
1025 /* Workaround to allow loading the binary-only wlandrv.ko crap
1026 * from the original Freecom firmware. */
1027 case MP_WLAN_MAGIC1:
1028 return ~3;
1029 case MP_WLAN_MAGIC2:
1030 return -1;
1031
1032 default:
1033 return 0;
1034 }
1035 }
1036
1037 static void mv88w8618_wlan_write(void *opaque, target_phys_addr_t offset,
1038 uint64_t value, unsigned size)
1039 {
1040 }
1041
1042 static const MemoryRegionOps mv88w8618_wlan_ops = {
1043 .read = mv88w8618_wlan_read,
1044 .write =mv88w8618_wlan_write,
1045 .endianness = DEVICE_NATIVE_ENDIAN,
1046 };
1047
1048 static int mv88w8618_wlan_init(SysBusDevice *dev)
1049 {
1050 MemoryRegion *iomem = g_new(MemoryRegion, 1);
1051
1052 memory_region_init_io(iomem, &mv88w8618_wlan_ops, NULL,
1053 "musicpal-wlan", MP_WLAN_SIZE);
1054 sysbus_init_mmio(dev, iomem);
1055 return 0;
1056 }
1057
1058 /* GPIO register offsets */
1059 #define MP_GPIO_OE_LO 0x008
1060 #define MP_GPIO_OUT_LO 0x00c
1061 #define MP_GPIO_IN_LO 0x010
1062 #define MP_GPIO_IER_LO 0x014
1063 #define MP_GPIO_IMR_LO 0x018
1064 #define MP_GPIO_ISR_LO 0x020
1065 #define MP_GPIO_OE_HI 0x508
1066 #define MP_GPIO_OUT_HI 0x50c
1067 #define MP_GPIO_IN_HI 0x510
1068 #define MP_GPIO_IER_HI 0x514
1069 #define MP_GPIO_IMR_HI 0x518
1070 #define MP_GPIO_ISR_HI 0x520
1071
1072 /* GPIO bits & masks */
1073 #define MP_GPIO_LCD_BRIGHTNESS 0x00070000
1074 #define MP_GPIO_I2C_DATA_BIT 29
1075 #define MP_GPIO_I2C_CLOCK_BIT 30
1076
1077 /* LCD brightness bits in GPIO_OE_HI */
1078 #define MP_OE_LCD_BRIGHTNESS 0x0007
1079
1080 typedef struct musicpal_gpio_state {
1081 SysBusDevice busdev;
1082 MemoryRegion iomem;
1083 uint32_t lcd_brightness;
1084 uint32_t out_state;
1085 uint32_t in_state;
1086 uint32_t ier;
1087 uint32_t imr;
1088 uint32_t isr;
1089 qemu_irq irq;
1090 qemu_irq out[5]; /* 3 brightness out + 2 lcd (data and clock ) */
1091 } musicpal_gpio_state;
1092
1093 static void musicpal_gpio_brightness_update(musicpal_gpio_state *s) {
1094 int i;
1095 uint32_t brightness;
1096
1097 /* compute brightness ratio */
1098 switch (s->lcd_brightness) {
1099 case 0x00000007:
1100 brightness = 0;
1101 break;
1102
1103 case 0x00020000:
1104 brightness = 1;
1105 break;
1106
1107 case 0x00020001:
1108 brightness = 2;
1109 break;
1110
1111 case 0x00040000:
1112 brightness = 3;
1113 break;
1114
1115 case 0x00010006:
1116 brightness = 4;
1117 break;
1118
1119 case 0x00020005:
1120 brightness = 5;
1121 break;
1122
1123 case 0x00040003:
1124 brightness = 6;
1125 break;
1126
1127 case 0x00030004:
1128 default:
1129 brightness = 7;
1130 }
1131
1132 /* set lcd brightness GPIOs */
1133 for (i = 0; i <= 2; i++) {
1134 qemu_set_irq(s->out[i], (brightness >> i) & 1);
1135 }
1136 }
1137
1138 static void musicpal_gpio_pin_event(void *opaque, int pin, int level)
1139 {
1140 musicpal_gpio_state *s = opaque;
1141 uint32_t mask = 1 << pin;
1142 uint32_t delta = level << pin;
1143 uint32_t old = s->in_state & mask;
1144
1145 s->in_state &= ~mask;
1146 s->in_state |= delta;
1147
1148 if ((old ^ delta) &&
1149 ((level && (s->imr & mask)) || (!level && (s->ier & mask)))) {
1150 s->isr = mask;
1151 qemu_irq_raise(s->irq);
1152 }
1153 }
1154
1155 static uint64_t musicpal_gpio_read(void *opaque, target_phys_addr_t offset,
1156 unsigned size)
1157 {
1158 musicpal_gpio_state *s = opaque;
1159
1160 switch (offset) {
1161 case MP_GPIO_OE_HI: /* used for LCD brightness control */
1162 return s->lcd_brightness & MP_OE_LCD_BRIGHTNESS;
1163
1164 case MP_GPIO_OUT_LO:
1165 return s->out_state & 0xFFFF;
1166 case MP_GPIO_OUT_HI:
1167 return s->out_state >> 16;
1168
1169 case MP_GPIO_IN_LO:
1170 return s->in_state & 0xFFFF;
1171 case MP_GPIO_IN_HI:
1172 return s->in_state >> 16;
1173
1174 case MP_GPIO_IER_LO:
1175 return s->ier & 0xFFFF;
1176 case MP_GPIO_IER_HI:
1177 return s->ier >> 16;
1178
1179 case MP_GPIO_IMR_LO:
1180 return s->imr & 0xFFFF;
1181 case MP_GPIO_IMR_HI:
1182 return s->imr >> 16;
1183
1184 case MP_GPIO_ISR_LO:
1185 return s->isr & 0xFFFF;
1186 case MP_GPIO_ISR_HI:
1187 return s->isr >> 16;
1188
1189 default:
1190 return 0;
1191 }
1192 }
1193
1194 static void musicpal_gpio_write(void *opaque, target_phys_addr_t offset,
1195 uint64_t value, unsigned size)
1196 {
1197 musicpal_gpio_state *s = opaque;
1198 switch (offset) {
1199 case MP_GPIO_OE_HI: /* used for LCD brightness control */
1200 s->lcd_brightness = (s->lcd_brightness & MP_GPIO_LCD_BRIGHTNESS) |
1201 (value & MP_OE_LCD_BRIGHTNESS);
1202 musicpal_gpio_brightness_update(s);
1203 break;
1204
1205 case MP_GPIO_OUT_LO:
1206 s->out_state = (s->out_state & 0xFFFF0000) | (value & 0xFFFF);
1207 break;
1208 case MP_GPIO_OUT_HI:
1209 s->out_state = (s->out_state & 0xFFFF) | (value << 16);
1210 s->lcd_brightness = (s->lcd_brightness & 0xFFFF) |
1211 (s->out_state & MP_GPIO_LCD_BRIGHTNESS);
1212 musicpal_gpio_brightness_update(s);
1213 qemu_set_irq(s->out[3], (s->out_state >> MP_GPIO_I2C_DATA_BIT) & 1);
1214 qemu_set_irq(s->out[4], (s->out_state >> MP_GPIO_I2C_CLOCK_BIT) & 1);
1215 break;
1216
1217 case MP_GPIO_IER_LO:
1218 s->ier = (s->ier & 0xFFFF0000) | (value & 0xFFFF);
1219 break;
1220 case MP_GPIO_IER_HI:
1221 s->ier = (s->ier & 0xFFFF) | (value << 16);
1222 break;
1223
1224 case MP_GPIO_IMR_LO:
1225 s->imr = (s->imr & 0xFFFF0000) | (value & 0xFFFF);
1226 break;
1227 case MP_GPIO_IMR_HI:
1228 s->imr = (s->imr & 0xFFFF) | (value << 16);
1229 break;
1230 }
1231 }
1232
1233 static const MemoryRegionOps musicpal_gpio_ops = {
1234 .read = musicpal_gpio_read,
1235 .write = musicpal_gpio_write,
1236 .endianness = DEVICE_NATIVE_ENDIAN,
1237 };
1238
1239 static void musicpal_gpio_reset(DeviceState *d)
1240 {
1241 musicpal_gpio_state *s = FROM_SYSBUS(musicpal_gpio_state,
1242 sysbus_from_qdev(d));
1243
1244 s->lcd_brightness = 0;
1245 s->out_state = 0;
1246 s->in_state = 0xffffffff;
1247 s->ier = 0;
1248 s->imr = 0;
1249 s->isr = 0;
1250 }
1251
1252 static int musicpal_gpio_init(SysBusDevice *dev)
1253 {
1254 musicpal_gpio_state *s = FROM_SYSBUS(musicpal_gpio_state, dev);
1255
1256 sysbus_init_irq(dev, &s->irq);
1257
1258 memory_region_init_io(&s->iomem, &musicpal_gpio_ops, s,
1259 "musicpal-gpio", MP_GPIO_SIZE);
1260 sysbus_init_mmio(dev, &s->iomem);
1261
1262 qdev_init_gpio_out(&dev->qdev, s->out, ARRAY_SIZE(s->out));
1263
1264 qdev_init_gpio_in(&dev->qdev, musicpal_gpio_pin_event, 32);
1265
1266 return 0;
1267 }
1268
1269 static const VMStateDescription musicpal_gpio_vmsd = {
1270 .name = "musicpal_gpio",
1271 .version_id = 1,
1272 .minimum_version_id = 1,
1273 .minimum_version_id_old = 1,
1274 .fields = (VMStateField[]) {
1275 VMSTATE_UINT32(lcd_brightness, musicpal_gpio_state),
1276 VMSTATE_UINT32(out_state, musicpal_gpio_state),
1277 VMSTATE_UINT32(in_state, musicpal_gpio_state),
1278 VMSTATE_UINT32(ier, musicpal_gpio_state),
1279 VMSTATE_UINT32(imr, musicpal_gpio_state),
1280 VMSTATE_UINT32(isr, musicpal_gpio_state),
1281 VMSTATE_END_OF_LIST()
1282 }
1283 };
1284
1285 static SysBusDeviceInfo musicpal_gpio_info = {
1286 .init = musicpal_gpio_init,
1287 .qdev.name = "musicpal_gpio",
1288 .qdev.size = sizeof(musicpal_gpio_state),
1289 .qdev.reset = musicpal_gpio_reset,
1290 .qdev.vmsd = &musicpal_gpio_vmsd,
1291 };
1292
1293 /* Keyboard codes & masks */
1294 #define KEY_RELEASED 0x80
1295 #define KEY_CODE 0x7f
1296
1297 #define KEYCODE_TAB 0x0f
1298 #define KEYCODE_ENTER 0x1c
1299 #define KEYCODE_F 0x21
1300 #define KEYCODE_M 0x32
1301
1302 #define KEYCODE_EXTENDED 0xe0
1303 #define KEYCODE_UP 0x48
1304 #define KEYCODE_DOWN 0x50
1305 #define KEYCODE_LEFT 0x4b
1306 #define KEYCODE_RIGHT 0x4d
1307
1308 #define MP_KEY_WHEEL_VOL (1 << 0)
1309 #define MP_KEY_WHEEL_VOL_INV (1 << 1)
1310 #define MP_KEY_WHEEL_NAV (1 << 2)
1311 #define MP_KEY_WHEEL_NAV_INV (1 << 3)
1312 #define MP_KEY_BTN_FAVORITS (1 << 4)
1313 #define MP_KEY_BTN_MENU (1 << 5)
1314 #define MP_KEY_BTN_VOLUME (1 << 6)
1315 #define MP_KEY_BTN_NAVIGATION (1 << 7)
1316
1317 typedef struct musicpal_key_state {
1318 SysBusDevice busdev;
1319 MemoryRegion iomem;
1320 uint32_t kbd_extended;
1321 uint32_t pressed_keys;
1322 qemu_irq out[8];
1323 } musicpal_key_state;
1324
1325 static void musicpal_key_event(void *opaque, int keycode)
1326 {
1327 musicpal_key_state *s = opaque;
1328 uint32_t event = 0;
1329 int i;
1330
1331 if (keycode == KEYCODE_EXTENDED) {
1332 s->kbd_extended = 1;
1333 return;
1334 }
1335
1336 if (s->kbd_extended) {
1337 switch (keycode & KEY_CODE) {
1338 case KEYCODE_UP:
1339 event = MP_KEY_WHEEL_NAV | MP_KEY_WHEEL_NAV_INV;
1340 break;
1341
1342 case KEYCODE_DOWN:
1343 event = MP_KEY_WHEEL_NAV;
1344 break;
1345
1346 case KEYCODE_LEFT:
1347 event = MP_KEY_WHEEL_VOL | MP_KEY_WHEEL_VOL_INV;
1348 break;
1349
1350 case KEYCODE_RIGHT:
1351 event = MP_KEY_WHEEL_VOL;
1352 break;
1353 }
1354 } else {
1355 switch (keycode & KEY_CODE) {
1356 case KEYCODE_F:
1357 event = MP_KEY_BTN_FAVORITS;
1358 break;
1359
1360 case KEYCODE_TAB:
1361 event = MP_KEY_BTN_VOLUME;
1362 break;
1363
1364 case KEYCODE_ENTER:
1365 event = MP_KEY_BTN_NAVIGATION;
1366 break;
1367
1368 case KEYCODE_M:
1369 event = MP_KEY_BTN_MENU;
1370 break;
1371 }
1372 /* Do not repeat already pressed buttons */
1373 if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) {
1374 event = 0;
1375 }
1376 }
1377
1378 if (event) {
1379 /* Raise GPIO pin first if repeating a key */
1380 if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) {
1381 for (i = 0; i <= 7; i++) {
1382 if (event & (1 << i)) {
1383 qemu_set_irq(s->out[i], 1);
1384 }
1385 }
1386 }
1387 for (i = 0; i <= 7; i++) {
1388 if (event & (1 << i)) {
1389 qemu_set_irq(s->out[i], !!(keycode & KEY_RELEASED));
1390 }
1391 }
1392 if (keycode & KEY_RELEASED) {
1393 s->pressed_keys &= ~event;
1394 } else {
1395 s->pressed_keys |= event;
1396 }
1397 }
1398
1399 s->kbd_extended = 0;
1400 }
1401
1402 static int musicpal_key_init(SysBusDevice *dev)
1403 {
1404 musicpal_key_state *s = FROM_SYSBUS(musicpal_key_state, dev);
1405
1406 memory_region_init(&s->iomem, "dummy", 0);
1407 sysbus_init_mmio(dev, &s->iomem);
1408
1409 s->kbd_extended = 0;
1410 s->pressed_keys = 0;
1411
1412 qdev_init_gpio_out(&dev->qdev, s->out, ARRAY_SIZE(s->out));
1413
1414 qemu_add_kbd_event_handler(musicpal_key_event, s);
1415
1416 return 0;
1417 }
1418
1419 static const VMStateDescription musicpal_key_vmsd = {
1420 .name = "musicpal_key",
1421 .version_id = 1,
1422 .minimum_version_id = 1,
1423 .minimum_version_id_old = 1,
1424 .fields = (VMStateField[]) {
1425 VMSTATE_UINT32(kbd_extended, musicpal_key_state),
1426 VMSTATE_UINT32(pressed_keys, musicpal_key_state),
1427 VMSTATE_END_OF_LIST()
1428 }
1429 };
1430
1431 static SysBusDeviceInfo musicpal_key_info = {
1432 .init = musicpal_key_init,
1433 .qdev.name = "musicpal_key",
1434 .qdev.size = sizeof(musicpal_key_state),
1435 .qdev.vmsd = &musicpal_key_vmsd,
1436 };
1437
1438 static struct arm_boot_info musicpal_binfo = {
1439 .loader_start = 0x0,
1440 .board_id = 0x20e,
1441 };
1442
1443 static void musicpal_init(ram_addr_t ram_size,
1444 const char *boot_device,
1445 const char *kernel_filename, const char *kernel_cmdline,
1446 const char *initrd_filename, const char *cpu_model)
1447 {
1448 CPUState *env;
1449 qemu_irq *cpu_pic;
1450 qemu_irq pic[32];
1451 DeviceState *dev;
1452 DeviceState *i2c_dev;
1453 DeviceState *lcd_dev;
1454 DeviceState *key_dev;
1455 DeviceState *wm8750_dev;
1456 SysBusDevice *s;
1457 i2c_bus *i2c;
1458 int i;
1459 unsigned long flash_size;
1460 DriveInfo *dinfo;
1461 MemoryRegion *address_space_mem = get_system_memory();
1462 MemoryRegion *ram = g_new(MemoryRegion, 1);
1463 MemoryRegion *sram = g_new(MemoryRegion, 1);
1464
1465 if (!cpu_model) {
1466 cpu_model = "arm926";
1467 }
1468 env = cpu_init(cpu_model);
1469 if (!env) {
1470 fprintf(stderr, "Unable to find CPU definition\n");
1471 exit(1);
1472 }
1473 cpu_pic = arm_pic_init_cpu(env);
1474
1475 /* For now we use a fixed - the original - RAM size */
1476 memory_region_init_ram(ram, "musicpal.ram", MP_RAM_DEFAULT_SIZE);
1477 vmstate_register_ram_global(ram);
1478 memory_region_add_subregion(address_space_mem, 0, ram);
1479
1480 memory_region_init_ram(sram, "musicpal.sram", MP_SRAM_SIZE);
1481 vmstate_register_ram_global(sram);
1482 memory_region_add_subregion(address_space_mem, MP_SRAM_BASE, sram);
1483
1484 dev = sysbus_create_simple("mv88w8618_pic", MP_PIC_BASE,
1485 cpu_pic[ARM_PIC_CPU_IRQ]);
1486 for (i = 0; i < 32; i++) {
1487 pic[i] = qdev_get_gpio_in(dev, i);
1488 }
1489 sysbus_create_varargs("mv88w8618_pit", MP_PIT_BASE, pic[MP_TIMER1_IRQ],
1490 pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ],
1491 pic[MP_TIMER4_IRQ], NULL);
1492
1493 if (serial_hds[0]) {
1494 serial_mm_init(address_space_mem, MP_UART1_BASE, 2, pic[MP_UART1_IRQ],
1495 1825000, serial_hds[0], DEVICE_NATIVE_ENDIAN);
1496 }
1497 if (serial_hds[1]) {
1498 serial_mm_init(address_space_mem, MP_UART2_BASE, 2, pic[MP_UART2_IRQ],
1499 1825000, serial_hds[1], DEVICE_NATIVE_ENDIAN);
1500 }
1501
1502 /* Register flash */
1503 dinfo = drive_get(IF_PFLASH, 0, 0);
1504 if (dinfo) {
1505 flash_size = bdrv_getlength(dinfo->bdrv);
1506 if (flash_size != 8*1024*1024 && flash_size != 16*1024*1024 &&
1507 flash_size != 32*1024*1024) {
1508 fprintf(stderr, "Invalid flash image size\n");
1509 exit(1);
1510 }
1511
1512 /*
1513 * The original U-Boot accesses the flash at 0xFE000000 instead of
1514 * 0xFF800000 (if there is 8 MB flash). So remap flash access if the
1515 * image is smaller than 32 MB.
1516 */
1517 #ifdef TARGET_WORDS_BIGENDIAN
1518 pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, NULL,
1519 "musicpal.flash", flash_size,
1520 dinfo->bdrv, 0x10000,
1521 (flash_size + 0xffff) >> 16,
1522 MP_FLASH_SIZE_MAX / flash_size,
1523 2, 0x00BF, 0x236D, 0x0000, 0x0000,
1524 0x5555, 0x2AAA, 1);
1525 #else
1526 pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, NULL,
1527 "musicpal.flash", flash_size,
1528 dinfo->bdrv, 0x10000,
1529 (flash_size + 0xffff) >> 16,
1530 MP_FLASH_SIZE_MAX / flash_size,
1531 2, 0x00BF, 0x236D, 0x0000, 0x0000,
1532 0x5555, 0x2AAA, 0);
1533 #endif
1534
1535 }
1536 sysbus_create_simple("mv88w8618_flashcfg", MP_FLASHCFG_BASE, NULL);
1537
1538 qemu_check_nic_model(&nd_table[0], "mv88w8618");
1539 dev = qdev_create(NULL, "mv88w8618_eth");
1540 qdev_set_nic_properties(dev, &nd_table[0]);
1541 qdev_init_nofail(dev);
1542 sysbus_mmio_map(sysbus_from_qdev(dev), 0, MP_ETH_BASE);
1543 sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[MP_ETH_IRQ]);
1544
1545 sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE, NULL);
1546
1547 musicpal_misc_init(sysbus_from_qdev(dev));
1548
1549 dev = sysbus_create_simple("musicpal_gpio", MP_GPIO_BASE, pic[MP_GPIO_IRQ]);
1550 i2c_dev = sysbus_create_simple("gpio_i2c", -1, NULL);
1551 i2c = (i2c_bus *)qdev_get_child_bus(i2c_dev, "i2c");
1552
1553 lcd_dev = sysbus_create_simple("musicpal_lcd", MP_LCD_BASE, NULL);
1554 key_dev = sysbus_create_simple("musicpal_key", -1, NULL);
1555
1556 /* I2C read data */
1557 qdev_connect_gpio_out(i2c_dev, 0,
1558 qdev_get_gpio_in(dev, MP_GPIO_I2C_DATA_BIT));
1559 /* I2C data */
1560 qdev_connect_gpio_out(dev, 3, qdev_get_gpio_in(i2c_dev, 0));
1561 /* I2C clock */
1562 qdev_connect_gpio_out(dev, 4, qdev_get_gpio_in(i2c_dev, 1));
1563
1564 for (i = 0; i < 3; i++) {
1565 qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(lcd_dev, i));
1566 }
1567 for (i = 0; i < 4; i++) {
1568 qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i + 8));
1569 }
1570 for (i = 4; i < 8; i++) {
1571 qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i + 15));
1572 }
1573
1574 wm8750_dev = i2c_create_slave(i2c, "wm8750", MP_WM_ADDR);
1575 dev = qdev_create(NULL, "mv88w8618_audio");
1576 s = sysbus_from_qdev(dev);
1577 qdev_prop_set_ptr(dev, "wm8750", wm8750_dev);
1578 qdev_init_nofail(dev);
1579 sysbus_mmio_map(s, 0, MP_AUDIO_BASE);
1580 sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]);
1581
1582 musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE;
1583 musicpal_binfo.kernel_filename = kernel_filename;
1584 musicpal_binfo.kernel_cmdline = kernel_cmdline;
1585 musicpal_binfo.initrd_filename = initrd_filename;
1586 arm_load_kernel(env, &musicpal_binfo);
1587 }
1588
1589 static QEMUMachine musicpal_machine = {
1590 .name = "musicpal",
1591 .desc = "Marvell 88w8618 / MusicPal (ARM926EJ-S)",
1592 .init = musicpal_init,
1593 };
1594
1595 static void musicpal_machine_init(void)
1596 {
1597 qemu_register_machine(&musicpal_machine);
1598 }
1599
1600 machine_init(musicpal_machine_init);
1601
1602 static void musicpal_register_devices(void)
1603 {
1604 sysbus_register_withprop(&mv88w8618_pic_info);
1605 sysbus_register_withprop(&mv88w8618_pit_info);
1606 sysbus_register_withprop(&mv88w8618_flashcfg_info);
1607 sysbus_register_withprop(&mv88w8618_eth_info);
1608 sysbus_register_dev("mv88w8618_wlan", sizeof(SysBusDevice),
1609 mv88w8618_wlan_init);
1610 sysbus_register_withprop(&musicpal_lcd_info);
1611 sysbus_register_withprop(&musicpal_gpio_info);
1612 sysbus_register_withprop(&musicpal_key_info);
1613 }
1614
1615 device_init(musicpal_register_devices)
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