hw/ne2000.c

   1 /*
   2  * QEMU NE2000 emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "vl.h"
  25
  26 /* debug NE2000 card */
  27 //#define DEBUG_NE2000
  28
  29 #define MAX_ETH_FRAME_SIZE 1514
  30
  31 #define E8390_CMD       0x00  /* The command register (for all pages) */
  32 /* Page 0 register offsets. */
  33 #define EN0_CLDALO      0x01    /* Low byte of current local dma addr  RD */
  34 #define EN0_STARTPG     0x01    /* Starting page of ring bfr WR */
  35 #define EN0_CLDAHI      0x02    /* High byte of current local dma addr  RD */
  36 #define EN0_STOPPG      0x02    /* Ending page +1 of ring bfr WR */
  37 #define EN0_BOUNDARY    0x03    /* Boundary page of ring bfr RD WR */
  38 #define EN0_TSR         0x04    /* Transmit status reg RD */
  39 #define EN0_TPSR        0x04    /* Transmit starting page WR */
  40 #define EN0_NCR         0x05    /* Number of collision reg RD */
  41 #define EN0_TCNTLO      0x05    /* Low  byte of tx byte count WR */
  42 #define EN0_FIFO        0x06    /* FIFO RD */
  43 #define EN0_TCNTHI      0x06    /* High byte of tx byte count WR */
  44 #define EN0_ISR         0x07    /* Interrupt status reg RD WR */
  45 #define EN0_CRDALO      0x08    /* low byte of current remote dma address RD */
  46 #define EN0_RSARLO      0x08    /* Remote start address reg 0 */
  47 #define EN0_CRDAHI      0x09    /* high byte, current remote dma address RD */
  48 #define EN0_RSARHI      0x09    /* Remote start address reg 1 */
  49 #define EN0_RCNTLO      0x0a    /* Remote byte count reg WR */
  50 #define EN0_RCNTHI      0x0b    /* Remote byte count reg WR */
  51 #define EN0_RSR         0x0c    /* rx status reg RD */
  52 #define EN0_RXCR        0x0c    /* RX configuration reg WR */
  53 #define EN0_TXCR        0x0d    /* TX configuration reg WR */
  54 #define EN0_COUNTER0    0x0d    /* Rcv alignment error counter RD */
  55 #define EN0_DCFG        0x0e    /* Data configuration reg WR */
  56 #define EN0_COUNTER1    0x0e    /* Rcv CRC error counter RD */
  57 #define EN0_IMR         0x0f    /* Interrupt mask reg WR */
  58 #define EN0_COUNTER2    0x0f    /* Rcv missed frame error counter RD */
  59
  60 #define EN1_PHYS        0x11
  61 #define EN1_CURPAG      0x17
  62 #define EN1_MULT        0x18
  63
  64 #define EN2_STARTPG     0x21    /* Starting page of ring bfr RD */
  65 #define EN2_STOPPG      0x22    /* Ending page +1 of ring bfr RD */
  66
  67 /*  Register accessed at EN_CMD, the 8390 base addr.  */
  68 #define E8390_STOP      0x01    /* Stop and reset the chip */
  69 #define E8390_START     0x02    /* Start the chip, clear reset */
  70 #define E8390_TRANS     0x04    /* Transmit a frame */
  71 #define E8390_RREAD     0x08    /* Remote read */
  72 #define E8390_RWRITE    0x10    /* Remote write  */
  73 #define E8390_NODMA     0x20    /* Remote DMA */
  74 #define E8390_PAGE0     0x00    /* Select page chip registers */
  75 #define E8390_PAGE1     0x40    /* using the two high-order bits */
  76 #define E8390_PAGE2     0x80    /* Page 3 is invalid. */
  77
  78 /* Bits in EN0_ISR - Interrupt status register */
  79 #define ENISR_RX        0x01    /* Receiver, no error */
  80 #define ENISR_TX        0x02    /* Transmitter, no error */
  81 #define ENISR_RX_ERR    0x04    /* Receiver, with error */
  82 #define ENISR_TX_ERR    0x08    /* Transmitter, with error */
  83 #define ENISR_OVER      0x10    /* Receiver overwrote the ring */
  84 #define ENISR_COUNTERS  0x20    /* Counters need emptying */
  85 #define ENISR_RDC       0x40    /* remote dma complete */
  86 #define ENISR_RESET     0x80    /* Reset completed */
  87 #define ENISR_ALL       0x3f    /* Interrupts we will enable */
  88
  89 /* Bits in received packet status byte and EN0_RSR*/
  90 #define ENRSR_RXOK      0x01    /* Received a good packet */
  91 #define ENRSR_CRC       0x02    /* CRC error */
  92 #define ENRSR_FAE       0x04    /* frame alignment error */
  93 #define ENRSR_FO        0x08    /* FIFO overrun */
  94 #define ENRSR_MPA       0x10    /* missed pkt */
  95 #define ENRSR_PHY       0x20    /* physical/multicast address */
  96 #define ENRSR_DIS       0x40    /* receiver disable. set in monitor mode */
  97 #define ENRSR_DEF       0x80    /* deferring */
  98
  99 /* Transmitted packet status, EN0_TSR. */
 100 #define ENTSR_PTX 0x01  /* Packet transmitted without error */
 101 #define ENTSR_ND  0x02  /* The transmit wasn't deferred. */
 102 #define ENTSR_COL 0x04  /* The transmit collided at least once. */
 103 #define ENTSR_ABT 0x08  /* The transmit collided 16 times, and was deferred. */
 104 #define ENTSR_CRS 0x10  /* The carrier sense was lost. */
 105 #define ENTSR_FU  0x20  /* A "FIFO underrun" occurred during transmit. */
 106 #define ENTSR_CDH 0x40  /* The collision detect "heartbeat" signal was lost. */
 107 #define ENTSR_OWC 0x80  /* There was an out-of-window collision. */
 108
 109 #define NE2000_PMEM_SIZE    (32*1024)
 110 #define NE2000_PMEM_START   (16*1024)
 111 #define NE2000_PMEM_END     (NE2000_PMEM_SIZE+NE2000_PMEM_START)
 112 #define NE2000_MEM_SIZE     NE2000_PMEM_END
 113
 114 typedef struct NE2000State {
 115     uint8_t cmd;
 116     uint32_t start;
 117     uint32_t stop;
 118     uint8_t boundary;
 119     uint8_t tsr;
 120     uint8_t tpsr;
 121     uint16_t tcnt;
 122     uint16_t rcnt;
 123     uint32_t rsar;
 124     uint8_t rsr;
 125     uint8_t rxcr;
 126     uint8_t isr;
 127     uint8_t dcfg;
 128     uint8_t imr;
 129     uint8_t phys[6]; /* mac address */
 130     uint8_t curpag;
 131     uint8_t mult[8]; /* multicast mask array */
 132     int irq;
 133     PCIDevice *pci_dev;
 134     VLANClientState *vc;
 135     uint8_t macaddr[6];
 136     uint8_t mem[NE2000_MEM_SIZE];
 137 } NE2000State;
 138
 139 static void ne2000_reset(NE2000State *s)
 140 {
 141     int i;
 142
 143     s->isr = ENISR_RESET;
 144     memcpy(s->mem, s->macaddr, 6);
 145     s->mem[14] = 0x57;
 146     s->mem[15] = 0x57;
 147
 148     /* duplicate prom data */
 149     for(i = 15;i >= 0; i--) {
 150         s->mem[2 * i] = s->mem[i];
 151         s->mem[2 * i + 1] = s->mem[i];
 152     }
 153 }
 154
 155 static void ne2000_update_irq(NE2000State *s)
 156 {
 157     int isr;
 158     isr = (s->isr & s->imr) & 0x7f;
 159 #if defined(DEBUG_NE2000)
 160     printf("NE2000: Set IRQ line %d to %d (%02x %02x)\n",
 161            s->irq, isr ? 1 : 0, s->isr, s->imr);
 162 #endif
 163     if (s->irq == 16) {
 164         /* PCI irq */
 165         pci_set_irq(s->pci_dev, 0, (isr != 0));
 166     } else {
 167         /* ISA irq */
 168         pic_set_irq(s->irq, (isr != 0));
 169     }
 170 }
 171
 172 #define POLYNOMIAL 0x04c11db6
 173
 174 /* From FreeBSD */
 175 /* XXX: optimize */
 176 static int compute_mcast_idx(const uint8_t *ep)
 177 {
 178     uint32_t crc;
 179     int carry, i, j;
 180     uint8_t b;
 181
 182     crc = 0xffffffff;
 183     for (i = 0; i < 6; i++) {
 184         b = *ep++;
 185         for (j = 0; j < 8; j++) {
 186             carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
 187             crc <<= 1;
 188             b >>= 1;
 189             if (carry)
 190                 crc = ((crc ^ POLYNOMIAL) | carry);
 191         }
 192     }
 193     return (crc >> 26);
 194 }
 195
 196 /* return the max buffer size if the NE2000 can receive more data */
 197 static int ne2000_can_receive(void *opaque)
 198 {
 199     NE2000State *s = opaque;
 200     int avail, index, boundary;
 201
 202     if (s->cmd & E8390_STOP)
 203         return 0;
 204     index = s->curpag << 8;
 205     boundary = s->boundary << 8;
 206     if (index < boundary)
 207         avail = boundary - index;
 208     else
 209         avail = (s->stop - s->start) - (index - boundary);
 210     if (avail < (MAX_ETH_FRAME_SIZE + 4))
 211         return 0;
 212     return MAX_ETH_FRAME_SIZE;
 213 }
 214
 215 #define MIN_BUF_SIZE 60
 216
 217 static void ne2000_receive(void *opaque, const uint8_t *buf, int size)
 218 {
 219     NE2000State *s = opaque;
 220     uint8_t *p;
 221     int total_len, next, avail, len, index, mcast_idx;
 222     uint8_t buf1[60];
 223     static const uint8_t broadcast_macaddr[6] =
 224         { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
 225
 226 #if defined(DEBUG_NE2000)
 227     printf("NE2000: received len=%d\n", size);
 228 #endif
 229
 230     if (!ne2000_can_receive(s))
 231         return;
 232
 233     /* XXX: check this */
 234     if (s->rxcr & 0x10) {
 235         /* promiscuous: receive all */
 236     } else {
 237         if (!memcmp(buf,  broadcast_macaddr, 6)) {
 238             /* broadcast address */
 239             if (!(s->rxcr & 0x04))
 240                 return;
 241         } else if (buf[0] & 0x01) {
 242             /* multicast */
 243             if (!(s->rxcr & 0x08))
 244                 return;
 245             mcast_idx = compute_mcast_idx(buf);
 246             if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
 247                 return;
 248         } else if (s->mem[0] == buf[0] &&
 249                    s->mem[2] == buf[1] &&
 250                    s->mem[4] == buf[2] &&
 251                    s->mem[6] == buf[3] &&
 252                    s->mem[8] == buf[4] &&
 253                    s->mem[10] == buf[5]) {
 254             /* match */
 255         } else {
 256             return;
 257         }
 258     }
 259
 260
 261     /* if too small buffer, then expand it */
 262     if (size < MIN_BUF_SIZE) {
 263         memcpy(buf1, buf, size);
 264         memset(buf1 + size, 0, MIN_BUF_SIZE - size);
 265         buf = buf1;
 266         size = MIN_BUF_SIZE;
 267     }
 268
 269     index = s->curpag << 8;
 270     /* 4 bytes for header */
 271     total_len = size + 4;
 272     /* address for next packet (4 bytes for CRC) */
 273     next = index + ((total_len + 4 + 255) & ~0xff);
 274     if (next >= s->stop)
 275         next -= (s->stop - s->start);
 276     /* prepare packet header */
 277     p = s->mem + index;
 278     s->rsr = ENRSR_RXOK; /* receive status */
 279     /* XXX: check this */
 280     if (buf[0] & 0x01)
 281         s->rsr |= ENRSR_PHY;
 282     p[0] = s->rsr;
 283     p[1] = next >> 8;
 284     p[2] = total_len;
 285     p[3] = total_len >> 8;
 286     index += 4;
 287
 288     /* write packet data */
 289     while (size > 0) {
 290         avail = s->stop - index;
 291         len = size;
 292         if (len > avail)
 293             len = avail;
 294         memcpy(s->mem + index, buf, len);
 295         buf += len;
 296         index += len;
 297         if (index == s->stop)
 298             index = s->start;
 299         size -= len;
 300     }
 301     s->curpag = next >> 8;
 302
 303     /* now we can signal we have receive something */
 304     s->isr |= ENISR_RX;
 305     ne2000_update_irq(s);
 306 }
 307
 308 static void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 309 {
 310     NE2000State *s = opaque;
 311     int offset, page, index;
 312
 313     addr &= 0xf;
 314 #ifdef DEBUG_NE2000
 315     printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val);
 316 #endif
 317     if (addr == E8390_CMD) {
 318         /* control register */
 319         s->cmd = val;
 320         if (!(val & E8390_STOP)) { /* START bit makes no sense on RTL8029... */
 321             s->isr &= ~ENISR_RESET;
 322             /* test specific case: zero length transfert */
 323             if ((val & (E8390_RREAD | E8390_RWRITE)) &&
 324                 s->rcnt == 0) {
 325                 s->isr |= ENISR_RDC;
 326                 ne2000_update_irq(s);
 327             }
 328             if (val & E8390_TRANS) {
 329                 index = (s->tpsr << 8);
 330                 /* XXX: next 2 lines are a hack to make netware 3.11 work */
 331                 if (index >= NE2000_PMEM_END)
 332                     index -= NE2000_PMEM_SIZE;
 333                 /* fail safe: check range on the transmitted length  */
 334                 if (index + s->tcnt <= NE2000_PMEM_END) {
 335                     qemu_send_packet(s->vc, s->mem + index, s->tcnt);
 336                 }
 337                 /* signal end of transfert */
 338                 s->tsr = ENTSR_PTX;
 339                 s->isr |= ENISR_TX;
 340                 s->cmd &= ~E8390_TRANS;
 341                 ne2000_update_irq(s);
 342             }
 343         }
 344     } else {
 345         page = s->cmd >> 6;
 346         offset = addr | (page << 4);
 347         switch(offset) {
 348         case EN0_STARTPG:
 349             s->start = val << 8;
 350             break;
 351         case EN0_STOPPG:
 352             s->stop = val << 8;
 353             break;
 354         case EN0_BOUNDARY:
 355             s->boundary = val;
 356             break;
 357         case EN0_IMR:
 358             s->imr = val;
 359             ne2000_update_irq(s);
 360             break;
 361         case EN0_TPSR:
 362             s->tpsr = val;
 363             break;
 364         case EN0_TCNTLO:
 365             s->tcnt = (s->tcnt & 0xff00) | val;
 366             break;
 367         case EN0_TCNTHI:
 368             s->tcnt = (s->tcnt & 0x00ff) | (val << 8);
 369             break;
 370         case EN0_RSARLO:
 371             s->rsar = (s->rsar & 0xff00) | val;
 372             break;
 373         case EN0_RSARHI:
 374             s->rsar = (s->rsar & 0x00ff) | (val << 8);
 375             break;
 376         case EN0_RCNTLO:
 377             s->rcnt = (s->rcnt & 0xff00) | val;
 378             break;
 379         case EN0_RCNTHI:
 380             s->rcnt = (s->rcnt & 0x00ff) | (val << 8);
 381             break;
 382         case EN0_RXCR:
 383             s->rxcr = val;
 384             break;
 385         case EN0_DCFG:
 386             s->dcfg = val;
 387             break;
 388         case EN0_ISR:
 389             s->isr &= ~(val & 0x7f);
 390             ne2000_update_irq(s);
 391             break;
 392         case EN1_PHYS ... EN1_PHYS + 5:
 393             s->phys[offset - EN1_PHYS] = val;
 394             break;
 395         case EN1_CURPAG:
 396             s->curpag = val;
 397             break;
 398         case EN1_MULT ... EN1_MULT + 7:
 399             s->mult[offset - EN1_MULT] = val;
 400             break;
 401         }
 402     }
 403 }
 404
 405 static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr)
 406 {
 407     NE2000State *s = opaque;
 408     int offset, page, ret;
 409
 410     addr &= 0xf;
 411     if (addr == E8390_CMD) {
 412         ret = s->cmd;
 413     } else {
 414         page = s->cmd >> 6;
 415         offset = addr | (page << 4);
 416         switch(offset) {
 417         case EN0_TSR:
 418             ret = s->tsr;
 419             break;
 420         case EN0_BOUNDARY:
 421             ret = s->boundary;
 422             break;
 423         case EN0_ISR:
 424             ret = s->isr;
 425             break;
 426         case EN0_RSARLO:
 427             ret = s->rsar & 0x00ff;
 428             break;
 429         case EN0_RSARHI:
 430             ret = s->rsar >> 8;
 431             break;
 432         case EN1_PHYS ... EN1_PHYS + 5:
 433             ret = s->phys[offset - EN1_PHYS];
 434             break;
 435         case EN1_CURPAG:
 436             ret = s->curpag;
 437             break;
 438         case EN1_MULT ... EN1_MULT + 7:
 439             ret = s->mult[offset - EN1_MULT];
 440             break;
 441         case EN0_RSR:
 442             ret = s->rsr;
 443             break;
 444         case EN2_STARTPG:
 445             ret = s->start >> 8;
 446             break;
 447         case EN2_STOPPG:
 448             ret = s->stop >> 8;
 449             break;
 450         default:
 451             ret = 0x00;
 452             break;
 453         }
 454     }
 455 #ifdef DEBUG_NE2000
 456     printf("NE2000: read addr=0x%x val=%02x\n", addr, ret);
 457 #endif
 458     return ret;
 459 }
 460
 461 static inline void ne2000_mem_writeb(NE2000State *s, uint32_t addr,
 462                                      uint32_t val)
 463 {
 464     if (addr < 32 ||
 465         (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
 466         s->mem[addr] = val;
 467     }
 468 }
 469
 470 static inline void ne2000_mem_writew(NE2000State *s, uint32_t addr,
 471                                      uint32_t val)
 472 {
 473     addr &= ~1; /* XXX: check exact behaviour if not even */
 474     if (addr < 32 ||
 475         (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
 476         *(uint16_t *)(s->mem + addr) = cpu_to_le16(val);
 477     }
 478 }
 479
 480 static inline void ne2000_mem_writel(NE2000State *s, uint32_t addr,
 481                                      uint32_t val)
 482 {
 483     addr &= ~1; /* XXX: check exact behaviour if not even */
 484     if (addr < 32 ||
 485         (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
 486         cpu_to_le32wu((uint32_t *)(s->mem + addr), val);
 487     }
 488 }
 489
 490 static inline uint32_t ne2000_mem_readb(NE2000State *s, uint32_t addr)
 491 {
 492     if (addr < 32 ||
 493         (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
 494         return s->mem[addr];
 495     } else {
 496         return 0xff;
 497     }
 498 }
 499
 500 static inline uint32_t ne2000_mem_readw(NE2000State *s, uint32_t addr)
 501 {
 502     addr &= ~1; /* XXX: check exact behaviour if not even */
 503     if (addr < 32 ||
 504         (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
 505         return le16_to_cpu(*(uint16_t *)(s->mem + addr));
 506     } else {
 507         return 0xffff;
 508     }
 509 }
 510
 511 static inline uint32_t ne2000_mem_readl(NE2000State *s, uint32_t addr)
 512 {
 513     addr &= ~1; /* XXX: check exact behaviour if not even */
 514     if (addr < 32 ||
 515         (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
 516         return le32_to_cpupu((uint32_t *)(s->mem + addr));
 517     } else {
 518         return 0xffffffff;
 519     }
 520 }
 521
 522 static inline void ne2000_dma_update(NE2000State *s, int len)
 523 {
 524     s->rsar += len;
 525     /* wrap */
 526     /* XXX: check what to do if rsar > stop */
 527     if (s->rsar == s->stop)
 528         s->rsar = s->start;
 529
 530     if (s->rcnt <= len) {
 531         s->rcnt = 0;
 532         /* signal end of transfert */
 533         s->isr |= ENISR_RDC;
 534         ne2000_update_irq(s);
 535     } else {
 536         s->rcnt -= len;
 537     }
 538 }
 539
 540 static void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 541 {
 542     NE2000State *s = opaque;
 543
 544 #ifdef DEBUG_NE2000
 545     printf("NE2000: asic write val=0x%04x\n", val);
 546 #endif
 547     if (s->rcnt == 0)
 548         return;
 549     if (s->dcfg & 0x01) {
 550         /* 16 bit access */
 551         ne2000_mem_writew(s, s->rsar, val);
 552         ne2000_dma_update(s, 2);
 553     } else {
 554         /* 8 bit access */
 555         ne2000_mem_writeb(s, s->rsar, val);
 556         ne2000_dma_update(s, 1);
 557     }
 558 }
 559
 560 static uint32_t ne2000_asic_ioport_read(void *opaque, uint32_t addr)
 561 {
 562     NE2000State *s = opaque;
 563     int ret;
 564
 565     if (s->dcfg & 0x01) {
 566         /* 16 bit access */
 567         ret = ne2000_mem_readw(s, s->rsar);
 568         ne2000_dma_update(s, 2);
 569     } else {
 570         /* 8 bit access */
 571         ret = ne2000_mem_readb(s, s->rsar);
 572         ne2000_dma_update(s, 1);
 573     }
 574 #ifdef DEBUG_NE2000
 575     printf("NE2000: asic read val=0x%04x\n", ret);
 576 #endif
 577     return ret;
 578 }
 579
 580 static void ne2000_asic_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
 581 {
 582     NE2000State *s = opaque;
 583
 584 #ifdef DEBUG_NE2000
 585     printf("NE2000: asic writel val=0x%04x\n", val);
 586 #endif
 587     if (s->rcnt == 0)
 588         return;
 589     /* 32 bit access */
 590     ne2000_mem_writel(s, s->rsar, val);
 591     ne2000_dma_update(s, 4);
 592 }
 593
 594 static uint32_t ne2000_asic_ioport_readl(void *opaque, uint32_t addr)
 595 {
 596     NE2000State *s = opaque;
 597     int ret;
 598
 599     /* 32 bit access */
 600     ret = ne2000_mem_readl(s, s->rsar);
 601     ne2000_dma_update(s, 4);
 602 #ifdef DEBUG_NE2000
 603     printf("NE2000: asic readl val=0x%04x\n", ret);
 604 #endif
 605     return ret;
 606 }
 607
 608 static void ne2000_reset_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 609 {
 610     /* nothing to do (end of reset pulse) */
 611 }
 612
 613 static uint32_t ne2000_reset_ioport_read(void *opaque, uint32_t addr)
 614 {
 615     NE2000State *s = opaque;
 616     ne2000_reset(s);
 617     return 0;
 618 }
 619
 620 static void ne2000_save(QEMUFile* f,void* opaque)
 621 {
 622         NE2000State* s=(NE2000State*)opaque;
 623
 624         qemu_put_8s(f, &s->cmd);
 625         qemu_put_be32s(f, &s->start);
 626         qemu_put_be32s(f, &s->stop);
 627         qemu_put_8s(f, &s->boundary);
 628         qemu_put_8s(f, &s->tsr);
 629         qemu_put_8s(f, &s->tpsr);
 630         qemu_put_be16s(f, &s->tcnt);
 631         qemu_put_be16s(f, &s->rcnt);
 632         qemu_put_be32s(f, &s->rsar);
 633         qemu_put_8s(f, &s->rsr);
 634         qemu_put_8s(f, &s->isr);
 635         qemu_put_8s(f, &s->dcfg);
 636         qemu_put_8s(f, &s->imr);
 637         qemu_put_buffer(f, s->phys, 6);
 638         qemu_put_8s(f, &s->curpag);
 639         qemu_put_buffer(f, s->mult, 8);
 640         qemu_put_be32s(f, &s->irq);
 641         qemu_put_buffer(f, s->mem, NE2000_MEM_SIZE);
 642 }
 643
 644 static int ne2000_load(QEMUFile* f,void* opaque,int version_id)
 645 {
 646         NE2000State* s=(NE2000State*)opaque;
 647
 648         if (version_id != 1)
 649             return -EINVAL;
 650
 651         qemu_get_8s(f, &s->cmd);
 652         qemu_get_be32s(f, &s->start);
 653         qemu_get_be32s(f, &s->stop);
 654         qemu_get_8s(f, &s->boundary);
 655         qemu_get_8s(f, &s->tsr);
 656         qemu_get_8s(f, &s->tpsr);
 657         qemu_get_be16s(f, &s->tcnt);
 658         qemu_get_be16s(f, &s->rcnt);
 659         qemu_get_be32s(f, &s->rsar);
 660         qemu_get_8s(f, &s->rsr);
 661         qemu_get_8s(f, &s->isr);
 662         qemu_get_8s(f, &s->dcfg);
 663         qemu_get_8s(f, &s->imr);
 664         qemu_get_buffer(f, s->phys, 6);
 665         qemu_get_8s(f, &s->curpag);
 666         qemu_get_buffer(f, s->mult, 8);
 667         qemu_get_be32s(f, &s->irq);
 668         qemu_get_buffer(f, s->mem, NE2000_MEM_SIZE);
 669
 670         return 0;
 671 }
 672
 673 void isa_ne2000_init(int base, int irq, NICInfo *nd)
 674 {
 675     NE2000State *s;
 676
 677     s = qemu_mallocz(sizeof(NE2000State));
 678     if (!s)
 679         return;
 680
 681     register_ioport_write(base, 16, 1, ne2000_ioport_write, s);
 682     register_ioport_read(base, 16, 1, ne2000_ioport_read, s);
 683
 684     register_ioport_write(base + 0x10, 1, 1, ne2000_asic_ioport_write, s);
 685     register_ioport_read(base + 0x10, 1, 1, ne2000_asic_ioport_read, s);
 686     register_ioport_write(base + 0x10, 2, 2, ne2000_asic_ioport_write, s);
 687     register_ioport_read(base + 0x10, 2, 2, ne2000_asic_ioport_read, s);
 688
 689     register_ioport_write(base + 0x1f, 1, 1, ne2000_reset_ioport_write, s);
 690     register_ioport_read(base + 0x1f, 1, 1, ne2000_reset_ioport_read, s);
 691     s->irq = irq;
 692     memcpy(s->macaddr, nd->macaddr, 6);
 693
 694     ne2000_reset(s);
 695
 696     s->vc = qemu_new_vlan_client(nd->vlan, ne2000_receive, s);
 697
 698     snprintf(s->vc->info_str, sizeof(s->vc->info_str),
 699              "ne2000 macaddr=%02x:%02x:%02x:%02x:%02x:%02x",
 700              s->macaddr[0],
 701              s->macaddr[1],
 702              s->macaddr[2],
 703              s->macaddr[3],
 704              s->macaddr[4],
 705              s->macaddr[5]);
 706
 707     register_savevm("ne2000", 0, 1, ne2000_save, ne2000_load, s);
 708 }
 709
 710 /***********************************************************/
 711 /* PCI NE2000 definitions */
 712
 713 typedef struct PCINE2000State {
 714     PCIDevice dev;
 715     NE2000State ne2000;
 716 } PCINE2000State;
 717
 718 static void ne2000_map(PCIDevice *pci_dev, int region_num,
 719                        uint32_t addr, uint32_t size, int type)
 720 {
 721     PCINE2000State *d = (PCINE2000State *)pci_dev;
 722     NE2000State *s = &d->ne2000;
 723
 724     register_ioport_write(addr, 16, 1, ne2000_ioport_write, s);
 725     register_ioport_read(addr, 16, 1, ne2000_ioport_read, s);
 726
 727     register_ioport_write(addr + 0x10, 1, 1, ne2000_asic_ioport_write, s);
 728     register_ioport_read(addr + 0x10, 1, 1, ne2000_asic_ioport_read, s);
 729     register_ioport_write(addr + 0x10, 2, 2, ne2000_asic_ioport_write, s);
 730     register_ioport_read(addr + 0x10, 2, 2, ne2000_asic_ioport_read, s);
 731     register_ioport_write(addr + 0x10, 4, 4, ne2000_asic_ioport_writel, s);
 732     register_ioport_read(addr + 0x10, 4, 4, ne2000_asic_ioport_readl, s);
 733
 734     register_ioport_write(addr + 0x1f, 1, 1, ne2000_reset_ioport_write, s);
 735     register_ioport_read(addr + 0x1f, 1, 1, ne2000_reset_ioport_read, s);
 736 }
 737
 738 void pci_ne2000_init(PCIBus *bus, NICInfo *nd)
 739 {
 740     PCINE2000State *d;
 741     NE2000State *s;
 742     uint8_t *pci_conf;
 743
 744     d = (PCINE2000State *)pci_register_device(bus,
 745                                               "NE2000", sizeof(PCINE2000State),
 746                                               -1,
 747                                               NULL, NULL);
 748     pci_conf = d->dev.config;
 749     pci_conf[0x00] = 0xec; // Realtek 8029
 750     pci_conf[0x01] = 0x10;
 751     pci_conf[0x02] = 0x29;
 752     pci_conf[0x03] = 0x80;
 753     pci_conf[0x0a] = 0x00; // ethernet network controller
 754     pci_conf[0x0b] = 0x02;
 755     pci_conf[0x0e] = 0x00; // header_type
 756     pci_conf[0x3d] = 1; // interrupt pin 0
 757
 758     pci_register_io_region(&d->dev, 0, 0x100,
 759                            PCI_ADDRESS_SPACE_IO, ne2000_map);
 760     s = &d->ne2000;
 761     s->irq = 16; // PCI interrupt
 762     s->pci_dev = (PCIDevice *)d;
 763     memcpy(s->macaddr, nd->macaddr, 6);
 764     ne2000_reset(s);
 765     s->vc = qemu_new_vlan_client(nd->vlan, ne2000_receive, s);
 766
 767     snprintf(s->vc->info_str, sizeof(s->vc->info_str),
 768              "ne2000 pci macaddr=%02x:%02x:%02x:%02x:%02x:%02x",
 769              s->macaddr[0],
 770              s->macaddr[1],
 771              s->macaddr[2],
 772              s->macaddr[3],
 773              s->macaddr[4],
 774              s->macaddr[5]);
 775
 776     /* XXX: instance number ? */
 777     register_savevm("ne2000", 0, 1, ne2000_save, ne2000_load, s);
 778     register_savevm("ne2000_pci", 0, 1, generic_pci_save, generic_pci_load,
 779                     &d->dev);
 780 }