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[mirror_qemu.git] / hw / net / dp8393x.c
1 /*
2 * QEMU NS SONIC DP8393x netcard
3 *
4 * Copyright (c) 2008-2009 Herve Poussineau
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "hw/irq.h"
22 #include "hw/qdev-properties.h"
23 #include "hw/sysbus.h"
24 #include "migration/vmstate.h"
25 #include "net/net.h"
26 #include "qapi/error.h"
27 #include "qemu/module.h"
28 #include "qemu/timer.h"
29 #include <zlib.h>
30
31 //#define DEBUG_SONIC
32
33 #define SONIC_PROM_SIZE 0x1000
34
35 #ifdef DEBUG_SONIC
36 #define DPRINTF(fmt, ...) \
37 do { printf("sonic: " fmt , ## __VA_ARGS__); } while (0)
38 static const char* reg_names[] = {
39 "CR", "DCR", "RCR", "TCR", "IMR", "ISR", "UTDA", "CTDA",
40 "TPS", "TFC", "TSA0", "TSA1", "TFS", "URDA", "CRDA", "CRBA0",
41 "CRBA1", "RBWC0", "RBWC1", "EOBC", "URRA", "RSA", "REA", "RRP",
42 "RWP", "TRBA0", "TRBA1", "0x1b", "0x1c", "0x1d", "0x1e", "LLFA",
43 "TTDA", "CEP", "CAP2", "CAP1", "CAP0", "CE", "CDP", "CDC",
44 "SR", "WT0", "WT1", "RSC", "CRCT", "FAET", "MPT", "MDT",
45 "0x30", "0x31", "0x32", "0x33", "0x34", "0x35", "0x36", "0x37",
46 "0x38", "0x39", "0x3a", "0x3b", "0x3c", "0x3d", "0x3e", "DCR2" };
47 #else
48 #define DPRINTF(fmt, ...) do {} while (0)
49 #endif
50
51 #define SONIC_ERROR(fmt, ...) \
52 do { printf("sonic ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
53
54 #define SONIC_CR 0x00
55 #define SONIC_DCR 0x01
56 #define SONIC_RCR 0x02
57 #define SONIC_TCR 0x03
58 #define SONIC_IMR 0x04
59 #define SONIC_ISR 0x05
60 #define SONIC_UTDA 0x06
61 #define SONIC_CTDA 0x07
62 #define SONIC_TPS 0x08
63 #define SONIC_TFC 0x09
64 #define SONIC_TSA0 0x0a
65 #define SONIC_TSA1 0x0b
66 #define SONIC_TFS 0x0c
67 #define SONIC_URDA 0x0d
68 #define SONIC_CRDA 0x0e
69 #define SONIC_CRBA0 0x0f
70 #define SONIC_CRBA1 0x10
71 #define SONIC_RBWC0 0x11
72 #define SONIC_RBWC1 0x12
73 #define SONIC_EOBC 0x13
74 #define SONIC_URRA 0x14
75 #define SONIC_RSA 0x15
76 #define SONIC_REA 0x16
77 #define SONIC_RRP 0x17
78 #define SONIC_RWP 0x18
79 #define SONIC_TRBA0 0x19
80 #define SONIC_TRBA1 0x1a
81 #define SONIC_LLFA 0x1f
82 #define SONIC_TTDA 0x20
83 #define SONIC_CEP 0x21
84 #define SONIC_CAP2 0x22
85 #define SONIC_CAP1 0x23
86 #define SONIC_CAP0 0x24
87 #define SONIC_CE 0x25
88 #define SONIC_CDP 0x26
89 #define SONIC_CDC 0x27
90 #define SONIC_SR 0x28
91 #define SONIC_WT0 0x29
92 #define SONIC_WT1 0x2a
93 #define SONIC_RSC 0x2b
94 #define SONIC_CRCT 0x2c
95 #define SONIC_FAET 0x2d
96 #define SONIC_MPT 0x2e
97 #define SONIC_MDT 0x2f
98 #define SONIC_DCR2 0x3f
99
100 #define SONIC_CR_HTX 0x0001
101 #define SONIC_CR_TXP 0x0002
102 #define SONIC_CR_RXDIS 0x0004
103 #define SONIC_CR_RXEN 0x0008
104 #define SONIC_CR_STP 0x0010
105 #define SONIC_CR_ST 0x0020
106 #define SONIC_CR_RST 0x0080
107 #define SONIC_CR_RRRA 0x0100
108 #define SONIC_CR_LCAM 0x0200
109 #define SONIC_CR_MASK 0x03bf
110
111 #define SONIC_DCR_DW 0x0020
112 #define SONIC_DCR_LBR 0x2000
113 #define SONIC_DCR_EXBUS 0x8000
114
115 #define SONIC_RCR_PRX 0x0001
116 #define SONIC_RCR_LBK 0x0002
117 #define SONIC_RCR_FAER 0x0004
118 #define SONIC_RCR_CRCR 0x0008
119 #define SONIC_RCR_CRS 0x0020
120 #define SONIC_RCR_LPKT 0x0040
121 #define SONIC_RCR_BC 0x0080
122 #define SONIC_RCR_MC 0x0100
123 #define SONIC_RCR_LB0 0x0200
124 #define SONIC_RCR_LB1 0x0400
125 #define SONIC_RCR_AMC 0x0800
126 #define SONIC_RCR_PRO 0x1000
127 #define SONIC_RCR_BRD 0x2000
128 #define SONIC_RCR_RNT 0x4000
129
130 #define SONIC_TCR_PTX 0x0001
131 #define SONIC_TCR_BCM 0x0002
132 #define SONIC_TCR_FU 0x0004
133 #define SONIC_TCR_EXC 0x0040
134 #define SONIC_TCR_CRSL 0x0080
135 #define SONIC_TCR_NCRS 0x0100
136 #define SONIC_TCR_EXD 0x0400
137 #define SONIC_TCR_CRCI 0x2000
138 #define SONIC_TCR_PINT 0x8000
139
140 #define SONIC_ISR_RBAE 0x0010
141 #define SONIC_ISR_RBE 0x0020
142 #define SONIC_ISR_RDE 0x0040
143 #define SONIC_ISR_TC 0x0080
144 #define SONIC_ISR_TXDN 0x0200
145 #define SONIC_ISR_PKTRX 0x0400
146 #define SONIC_ISR_PINT 0x0800
147 #define SONIC_ISR_LCD 0x1000
148
149 #define SONIC_DESC_EOL 0x0001
150 #define SONIC_DESC_ADDR 0xFFFE
151
152 #define TYPE_DP8393X "dp8393x"
153 #define DP8393X(obj) OBJECT_CHECK(dp8393xState, (obj), TYPE_DP8393X)
154
155 typedef struct dp8393xState {
156 SysBusDevice parent_obj;
157
158 /* Hardware */
159 uint8_t it_shift;
160 bool big_endian;
161 bool last_rba_is_full;
162 qemu_irq irq;
163 #ifdef DEBUG_SONIC
164 int irq_level;
165 #endif
166 QEMUTimer *watchdog;
167 int64_t wt_last_update;
168 NICConf conf;
169 NICState *nic;
170 MemoryRegion mmio;
171 MemoryRegion prom;
172
173 /* Registers */
174 uint8_t cam[16][6];
175 uint16_t regs[0x40];
176
177 /* Temporaries */
178 uint8_t tx_buffer[0x10000];
179 uint16_t data[12];
180 int loopback_packet;
181
182 /* Memory access */
183 MemoryRegion *dma_mr;
184 AddressSpace as;
185 } dp8393xState;
186
187 /* Accessor functions for values which are formed by
188 * concatenating two 16 bit device registers. By putting these
189 * in their own functions with a uint32_t return type we avoid the
190 * pitfall of implicit sign extension where ((x << 16) | y) is a
191 * signed 32 bit integer that might get sign-extended to a 64 bit integer.
192 */
193 static uint32_t dp8393x_cdp(dp8393xState *s)
194 {
195 return (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_CDP];
196 }
197
198 static uint32_t dp8393x_crba(dp8393xState *s)
199 {
200 return (s->regs[SONIC_CRBA1] << 16) | s->regs[SONIC_CRBA0];
201 }
202
203 static uint32_t dp8393x_crda(dp8393xState *s)
204 {
205 return (s->regs[SONIC_URDA] << 16) |
206 (s->regs[SONIC_CRDA] & SONIC_DESC_ADDR);
207 }
208
209 static uint32_t dp8393x_rbwc(dp8393xState *s)
210 {
211 return (s->regs[SONIC_RBWC1] << 16) | s->regs[SONIC_RBWC0];
212 }
213
214 static uint32_t dp8393x_rrp(dp8393xState *s)
215 {
216 return (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_RRP];
217 }
218
219 static uint32_t dp8393x_tsa(dp8393xState *s)
220 {
221 return (s->regs[SONIC_TSA1] << 16) | s->regs[SONIC_TSA0];
222 }
223
224 static uint32_t dp8393x_ttda(dp8393xState *s)
225 {
226 return (s->regs[SONIC_UTDA] << 16) |
227 (s->regs[SONIC_TTDA] & SONIC_DESC_ADDR);
228 }
229
230 static uint32_t dp8393x_wt(dp8393xState *s)
231 {
232 return s->regs[SONIC_WT1] << 16 | s->regs[SONIC_WT0];
233 }
234
235 static uint16_t dp8393x_get(dp8393xState *s, int width, int offset)
236 {
237 uint16_t val;
238
239 if (s->big_endian) {
240 val = be16_to_cpu(s->data[offset * width + width - 1]);
241 } else {
242 val = le16_to_cpu(s->data[offset * width]);
243 }
244 return val;
245 }
246
247 static void dp8393x_put(dp8393xState *s, int width, int offset,
248 uint16_t val)
249 {
250 if (s->big_endian) {
251 if (width == 2) {
252 s->data[offset * 2] = 0;
253 s->data[offset * 2 + 1] = cpu_to_be16(val);
254 } else {
255 s->data[offset] = cpu_to_be16(val);
256 }
257 } else {
258 if (width == 2) {
259 s->data[offset * 2] = cpu_to_le16(val);
260 s->data[offset * 2 + 1] = 0;
261 } else {
262 s->data[offset] = cpu_to_le16(val);
263 }
264 }
265 }
266
267 static void dp8393x_update_irq(dp8393xState *s)
268 {
269 int level = (s->regs[SONIC_IMR] & s->regs[SONIC_ISR]) ? 1 : 0;
270
271 #ifdef DEBUG_SONIC
272 if (level != s->irq_level) {
273 s->irq_level = level;
274 if (level) {
275 DPRINTF("raise irq, isr is 0x%04x\n", s->regs[SONIC_ISR]);
276 } else {
277 DPRINTF("lower irq\n");
278 }
279 }
280 #endif
281
282 qemu_set_irq(s->irq, level);
283 }
284
285 static void dp8393x_do_load_cam(dp8393xState *s)
286 {
287 int width, size;
288 uint16_t index = 0;
289
290 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1;
291 size = sizeof(uint16_t) * 4 * width;
292
293 while (s->regs[SONIC_CDC] & 0x1f) {
294 /* Fill current entry */
295 address_space_read(&s->as, dp8393x_cdp(s),
296 MEMTXATTRS_UNSPECIFIED, s->data, size);
297 s->cam[index][0] = dp8393x_get(s, width, 1) & 0xff;
298 s->cam[index][1] = dp8393x_get(s, width, 1) >> 8;
299 s->cam[index][2] = dp8393x_get(s, width, 2) & 0xff;
300 s->cam[index][3] = dp8393x_get(s, width, 2) >> 8;
301 s->cam[index][4] = dp8393x_get(s, width, 3) & 0xff;
302 s->cam[index][5] = dp8393x_get(s, width, 3) >> 8;
303 DPRINTF("load cam[%d] with %02x%02x%02x%02x%02x%02x\n", index,
304 s->cam[index][0], s->cam[index][1], s->cam[index][2],
305 s->cam[index][3], s->cam[index][4], s->cam[index][5]);
306 /* Move to next entry */
307 s->regs[SONIC_CDC]--;
308 s->regs[SONIC_CDP] += size;
309 index++;
310 }
311
312 /* Read CAM enable */
313 address_space_read(&s->as, dp8393x_cdp(s),
314 MEMTXATTRS_UNSPECIFIED, s->data, size);
315 s->regs[SONIC_CE] = dp8393x_get(s, width, 0);
316 DPRINTF("load cam done. cam enable mask 0x%04x\n", s->regs[SONIC_CE]);
317
318 /* Done */
319 s->regs[SONIC_CR] &= ~SONIC_CR_LCAM;
320 s->regs[SONIC_ISR] |= SONIC_ISR_LCD;
321 dp8393x_update_irq(s);
322 }
323
324 static void dp8393x_do_read_rra(dp8393xState *s)
325 {
326 int width, size;
327
328 /* Read memory */
329 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1;
330 size = sizeof(uint16_t) * 4 * width;
331 address_space_read(&s->as, dp8393x_rrp(s),
332 MEMTXATTRS_UNSPECIFIED, s->data, size);
333
334 /* Update SONIC registers */
335 s->regs[SONIC_CRBA0] = dp8393x_get(s, width, 0);
336 s->regs[SONIC_CRBA1] = dp8393x_get(s, width, 1);
337 s->regs[SONIC_RBWC0] = dp8393x_get(s, width, 2);
338 s->regs[SONIC_RBWC1] = dp8393x_get(s, width, 3);
339 DPRINTF("CRBA0/1: 0x%04x/0x%04x, RBWC0/1: 0x%04x/0x%04x\n",
340 s->regs[SONIC_CRBA0], s->regs[SONIC_CRBA1],
341 s->regs[SONIC_RBWC0], s->regs[SONIC_RBWC1]);
342
343 /* Go to next entry */
344 s->regs[SONIC_RRP] += size;
345
346 /* Handle wrap */
347 if (s->regs[SONIC_RRP] == s->regs[SONIC_REA]) {
348 s->regs[SONIC_RRP] = s->regs[SONIC_RSA];
349 }
350
351 /* Warn the host if CRBA now has the last available resource */
352 if (s->regs[SONIC_RRP] == s->regs[SONIC_RWP])
353 {
354 s->regs[SONIC_ISR] |= SONIC_ISR_RBE;
355 dp8393x_update_irq(s);
356 }
357
358 /* Allow packet reception */
359 s->last_rba_is_full = false;
360 }
361
362 static void dp8393x_do_software_reset(dp8393xState *s)
363 {
364 timer_del(s->watchdog);
365
366 s->regs[SONIC_CR] &= ~(SONIC_CR_LCAM | SONIC_CR_RRRA | SONIC_CR_TXP | SONIC_CR_HTX);
367 s->regs[SONIC_CR] |= SONIC_CR_RST | SONIC_CR_RXDIS;
368 }
369
370 static void dp8393x_set_next_tick(dp8393xState *s)
371 {
372 uint32_t ticks;
373 int64_t delay;
374
375 if (s->regs[SONIC_CR] & SONIC_CR_STP) {
376 timer_del(s->watchdog);
377 return;
378 }
379
380 ticks = dp8393x_wt(s);
381 s->wt_last_update = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
382 delay = NANOSECONDS_PER_SECOND * ticks / 5000000;
383 timer_mod(s->watchdog, s->wt_last_update + delay);
384 }
385
386 static void dp8393x_update_wt_regs(dp8393xState *s)
387 {
388 int64_t elapsed;
389 uint32_t val;
390
391 if (s->regs[SONIC_CR] & SONIC_CR_STP) {
392 timer_del(s->watchdog);
393 return;
394 }
395
396 elapsed = s->wt_last_update - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
397 val = dp8393x_wt(s);
398 val -= elapsed / 5000000;
399 s->regs[SONIC_WT1] = (val >> 16) & 0xffff;
400 s->regs[SONIC_WT0] = (val >> 0) & 0xffff;
401 dp8393x_set_next_tick(s);
402
403 }
404
405 static void dp8393x_do_start_timer(dp8393xState *s)
406 {
407 s->regs[SONIC_CR] &= ~SONIC_CR_STP;
408 dp8393x_set_next_tick(s);
409 }
410
411 static void dp8393x_do_stop_timer(dp8393xState *s)
412 {
413 s->regs[SONIC_CR] &= ~SONIC_CR_ST;
414 dp8393x_update_wt_regs(s);
415 }
416
417 static int dp8393x_can_receive(NetClientState *nc);
418
419 static void dp8393x_do_receiver_enable(dp8393xState *s)
420 {
421 s->regs[SONIC_CR] &= ~SONIC_CR_RXDIS;
422 if (dp8393x_can_receive(s->nic->ncs)) {
423 qemu_flush_queued_packets(qemu_get_queue(s->nic));
424 }
425 }
426
427 static void dp8393x_do_receiver_disable(dp8393xState *s)
428 {
429 s->regs[SONIC_CR] &= ~SONIC_CR_RXEN;
430 }
431
432 static void dp8393x_do_transmit_packets(dp8393xState *s)
433 {
434 NetClientState *nc = qemu_get_queue(s->nic);
435 int width, size;
436 int tx_len, len;
437 uint16_t i;
438
439 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1;
440
441 while (1) {
442 /* Read memory */
443 size = sizeof(uint16_t) * 6 * width;
444 s->regs[SONIC_TTDA] = s->regs[SONIC_CTDA];
445 DPRINTF("Transmit packet at %08x\n", dp8393x_ttda(s));
446 address_space_read(&s->as, dp8393x_ttda(s) + sizeof(uint16_t) * width,
447 MEMTXATTRS_UNSPECIFIED, s->data, size);
448 tx_len = 0;
449
450 /* Update registers */
451 s->regs[SONIC_TCR] = dp8393x_get(s, width, 0) & 0xf000;
452 s->regs[SONIC_TPS] = dp8393x_get(s, width, 1);
453 s->regs[SONIC_TFC] = dp8393x_get(s, width, 2);
454 s->regs[SONIC_TSA0] = dp8393x_get(s, width, 3);
455 s->regs[SONIC_TSA1] = dp8393x_get(s, width, 4);
456 s->regs[SONIC_TFS] = dp8393x_get(s, width, 5);
457
458 /* Handle programmable interrupt */
459 if (s->regs[SONIC_TCR] & SONIC_TCR_PINT) {
460 s->regs[SONIC_ISR] |= SONIC_ISR_PINT;
461 } else {
462 s->regs[SONIC_ISR] &= ~SONIC_ISR_PINT;
463 }
464
465 for (i = 0; i < s->regs[SONIC_TFC]; ) {
466 /* Append fragment */
467 len = s->regs[SONIC_TFS];
468 if (tx_len + len > sizeof(s->tx_buffer)) {
469 len = sizeof(s->tx_buffer) - tx_len;
470 }
471 address_space_read(&s->as, dp8393x_tsa(s), MEMTXATTRS_UNSPECIFIED,
472 &s->tx_buffer[tx_len], len);
473 tx_len += len;
474
475 i++;
476 if (i != s->regs[SONIC_TFC]) {
477 /* Read next fragment details */
478 size = sizeof(uint16_t) * 3 * width;
479 address_space_read(&s->as,
480 dp8393x_ttda(s)
481 + sizeof(uint16_t) * width * (4 + 3 * i),
482 MEMTXATTRS_UNSPECIFIED, s->data,
483 size);
484 s->regs[SONIC_TSA0] = dp8393x_get(s, width, 0);
485 s->regs[SONIC_TSA1] = dp8393x_get(s, width, 1);
486 s->regs[SONIC_TFS] = dp8393x_get(s, width, 2);
487 }
488 }
489
490 /* Handle Ethernet checksum */
491 if (!(s->regs[SONIC_TCR] & SONIC_TCR_CRCI)) {
492 /* Don't append FCS there, to look like slirp packets
493 * which don't have one */
494 } else {
495 /* Remove existing FCS */
496 tx_len -= 4;
497 }
498
499 if (s->regs[SONIC_RCR] & (SONIC_RCR_LB1 | SONIC_RCR_LB0)) {
500 /* Loopback */
501 s->regs[SONIC_TCR] |= SONIC_TCR_CRSL;
502 if (nc->info->can_receive(nc)) {
503 s->loopback_packet = 1;
504 nc->info->receive(nc, s->tx_buffer, tx_len);
505 }
506 } else {
507 /* Transmit packet */
508 qemu_send_packet(nc, s->tx_buffer, tx_len);
509 }
510 s->regs[SONIC_TCR] |= SONIC_TCR_PTX;
511
512 /* Write status */
513 dp8393x_put(s, width, 0,
514 s->regs[SONIC_TCR] & 0x0fff); /* status */
515 size = sizeof(uint16_t) * width;
516 address_space_write(&s->as, dp8393x_ttda(s),
517 MEMTXATTRS_UNSPECIFIED, s->data, size);
518
519 if (!(s->regs[SONIC_CR] & SONIC_CR_HTX)) {
520 /* Read footer of packet */
521 size = sizeof(uint16_t) * width;
522 address_space_read(&s->as,
523 dp8393x_ttda(s)
524 + sizeof(uint16_t) * width
525 * (4 + 3 * s->regs[SONIC_TFC]),
526 MEMTXATTRS_UNSPECIFIED, s->data,
527 size);
528 s->regs[SONIC_CTDA] = dp8393x_get(s, width, 0);
529 if (s->regs[SONIC_CTDA] & SONIC_DESC_EOL) {
530 /* EOL detected */
531 break;
532 }
533 }
534 }
535
536 /* Done */
537 s->regs[SONIC_CR] &= ~SONIC_CR_TXP;
538 s->regs[SONIC_ISR] |= SONIC_ISR_TXDN;
539 dp8393x_update_irq(s);
540 }
541
542 static void dp8393x_do_halt_transmission(dp8393xState *s)
543 {
544 /* Nothing to do */
545 }
546
547 static void dp8393x_do_command(dp8393xState *s, uint16_t command)
548 {
549 if ((s->regs[SONIC_CR] & SONIC_CR_RST) && !(command & SONIC_CR_RST)) {
550 s->regs[SONIC_CR] &= ~SONIC_CR_RST;
551 return;
552 }
553
554 s->regs[SONIC_CR] |= (command & SONIC_CR_MASK);
555
556 if (command & SONIC_CR_HTX)
557 dp8393x_do_halt_transmission(s);
558 if (command & SONIC_CR_TXP)
559 dp8393x_do_transmit_packets(s);
560 if (command & SONIC_CR_RXDIS)
561 dp8393x_do_receiver_disable(s);
562 if (command & SONIC_CR_RXEN)
563 dp8393x_do_receiver_enable(s);
564 if (command & SONIC_CR_STP)
565 dp8393x_do_stop_timer(s);
566 if (command & SONIC_CR_ST)
567 dp8393x_do_start_timer(s);
568 if (command & SONIC_CR_RST)
569 dp8393x_do_software_reset(s);
570 if (command & SONIC_CR_RRRA) {
571 dp8393x_do_read_rra(s);
572 s->regs[SONIC_CR] &= ~SONIC_CR_RRRA;
573 }
574 if (command & SONIC_CR_LCAM)
575 dp8393x_do_load_cam(s);
576 }
577
578 static uint64_t dp8393x_read(void *opaque, hwaddr addr, unsigned int size)
579 {
580 dp8393xState *s = opaque;
581 int reg = addr >> s->it_shift;
582 uint16_t val = 0;
583
584 switch (reg) {
585 /* Update data before reading it */
586 case SONIC_WT0:
587 case SONIC_WT1:
588 dp8393x_update_wt_regs(s);
589 val = s->regs[reg];
590 break;
591 /* Accept read to some registers only when in reset mode */
592 case SONIC_CAP2:
593 case SONIC_CAP1:
594 case SONIC_CAP0:
595 if (s->regs[SONIC_CR] & SONIC_CR_RST) {
596 val = s->cam[s->regs[SONIC_CEP] & 0xf][2* (SONIC_CAP0 - reg) + 1] << 8;
597 val |= s->cam[s->regs[SONIC_CEP] & 0xf][2* (SONIC_CAP0 - reg)];
598 }
599 break;
600 /* All other registers have no special contrainst */
601 default:
602 val = s->regs[reg];
603 }
604
605 DPRINTF("read 0x%04x from reg %s\n", val, reg_names[reg]);
606
607 return s->big_endian ? val << 16 : val;
608 }
609
610 static void dp8393x_write(void *opaque, hwaddr addr, uint64_t data,
611 unsigned int size)
612 {
613 dp8393xState *s = opaque;
614 int reg = addr >> s->it_shift;
615 uint32_t val = s->big_endian ? data >> 16 : data;
616
617 DPRINTF("write 0x%04x to reg %s\n", (uint16_t)val, reg_names[reg]);
618
619 switch (reg) {
620 /* Command register */
621 case SONIC_CR:
622 dp8393x_do_command(s, val);
623 break;
624 /* Prevent write to read-only registers */
625 case SONIC_CAP2:
626 case SONIC_CAP1:
627 case SONIC_CAP0:
628 case SONIC_SR:
629 case SONIC_MDT:
630 DPRINTF("writing to reg %d invalid\n", reg);
631 break;
632 /* Accept write to some registers only when in reset mode */
633 case SONIC_DCR:
634 if (s->regs[SONIC_CR] & SONIC_CR_RST) {
635 s->regs[reg] = val & 0xbfff;
636 } else {
637 DPRINTF("writing to DCR invalid\n");
638 }
639 break;
640 case SONIC_DCR2:
641 if (s->regs[SONIC_CR] & SONIC_CR_RST) {
642 s->regs[reg] = val & 0xf017;
643 } else {
644 DPRINTF("writing to DCR2 invalid\n");
645 }
646 break;
647 /* 12 lower bytes are Read Only */
648 case SONIC_TCR:
649 s->regs[reg] = val & 0xf000;
650 break;
651 /* 9 lower bytes are Read Only */
652 case SONIC_RCR:
653 s->regs[reg] = val & 0xffe0;
654 break;
655 /* Ignore most significant bit */
656 case SONIC_IMR:
657 s->regs[reg] = val & 0x7fff;
658 dp8393x_update_irq(s);
659 break;
660 /* Clear bits by writing 1 to them */
661 case SONIC_ISR:
662 val &= s->regs[reg];
663 s->regs[reg] &= ~val;
664 if (val & SONIC_ISR_RBE) {
665 dp8393x_do_read_rra(s);
666 }
667 dp8393x_update_irq(s);
668 break;
669 /* The guest is required to store aligned pointers here */
670 case SONIC_RSA:
671 case SONIC_REA:
672 case SONIC_RRP:
673 case SONIC_RWP:
674 if (s->regs[SONIC_DCR] & SONIC_DCR_DW) {
675 s->regs[reg] = val & 0xfffc;
676 } else {
677 s->regs[reg] = val & 0xfffe;
678 }
679 break;
680 /* Invert written value for some registers */
681 case SONIC_CRCT:
682 case SONIC_FAET:
683 case SONIC_MPT:
684 s->regs[reg] = val ^ 0xffff;
685 break;
686 /* All other registers have no special contrainst */
687 default:
688 s->regs[reg] = val;
689 }
690
691 if (reg == SONIC_WT0 || reg == SONIC_WT1) {
692 dp8393x_set_next_tick(s);
693 }
694 }
695
696 static const MemoryRegionOps dp8393x_ops = {
697 .read = dp8393x_read,
698 .write = dp8393x_write,
699 .impl.min_access_size = 4,
700 .impl.max_access_size = 4,
701 .endianness = DEVICE_NATIVE_ENDIAN,
702 };
703
704 static void dp8393x_watchdog(void *opaque)
705 {
706 dp8393xState *s = opaque;
707
708 if (s->regs[SONIC_CR] & SONIC_CR_STP) {
709 return;
710 }
711
712 s->regs[SONIC_WT1] = 0xffff;
713 s->regs[SONIC_WT0] = 0xffff;
714 dp8393x_set_next_tick(s);
715
716 /* Signal underflow */
717 s->regs[SONIC_ISR] |= SONIC_ISR_TC;
718 dp8393x_update_irq(s);
719 }
720
721 static int dp8393x_can_receive(NetClientState *nc)
722 {
723 dp8393xState *s = qemu_get_nic_opaque(nc);
724
725 if (!(s->regs[SONIC_CR] & SONIC_CR_RXEN))
726 return 0;
727 return 1;
728 }
729
730 static int dp8393x_receive_filter(dp8393xState *s, const uint8_t * buf,
731 int size)
732 {
733 static const uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
734 int i;
735
736 /* Check promiscuous mode */
737 if ((s->regs[SONIC_RCR] & SONIC_RCR_PRO) && (buf[0] & 1) == 0) {
738 return 0;
739 }
740
741 /* Check multicast packets */
742 if ((s->regs[SONIC_RCR] & SONIC_RCR_AMC) && (buf[0] & 1) == 1) {
743 return SONIC_RCR_MC;
744 }
745
746 /* Check broadcast */
747 if ((s->regs[SONIC_RCR] & SONIC_RCR_BRD) && !memcmp(buf, bcast, sizeof(bcast))) {
748 return SONIC_RCR_BC;
749 }
750
751 /* Check CAM */
752 for (i = 0; i < 16; i++) {
753 if (s->regs[SONIC_CE] & (1 << i)) {
754 /* Entry enabled */
755 if (!memcmp(buf, s->cam[i], sizeof(s->cam[i]))) {
756 return 0;
757 }
758 }
759 }
760
761 return -1;
762 }
763
764 static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
765 size_t pkt_size)
766 {
767 dp8393xState *s = qemu_get_nic_opaque(nc);
768 int packet_type;
769 uint32_t available, address;
770 int width, rx_len, padded_len;
771 uint32_t checksum;
772 int size;
773
774 s->regs[SONIC_RCR] &= ~(SONIC_RCR_PRX | SONIC_RCR_LBK | SONIC_RCR_FAER |
775 SONIC_RCR_CRCR | SONIC_RCR_LPKT | SONIC_RCR_BC | SONIC_RCR_MC);
776
777 if (s->last_rba_is_full) {
778 return pkt_size;
779 }
780
781 rx_len = pkt_size + sizeof(checksum);
782 if (s->regs[SONIC_DCR] & SONIC_DCR_DW) {
783 width = 2;
784 padded_len = ((rx_len - 1) | 3) + 1;
785 } else {
786 width = 1;
787 padded_len = ((rx_len - 1) | 1) + 1;
788 }
789
790 if (padded_len > dp8393x_rbwc(s) * 2) {
791 DPRINTF("oversize packet, pkt_size is %d\n", pkt_size);
792 s->regs[SONIC_ISR] |= SONIC_ISR_RBAE;
793 dp8393x_update_irq(s);
794 s->regs[SONIC_RCR] |= SONIC_RCR_LPKT;
795 goto done;
796 }
797
798 packet_type = dp8393x_receive_filter(s, buf, pkt_size);
799 if (packet_type < 0) {
800 DPRINTF("packet not for netcard\n");
801 return -1;
802 }
803
804 /* Check for EOL */
805 if (s->regs[SONIC_LLFA] & SONIC_DESC_EOL) {
806 /* Are we still in resource exhaustion? */
807 size = sizeof(uint16_t) * 1 * width;
808 address = dp8393x_crda(s) + sizeof(uint16_t) * 5 * width;
809 address_space_read(&s->as, address, MEMTXATTRS_UNSPECIFIED,
810 s->data, size);
811 s->regs[SONIC_LLFA] = dp8393x_get(s, width, 0);
812 if (s->regs[SONIC_LLFA] & SONIC_DESC_EOL) {
813 /* Still EOL ; stop reception */
814 return -1;
815 }
816 /* Link has been updated by host */
817
818 /* Clear in_use */
819 size = sizeof(uint16_t) * width;
820 address = dp8393x_crda(s) + sizeof(uint16_t) * 6 * width;
821 dp8393x_put(s, width, 0, 0);
822 address_space_rw(&s->as, address, MEMTXATTRS_UNSPECIFIED,
823 (uint8_t *)s->data, size, 1);
824
825 /* Move to next descriptor */
826 s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA];
827 s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX;
828 }
829
830 /* Save current position */
831 s->regs[SONIC_TRBA1] = s->regs[SONIC_CRBA1];
832 s->regs[SONIC_TRBA0] = s->regs[SONIC_CRBA0];
833
834 /* Calculate the ethernet checksum */
835 checksum = cpu_to_le32(crc32(0, buf, pkt_size));
836
837 /* Put packet into RBA */
838 DPRINTF("Receive packet at %08x\n", dp8393x_crba(s));
839 address = dp8393x_crba(s);
840 address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED,
841 buf, pkt_size);
842 address += pkt_size;
843
844 /* Put frame checksum into RBA */
845 address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED,
846 &checksum, sizeof(checksum));
847 address += sizeof(checksum);
848
849 /* Pad short packets to keep pointers aligned */
850 if (rx_len < padded_len) {
851 size = padded_len - rx_len;
852 address_space_rw(&s->as, address, MEMTXATTRS_UNSPECIFIED,
853 (uint8_t *)"\xFF\xFF\xFF", size, 1);
854 address += size;
855 }
856
857 s->regs[SONIC_CRBA1] = address >> 16;
858 s->regs[SONIC_CRBA0] = address & 0xffff;
859 available = dp8393x_rbwc(s);
860 available -= padded_len >> 1;
861 s->regs[SONIC_RBWC1] = available >> 16;
862 s->regs[SONIC_RBWC0] = available & 0xffff;
863
864 /* Update status */
865 if (dp8393x_rbwc(s) < s->regs[SONIC_EOBC]) {
866 s->regs[SONIC_RCR] |= SONIC_RCR_LPKT;
867 }
868 s->regs[SONIC_RCR] |= packet_type;
869 s->regs[SONIC_RCR] |= SONIC_RCR_PRX;
870 if (s->loopback_packet) {
871 s->regs[SONIC_RCR] |= SONIC_RCR_LBK;
872 s->loopback_packet = 0;
873 }
874
875 /* Write status to memory */
876 DPRINTF("Write status at %08x\n", dp8393x_crda(s));
877 dp8393x_put(s, width, 0, s->regs[SONIC_RCR]); /* status */
878 dp8393x_put(s, width, 1, rx_len); /* byte count */
879 dp8393x_put(s, width, 2, s->regs[SONIC_TRBA0]); /* pkt_ptr0 */
880 dp8393x_put(s, width, 3, s->regs[SONIC_TRBA1]); /* pkt_ptr1 */
881 dp8393x_put(s, width, 4, s->regs[SONIC_RSC]); /* seq_no */
882 size = sizeof(uint16_t) * 5 * width;
883 address_space_write(&s->as, dp8393x_crda(s),
884 MEMTXATTRS_UNSPECIFIED,
885 s->data, size);
886
887 /* Check link field */
888 size = sizeof(uint16_t) * width;
889 address_space_read(&s->as,
890 dp8393x_crda(s) + sizeof(uint16_t) * 5 * width,
891 MEMTXATTRS_UNSPECIFIED, s->data, size);
892 s->regs[SONIC_LLFA] = dp8393x_get(s, width, 0);
893 if (s->regs[SONIC_LLFA] & SONIC_DESC_EOL) {
894 /* EOL detected */
895 s->regs[SONIC_ISR] |= SONIC_ISR_RDE;
896 } else {
897 /* Clear in_use */
898 size = sizeof(uint16_t) * width;
899 address = dp8393x_crda(s) + sizeof(uint16_t) * 6 * width;
900 dp8393x_put(s, width, 0, 0);
901 address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED,
902 s->data, size);
903
904 /* Move to next descriptor */
905 s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA];
906 s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX;
907 }
908
909 dp8393x_update_irq(s);
910
911 s->regs[SONIC_RSC] = (s->regs[SONIC_RSC] & 0xff00) |
912 ((s->regs[SONIC_RSC] + 1) & 0x00ff);
913
914 done:
915
916 if (s->regs[SONIC_RCR] & SONIC_RCR_LPKT) {
917 if (s->regs[SONIC_RRP] == s->regs[SONIC_RWP]) {
918 /* Stop packet reception */
919 s->last_rba_is_full = true;
920 } else {
921 /* Read next resource */
922 dp8393x_do_read_rra(s);
923 }
924 }
925
926 return pkt_size;
927 }
928
929 static void dp8393x_reset(DeviceState *dev)
930 {
931 dp8393xState *s = DP8393X(dev);
932 timer_del(s->watchdog);
933
934 memset(s->regs, 0, sizeof(s->regs));
935 s->regs[SONIC_SR] = 0x0004; /* only revision recognized by Linux/mips */
936 s->regs[SONIC_CR] = SONIC_CR_RST | SONIC_CR_STP | SONIC_CR_RXDIS;
937 s->regs[SONIC_DCR] &= ~(SONIC_DCR_EXBUS | SONIC_DCR_LBR);
938 s->regs[SONIC_RCR] &= ~(SONIC_RCR_LB0 | SONIC_RCR_LB1 | SONIC_RCR_BRD | SONIC_RCR_RNT);
939 s->regs[SONIC_TCR] |= SONIC_TCR_NCRS | SONIC_TCR_PTX;
940 s->regs[SONIC_TCR] &= ~SONIC_TCR_BCM;
941 s->regs[SONIC_IMR] = 0;
942 s->regs[SONIC_ISR] = 0;
943 s->regs[SONIC_DCR2] = 0;
944 s->regs[SONIC_EOBC] = 0x02F8;
945 s->regs[SONIC_RSC] = 0;
946 s->regs[SONIC_CE] = 0;
947 s->regs[SONIC_RSC] = 0;
948
949 /* Network cable is connected */
950 s->regs[SONIC_RCR] |= SONIC_RCR_CRS;
951
952 dp8393x_update_irq(s);
953 }
954
955 static NetClientInfo net_dp83932_info = {
956 .type = NET_CLIENT_DRIVER_NIC,
957 .size = sizeof(NICState),
958 .can_receive = dp8393x_can_receive,
959 .receive = dp8393x_receive,
960 };
961
962 static void dp8393x_instance_init(Object *obj)
963 {
964 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
965 dp8393xState *s = DP8393X(obj);
966
967 sysbus_init_mmio(sbd, &s->mmio);
968 sysbus_init_mmio(sbd, &s->prom);
969 sysbus_init_irq(sbd, &s->irq);
970 }
971
972 static void dp8393x_realize(DeviceState *dev, Error **errp)
973 {
974 dp8393xState *s = DP8393X(dev);
975 int i, checksum;
976 uint8_t *prom;
977 Error *local_err = NULL;
978
979 address_space_init(&s->as, s->dma_mr, "dp8393x");
980 memory_region_init_io(&s->mmio, OBJECT(dev), &dp8393x_ops, s,
981 "dp8393x-regs", 0x40 << s->it_shift);
982
983 s->nic = qemu_new_nic(&net_dp83932_info, &s->conf,
984 object_get_typename(OBJECT(dev)), dev->id, s);
985 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
986
987 s->watchdog = timer_new_ns(QEMU_CLOCK_VIRTUAL, dp8393x_watchdog, s);
988
989 memory_region_init_rom(&s->prom, OBJECT(dev), "dp8393x-prom",
990 SONIC_PROM_SIZE, &local_err);
991 if (local_err) {
992 error_propagate(errp, local_err);
993 return;
994 }
995 prom = memory_region_get_ram_ptr(&s->prom);
996 checksum = 0;
997 for (i = 0; i < 6; i++) {
998 prom[i] = s->conf.macaddr.a[i];
999 checksum += prom[i];
1000 if (checksum > 0xff) {
1001 checksum = (checksum + 1) & 0xff;
1002 }
1003 }
1004 prom[7] = 0xff - checksum;
1005 }
1006
1007 static const VMStateDescription vmstate_dp8393x = {
1008 .name = "dp8393x",
1009 .version_id = 0,
1010 .minimum_version_id = 0,
1011 .fields = (VMStateField []) {
1012 VMSTATE_BUFFER_UNSAFE(cam, dp8393xState, 0, 16 * 6),
1013 VMSTATE_UINT16_ARRAY(regs, dp8393xState, 0x40),
1014 VMSTATE_END_OF_LIST()
1015 }
1016 };
1017
1018 static Property dp8393x_properties[] = {
1019 DEFINE_NIC_PROPERTIES(dp8393xState, conf),
1020 DEFINE_PROP_LINK("dma_mr", dp8393xState, dma_mr,
1021 TYPE_MEMORY_REGION, MemoryRegion *),
1022 DEFINE_PROP_UINT8("it_shift", dp8393xState, it_shift, 0),
1023 DEFINE_PROP_BOOL("big_endian", dp8393xState, big_endian, false),
1024 DEFINE_PROP_END_OF_LIST(),
1025 };
1026
1027 static void dp8393x_class_init(ObjectClass *klass, void *data)
1028 {
1029 DeviceClass *dc = DEVICE_CLASS(klass);
1030
1031 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
1032 dc->realize = dp8393x_realize;
1033 dc->reset = dp8393x_reset;
1034 dc->vmsd = &vmstate_dp8393x;
1035 device_class_set_props(dc, dp8393x_properties);
1036 }
1037
1038 static const TypeInfo dp8393x_info = {
1039 .name = TYPE_DP8393X,
1040 .parent = TYPE_SYS_BUS_DEVICE,
1041 .instance_size = sizeof(dp8393xState),
1042 .instance_init = dp8393x_instance_init,
1043 .class_init = dp8393x_class_init,
1044 };
1045
1046 static void dp8393x_register_types(void)
1047 {
1048 type_register_static(&dp8393x_info);
1049 }
1050
1051 type_init(dp8393x_register_types)
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