2 * QEMU NS SONIC DP8393x netcard
4 * Copyright (c) 2008-2009 Herve Poussineau
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/timer.h"
23 #include "hw/mips/mips.h"
27 /* Calculate CRCs properly on Rx packets */
28 #define SONIC_CALCULATE_RXCRC
30 #if defined(SONIC_CALCULATE_RXCRC)
36 #define DPRINTF(fmt, ...) \
37 do { printf("sonic: " fmt , ## __VA_ARGS__); } while (0)
38 static const char* reg_names
[] = {
39 "CR", "DCR", "RCR", "TCR", "IMR", "ISR", "UTDA", "CTDA",
40 "TPS", "TFC", "TSA0", "TSA1", "TFS", "URDA", "CRDA", "CRBA0",
41 "CRBA1", "RBWC0", "RBWC1", "EOBC", "URRA", "RSA", "REA", "RRP",
42 "RWP", "TRBA0", "TRBA1", "0x1b", "0x1c", "0x1d", "0x1e", "LLFA",
43 "TTDA", "CEP", "CAP2", "CAP1", "CAP0", "CE", "CDP", "CDC",
44 "SR", "WT0", "WT1", "RSC", "CRCT", "FAET", "MPT", "MDT",
45 "0x30", "0x31", "0x32", "0x33", "0x34", "0x35", "0x36", "0x37",
46 "0x38", "0x39", "0x3a", "0x3b", "0x3c", "0x3d", "0x3e", "DCR2" };
48 #define DPRINTF(fmt, ...) do {} while (0)
51 #define SONIC_ERROR(fmt, ...) \
52 do { printf("sonic ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
55 #define SONIC_DCR 0x01
56 #define SONIC_RCR 0x02
57 #define SONIC_TCR 0x03
58 #define SONIC_IMR 0x04
59 #define SONIC_ISR 0x05
60 #define SONIC_UTDA 0x06
61 #define SONIC_CTDA 0x07
62 #define SONIC_TPS 0x08
63 #define SONIC_TFC 0x09
64 #define SONIC_TSA0 0x0a
65 #define SONIC_TSA1 0x0b
66 #define SONIC_TFS 0x0c
67 #define SONIC_URDA 0x0d
68 #define SONIC_CRDA 0x0e
69 #define SONIC_CRBA0 0x0f
70 #define SONIC_CRBA1 0x10
71 #define SONIC_RBWC0 0x11
72 #define SONIC_RBWC1 0x12
73 #define SONIC_EOBC 0x13
74 #define SONIC_URRA 0x14
75 #define SONIC_RSA 0x15
76 #define SONIC_REA 0x16
77 #define SONIC_RRP 0x17
78 #define SONIC_RWP 0x18
79 #define SONIC_TRBA0 0x19
80 #define SONIC_TRBA1 0x1a
81 #define SONIC_LLFA 0x1f
82 #define SONIC_TTDA 0x20
83 #define SONIC_CEP 0x21
84 #define SONIC_CAP2 0x22
85 #define SONIC_CAP1 0x23
86 #define SONIC_CAP0 0x24
88 #define SONIC_CDP 0x26
89 #define SONIC_CDC 0x27
91 #define SONIC_WT0 0x29
92 #define SONIC_WT1 0x2a
93 #define SONIC_RSC 0x2b
94 #define SONIC_CRCT 0x2c
95 #define SONIC_FAET 0x2d
96 #define SONIC_MPT 0x2e
97 #define SONIC_MDT 0x2f
98 #define SONIC_DCR2 0x3f
100 #define SONIC_CR_HTX 0x0001
101 #define SONIC_CR_TXP 0x0002
102 #define SONIC_CR_RXDIS 0x0004
103 #define SONIC_CR_RXEN 0x0008
104 #define SONIC_CR_STP 0x0010
105 #define SONIC_CR_ST 0x0020
106 #define SONIC_CR_RST 0x0080
107 #define SONIC_CR_RRRA 0x0100
108 #define SONIC_CR_LCAM 0x0200
109 #define SONIC_CR_MASK 0x03bf
111 #define SONIC_DCR_DW 0x0020
112 #define SONIC_DCR_LBR 0x2000
113 #define SONIC_DCR_EXBUS 0x8000
115 #define SONIC_RCR_PRX 0x0001
116 #define SONIC_RCR_LBK 0x0002
117 #define SONIC_RCR_FAER 0x0004
118 #define SONIC_RCR_CRCR 0x0008
119 #define SONIC_RCR_CRS 0x0020
120 #define SONIC_RCR_LPKT 0x0040
121 #define SONIC_RCR_BC 0x0080
122 #define SONIC_RCR_MC 0x0100
123 #define SONIC_RCR_LB0 0x0200
124 #define SONIC_RCR_LB1 0x0400
125 #define SONIC_RCR_AMC 0x0800
126 #define SONIC_RCR_PRO 0x1000
127 #define SONIC_RCR_BRD 0x2000
128 #define SONIC_RCR_RNT 0x4000
130 #define SONIC_TCR_PTX 0x0001
131 #define SONIC_TCR_BCM 0x0002
132 #define SONIC_TCR_FU 0x0004
133 #define SONIC_TCR_EXC 0x0040
134 #define SONIC_TCR_CRSL 0x0080
135 #define SONIC_TCR_NCRS 0x0100
136 #define SONIC_TCR_EXD 0x0400
137 #define SONIC_TCR_CRCI 0x2000
138 #define SONIC_TCR_PINT 0x8000
140 #define SONIC_ISR_RBE 0x0020
141 #define SONIC_ISR_RDE 0x0040
142 #define SONIC_ISR_TC 0x0080
143 #define SONIC_ISR_TXDN 0x0200
144 #define SONIC_ISR_PKTRX 0x0400
145 #define SONIC_ISR_PINT 0x0800
146 #define SONIC_ISR_LCD 0x1000
148 typedef struct dp8393xState
{
156 int64_t wt_last_update
;
159 MemoryRegion
*address_space
;
167 uint8_t tx_buffer
[0x10000];
174 static void dp8393x_update_irq(dp8393xState
*s
)
176 int level
= (s
->regs
[SONIC_IMR
] & s
->regs
[SONIC_ISR
]) ? 1 : 0;
179 if (level
!= s
->irq_level
) {
180 s
->irq_level
= level
;
182 DPRINTF("raise irq, isr is 0x%04x\n", s
->regs
[SONIC_ISR
]);
184 DPRINTF("lower irq\n");
189 qemu_set_irq(s
->irq
, level
);
192 static void do_load_cam(dp8393xState
*s
)
198 width
= (s
->regs
[SONIC_DCR
] & SONIC_DCR_DW
) ? 2 : 1;
199 size
= sizeof(uint16_t) * 4 * width
;
201 while (s
->regs
[SONIC_CDC
] & 0x1f) {
202 /* Fill current entry */
203 address_space_rw(&s
->as
,
204 (s
->regs
[SONIC_URRA
] << 16) | s
->regs
[SONIC_CDP
],
205 MEMTXATTRS_UNSPECIFIED
, (uint8_t *)data
, size
, 0);
206 s
->cam
[index
][0] = data
[1 * width
] & 0xff;
207 s
->cam
[index
][1] = data
[1 * width
] >> 8;
208 s
->cam
[index
][2] = data
[2 * width
] & 0xff;
209 s
->cam
[index
][3] = data
[2 * width
] >> 8;
210 s
->cam
[index
][4] = data
[3 * width
] & 0xff;
211 s
->cam
[index
][5] = data
[3 * width
] >> 8;
212 DPRINTF("load cam[%d] with %02x%02x%02x%02x%02x%02x\n", index
,
213 s
->cam
[index
][0], s
->cam
[index
][1], s
->cam
[index
][2],
214 s
->cam
[index
][3], s
->cam
[index
][4], s
->cam
[index
][5]);
215 /* Move to next entry */
216 s
->regs
[SONIC_CDC
]--;
217 s
->regs
[SONIC_CDP
] += size
;
221 /* Read CAM enable */
222 address_space_rw(&s
->as
,
223 (s
->regs
[SONIC_URRA
] << 16) | s
->regs
[SONIC_CDP
],
224 MEMTXATTRS_UNSPECIFIED
, (uint8_t *)data
, size
, 0);
225 s
->regs
[SONIC_CE
] = data
[0 * width
];
226 DPRINTF("load cam done. cam enable mask 0x%04x\n", s
->regs
[SONIC_CE
]);
229 s
->regs
[SONIC_CR
] &= ~SONIC_CR_LCAM
;
230 s
->regs
[SONIC_ISR
] |= SONIC_ISR_LCD
;
231 dp8393x_update_irq(s
);
234 static void do_read_rra(dp8393xState
*s
)
240 width
= (s
->regs
[SONIC_DCR
] & SONIC_DCR_DW
) ? 2 : 1;
241 size
= sizeof(uint16_t) * 4 * width
;
242 address_space_rw(&s
->as
,
243 (s
->regs
[SONIC_URRA
] << 16) | s
->regs
[SONIC_RRP
],
244 MEMTXATTRS_UNSPECIFIED
, (uint8_t *)data
, size
, 0);
246 /* Update SONIC registers */
247 s
->regs
[SONIC_CRBA0
] = data
[0 * width
];
248 s
->regs
[SONIC_CRBA1
] = data
[1 * width
];
249 s
->regs
[SONIC_RBWC0
] = data
[2 * width
];
250 s
->regs
[SONIC_RBWC1
] = data
[3 * width
];
251 DPRINTF("CRBA0/1: 0x%04x/0x%04x, RBWC0/1: 0x%04x/0x%04x\n",
252 s
->regs
[SONIC_CRBA0
], s
->regs
[SONIC_CRBA1
],
253 s
->regs
[SONIC_RBWC0
], s
->regs
[SONIC_RBWC1
]);
255 /* Go to next entry */
256 s
->regs
[SONIC_RRP
] += size
;
259 if (s
->regs
[SONIC_RRP
] == s
->regs
[SONIC_REA
]) {
260 s
->regs
[SONIC_RRP
] = s
->regs
[SONIC_RSA
];
263 /* Check resource exhaustion */
264 if (s
->regs
[SONIC_RRP
] == s
->regs
[SONIC_RWP
])
266 s
->regs
[SONIC_ISR
] |= SONIC_ISR_RBE
;
267 dp8393x_update_irq(s
);
271 s
->regs
[SONIC_CR
] &= ~SONIC_CR_RRRA
;
274 static void do_software_reset(dp8393xState
*s
)
276 timer_del(s
->watchdog
);
278 s
->regs
[SONIC_CR
] &= ~(SONIC_CR_LCAM
| SONIC_CR_RRRA
| SONIC_CR_TXP
| SONIC_CR_HTX
);
279 s
->regs
[SONIC_CR
] |= SONIC_CR_RST
| SONIC_CR_RXDIS
;
282 static void set_next_tick(dp8393xState
*s
)
287 if (s
->regs
[SONIC_CR
] & SONIC_CR_STP
) {
288 timer_del(s
->watchdog
);
292 ticks
= s
->regs
[SONIC_WT1
] << 16 | s
->regs
[SONIC_WT0
];
293 s
->wt_last_update
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
294 delay
= get_ticks_per_sec() * ticks
/ 5000000;
295 timer_mod(s
->watchdog
, s
->wt_last_update
+ delay
);
298 static void update_wt_regs(dp8393xState
*s
)
303 if (s
->regs
[SONIC_CR
] & SONIC_CR_STP
) {
304 timer_del(s
->watchdog
);
308 elapsed
= s
->wt_last_update
- qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
309 val
= s
->regs
[SONIC_WT1
] << 16 | s
->regs
[SONIC_WT0
];
310 val
-= elapsed
/ 5000000;
311 s
->regs
[SONIC_WT1
] = (val
>> 16) & 0xffff;
312 s
->regs
[SONIC_WT0
] = (val
>> 0) & 0xffff;
317 static void do_start_timer(dp8393xState
*s
)
319 s
->regs
[SONIC_CR
] &= ~SONIC_CR_STP
;
323 static void do_stop_timer(dp8393xState
*s
)
325 s
->regs
[SONIC_CR
] &= ~SONIC_CR_ST
;
329 static void do_receiver_enable(dp8393xState
*s
)
331 s
->regs
[SONIC_CR
] &= ~SONIC_CR_RXDIS
;
334 static void do_receiver_disable(dp8393xState
*s
)
336 s
->regs
[SONIC_CR
] &= ~SONIC_CR_RXEN
;
339 static void do_transmit_packets(dp8393xState
*s
)
341 NetClientState
*nc
= qemu_get_queue(s
->nic
);
347 width
= (s
->regs
[SONIC_DCR
] & SONIC_DCR_DW
) ? 2 : 1;
351 DPRINTF("Transmit packet at %08x\n",
352 (s
->regs
[SONIC_UTDA
] << 16) | s
->regs
[SONIC_CTDA
]);
353 size
= sizeof(uint16_t) * 6 * width
;
354 s
->regs
[SONIC_TTDA
] = s
->regs
[SONIC_CTDA
];
355 address_space_rw(&s
->as
,
356 ((s
->regs
[SONIC_UTDA
] << 16) | s
->regs
[SONIC_TTDA
]) + sizeof(uint16_t) * width
,
357 MEMTXATTRS_UNSPECIFIED
, (uint8_t *)data
, size
, 0);
360 /* Update registers */
361 s
->regs
[SONIC_TCR
] = data
[0 * width
] & 0xf000;
362 s
->regs
[SONIC_TPS
] = data
[1 * width
];
363 s
->regs
[SONIC_TFC
] = data
[2 * width
];
364 s
->regs
[SONIC_TSA0
] = data
[3 * width
];
365 s
->regs
[SONIC_TSA1
] = data
[4 * width
];
366 s
->regs
[SONIC_TFS
] = data
[5 * width
];
368 /* Handle programmable interrupt */
369 if (s
->regs
[SONIC_TCR
] & SONIC_TCR_PINT
) {
370 s
->regs
[SONIC_ISR
] |= SONIC_ISR_PINT
;
372 s
->regs
[SONIC_ISR
] &= ~SONIC_ISR_PINT
;
375 for (i
= 0; i
< s
->regs
[SONIC_TFC
]; ) {
376 /* Append fragment */
377 len
= s
->regs
[SONIC_TFS
];
378 if (tx_len
+ len
> sizeof(s
->tx_buffer
)) {
379 len
= sizeof(s
->tx_buffer
) - tx_len
;
381 address_space_rw(&s
->as
,
382 (s
->regs
[SONIC_TSA1
] << 16) | s
->regs
[SONIC_TSA0
],
383 MEMTXATTRS_UNSPECIFIED
, &s
->tx_buffer
[tx_len
], len
, 0);
387 if (i
!= s
->regs
[SONIC_TFC
]) {
388 /* Read next fragment details */
389 size
= sizeof(uint16_t) * 3 * width
;
390 address_space_rw(&s
->as
,
391 ((s
->regs
[SONIC_UTDA
] << 16) | s
->regs
[SONIC_TTDA
]) + sizeof(uint16_t) * (4 + 3 * i
) * width
,
392 MEMTXATTRS_UNSPECIFIED
, (uint8_t *)data
, size
, 0);
393 s
->regs
[SONIC_TSA0
] = data
[0 * width
];
394 s
->regs
[SONIC_TSA1
] = data
[1 * width
];
395 s
->regs
[SONIC_TFS
] = data
[2 * width
];
399 /* Handle Ethernet checksum */
400 if (!(s
->regs
[SONIC_TCR
] & SONIC_TCR_CRCI
)) {
401 /* Don't append FCS there, to look like slirp packets
402 * which don't have one */
404 /* Remove existing FCS */
408 if (s
->regs
[SONIC_RCR
] & (SONIC_RCR_LB1
| SONIC_RCR_LB0
)) {
410 s
->regs
[SONIC_TCR
] |= SONIC_TCR_CRSL
;
411 if (nc
->info
->can_receive(nc
)) {
412 s
->loopback_packet
= 1;
413 nc
->info
->receive(nc
, s
->tx_buffer
, tx_len
);
416 /* Transmit packet */
417 qemu_send_packet(nc
, s
->tx_buffer
, tx_len
);
419 s
->regs
[SONIC_TCR
] |= SONIC_TCR_PTX
;
422 data
[0 * width
] = s
->regs
[SONIC_TCR
] & 0x0fff; /* status */
423 size
= sizeof(uint16_t) * width
;
424 address_space_rw(&s
->as
,
425 (s
->regs
[SONIC_UTDA
] << 16) | s
->regs
[SONIC_TTDA
],
426 MEMTXATTRS_UNSPECIFIED
, (uint8_t *)data
, size
, 1);
428 if (!(s
->regs
[SONIC_CR
] & SONIC_CR_HTX
)) {
429 /* Read footer of packet */
430 size
= sizeof(uint16_t) * width
;
431 address_space_rw(&s
->as
,
432 ((s
->regs
[SONIC_UTDA
] << 16) | s
->regs
[SONIC_TTDA
]) + sizeof(uint16_t) * (4 + 3 * s
->regs
[SONIC_TFC
]) * width
,
433 MEMTXATTRS_UNSPECIFIED
, (uint8_t *)data
, size
, 0);
434 s
->regs
[SONIC_CTDA
] = data
[0 * width
] & ~0x1;
435 if (data
[0 * width
] & 0x1) {
443 s
->regs
[SONIC_CR
] &= ~SONIC_CR_TXP
;
444 s
->regs
[SONIC_ISR
] |= SONIC_ISR_TXDN
;
445 dp8393x_update_irq(s
);
448 static void do_halt_transmission(dp8393xState
*s
)
453 static void do_command(dp8393xState
*s
, uint16_t command
)
455 if ((s
->regs
[SONIC_CR
] & SONIC_CR_RST
) && !(command
& SONIC_CR_RST
)) {
456 s
->regs
[SONIC_CR
] &= ~SONIC_CR_RST
;
460 s
->regs
[SONIC_CR
] |= (command
& SONIC_CR_MASK
);
462 if (command
& SONIC_CR_HTX
)
463 do_halt_transmission(s
);
464 if (command
& SONIC_CR_TXP
)
465 do_transmit_packets(s
);
466 if (command
& SONIC_CR_RXDIS
)
467 do_receiver_disable(s
);
468 if (command
& SONIC_CR_RXEN
)
469 do_receiver_enable(s
);
470 if (command
& SONIC_CR_STP
)
472 if (command
& SONIC_CR_ST
)
474 if (command
& SONIC_CR_RST
)
475 do_software_reset(s
);
476 if (command
& SONIC_CR_RRRA
)
478 if (command
& SONIC_CR_LCAM
)
482 static uint16_t read_register(dp8393xState
*s
, int reg
)
487 /* Update data before reading it */
493 /* Accept read to some registers only when in reset mode */
497 if (s
->regs
[SONIC_CR
] & SONIC_CR_RST
) {
498 val
= s
->cam
[s
->regs
[SONIC_CEP
] & 0xf][2* (SONIC_CAP0
- reg
) + 1] << 8;
499 val
|= s
->cam
[s
->regs
[SONIC_CEP
] & 0xf][2* (SONIC_CAP0
- reg
)];
502 /* All other registers have no special contrainst */
507 DPRINTF("read 0x%04x from reg %s\n", val
, reg_names
[reg
]);
512 static void write_register(dp8393xState
*s
, int reg
, uint16_t val
)
514 DPRINTF("write 0x%04x to reg %s\n", val
, reg_names
[reg
]);
517 /* Command register */
521 /* Prevent write to read-only registers */
527 DPRINTF("writing to reg %d invalid\n", reg
);
529 /* Accept write to some registers only when in reset mode */
531 if (s
->regs
[SONIC_CR
] & SONIC_CR_RST
) {
532 s
->regs
[reg
] = val
& 0xbfff;
534 DPRINTF("writing to DCR invalid\n");
538 if (s
->regs
[SONIC_CR
] & SONIC_CR_RST
) {
539 s
->regs
[reg
] = val
& 0xf017;
541 DPRINTF("writing to DCR2 invalid\n");
544 /* 12 lower bytes are Read Only */
546 s
->regs
[reg
] = val
& 0xf000;
548 /* 9 lower bytes are Read Only */
550 s
->regs
[reg
] = val
& 0xffe0;
552 /* Ignore most significant bit */
554 s
->regs
[reg
] = val
& 0x7fff;
555 dp8393x_update_irq(s
);
557 /* Clear bits by writing 1 to them */
560 s
->regs
[reg
] &= ~val
;
561 if (val
& SONIC_ISR_RBE
) {
564 dp8393x_update_irq(s
);
566 /* Ignore least significant bit */
571 s
->regs
[reg
] = val
& 0xfffe;
573 /* Invert written value for some registers */
577 s
->regs
[reg
] = val
^ 0xffff;
579 /* All other registers have no special contrainst */
584 if (reg
== SONIC_WT0
|| reg
== SONIC_WT1
) {
589 static void dp8393x_watchdog(void *opaque
)
591 dp8393xState
*s
= opaque
;
593 if (s
->regs
[SONIC_CR
] & SONIC_CR_STP
) {
597 s
->regs
[SONIC_WT1
] = 0xffff;
598 s
->regs
[SONIC_WT0
] = 0xffff;
601 /* Signal underflow */
602 s
->regs
[SONIC_ISR
] |= SONIC_ISR_TC
;
603 dp8393x_update_irq(s
);
606 static uint32_t dp8393x_readw(void *opaque
, hwaddr addr
)
608 dp8393xState
*s
= opaque
;
611 if ((addr
& ((1 << s
->it_shift
) - 1)) != 0) {
615 reg
= addr
>> s
->it_shift
;
616 return read_register(s
, reg
);
619 static uint32_t dp8393x_readb(void *opaque
, hwaddr addr
)
621 uint16_t v
= dp8393x_readw(opaque
, addr
& ~0x1);
622 return (v
>> (8 * (addr
& 0x1))) & 0xff;
625 static uint32_t dp8393x_readl(void *opaque
, hwaddr addr
)
628 v
= dp8393x_readw(opaque
, addr
);
629 v
|= dp8393x_readw(opaque
, addr
+ 2) << 16;
633 static void dp8393x_writew(void *opaque
, hwaddr addr
, uint32_t val
)
635 dp8393xState
*s
= opaque
;
638 if ((addr
& ((1 << s
->it_shift
) - 1)) != 0) {
642 reg
= addr
>> s
->it_shift
;
644 write_register(s
, reg
, (uint16_t)val
);
647 static void dp8393x_writeb(void *opaque
, hwaddr addr
, uint32_t val
)
649 uint16_t old_val
= dp8393x_readw(opaque
, addr
& ~0x1);
653 val
= val
| (old_val
& 0xff00);
656 val
= (val
<< 8) | (old_val
& 0x00ff);
659 dp8393x_writew(opaque
, addr
& ~0x1, val
);
662 static void dp8393x_writel(void *opaque
, hwaddr addr
, uint32_t val
)
664 dp8393x_writew(opaque
, addr
, val
& 0xffff);
665 dp8393x_writew(opaque
, addr
+ 2, (val
>> 16) & 0xffff);
668 static const MemoryRegionOps dp8393x_ops
= {
670 .read
= { dp8393x_readb
, dp8393x_readw
, dp8393x_readl
, },
671 .write
= { dp8393x_writeb
, dp8393x_writew
, dp8393x_writel
, },
673 .endianness
= DEVICE_NATIVE_ENDIAN
,
676 static int nic_can_receive(NetClientState
*nc
)
678 dp8393xState
*s
= qemu_get_nic_opaque(nc
);
680 if (!(s
->regs
[SONIC_CR
] & SONIC_CR_RXEN
))
682 if (s
->regs
[SONIC_ISR
] & SONIC_ISR_RBE
)
687 static int receive_filter(dp8393xState
*s
, const uint8_t * buf
, int size
)
689 static const uint8_t bcast
[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
692 /* Check for runt packet (remember that checksum is not there) */
694 return (s
->regs
[SONIC_RCR
] & SONIC_RCR_RNT
) ? 0 : -1;
697 /* Check promiscuous mode */
698 if ((s
->regs
[SONIC_RCR
] & SONIC_RCR_PRO
) && (buf
[0] & 1) == 0) {
702 /* Check multicast packets */
703 if ((s
->regs
[SONIC_RCR
] & SONIC_RCR_AMC
) && (buf
[0] & 1) == 1) {
707 /* Check broadcast */
708 if ((s
->regs
[SONIC_RCR
] & SONIC_RCR_BRD
) && !memcmp(buf
, bcast
, sizeof(bcast
))) {
713 for (i
= 0; i
< 16; i
++) {
714 if (s
->regs
[SONIC_CE
] & (1 << i
)) {
716 if (!memcmp(buf
, s
->cam
[i
], sizeof(s
->cam
[i
]))) {
725 static ssize_t
nic_receive(NetClientState
*nc
, const uint8_t * buf
, size_t size
)
727 dp8393xState
*s
= qemu_get_nic_opaque(nc
);
730 uint32_t available
, address
;
731 int width
, rx_len
= size
;
734 width
= (s
->regs
[SONIC_DCR
] & SONIC_DCR_DW
) ? 2 : 1;
736 s
->regs
[SONIC_RCR
] &= ~(SONIC_RCR_PRX
| SONIC_RCR_LBK
| SONIC_RCR_FAER
|
737 SONIC_RCR_CRCR
| SONIC_RCR_LPKT
| SONIC_RCR_BC
| SONIC_RCR_MC
);
739 packet_type
= receive_filter(s
, buf
, size
);
740 if (packet_type
< 0) {
741 DPRINTF("packet not for netcard\n");
745 /* XXX: Check byte ordering */
748 if (s
->regs
[SONIC_LLFA
] & 0x1) {
749 /* Are we still in resource exhaustion? */
750 size
= sizeof(uint16_t) * 1 * width
;
751 address
= ((s
->regs
[SONIC_URDA
] << 16) | s
->regs
[SONIC_CRDA
]) + sizeof(uint16_t) * 5 * width
;
752 address_space_rw(&s
->as
, address
, MEMTXATTRS_UNSPECIFIED
,
753 (uint8_t *)data
, size
, 0);
754 if (data
[0 * width
] & 0x1) {
755 /* Still EOL ; stop reception */
758 s
->regs
[SONIC_CRDA
] = s
->regs
[SONIC_LLFA
];
762 /* Save current position */
763 s
->regs
[SONIC_TRBA1
] = s
->regs
[SONIC_CRBA1
];
764 s
->regs
[SONIC_TRBA0
] = s
->regs
[SONIC_CRBA0
];
766 /* Calculate the ethernet checksum */
767 #ifdef SONIC_CALCULATE_RXCRC
768 checksum
= cpu_to_le32(crc32(0, buf
, rx_len
));
773 /* Put packet into RBA */
774 DPRINTF("Receive packet at %08x\n", (s
->regs
[SONIC_CRBA1
] << 16) | s
->regs
[SONIC_CRBA0
]);
775 address
= (s
->regs
[SONIC_CRBA1
] << 16) | s
->regs
[SONIC_CRBA0
];
776 address_space_rw(&s
->as
, address
,
777 MEMTXATTRS_UNSPECIFIED
, (uint8_t *)buf
, rx_len
, 1);
779 address_space_rw(&s
->as
, address
,
780 MEMTXATTRS_UNSPECIFIED
, (uint8_t *)&checksum
, 4, 1);
782 s
->regs
[SONIC_CRBA1
] = address
>> 16;
783 s
->regs
[SONIC_CRBA0
] = address
& 0xffff;
784 available
= (s
->regs
[SONIC_RBWC1
] << 16) | s
->regs
[SONIC_RBWC0
];
785 available
-= rx_len
/ 2;
786 s
->regs
[SONIC_RBWC1
] = available
>> 16;
787 s
->regs
[SONIC_RBWC0
] = available
& 0xffff;
790 if (((s
->regs
[SONIC_RBWC1
] << 16) | s
->regs
[SONIC_RBWC0
]) < s
->regs
[SONIC_EOBC
]) {
791 s
->regs
[SONIC_RCR
] |= SONIC_RCR_LPKT
;
793 s
->regs
[SONIC_RCR
] |= packet_type
;
794 s
->regs
[SONIC_RCR
] |= SONIC_RCR_PRX
;
795 if (s
->loopback_packet
) {
796 s
->regs
[SONIC_RCR
] |= SONIC_RCR_LBK
;
797 s
->loopback_packet
= 0;
800 /* Write status to memory */
801 DPRINTF("Write status at %08x\n", (s
->regs
[SONIC_URDA
] << 16) | s
->regs
[SONIC_CRDA
]);
802 data
[0 * width
] = s
->regs
[SONIC_RCR
]; /* status */
803 data
[1 * width
] = rx_len
; /* byte count */
804 data
[2 * width
] = s
->regs
[SONIC_TRBA0
]; /* pkt_ptr0 */
805 data
[3 * width
] = s
->regs
[SONIC_TRBA1
]; /* pkt_ptr1 */
806 data
[4 * width
] = s
->regs
[SONIC_RSC
]; /* seq_no */
807 size
= sizeof(uint16_t) * 5 * width
;
808 address_space_rw(&s
->as
, (s
->regs
[SONIC_URDA
] << 16) | s
->regs
[SONIC_CRDA
],
809 MEMTXATTRS_UNSPECIFIED
, (uint8_t *)data
, size
, 1);
811 /* Move to next descriptor */
812 size
= sizeof(uint16_t) * width
;
813 address_space_rw(&s
->as
,
814 ((s
->regs
[SONIC_URDA
] << 16) | s
->regs
[SONIC_CRDA
]) + sizeof(uint16_t) * 5 * width
,
815 MEMTXATTRS_UNSPECIFIED
, (uint8_t *)data
, size
, 0);
816 s
->regs
[SONIC_LLFA
] = data
[0 * width
];
817 if (s
->regs
[SONIC_LLFA
] & 0x1) {
819 s
->regs
[SONIC_ISR
] |= SONIC_ISR_RDE
;
821 data
[0 * width
] = 0; /* in_use */
822 address_space_rw(&s
->as
,
823 ((s
->regs
[SONIC_URDA
] << 16) | s
->regs
[SONIC_CRDA
]) + sizeof(uint16_t) * 6 * width
,
824 MEMTXATTRS_UNSPECIFIED
, (uint8_t *)data
, size
, 1);
825 s
->regs
[SONIC_CRDA
] = s
->regs
[SONIC_LLFA
];
826 s
->regs
[SONIC_ISR
] |= SONIC_ISR_PKTRX
;
827 s
->regs
[SONIC_RSC
] = (s
->regs
[SONIC_RSC
] & 0xff00) | (((s
->regs
[SONIC_RSC
] & 0x00ff) + 1) & 0x00ff);
829 if (s
->regs
[SONIC_RCR
] & SONIC_RCR_LPKT
) {
836 dp8393x_update_irq(s
);
841 static void nic_reset(void *opaque
)
843 dp8393xState
*s
= opaque
;
844 timer_del(s
->watchdog
);
846 s
->regs
[SONIC_CR
] = SONIC_CR_RST
| SONIC_CR_STP
| SONIC_CR_RXDIS
;
847 s
->regs
[SONIC_DCR
] &= ~(SONIC_DCR_EXBUS
| SONIC_DCR_LBR
);
848 s
->regs
[SONIC_RCR
] &= ~(SONIC_RCR_LB0
| SONIC_RCR_LB1
| SONIC_RCR_BRD
| SONIC_RCR_RNT
);
849 s
->regs
[SONIC_TCR
] |= SONIC_TCR_NCRS
| SONIC_TCR_PTX
;
850 s
->regs
[SONIC_TCR
] &= ~SONIC_TCR_BCM
;
851 s
->regs
[SONIC_IMR
] = 0;
852 s
->regs
[SONIC_ISR
] = 0;
853 s
->regs
[SONIC_DCR2
] = 0;
854 s
->regs
[SONIC_EOBC
] = 0x02F8;
855 s
->regs
[SONIC_RSC
] = 0;
856 s
->regs
[SONIC_CE
] = 0;
857 s
->regs
[SONIC_RSC
] = 0;
859 /* Network cable is connected */
860 s
->regs
[SONIC_RCR
] |= SONIC_RCR_CRS
;
862 dp8393x_update_irq(s
);
865 static NetClientInfo net_dp83932_info
= {
866 .type
= NET_CLIENT_OPTIONS_KIND_NIC
,
867 .size
= sizeof(NICState
),
868 .can_receive
= nic_can_receive
,
869 .receive
= nic_receive
,
872 void dp83932_init(NICInfo
*nd
, hwaddr base
, int it_shift
,
873 MemoryRegion
*address_space
,
874 qemu_irq irq
, MemoryRegion
*dma_mr
)
878 qemu_check_nic_model(nd
, "dp83932");
880 s
= g_malloc0(sizeof(dp8393xState
));
882 s
->address_space
= address_space
;
883 address_space_init(&s
->as
, dma_mr
, "dp8393x-dma");
884 s
->it_shift
= it_shift
;
886 s
->watchdog
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, dp8393x_watchdog
, s
);
887 s
->regs
[SONIC_SR
] = 0x0004; /* only revision recognized by Linux */
889 s
->conf
.macaddr
= nd
->macaddr
;
890 s
->conf
.peers
.ncs
[0] = nd
->netdev
;
892 s
->nic
= qemu_new_nic(&net_dp83932_info
, &s
->conf
, nd
->model
, nd
->name
, s
);
894 qemu_format_nic_info_str(qemu_get_queue(s
->nic
), s
->conf
.macaddr
.a
);
895 qemu_register_reset(nic_reset
, s
);
898 memory_region_init_io(&s
->mmio
, NULL
, &dp8393x_ops
, s
,
899 "dp8393x", 0x40 << it_shift
);
900 memory_region_add_subregion(address_space
, base
, &s
->mmio
);