]> git.proxmox.com Git - mirror_qemu.git/blob - hw/net/e1000e_core.c
projects / mirror_qemu.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
hostmem-file: add offset option
[mirror_qemu.git] / hw / net / e1000e_core.c
1 /*
2 * Core code for QEMU e1000e emulation
3 *
4 * Software developer's manuals:
5 * http://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-datasheet.pdf
6 *
7 * Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com)
8 * Developed by Daynix Computing LTD (http://www.daynix.com)
9 *
10 * Authors:
11 * Dmitry Fleytman <dmitry@daynix.com>
12 * Leonid Bloch <leonid@daynix.com>
13 * Yan Vugenfirer <yan@daynix.com>
14 *
15 * Based on work done by:
16 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
17 * Copyright (c) 2008 Qumranet
18 * Based on work done by:
19 * Copyright (c) 2007 Dan Aloni
20 * Copyright (c) 2004 Antony T Curtis
21 *
22 * This library is free software; you can redistribute it and/or
23 * modify it under the terms of the GNU Lesser General Public
24 * License as published by the Free Software Foundation; either
25 * version 2.1 of the License, or (at your option) any later version.
26 *
27 * This library is distributed in the hope that it will be useful,
28 * but WITHOUT ANY WARRANTY; without even the implied warranty of
29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
30 * Lesser General Public License for more details.
31 *
32 * You should have received a copy of the GNU Lesser General Public
33 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
34 */
35
36 #include "qemu/osdep.h"
37 #include "qemu/log.h"
38 #include "net/net.h"
39 #include "net/tap.h"
40 #include "hw/net/mii.h"
41 #include "hw/pci/msi.h"
42 #include "hw/pci/msix.h"
43 #include "sysemu/runstate.h"
44
45 #include "net_tx_pkt.h"
46 #include "net_rx_pkt.h"
47
48 #include "e1000_common.h"
49 #include "e1000x_common.h"
50 #include "e1000e_core.h"
51
52 #include "trace.h"
53
54 /* No more then 7813 interrupts per second according to spec 10.2.4.2 */
55 #define E1000E_MIN_XITR (500)
56
57 #define E1000E_MAX_TX_FRAGS (64)
58
59 union e1000_rx_desc_union {
60 struct e1000_rx_desc legacy;
61 union e1000_rx_desc_extended extended;
62 union e1000_rx_desc_packet_split packet_split;
63 };
64
65 static ssize_t
66 e1000e_receive_internal(E1000ECore *core, const struct iovec *iov, int iovcnt,
67 bool has_vnet);
68
69 static inline void
70 e1000e_set_interrupt_cause(E1000ECore *core, uint32_t val);
71
72 static void e1000e_reset(E1000ECore *core, bool sw);
73
74 static inline void
75 e1000e_process_ts_option(E1000ECore *core, struct e1000_tx_desc *dp)
76 {
77 if (le32_to_cpu(dp->upper.data) & E1000_TXD_EXTCMD_TSTAMP) {
78 trace_e1000e_wrn_no_ts_support();
79 }
80 }
81
82 static inline void
83 e1000e_process_snap_option(E1000ECore *core, uint32_t cmd_and_length)
84 {
85 if (cmd_and_length & E1000_TXD_CMD_SNAP) {
86 trace_e1000e_wrn_no_snap_support();
87 }
88 }
89
90 static inline void
91 e1000e_raise_legacy_irq(E1000ECore *core)
92 {
93 trace_e1000e_irq_legacy_notify(true);
94 e1000x_inc_reg_if_not_full(core->mac, IAC);
95 pci_set_irq(core->owner, 1);
96 }
97
98 static inline void
99 e1000e_lower_legacy_irq(E1000ECore *core)
100 {
101 trace_e1000e_irq_legacy_notify(false);
102 pci_set_irq(core->owner, 0);
103 }
104
105 static inline void
106 e1000e_intrmgr_rearm_timer(E1000IntrDelayTimer *timer)
107 {
108 int64_t delay_ns = (int64_t) timer->core->mac[timer->delay_reg] *
109 timer->delay_resolution_ns;
110
111 trace_e1000e_irq_rearm_timer(timer->delay_reg << 2, delay_ns);
112
113 timer_mod(timer->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + delay_ns);
114
115 timer->running = true;
116 }
117
118 static void
119 e1000e_intmgr_timer_resume(E1000IntrDelayTimer *timer)
120 {
121 if (timer->running) {
122 e1000e_intrmgr_rearm_timer(timer);
123 }
124 }
125
126 static void
127 e1000e_intmgr_timer_pause(E1000IntrDelayTimer *timer)
128 {
129 if (timer->running) {
130 timer_del(timer->timer);
131 }
132 }
133
134 static inline void
135 e1000e_intrmgr_stop_timer(E1000IntrDelayTimer *timer)
136 {
137 if (timer->running) {
138 timer_del(timer->timer);
139 timer->running = false;
140 }
141 }
142
143 static inline void
144 e1000e_intrmgr_fire_delayed_interrupts(E1000ECore *core)
145 {
146 trace_e1000e_irq_fire_delayed_interrupts();
147 e1000e_set_interrupt_cause(core, 0);
148 }
149
150 static void
151 e1000e_intrmgr_on_timer(void *opaque)
152 {
153 E1000IntrDelayTimer *timer = opaque;
154
155 trace_e1000e_irq_throttling_timer(timer->delay_reg << 2);
156
157 timer->running = false;
158 e1000e_intrmgr_fire_delayed_interrupts(timer->core);
159 }
160
161 static void
162 e1000e_intrmgr_on_throttling_timer(void *opaque)
163 {
164 E1000IntrDelayTimer *timer = opaque;
165
166 timer->running = false;
167
168 if (msi_enabled(timer->core->owner)) {
169 trace_e1000e_irq_msi_notify_postponed();
170 /* Clear msi_causes_pending to fire MSI eventually */
171 timer->core->msi_causes_pending = 0;
172 e1000e_set_interrupt_cause(timer->core, 0);
173 } else {
174 trace_e1000e_irq_legacy_notify_postponed();
175 e1000e_set_interrupt_cause(timer->core, 0);
176 }
177 }
178
179 static void
180 e1000e_intrmgr_on_msix_throttling_timer(void *opaque)
181 {
182 E1000IntrDelayTimer *timer = opaque;
183 int idx = timer - &timer->core->eitr[0];
184
185 timer->running = false;
186
187 trace_e1000e_irq_msix_notify_postponed_vec(idx);
188 msix_notify(timer->core->owner, idx);
189 }
190
191 static void
192 e1000e_intrmgr_initialize_all_timers(E1000ECore *core, bool create)
193 {
194 int i;
195
196 core->radv.delay_reg = RADV;
197 core->rdtr.delay_reg = RDTR;
198 core->raid.delay_reg = RAID;
199 core->tadv.delay_reg = TADV;
200 core->tidv.delay_reg = TIDV;
201
202 core->radv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES;
203 core->rdtr.delay_resolution_ns = E1000_INTR_DELAY_NS_RES;
204 core->raid.delay_resolution_ns = E1000_INTR_DELAY_NS_RES;
205 core->tadv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES;
206 core->tidv.delay_resolution_ns = E1000_INTR_DELAY_NS_RES;
207
208 core->radv.core = core;
209 core->rdtr.core = core;
210 core->raid.core = core;
211 core->tadv.core = core;
212 core->tidv.core = core;
213
214 core->itr.core = core;
215 core->itr.delay_reg = ITR;
216 core->itr.delay_resolution_ns = E1000_INTR_THROTTLING_NS_RES;
217
218 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
219 core->eitr[i].core = core;
220 core->eitr[i].delay_reg = EITR + i;
221 core->eitr[i].delay_resolution_ns = E1000_INTR_THROTTLING_NS_RES;
222 }
223
224 if (!create) {
225 return;
226 }
227
228 core->radv.timer =
229 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->radv);
230 core->rdtr.timer =
231 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->rdtr);
232 core->raid.timer =
233 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->raid);
234
235 core->tadv.timer =
236 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->tadv);
237 core->tidv.timer =
238 timer_new_ns(QEMU_CLOCK_VIRTUAL, e1000e_intrmgr_on_timer, &core->tidv);
239
240 core->itr.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
241 e1000e_intrmgr_on_throttling_timer,
242 &core->itr);
243
244 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
245 core->eitr[i].timer =
246 timer_new_ns(QEMU_CLOCK_VIRTUAL,
247 e1000e_intrmgr_on_msix_throttling_timer,
248 &core->eitr[i]);
249 }
250 }
251
252 static inline void
253 e1000e_intrmgr_stop_delay_timers(E1000ECore *core)
254 {
255 e1000e_intrmgr_stop_timer(&core->radv);
256 e1000e_intrmgr_stop_timer(&core->rdtr);
257 e1000e_intrmgr_stop_timer(&core->raid);
258 e1000e_intrmgr_stop_timer(&core->tidv);
259 e1000e_intrmgr_stop_timer(&core->tadv);
260 }
261
262 static bool
263 e1000e_intrmgr_delay_rx_causes(E1000ECore *core, uint32_t *causes)
264 {
265 uint32_t delayable_causes;
266 uint32_t rdtr = core->mac[RDTR];
267 uint32_t radv = core->mac[RADV];
268 uint32_t raid = core->mac[RAID];
269
270 if (msix_enabled(core->owner)) {
271 return false;
272 }
273
274 delayable_causes = E1000_ICR_RXQ0 |
275 E1000_ICR_RXQ1 |
276 E1000_ICR_RXT0;
277
278 if (!(core->mac[RFCTL] & E1000_RFCTL_ACK_DIS)) {
279 delayable_causes |= E1000_ICR_ACK;
280 }
281
282 /* Clean up all causes that may be delayed */
283 core->delayed_causes |= *causes & delayable_causes;
284 *causes &= ~delayable_causes;
285
286 /*
287 * Check if delayed RX interrupts disabled by client
288 * or if there are causes that cannot be delayed
289 */
290 if ((rdtr == 0) || (*causes != 0)) {
291 return false;
292 }
293
294 /*
295 * Check if delayed RX ACK interrupts disabled by client
296 * and there is an ACK packet received
297 */
298 if ((raid == 0) && (core->delayed_causes & E1000_ICR_ACK)) {
299 return false;
300 }
301
302 /* All causes delayed */
303 e1000e_intrmgr_rearm_timer(&core->rdtr);
304
305 if (!core->radv.running && (radv != 0)) {
306 e1000e_intrmgr_rearm_timer(&core->radv);
307 }
308
309 if (!core->raid.running && (core->delayed_causes & E1000_ICR_ACK)) {
310 e1000e_intrmgr_rearm_timer(&core->raid);
311 }
312
313 return true;
314 }
315
316 static bool
317 e1000e_intrmgr_delay_tx_causes(E1000ECore *core, uint32_t *causes)
318 {
319 static const uint32_t delayable_causes = E1000_ICR_TXQ0 |
320 E1000_ICR_TXQ1 |
321 E1000_ICR_TXQE |
322 E1000_ICR_TXDW;
323
324 if (msix_enabled(core->owner)) {
325 return false;
326 }
327
328 /* Clean up all causes that may be delayed */
329 core->delayed_causes |= *causes & delayable_causes;
330 *causes &= ~delayable_causes;
331
332 /* If there are causes that cannot be delayed */
333 if (*causes != 0) {
334 return false;
335 }
336
337 /* All causes delayed */
338 e1000e_intrmgr_rearm_timer(&core->tidv);
339
340 if (!core->tadv.running && (core->mac[TADV] != 0)) {
341 e1000e_intrmgr_rearm_timer(&core->tadv);
342 }
343
344 return true;
345 }
346
347 static uint32_t
348 e1000e_intmgr_collect_delayed_causes(E1000ECore *core)
349 {
350 uint32_t res;
351
352 if (msix_enabled(core->owner)) {
353 assert(core->delayed_causes == 0);
354 return 0;
355 }
356
357 res = core->delayed_causes;
358 core->delayed_causes = 0;
359
360 e1000e_intrmgr_stop_delay_timers(core);
361
362 return res;
363 }
364
365 static void
366 e1000e_intrmgr_fire_all_timers(E1000ECore *core)
367 {
368 int i;
369 uint32_t val = e1000e_intmgr_collect_delayed_causes(core);
370
371 trace_e1000e_irq_adding_delayed_causes(val, core->mac[ICR]);
372 core->mac[ICR] |= val;
373
374 if (core->itr.running) {
375 timer_del(core->itr.timer);
376 e1000e_intrmgr_on_throttling_timer(&core->itr);
377 }
378
379 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
380 if (core->eitr[i].running) {
381 timer_del(core->eitr[i].timer);
382 e1000e_intrmgr_on_msix_throttling_timer(&core->eitr[i]);
383 }
384 }
385 }
386
387 static void
388 e1000e_intrmgr_resume(E1000ECore *core)
389 {
390 int i;
391
392 e1000e_intmgr_timer_resume(&core->radv);
393 e1000e_intmgr_timer_resume(&core->rdtr);
394 e1000e_intmgr_timer_resume(&core->raid);
395 e1000e_intmgr_timer_resume(&core->tidv);
396 e1000e_intmgr_timer_resume(&core->tadv);
397
398 e1000e_intmgr_timer_resume(&core->itr);
399
400 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
401 e1000e_intmgr_timer_resume(&core->eitr[i]);
402 }
403 }
404
405 static void
406 e1000e_intrmgr_pause(E1000ECore *core)
407 {
408 int i;
409
410 e1000e_intmgr_timer_pause(&core->radv);
411 e1000e_intmgr_timer_pause(&core->rdtr);
412 e1000e_intmgr_timer_pause(&core->raid);
413 e1000e_intmgr_timer_pause(&core->tidv);
414 e1000e_intmgr_timer_pause(&core->tadv);
415
416 e1000e_intmgr_timer_pause(&core->itr);
417
418 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
419 e1000e_intmgr_timer_pause(&core->eitr[i]);
420 }
421 }
422
423 static void
424 e1000e_intrmgr_reset(E1000ECore *core)
425 {
426 int i;
427
428 core->delayed_causes = 0;
429
430 e1000e_intrmgr_stop_delay_timers(core);
431
432 e1000e_intrmgr_stop_timer(&core->itr);
433
434 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
435 e1000e_intrmgr_stop_timer(&core->eitr[i]);
436 }
437 }
438
439 static void
440 e1000e_intrmgr_pci_unint(E1000ECore *core)
441 {
442 int i;
443
444 timer_free(core->radv.timer);
445 timer_free(core->rdtr.timer);
446 timer_free(core->raid.timer);
447
448 timer_free(core->tadv.timer);
449 timer_free(core->tidv.timer);
450
451 timer_free(core->itr.timer);
452
453 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
454 timer_free(core->eitr[i].timer);
455 }
456 }
457
458 static void
459 e1000e_intrmgr_pci_realize(E1000ECore *core)
460 {
461 e1000e_intrmgr_initialize_all_timers(core, true);
462 }
463
464 static inline bool
465 e1000e_rx_csum_enabled(E1000ECore *core)
466 {
467 return (core->mac[RXCSUM] & E1000_RXCSUM_PCSD) ? false : true;
468 }
469
470 static inline bool
471 e1000e_rx_use_legacy_descriptor(E1000ECore *core)
472 {
473 return (core->mac[RFCTL] & E1000_RFCTL_EXTEN) ? false : true;
474 }
475
476 static inline bool
477 e1000e_rx_use_ps_descriptor(E1000ECore *core)
478 {
479 return !e1000e_rx_use_legacy_descriptor(core) &&
480 (core->mac[RCTL] & E1000_RCTL_DTYP_PS);
481 }
482
483 static inline bool
484 e1000e_rss_enabled(E1000ECore *core)
485 {
486 return E1000_MRQC_ENABLED(core->mac[MRQC]) &&
487 !e1000e_rx_csum_enabled(core) &&
488 !e1000e_rx_use_legacy_descriptor(core);
489 }
490
491 typedef struct E1000E_RSSInfo_st {
492 bool enabled;
493 uint32_t hash;
494 uint32_t queue;
495 uint32_t type;
496 } E1000E_RSSInfo;
497
498 static uint32_t
499 e1000e_rss_get_hash_type(E1000ECore *core, struct NetRxPkt *pkt)
500 {
501 bool hasip4, hasip6;
502 EthL4HdrProto l4hdr_proto;
503
504 assert(e1000e_rss_enabled(core));
505
506 net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto);
507
508 if (hasip4) {
509 trace_e1000e_rx_rss_ip4(l4hdr_proto, core->mac[MRQC],
510 E1000_MRQC_EN_TCPIPV4(core->mac[MRQC]),
511 E1000_MRQC_EN_IPV4(core->mac[MRQC]));
512
513 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP &&
514 E1000_MRQC_EN_TCPIPV4(core->mac[MRQC])) {
515 return E1000_MRQ_RSS_TYPE_IPV4TCP;
516 }
517
518 if (E1000_MRQC_EN_IPV4(core->mac[MRQC])) {
519 return E1000_MRQ_RSS_TYPE_IPV4;
520 }
521 } else if (hasip6) {
522 eth_ip6_hdr_info *ip6info = net_rx_pkt_get_ip6_info(pkt);
523
524 bool ex_dis = core->mac[RFCTL] & E1000_RFCTL_IPV6_EX_DIS;
525 bool new_ex_dis = core->mac[RFCTL] & E1000_RFCTL_NEW_IPV6_EXT_DIS;
526
527 /*
528 * Following two traces must not be combined because resulting
529 * event will have 11 arguments totally and some trace backends
530 * (at least "ust") have limitation of maximum 10 arguments per
531 * event. Events with more arguments fail to compile for
532 * backends like these.
533 */
534 trace_e1000e_rx_rss_ip6_rfctl(core->mac[RFCTL]);
535 trace_e1000e_rx_rss_ip6(ex_dis, new_ex_dis, l4hdr_proto,
536 ip6info->has_ext_hdrs,
537 ip6info->rss_ex_dst_valid,
538 ip6info->rss_ex_src_valid,
539 core->mac[MRQC],
540 E1000_MRQC_EN_TCPIPV6(core->mac[MRQC]),
541 E1000_MRQC_EN_IPV6EX(core->mac[MRQC]),
542 E1000_MRQC_EN_IPV6(core->mac[MRQC]));
543
544 if ((!ex_dis || !ip6info->has_ext_hdrs) &&
545 (!new_ex_dis || !(ip6info->rss_ex_dst_valid ||
546 ip6info->rss_ex_src_valid))) {
547
548 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP &&
549 E1000_MRQC_EN_TCPIPV6(core->mac[MRQC])) {
550 return E1000_MRQ_RSS_TYPE_IPV6TCP;
551 }
552
553 if (E1000_MRQC_EN_IPV6EX(core->mac[MRQC])) {
554 return E1000_MRQ_RSS_TYPE_IPV6EX;
555 }
556
557 }
558
559 if (E1000_MRQC_EN_IPV6(core->mac[MRQC])) {
560 return E1000_MRQ_RSS_TYPE_IPV6;
561 }
562
563 }
564
565 return E1000_MRQ_RSS_TYPE_NONE;
566 }
567
568 static uint32_t
569 e1000e_rss_calc_hash(E1000ECore *core,
570 struct NetRxPkt *pkt,
571 E1000E_RSSInfo *info)
572 {
573 NetRxPktRssType type;
574
575 assert(e1000e_rss_enabled(core));
576
577 switch (info->type) {
578 case E1000_MRQ_RSS_TYPE_IPV4:
579 type = NetPktRssIpV4;
580 break;
581 case E1000_MRQ_RSS_TYPE_IPV4TCP:
582 type = NetPktRssIpV4Tcp;
583 break;
584 case E1000_MRQ_RSS_TYPE_IPV6TCP:
585 type = NetPktRssIpV6TcpEx;
586 break;
587 case E1000_MRQ_RSS_TYPE_IPV6:
588 type = NetPktRssIpV6;
589 break;
590 case E1000_MRQ_RSS_TYPE_IPV6EX:
591 type = NetPktRssIpV6Ex;
592 break;
593 default:
594 assert(false);
595 return 0;
596 }
597
598 return net_rx_pkt_calc_rss_hash(pkt, type, (uint8_t *) &core->mac[RSSRK]);
599 }
600
601 static void
602 e1000e_rss_parse_packet(E1000ECore *core,
603 struct NetRxPkt *pkt,
604 E1000E_RSSInfo *info)
605 {
606 trace_e1000e_rx_rss_started();
607
608 if (!e1000e_rss_enabled(core)) {
609 info->enabled = false;
610 info->hash = 0;
611 info->queue = 0;
612 info->type = 0;
613 trace_e1000e_rx_rss_disabled();
614 return;
615 }
616
617 info->enabled = true;
618
619 info->type = e1000e_rss_get_hash_type(core, pkt);
620
621 trace_e1000e_rx_rss_type(info->type);
622
623 if (info->type == E1000_MRQ_RSS_TYPE_NONE) {
624 info->hash = 0;
625 info->queue = 0;
626 return;
627 }
628
629 info->hash = e1000e_rss_calc_hash(core, pkt, info);
630 info->queue = E1000_RSS_QUEUE(&core->mac[RETA], info->hash);
631 }
632
633 static bool
634 e1000e_setup_tx_offloads(E1000ECore *core, struct e1000e_tx *tx)
635 {
636 if (tx->props.tse && tx->cptse) {
637 if (!net_tx_pkt_build_vheader(tx->tx_pkt, true, true, tx->props.mss)) {
638 return false;
639 }
640
641 net_tx_pkt_update_ip_checksums(tx->tx_pkt);
642 e1000x_inc_reg_if_not_full(core->mac, TSCTC);
643 return true;
644 }
645
646 if (tx->sum_needed & E1000_TXD_POPTS_TXSM) {
647 if (!net_tx_pkt_build_vheader(tx->tx_pkt, false, true, 0)) {
648 return false;
649 }
650 }
651
652 if (tx->sum_needed & E1000_TXD_POPTS_IXSM) {
653 net_tx_pkt_update_ip_hdr_checksum(tx->tx_pkt);
654 }
655
656 return true;
657 }
658
659 static void e1000e_tx_pkt_callback(void *core,
660 const struct iovec *iov,
661 int iovcnt,
662 const struct iovec *virt_iov,
663 int virt_iovcnt)
664 {
665 e1000e_receive_internal(core, virt_iov, virt_iovcnt, true);
666 }
667
668 static bool
669 e1000e_tx_pkt_send(E1000ECore *core, struct e1000e_tx *tx, int queue_index)
670 {
671 int target_queue = MIN(core->max_queue_num, queue_index);
672 NetClientState *queue = qemu_get_subqueue(core->owner_nic, target_queue);
673
674 if (!e1000e_setup_tx_offloads(core, tx)) {
675 return false;
676 }
677
678 net_tx_pkt_dump(tx->tx_pkt);
679
680 if ((core->phy[0][MII_BMCR] & MII_BMCR_LOOPBACK) ||
681 ((core->mac[RCTL] & E1000_RCTL_LBM_MAC) == E1000_RCTL_LBM_MAC)) {
682 return net_tx_pkt_send_custom(tx->tx_pkt, false,
683 e1000e_tx_pkt_callback, core);
684 } else {
685 return net_tx_pkt_send(tx->tx_pkt, queue);
686 }
687 }
688
689 static void
690 e1000e_on_tx_done_update_stats(E1000ECore *core, struct NetTxPkt *tx_pkt)
691 {
692 static const int PTCregs[6] = { PTC64, PTC127, PTC255, PTC511,
693 PTC1023, PTC1522 };
694
695 size_t tot_len = net_tx_pkt_get_total_len(tx_pkt) + 4;
696
697 e1000x_increase_size_stats(core->mac, PTCregs, tot_len);
698 e1000x_inc_reg_if_not_full(core->mac, TPT);
699 e1000x_grow_8reg_if_not_full(core->mac, TOTL, tot_len);
700
701 switch (net_tx_pkt_get_packet_type(tx_pkt)) {
702 case ETH_PKT_BCAST:
703 e1000x_inc_reg_if_not_full(core->mac, BPTC);
704 break;
705 case ETH_PKT_MCAST:
706 e1000x_inc_reg_if_not_full(core->mac, MPTC);
707 break;
708 case ETH_PKT_UCAST:
709 break;
710 default:
711 g_assert_not_reached();
712 }
713
714 core->mac[GPTC] = core->mac[TPT];
715 core->mac[GOTCL] = core->mac[TOTL];
716 core->mac[GOTCH] = core->mac[TOTH];
717 }
718
719 static void
720 e1000e_process_tx_desc(E1000ECore *core,
721 struct e1000e_tx *tx,
722 struct e1000_tx_desc *dp,
723 int queue_index)
724 {
725 uint32_t txd_lower = le32_to_cpu(dp->lower.data);
726 uint32_t dtype = txd_lower & (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D);
727 unsigned int split_size = txd_lower & 0xffff;
728 uint64_t addr;
729 struct e1000_context_desc *xp = (struct e1000_context_desc *)dp;
730 bool eop = txd_lower & E1000_TXD_CMD_EOP;
731
732 if (dtype == E1000_TXD_CMD_DEXT) { /* context descriptor */
733 e1000x_read_tx_ctx_descr(xp, &tx->props);
734 e1000e_process_snap_option(core, le32_to_cpu(xp->cmd_and_length));
735 return;
736 } else if (dtype == (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)) {
737 /* data descriptor */
738 tx->sum_needed = le32_to_cpu(dp->upper.data) >> 8;
739 tx->cptse = (txd_lower & E1000_TXD_CMD_TSE) ? 1 : 0;
740 e1000e_process_ts_option(core, dp);
741 } else {
742 /* legacy descriptor */
743 e1000e_process_ts_option(core, dp);
744 tx->cptse = 0;
745 }
746
747 addr = le64_to_cpu(dp->buffer_addr);
748
749 if (!tx->skip_cp) {
750 if (!net_tx_pkt_add_raw_fragment(tx->tx_pkt, addr, split_size)) {
751 tx->skip_cp = true;
752 }
753 }
754
755 if (eop) {
756 if (!tx->skip_cp && net_tx_pkt_parse(tx->tx_pkt)) {
757 if (e1000x_vlan_enabled(core->mac) &&
758 e1000x_is_vlan_txd(txd_lower)) {
759 net_tx_pkt_setup_vlan_header_ex(tx->tx_pkt,
760 le16_to_cpu(dp->upper.fields.special), core->mac[VET]);
761 }
762 if (e1000e_tx_pkt_send(core, tx, queue_index)) {
763 e1000e_on_tx_done_update_stats(core, tx->tx_pkt);
764 }
765 }
766
767 tx->skip_cp = false;
768 net_tx_pkt_reset(tx->tx_pkt, core->owner);
769
770 tx->sum_needed = 0;
771 tx->cptse = 0;
772 }
773 }
774
775 static inline uint32_t
776 e1000e_tx_wb_interrupt_cause(E1000ECore *core, int queue_idx)
777 {
778 if (!msix_enabled(core->owner)) {
779 return E1000_ICR_TXDW;
780 }
781
782 return (queue_idx == 0) ? E1000_ICR_TXQ0 : E1000_ICR_TXQ1;
783 }
784
785 static inline uint32_t
786 e1000e_rx_wb_interrupt_cause(E1000ECore *core, int queue_idx,
787 bool min_threshold_hit)
788 {
789 if (!msix_enabled(core->owner)) {
790 return E1000_ICS_RXT0 | (min_threshold_hit ? E1000_ICS_RXDMT0 : 0);
791 }
792
793 return (queue_idx == 0) ? E1000_ICR_RXQ0 : E1000_ICR_RXQ1;
794 }
795
796 static uint32_t
797 e1000e_txdesc_writeback(E1000ECore *core, dma_addr_t base,
798 struct e1000_tx_desc *dp, bool *ide, int queue_idx)
799 {
800 uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data);
801
802 if (!(txd_lower & E1000_TXD_CMD_RS) &&
803 !(core->mac[IVAR] & E1000_IVAR_TX_INT_EVERY_WB)) {
804 return 0;
805 }
806
807 *ide = (txd_lower & E1000_TXD_CMD_IDE) ? true : false;
808
809 txd_upper = le32_to_cpu(dp->upper.data) | E1000_TXD_STAT_DD;
810
811 dp->upper.data = cpu_to_le32(txd_upper);
812 pci_dma_write(core->owner, base + ((char *)&dp->upper - (char *)dp),
813 &dp->upper, sizeof(dp->upper));
814 return e1000e_tx_wb_interrupt_cause(core, queue_idx);
815 }
816
817 typedef struct E1000E_RingInfo_st {
818 int dbah;
819 int dbal;
820 int dlen;
821 int dh;
822 int dt;
823 int idx;
824 } E1000E_RingInfo;
825
826 static inline bool
827 e1000e_ring_empty(E1000ECore *core, const E1000E_RingInfo *r)
828 {
829 return core->mac[r->dh] == core->mac[r->dt] ||
830 core->mac[r->dt] >= core->mac[r->dlen] / E1000_RING_DESC_LEN;
831 }
832
833 static inline uint64_t
834 e1000e_ring_base(E1000ECore *core, const E1000E_RingInfo *r)
835 {
836 uint64_t bah = core->mac[r->dbah];
837 uint64_t bal = core->mac[r->dbal];
838
839 return (bah << 32) + bal;
840 }
841
842 static inline uint64_t
843 e1000e_ring_head_descr(E1000ECore *core, const E1000E_RingInfo *r)
844 {
845 return e1000e_ring_base(core, r) + E1000_RING_DESC_LEN * core->mac[r->dh];
846 }
847
848 static inline void
849 e1000e_ring_advance(E1000ECore *core, const E1000E_RingInfo *r, uint32_t count)
850 {
851 core->mac[r->dh] += count;
852
853 if (core->mac[r->dh] * E1000_RING_DESC_LEN >= core->mac[r->dlen]) {
854 core->mac[r->dh] = 0;
855 }
856 }
857
858 static inline uint32_t
859 e1000e_ring_free_descr_num(E1000ECore *core, const E1000E_RingInfo *r)
860 {
861 trace_e1000e_ring_free_space(r->idx, core->mac[r->dlen],
862 core->mac[r->dh], core->mac[r->dt]);
863
864 if (core->mac[r->dh] <= core->mac[r->dt]) {
865 return core->mac[r->dt] - core->mac[r->dh];
866 }
867
868 if (core->mac[r->dh] > core->mac[r->dt]) {
869 return core->mac[r->dlen] / E1000_RING_DESC_LEN +
870 core->mac[r->dt] - core->mac[r->dh];
871 }
872
873 g_assert_not_reached();
874 return 0;
875 }
876
877 static inline bool
878 e1000e_ring_enabled(E1000ECore *core, const E1000E_RingInfo *r)
879 {
880 return core->mac[r->dlen] > 0;
881 }
882
883 static inline uint32_t
884 e1000e_ring_len(E1000ECore *core, const E1000E_RingInfo *r)
885 {
886 return core->mac[r->dlen];
887 }
888
889 typedef struct E1000E_TxRing_st {
890 const E1000E_RingInfo *i;
891 struct e1000e_tx *tx;
892 } E1000E_TxRing;
893
894 static inline int
895 e1000e_mq_queue_idx(int base_reg_idx, int reg_idx)
896 {
897 return (reg_idx - base_reg_idx) / (0x100 >> 2);
898 }
899
900 static inline void
901 e1000e_tx_ring_init(E1000ECore *core, E1000E_TxRing *txr, int idx)
902 {
903 static const E1000E_RingInfo i[E1000E_NUM_QUEUES] = {
904 { TDBAH, TDBAL, TDLEN, TDH, TDT, 0 },
905 { TDBAH1, TDBAL1, TDLEN1, TDH1, TDT1, 1 }
906 };
907
908 assert(idx < ARRAY_SIZE(i));
909
910 txr->i = &i[idx];
911 txr->tx = &core->tx[idx];
912 }
913
914 typedef struct E1000E_RxRing_st {
915 const E1000E_RingInfo *i;
916 } E1000E_RxRing;
917
918 static inline void
919 e1000e_rx_ring_init(E1000ECore *core, E1000E_RxRing *rxr, int idx)
920 {
921 static const E1000E_RingInfo i[E1000E_NUM_QUEUES] = {
922 { RDBAH0, RDBAL0, RDLEN0, RDH0, RDT0, 0 },
923 { RDBAH1, RDBAL1, RDLEN1, RDH1, RDT1, 1 }
924 };
925
926 assert(idx < ARRAY_SIZE(i));
927
928 rxr->i = &i[idx];
929 }
930
931 static void
932 e1000e_start_xmit(E1000ECore *core, const E1000E_TxRing *txr)
933 {
934 dma_addr_t base;
935 struct e1000_tx_desc desc;
936 bool ide = false;
937 const E1000E_RingInfo *txi = txr->i;
938 uint32_t cause = E1000_ICS_TXQE;
939
940 if (!(core->mac[TCTL] & E1000_TCTL_EN)) {
941 trace_e1000e_tx_disabled();
942 return;
943 }
944
945 while (!e1000e_ring_empty(core, txi)) {
946 base = e1000e_ring_head_descr(core, txi);
947
948 pci_dma_read(core->owner, base, &desc, sizeof(desc));
949
950 trace_e1000e_tx_descr((void *)(intptr_t)desc.buffer_addr,
951 desc.lower.data, desc.upper.data);
952
953 e1000e_process_tx_desc(core, txr->tx, &desc, txi->idx);
954 cause |= e1000e_txdesc_writeback(core, base, &desc, &ide, txi->idx);
955
956 e1000e_ring_advance(core, txi, 1);
957 }
958
959 if (!ide || !e1000e_intrmgr_delay_tx_causes(core, &cause)) {
960 e1000e_set_interrupt_cause(core, cause);
961 }
962 }
963
964 static bool
965 e1000e_has_rxbufs(E1000ECore *core, const E1000E_RingInfo *r,
966 size_t total_size)
967 {
968 uint32_t bufs = e1000e_ring_free_descr_num(core, r);
969
970 trace_e1000e_rx_has_buffers(r->idx, bufs, total_size,
971 core->rx_desc_buf_size);
972
973 return total_size <= bufs / (core->rx_desc_len / E1000_MIN_RX_DESC_LEN) *
974 core->rx_desc_buf_size;
975 }
976
977 void
978 e1000e_start_recv(E1000ECore *core)
979 {
980 int i;
981
982 trace_e1000e_rx_start_recv();
983
984 for (i = 0; i <= core->max_queue_num; i++) {
985 qemu_flush_queued_packets(qemu_get_subqueue(core->owner_nic, i));
986 }
987 }
988
989 bool
990 e1000e_can_receive(E1000ECore *core)
991 {
992 int i;
993
994 if (!e1000x_rx_ready(core->owner, core->mac)) {
995 return false;
996 }
997
998 for (i = 0; i < E1000E_NUM_QUEUES; i++) {
999 E1000E_RxRing rxr;
1000
1001 e1000e_rx_ring_init(core, &rxr, i);
1002 if (e1000e_ring_enabled(core, rxr.i) &&
1003 e1000e_has_rxbufs(core, rxr.i, 1)) {
1004 trace_e1000e_rx_can_recv();
1005 return true;
1006 }
1007 }
1008
1009 trace_e1000e_rx_can_recv_rings_full();
1010 return false;
1011 }
1012
1013 ssize_t
1014 e1000e_receive(E1000ECore *core, const uint8_t *buf, size_t size)
1015 {
1016 const struct iovec iov = {
1017 .iov_base = (uint8_t *)buf,
1018 .iov_len = size
1019 };
1020
1021 return e1000e_receive_iov(core, &iov, 1);
1022 }
1023
1024 static inline bool
1025 e1000e_rx_l3_cso_enabled(E1000ECore *core)
1026 {
1027 return !!(core->mac[RXCSUM] & E1000_RXCSUM_IPOFLD);
1028 }
1029
1030 static inline bool
1031 e1000e_rx_l4_cso_enabled(E1000ECore *core)
1032 {
1033 return !!(core->mac[RXCSUM] & E1000_RXCSUM_TUOFLD);
1034 }
1035
1036 static bool
1037 e1000e_receive_filter(E1000ECore *core, const uint8_t *buf, int size)
1038 {
1039 uint32_t rctl = core->mac[RCTL];
1040
1041 if (e1000x_is_vlan_packet(buf, core->mac[VET]) &&
1042 e1000x_vlan_rx_filter_enabled(core->mac)) {
1043 uint16_t vid = lduw_be_p(&PKT_GET_VLAN_HDR(buf)->h_tci);
1044 uint32_t vfta =
1045 ldl_le_p((uint32_t *)(core->mac + VFTA) +
1046 ((vid >> E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK));
1047 if ((vfta & (1 << (vid & E1000_VFTA_ENTRY_BIT_SHIFT_MASK))) == 0) {
1048 trace_e1000e_rx_flt_vlan_mismatch(vid);
1049 return false;
1050 } else {
1051 trace_e1000e_rx_flt_vlan_match(vid);
1052 }
1053 }
1054
1055 switch (net_rx_pkt_get_packet_type(core->rx_pkt)) {
1056 case ETH_PKT_UCAST:
1057 if (rctl & E1000_RCTL_UPE) {
1058 return true; /* promiscuous ucast */
1059 }
1060 break;
1061
1062 case ETH_PKT_BCAST:
1063 if (rctl & E1000_RCTL_BAM) {
1064 return true; /* broadcast enabled */
1065 }
1066 break;
1067
1068 case ETH_PKT_MCAST:
1069 if (rctl & E1000_RCTL_MPE) {
1070 return true; /* promiscuous mcast */
1071 }
1072 break;
1073
1074 default:
1075 g_assert_not_reached();
1076 }
1077
1078 return e1000x_rx_group_filter(core->mac, buf);
1079 }
1080
1081 static inline void
1082 e1000e_read_lgcy_rx_descr(E1000ECore *core, struct e1000_rx_desc *desc,
1083 hwaddr *buff_addr)
1084 {
1085 *buff_addr = le64_to_cpu(desc->buffer_addr);
1086 }
1087
1088 static inline void
1089 e1000e_read_ext_rx_descr(E1000ECore *core, union e1000_rx_desc_extended *desc,
1090 hwaddr *buff_addr)
1091 {
1092 *buff_addr = le64_to_cpu(desc->read.buffer_addr);
1093 }
1094
1095 static inline void
1096 e1000e_read_ps_rx_descr(E1000ECore *core,
1097 union e1000_rx_desc_packet_split *desc,
1098 hwaddr buff_addr[MAX_PS_BUFFERS])
1099 {
1100 int i;
1101
1102 for (i = 0; i < MAX_PS_BUFFERS; i++) {
1103 buff_addr[i] = le64_to_cpu(desc->read.buffer_addr[i]);
1104 }
1105
1106 trace_e1000e_rx_desc_ps_read(buff_addr[0], buff_addr[1],
1107 buff_addr[2], buff_addr[3]);
1108 }
1109
1110 static inline void
1111 e1000e_read_rx_descr(E1000ECore *core, union e1000_rx_desc_union *desc,
1112 hwaddr buff_addr[MAX_PS_BUFFERS])
1113 {
1114 if (e1000e_rx_use_legacy_descriptor(core)) {
1115 e1000e_read_lgcy_rx_descr(core, &desc->legacy, &buff_addr[0]);
1116 buff_addr[1] = buff_addr[2] = buff_addr[3] = 0;
1117 } else {
1118 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) {
1119 e1000e_read_ps_rx_descr(core, &desc->packet_split, buff_addr);
1120 } else {
1121 e1000e_read_ext_rx_descr(core, &desc->extended, &buff_addr[0]);
1122 buff_addr[1] = buff_addr[2] = buff_addr[3] = 0;
1123 }
1124 }
1125 }
1126
1127 static void
1128 e1000e_verify_csum_in_sw(E1000ECore *core,
1129 struct NetRxPkt *pkt,
1130 uint32_t *status_flags,
1131 EthL4HdrProto l4hdr_proto)
1132 {
1133 bool csum_valid;
1134 uint32_t csum_error;
1135
1136 if (e1000e_rx_l3_cso_enabled(core)) {
1137 if (!net_rx_pkt_validate_l3_csum(pkt, &csum_valid)) {
1138 trace_e1000e_rx_metadata_l3_csum_validation_failed();
1139 } else {
1140 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_IPE;
1141 *status_flags |= E1000_RXD_STAT_IPCS | csum_error;
1142 }
1143 } else {
1144 trace_e1000e_rx_metadata_l3_cso_disabled();
1145 }
1146
1147 if (!e1000e_rx_l4_cso_enabled(core)) {
1148 trace_e1000e_rx_metadata_l4_cso_disabled();
1149 return;
1150 }
1151
1152 if (!net_rx_pkt_validate_l4_csum(pkt, &csum_valid)) {
1153 trace_e1000e_rx_metadata_l4_csum_validation_failed();
1154 return;
1155 }
1156
1157 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_TCPE;
1158 *status_flags |= E1000_RXD_STAT_TCPCS | csum_error;
1159
1160 if (l4hdr_proto == ETH_L4_HDR_PROTO_UDP) {
1161 *status_flags |= E1000_RXD_STAT_UDPCS;
1162 }
1163 }
1164
1165 static inline bool
1166 e1000e_is_tcp_ack(E1000ECore *core, struct NetRxPkt *rx_pkt)
1167 {
1168 if (!net_rx_pkt_is_tcp_ack(rx_pkt)) {
1169 return false;
1170 }
1171
1172 if (core->mac[RFCTL] & E1000_RFCTL_ACK_DATA_DIS) {
1173 return !net_rx_pkt_has_tcp_data(rx_pkt);
1174 }
1175
1176 return true;
1177 }
1178
1179 static void
1180 e1000e_build_rx_metadata(E1000ECore *core,
1181 struct NetRxPkt *pkt,
1182 bool is_eop,
1183 const E1000E_RSSInfo *rss_info,
1184 uint32_t *rss, uint32_t *mrq,
1185 uint32_t *status_flags,
1186 uint16_t *ip_id,
1187 uint16_t *vlan_tag)
1188 {
1189 struct virtio_net_hdr *vhdr;
1190 bool hasip4, hasip6;
1191 EthL4HdrProto l4hdr_proto;
1192 uint32_t pkt_type;
1193
1194 *status_flags = E1000_RXD_STAT_DD;
1195
1196 /* No additional metadata needed for non-EOP descriptors */
1197 if (!is_eop) {
1198 goto func_exit;
1199 }
1200
1201 *status_flags |= E1000_RXD_STAT_EOP;
1202
1203 net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto);
1204 trace_e1000e_rx_metadata_protocols(hasip4, hasip6, l4hdr_proto);
1205
1206 /* VLAN state */
1207 if (net_rx_pkt_is_vlan_stripped(pkt)) {
1208 *status_flags |= E1000_RXD_STAT_VP;
1209 *vlan_tag = cpu_to_le16(net_rx_pkt_get_vlan_tag(pkt));
1210 trace_e1000e_rx_metadata_vlan(*vlan_tag);
1211 }
1212
1213 /* Packet parsing results */
1214 if ((core->mac[RXCSUM] & E1000_RXCSUM_PCSD) != 0) {
1215 if (rss_info->enabled) {
1216 *rss = cpu_to_le32(rss_info->hash);
1217 *mrq = cpu_to_le32(rss_info->type | (rss_info->queue << 8));
1218 trace_e1000e_rx_metadata_rss(*rss, *mrq);
1219 }
1220 } else if (hasip4) {
1221 *status_flags |= E1000_RXD_STAT_IPIDV;
1222 *ip_id = cpu_to_le16(net_rx_pkt_get_ip_id(pkt));
1223 trace_e1000e_rx_metadata_ip_id(*ip_id);
1224 }
1225
1226 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP && e1000e_is_tcp_ack(core, pkt)) {
1227 *status_flags |= E1000_RXD_STAT_ACK;
1228 trace_e1000e_rx_metadata_ack();
1229 }
1230
1231 if (hasip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_DIS)) {
1232 trace_e1000e_rx_metadata_ipv6_filtering_disabled();
1233 pkt_type = E1000_RXD_PKT_MAC;
1234 } else if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP ||
1235 l4hdr_proto == ETH_L4_HDR_PROTO_UDP) {
1236 pkt_type = hasip4 ? E1000_RXD_PKT_IP4_XDP : E1000_RXD_PKT_IP6_XDP;
1237 } else if (hasip4 || hasip6) {
1238 pkt_type = hasip4 ? E1000_RXD_PKT_IP4 : E1000_RXD_PKT_IP6;
1239 } else {
1240 pkt_type = E1000_RXD_PKT_MAC;
1241 }
1242
1243 *status_flags |= E1000_RXD_PKT_TYPE(pkt_type);
1244 trace_e1000e_rx_metadata_pkt_type(pkt_type);
1245
1246 /* RX CSO information */
1247 if (hasip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_XSUM_DIS)) {
1248 trace_e1000e_rx_metadata_ipv6_sum_disabled();
1249 goto func_exit;
1250 }
1251
1252 vhdr = net_rx_pkt_get_vhdr(pkt);
1253
1254 if (!(vhdr->flags & VIRTIO_NET_HDR_F_DATA_VALID) &&
1255 !(vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM)) {
1256 trace_e1000e_rx_metadata_virthdr_no_csum_info();
1257 e1000e_verify_csum_in_sw(core, pkt, status_flags, l4hdr_proto);
1258 goto func_exit;
1259 }
1260
1261 if (e1000e_rx_l3_cso_enabled(core)) {
1262 *status_flags |= hasip4 ? E1000_RXD_STAT_IPCS : 0;
1263 } else {
1264 trace_e1000e_rx_metadata_l3_cso_disabled();
1265 }
1266
1267 if (e1000e_rx_l4_cso_enabled(core)) {
1268 switch (l4hdr_proto) {
1269 case ETH_L4_HDR_PROTO_TCP:
1270 *status_flags |= E1000_RXD_STAT_TCPCS;
1271 break;
1272
1273 case ETH_L4_HDR_PROTO_UDP:
1274 *status_flags |= E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS;
1275 break;
1276
1277 default:
1278 break;
1279 }
1280 } else {
1281 trace_e1000e_rx_metadata_l4_cso_disabled();
1282 }
1283
1284 trace_e1000e_rx_metadata_status_flags(*status_flags);
1285
1286 func_exit:
1287 *status_flags = cpu_to_le32(*status_flags);
1288 }
1289
1290 static inline void
1291 e1000e_write_lgcy_rx_descr(E1000ECore *core, struct e1000_rx_desc *desc,
1292 struct NetRxPkt *pkt,
1293 const E1000E_RSSInfo *rss_info,
1294 uint16_t length)
1295 {
1296 uint32_t status_flags, rss, mrq;
1297 uint16_t ip_id;
1298
1299 assert(!rss_info->enabled);
1300
1301 desc->length = cpu_to_le16(length);
1302 desc->csum = 0;
1303
1304 e1000e_build_rx_metadata(core, pkt, pkt != NULL,
1305 rss_info,
1306 &rss, &mrq,
1307 &status_flags, &ip_id,
1308 &desc->special);
1309 desc->errors = (uint8_t) (le32_to_cpu(status_flags) >> 24);
1310 desc->status = (uint8_t) le32_to_cpu(status_flags);
1311 }
1312
1313 static inline void
1314 e1000e_write_ext_rx_descr(E1000ECore *core, union e1000_rx_desc_extended *desc,
1315 struct NetRxPkt *pkt,
1316 const E1000E_RSSInfo *rss_info,
1317 uint16_t length)
1318 {
1319 memset(&desc->wb, 0, sizeof(desc->wb));
1320
1321 desc->wb.upper.length = cpu_to_le16(length);
1322
1323 e1000e_build_rx_metadata(core, pkt, pkt != NULL,
1324 rss_info,
1325 &desc->wb.lower.hi_dword.rss,
1326 &desc->wb.lower.mrq,
1327 &desc->wb.upper.status_error,
1328 &desc->wb.lower.hi_dword.csum_ip.ip_id,
1329 &desc->wb.upper.vlan);
1330 }
1331
1332 static inline void
1333 e1000e_write_ps_rx_descr(E1000ECore *core,
1334 union e1000_rx_desc_packet_split *desc,
1335 struct NetRxPkt *pkt,
1336 const E1000E_RSSInfo *rss_info,
1337 size_t ps_hdr_len,
1338 uint16_t(*written)[MAX_PS_BUFFERS])
1339 {
1340 int i;
1341
1342 memset(&desc->wb, 0, sizeof(desc->wb));
1343
1344 desc->wb.middle.length0 = cpu_to_le16((*written)[0]);
1345
1346 for (i = 0; i < PS_PAGE_BUFFERS; i++) {
1347 desc->wb.upper.length[i] = cpu_to_le16((*written)[i + 1]);
1348 }
1349
1350 e1000e_build_rx_metadata(core, pkt, pkt != NULL,
1351 rss_info,
1352 &desc->wb.lower.hi_dword.rss,
1353 &desc->wb.lower.mrq,
1354 &desc->wb.middle.status_error,
1355 &desc->wb.lower.hi_dword.csum_ip.ip_id,
1356 &desc->wb.middle.vlan);
1357
1358 desc->wb.upper.header_status =
1359 cpu_to_le16(ps_hdr_len | (ps_hdr_len ? E1000_RXDPS_HDRSTAT_HDRSP : 0));
1360
1361 trace_e1000e_rx_desc_ps_write((*written)[0], (*written)[1],
1362 (*written)[2], (*written)[3]);
1363 }
1364
1365 static inline void
1366 e1000e_write_rx_descr(E1000ECore *core, union e1000_rx_desc_union *desc,
1367 struct NetRxPkt *pkt, const E1000E_RSSInfo *rss_info,
1368 size_t ps_hdr_len, uint16_t(*written)[MAX_PS_BUFFERS])
1369 {
1370 if (e1000e_rx_use_legacy_descriptor(core)) {
1371 assert(ps_hdr_len == 0);
1372 e1000e_write_lgcy_rx_descr(core, &desc->legacy, pkt, rss_info,
1373 (*written)[0]);
1374 } else {
1375 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) {
1376 e1000e_write_ps_rx_descr(core, &desc->packet_split, pkt, rss_info,
1377 ps_hdr_len, written);
1378 } else {
1379 assert(ps_hdr_len == 0);
1380 e1000e_write_ext_rx_descr(core, &desc->extended, pkt, rss_info,
1381 (*written)[0]);
1382 }
1383 }
1384 }
1385
1386 static inline void
1387 e1000e_pci_dma_write_rx_desc(E1000ECore *core, dma_addr_t addr,
1388 union e1000_rx_desc_union *desc, dma_addr_t len)
1389 {
1390 PCIDevice *dev = core->owner;
1391
1392 if (e1000e_rx_use_legacy_descriptor(core)) {
1393 struct e1000_rx_desc *d = &desc->legacy;
1394 size_t offset = offsetof(struct e1000_rx_desc, status);
1395 uint8_t status = d->status;
1396
1397 d->status &= ~E1000_RXD_STAT_DD;
1398 pci_dma_write(dev, addr, desc, len);
1399
1400 if (status & E1000_RXD_STAT_DD) {
1401 d->status = status;
1402 pci_dma_write(dev, addr + offset, &status, sizeof(status));
1403 }
1404 } else {
1405 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) {
1406 union e1000_rx_desc_packet_split *d = &desc->packet_split;
1407 size_t offset = offsetof(union e1000_rx_desc_packet_split,
1408 wb.middle.status_error);
1409 uint32_t status = d->wb.middle.status_error;
1410
1411 d->wb.middle.status_error &= ~E1000_RXD_STAT_DD;
1412 pci_dma_write(dev, addr, desc, len);
1413
1414 if (status & E1000_RXD_STAT_DD) {
1415 d->wb.middle.status_error = status;
1416 pci_dma_write(dev, addr + offset, &status, sizeof(status));
1417 }
1418 } else {
1419 union e1000_rx_desc_extended *d = &desc->extended;
1420 size_t offset = offsetof(union e1000_rx_desc_extended,
1421 wb.upper.status_error);
1422 uint32_t status = d->wb.upper.status_error;
1423
1424 d->wb.upper.status_error &= ~E1000_RXD_STAT_DD;
1425 pci_dma_write(dev, addr, desc, len);
1426
1427 if (status & E1000_RXD_STAT_DD) {
1428 d->wb.upper.status_error = status;
1429 pci_dma_write(dev, addr + offset, &status, sizeof(status));
1430 }
1431 }
1432 }
1433 }
1434
1435 typedef struct e1000e_ba_state_st {
1436 uint16_t written[MAX_PS_BUFFERS];
1437 uint8_t cur_idx;
1438 } e1000e_ba_state;
1439
1440 static inline void
1441 e1000e_write_hdr_to_rx_buffers(E1000ECore *core,
1442 hwaddr ba[MAX_PS_BUFFERS],
1443 e1000e_ba_state *bastate,
1444 const char *data,
1445 dma_addr_t data_len)
1446 {
1447 assert(data_len <= core->rxbuf_sizes[0] - bastate->written[0]);
1448
1449 pci_dma_write(core->owner, ba[0] + bastate->written[0], data, data_len);
1450 bastate->written[0] += data_len;
1451
1452 bastate->cur_idx = 1;
1453 }
1454
1455 static void
1456 e1000e_write_to_rx_buffers(E1000ECore *core,
1457 hwaddr ba[MAX_PS_BUFFERS],
1458 e1000e_ba_state *bastate,
1459 const char *data,
1460 dma_addr_t data_len)
1461 {
1462 while (data_len > 0) {
1463 uint32_t cur_buf_len = core->rxbuf_sizes[bastate->cur_idx];
1464 uint32_t cur_buf_bytes_left = cur_buf_len -
1465 bastate->written[bastate->cur_idx];
1466 uint32_t bytes_to_write = MIN(data_len, cur_buf_bytes_left);
1467
1468 trace_e1000e_rx_desc_buff_write(bastate->cur_idx,
1469 ba[bastate->cur_idx],
1470 bastate->written[bastate->cur_idx],
1471 data,
1472 bytes_to_write);
1473
1474 pci_dma_write(core->owner,
1475 ba[bastate->cur_idx] + bastate->written[bastate->cur_idx],
1476 data, bytes_to_write);
1477
1478 bastate->written[bastate->cur_idx] += bytes_to_write;
1479 data += bytes_to_write;
1480 data_len -= bytes_to_write;
1481
1482 if (bastate->written[bastate->cur_idx] == cur_buf_len) {
1483 bastate->cur_idx++;
1484 }
1485
1486 assert(bastate->cur_idx < MAX_PS_BUFFERS);
1487 }
1488 }
1489
1490 static void
1491 e1000e_update_rx_stats(E1000ECore *core,
1492 size_t data_size,
1493 size_t data_fcs_size)
1494 {
1495 e1000x_update_rx_total_stats(core->mac, data_size, data_fcs_size);
1496
1497 switch (net_rx_pkt_get_packet_type(core->rx_pkt)) {
1498 case ETH_PKT_BCAST:
1499 e1000x_inc_reg_if_not_full(core->mac, BPRC);
1500 break;
1501
1502 case ETH_PKT_MCAST:
1503 e1000x_inc_reg_if_not_full(core->mac, MPRC);
1504 break;
1505
1506 default:
1507 break;
1508 }
1509 }
1510
1511 static inline bool
1512 e1000e_rx_descr_threshold_hit(E1000ECore *core, const E1000E_RingInfo *rxi)
1513 {
1514 return e1000e_ring_free_descr_num(core, rxi) ==
1515 e1000e_ring_len(core, rxi) >> core->rxbuf_min_shift;
1516 }
1517
1518 static bool
1519 e1000e_do_ps(E1000ECore *core, struct NetRxPkt *pkt, size_t *hdr_len)
1520 {
1521 bool hasip4, hasip6;
1522 EthL4HdrProto l4hdr_proto;
1523 bool fragment;
1524
1525 if (!e1000e_rx_use_ps_descriptor(core)) {
1526 return false;
1527 }
1528
1529 net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto);
1530
1531 if (hasip4) {
1532 fragment = net_rx_pkt_get_ip4_info(pkt)->fragment;
1533 } else if (hasip6) {
1534 fragment = net_rx_pkt_get_ip6_info(pkt)->fragment;
1535 } else {
1536 return false;
1537 }
1538
1539 if (fragment && (core->mac[RFCTL] & E1000_RFCTL_IPFRSP_DIS)) {
1540 return false;
1541 }
1542
1543 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP ||
1544 l4hdr_proto == ETH_L4_HDR_PROTO_UDP) {
1545 *hdr_len = net_rx_pkt_get_l5_hdr_offset(pkt);
1546 } else {
1547 *hdr_len = net_rx_pkt_get_l4_hdr_offset(pkt);
1548 }
1549
1550 if ((*hdr_len > core->rxbuf_sizes[0]) ||
1551 (*hdr_len > net_rx_pkt_get_total_len(pkt))) {
1552 return false;
1553 }
1554
1555 return true;
1556 }
1557
1558 static void
1559 e1000e_write_packet_to_guest(E1000ECore *core, struct NetRxPkt *pkt,
1560 const E1000E_RxRing *rxr,
1561 const E1000E_RSSInfo *rss_info)
1562 {
1563 PCIDevice *d = core->owner;
1564 dma_addr_t base;
1565 union e1000_rx_desc_union desc;
1566 size_t desc_size;
1567 size_t desc_offset = 0;
1568 size_t iov_ofs = 0;
1569
1570 struct iovec *iov = net_rx_pkt_get_iovec(pkt);
1571 size_t size = net_rx_pkt_get_total_len(pkt);
1572 size_t total_size = size + e1000x_fcs_len(core->mac);
1573 const E1000E_RingInfo *rxi;
1574 size_t ps_hdr_len = 0;
1575 bool do_ps = e1000e_do_ps(core, pkt, &ps_hdr_len);
1576 bool is_first = true;
1577
1578 rxi = rxr->i;
1579
1580 do {
1581 hwaddr ba[MAX_PS_BUFFERS];
1582 e1000e_ba_state bastate = { { 0 } };
1583 bool is_last = false;
1584
1585 desc_size = total_size - desc_offset;
1586
1587 if (desc_size > core->rx_desc_buf_size) {
1588 desc_size = core->rx_desc_buf_size;
1589 }
1590
1591 if (e1000e_ring_empty(core, rxi)) {
1592 return;
1593 }
1594
1595 base = e1000e_ring_head_descr(core, rxi);
1596
1597 pci_dma_read(d, base, &desc, core->rx_desc_len);
1598
1599 trace_e1000e_rx_descr(rxi->idx, base, core->rx_desc_len);
1600
1601 e1000e_read_rx_descr(core, &desc, ba);
1602
1603 if (ba[0]) {
1604 if (desc_offset < size) {
1605 static const uint32_t fcs_pad;
1606 size_t iov_copy;
1607 size_t copy_size = size - desc_offset;
1608 if (copy_size > core->rx_desc_buf_size) {
1609 copy_size = core->rx_desc_buf_size;
1610 }
1611
1612 /* For PS mode copy the packet header first */
1613 if (do_ps) {
1614 if (is_first) {
1615 size_t ps_hdr_copied = 0;
1616 do {
1617 iov_copy = MIN(ps_hdr_len - ps_hdr_copied,
1618 iov->iov_len - iov_ofs);
1619
1620 e1000e_write_hdr_to_rx_buffers(core, ba, &bastate,
1621 iov->iov_base, iov_copy);
1622
1623 copy_size -= iov_copy;
1624 ps_hdr_copied += iov_copy;
1625
1626 iov_ofs += iov_copy;
1627 if (iov_ofs == iov->iov_len) {
1628 iov++;
1629 iov_ofs = 0;
1630 }
1631 } while (ps_hdr_copied < ps_hdr_len);
1632
1633 is_first = false;
1634 } else {
1635 /* Leave buffer 0 of each descriptor except first */
1636 /* empty as per spec 7.1.5.1 */
1637 e1000e_write_hdr_to_rx_buffers(core, ba, &bastate,
1638 NULL, 0);
1639 }
1640 }
1641
1642 /* Copy packet payload */
1643 while (copy_size) {
1644 iov_copy = MIN(copy_size, iov->iov_len - iov_ofs);
1645
1646 e1000e_write_to_rx_buffers(core, ba, &bastate,
1647 iov->iov_base + iov_ofs, iov_copy);
1648
1649 copy_size -= iov_copy;
1650 iov_ofs += iov_copy;
1651 if (iov_ofs == iov->iov_len) {
1652 iov++;
1653 iov_ofs = 0;
1654 }
1655 }
1656
1657 if (desc_offset + desc_size >= total_size) {
1658 /* Simulate FCS checksum presence in the last descriptor */
1659 e1000e_write_to_rx_buffers(core, ba, &bastate,
1660 (const char *) &fcs_pad, e1000x_fcs_len(core->mac));
1661 }
1662 }
1663 } else { /* as per intel docs; skip descriptors with null buf addr */
1664 trace_e1000e_rx_null_descriptor();
1665 }
1666 desc_offset += desc_size;
1667 if (desc_offset >= total_size) {
1668 is_last = true;
1669 }
1670
1671 e1000e_write_rx_descr(core, &desc, is_last ? core->rx_pkt : NULL,
1672 rss_info, do_ps ? ps_hdr_len : 0, &bastate.written);
1673 e1000e_pci_dma_write_rx_desc(core, base, &desc, core->rx_desc_len);
1674
1675 e1000e_ring_advance(core, rxi,
1676 core->rx_desc_len / E1000_MIN_RX_DESC_LEN);
1677
1678 } while (desc_offset < total_size);
1679
1680 e1000e_update_rx_stats(core, size, total_size);
1681 }
1682
1683 static inline void
1684 e1000e_rx_fix_l4_csum(E1000ECore *core, struct NetRxPkt *pkt)
1685 {
1686 struct virtio_net_hdr *vhdr = net_rx_pkt_get_vhdr(pkt);
1687
1688 if (vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM) {
1689 net_rx_pkt_fix_l4_csum(pkt);
1690 }
1691 }
1692
1693 ssize_t
1694 e1000e_receive_iov(E1000ECore *core, const struct iovec *iov, int iovcnt)
1695 {
1696 return e1000e_receive_internal(core, iov, iovcnt, core->has_vnet);
1697 }
1698
1699 static ssize_t
1700 e1000e_receive_internal(E1000ECore *core, const struct iovec *iov, int iovcnt,
1701 bool has_vnet)
1702 {
1703 static const int maximum_ethernet_hdr_len = (ETH_HLEN + 4);
1704
1705 uint32_t n = 0;
1706 uint8_t min_buf[ETH_ZLEN];
1707 struct iovec min_iov;
1708 uint8_t *filter_buf;
1709 size_t size, orig_size;
1710 size_t iov_ofs = 0;
1711 E1000E_RxRing rxr;
1712 E1000E_RSSInfo rss_info;
1713 size_t total_size;
1714 ssize_t retval;
1715 bool rdmts_hit;
1716
1717 trace_e1000e_rx_receive_iov(iovcnt);
1718
1719 if (!e1000x_hw_rx_enabled(core->mac)) {
1720 return -1;
1721 }
1722
1723 /* Pull virtio header in */
1724 if (has_vnet) {
1725 net_rx_pkt_set_vhdr_iovec(core->rx_pkt, iov, iovcnt);
1726 iov_ofs = sizeof(struct virtio_net_hdr);
1727 } else {
1728 net_rx_pkt_unset_vhdr(core->rx_pkt);
1729 }
1730
1731 filter_buf = iov->iov_base + iov_ofs;
1732 orig_size = iov_size(iov, iovcnt);
1733 size = orig_size - iov_ofs;
1734
1735 /* Pad to minimum Ethernet frame length */
1736 if (size < sizeof(min_buf)) {
1737 iov_to_buf(iov, iovcnt, iov_ofs, min_buf, size);
1738 memset(&min_buf[size], 0, sizeof(min_buf) - size);
1739 e1000x_inc_reg_if_not_full(core->mac, RUC);
1740 min_iov.iov_base = filter_buf = min_buf;
1741 min_iov.iov_len = size = sizeof(min_buf);
1742 iovcnt = 1;
1743 iov = &min_iov;
1744 iov_ofs = 0;
1745 } else if (iov->iov_len < maximum_ethernet_hdr_len) {
1746 /* This is very unlikely, but may happen. */
1747 iov_to_buf(iov, iovcnt, iov_ofs, min_buf, maximum_ethernet_hdr_len);
1748 filter_buf = min_buf;
1749 }
1750
1751 /* Discard oversized packets if !LPE and !SBP. */
1752 if (e1000x_is_oversized(core->mac, size)) {
1753 return orig_size;
1754 }
1755
1756 net_rx_pkt_set_packet_type(core->rx_pkt,
1757 get_eth_packet_type(PKT_GET_ETH_HDR(filter_buf)));
1758
1759 if (!e1000e_receive_filter(core, filter_buf, size)) {
1760 trace_e1000e_rx_flt_dropped();
1761 return orig_size;
1762 }
1763
1764 net_rx_pkt_attach_iovec_ex(core->rx_pkt, iov, iovcnt, iov_ofs,
1765 e1000x_vlan_enabled(core->mac), core->mac[VET]);
1766
1767 e1000e_rss_parse_packet(core, core->rx_pkt, &rss_info);
1768 e1000e_rx_ring_init(core, &rxr, rss_info.queue);
1769
1770 total_size = net_rx_pkt_get_total_len(core->rx_pkt) +
1771 e1000x_fcs_len(core->mac);
1772
1773 if (e1000e_has_rxbufs(core, rxr.i, total_size)) {
1774 e1000e_rx_fix_l4_csum(core, core->rx_pkt);
1775
1776 e1000e_write_packet_to_guest(core, core->rx_pkt, &rxr, &rss_info);
1777
1778 retval = orig_size;
1779
1780 /* Perform small receive detection (RSRPD) */
1781 if (total_size < core->mac[RSRPD]) {
1782 n |= E1000_ICS_SRPD;
1783 }
1784
1785 /* Perform ACK receive detection */
1786 if (!(core->mac[RFCTL] & E1000_RFCTL_ACK_DIS) &&
1787 (e1000e_is_tcp_ack(core, core->rx_pkt))) {
1788 n |= E1000_ICS_ACK;
1789 }
1790
1791 /* Check if receive descriptor minimum threshold hit */
1792 rdmts_hit = e1000e_rx_descr_threshold_hit(core, rxr.i);
1793 n |= e1000e_rx_wb_interrupt_cause(core, rxr.i->idx, rdmts_hit);
1794
1795 trace_e1000e_rx_written_to_guest(rxr.i->idx);
1796 } else {
1797 n |= E1000_ICS_RXO;
1798 retval = 0;
1799
1800 trace_e1000e_rx_not_written_to_guest(rxr.i->idx);
1801 }
1802
1803 if (!e1000e_intrmgr_delay_rx_causes(core, &n)) {
1804 trace_e1000e_rx_interrupt_set(n);
1805 e1000e_set_interrupt_cause(core, n);
1806 } else {
1807 trace_e1000e_rx_interrupt_delayed(n);
1808 }
1809
1810 return retval;
1811 }
1812
1813 static inline bool
1814 e1000e_have_autoneg(E1000ECore *core)
1815 {
1816 return core->phy[0][MII_BMCR] & MII_BMCR_AUTOEN;
1817 }
1818
1819 static void e1000e_update_flowctl_status(E1000ECore *core)
1820 {
1821 if (e1000e_have_autoneg(core) &&
1822 core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP) {
1823 trace_e1000e_link_autoneg_flowctl(true);
1824 core->mac[CTRL] |= E1000_CTRL_TFCE | E1000_CTRL_RFCE;
1825 } else {
1826 trace_e1000e_link_autoneg_flowctl(false);
1827 }
1828 }
1829
1830 static inline void
1831 e1000e_link_down(E1000ECore *core)
1832 {
1833 e1000x_update_regs_on_link_down(core->mac, core->phy[0]);
1834 e1000e_update_flowctl_status(core);
1835 }
1836
1837 static inline void
1838 e1000e_set_phy_ctrl(E1000ECore *core, int index, uint16_t val)
1839 {
1840 /* bits 0-5 reserved; MII_BMCR_[ANRESTART,RESET] are self clearing */
1841 core->phy[0][MII_BMCR] = val & ~(0x3f |
1842 MII_BMCR_RESET |
1843 MII_BMCR_ANRESTART);
1844
1845 if ((val & MII_BMCR_ANRESTART) &&
1846 e1000e_have_autoneg(core)) {
1847 e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_timer);
1848 }
1849 }
1850
1851 static void
1852 e1000e_set_phy_oem_bits(E1000ECore *core, int index, uint16_t val)
1853 {
1854 core->phy[0][PHY_OEM_BITS] = val & ~BIT(10);
1855
1856 if (val & BIT(10)) {
1857 e1000x_restart_autoneg(core->mac, core->phy[0], core->autoneg_timer);
1858 }
1859 }
1860
1861 static void
1862 e1000e_set_phy_page(E1000ECore *core, int index, uint16_t val)
1863 {
1864 core->phy[0][PHY_PAGE] = val & PHY_PAGE_RW_MASK;
1865 }
1866
1867 void
1868 e1000e_core_set_link_status(E1000ECore *core)
1869 {
1870 NetClientState *nc = qemu_get_queue(core->owner_nic);
1871 uint32_t old_status = core->mac[STATUS];
1872
1873 trace_e1000e_link_status_changed(nc->link_down ? false : true);
1874
1875 if (nc->link_down) {
1876 e1000x_update_regs_on_link_down(core->mac, core->phy[0]);
1877 } else {
1878 if (e1000e_have_autoneg(core) &&
1879 !(core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP)) {
1880 e1000x_restart_autoneg(core->mac, core->phy[0],
1881 core->autoneg_timer);
1882 } else {
1883 e1000x_update_regs_on_link_up(core->mac, core->phy[0]);
1884 e1000e_start_recv(core);
1885 }
1886 }
1887
1888 if (core->mac[STATUS] != old_status) {
1889 e1000e_set_interrupt_cause(core, E1000_ICR_LSC);
1890 }
1891 }
1892
1893 static void
1894 e1000e_set_ctrl(E1000ECore *core, int index, uint32_t val)
1895 {
1896 trace_e1000e_core_ctrl_write(index, val);
1897
1898 /* RST is self clearing */
1899 core->mac[CTRL] = val & ~E1000_CTRL_RST;
1900 core->mac[CTRL_DUP] = core->mac[CTRL];
1901
1902 trace_e1000e_link_set_params(
1903 !!(val & E1000_CTRL_ASDE),
1904 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT,
1905 !!(val & E1000_CTRL_FRCSPD),
1906 !!(val & E1000_CTRL_FRCDPX),
1907 !!(val & E1000_CTRL_RFCE),
1908 !!(val & E1000_CTRL_TFCE));
1909
1910 if (val & E1000_CTRL_RST) {
1911 trace_e1000e_core_ctrl_sw_reset();
1912 e1000e_reset(core, true);
1913 }
1914
1915 if (val & E1000_CTRL_PHY_RST) {
1916 trace_e1000e_core_ctrl_phy_reset();
1917 core->mac[STATUS] |= E1000_STATUS_PHYRA;
1918 }
1919 }
1920
1921 static void
1922 e1000e_set_rfctl(E1000ECore *core, int index, uint32_t val)
1923 {
1924 trace_e1000e_rx_set_rfctl(val);
1925
1926 if (!(val & E1000_RFCTL_ISCSI_DIS)) {
1927 trace_e1000e_wrn_iscsi_filtering_not_supported();
1928 }
1929
1930 if (!(val & E1000_RFCTL_NFSW_DIS)) {
1931 trace_e1000e_wrn_nfsw_filtering_not_supported();
1932 }
1933
1934 if (!(val & E1000_RFCTL_NFSR_DIS)) {
1935 trace_e1000e_wrn_nfsr_filtering_not_supported();
1936 }
1937
1938 core->mac[RFCTL] = val;
1939 }
1940
1941 static void
1942 e1000e_calc_per_desc_buf_size(E1000ECore *core)
1943 {
1944 int i;
1945 core->rx_desc_buf_size = 0;
1946
1947 for (i = 0; i < ARRAY_SIZE(core->rxbuf_sizes); i++) {
1948 core->rx_desc_buf_size += core->rxbuf_sizes[i];
1949 }
1950 }
1951
1952 static void
1953 e1000e_parse_rxbufsize(E1000ECore *core)
1954 {
1955 uint32_t rctl = core->mac[RCTL];
1956
1957 memset(core->rxbuf_sizes, 0, sizeof(core->rxbuf_sizes));
1958
1959 if (rctl & E1000_RCTL_DTYP_MASK) {
1960 uint32_t bsize;
1961
1962 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE0_MASK;
1963 core->rxbuf_sizes[0] = (bsize >> E1000_PSRCTL_BSIZE0_SHIFT) * 128;
1964
1965 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE1_MASK;
1966 core->rxbuf_sizes[1] = (bsize >> E1000_PSRCTL_BSIZE1_SHIFT) * 1024;
1967
1968 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE2_MASK;
1969 core->rxbuf_sizes[2] = (bsize >> E1000_PSRCTL_BSIZE2_SHIFT) * 1024;
1970
1971 bsize = core->mac[PSRCTL] & E1000_PSRCTL_BSIZE3_MASK;
1972 core->rxbuf_sizes[3] = (bsize >> E1000_PSRCTL_BSIZE3_SHIFT) * 1024;
1973 } else if (rctl & E1000_RCTL_FLXBUF_MASK) {
1974 int flxbuf = rctl & E1000_RCTL_FLXBUF_MASK;
1975 core->rxbuf_sizes[0] = (flxbuf >> E1000_RCTL_FLXBUF_SHIFT) * 1024;
1976 } else {
1977 core->rxbuf_sizes[0] = e1000x_rxbufsize(rctl);
1978 }
1979
1980 trace_e1000e_rx_desc_buff_sizes(core->rxbuf_sizes[0], core->rxbuf_sizes[1],
1981 core->rxbuf_sizes[2], core->rxbuf_sizes[3]);
1982
1983 e1000e_calc_per_desc_buf_size(core);
1984 }
1985
1986 static void
1987 e1000e_calc_rxdesclen(E1000ECore *core)
1988 {
1989 if (e1000e_rx_use_legacy_descriptor(core)) {
1990 core->rx_desc_len = sizeof(struct e1000_rx_desc);
1991 } else {
1992 if (core->mac[RCTL] & E1000_RCTL_DTYP_PS) {
1993 core->rx_desc_len = sizeof(union e1000_rx_desc_packet_split);
1994 } else {
1995 core->rx_desc_len = sizeof(union e1000_rx_desc_extended);
1996 }
1997 }
1998 trace_e1000e_rx_desc_len(core->rx_desc_len);
1999 }
2000
2001 static void
2002 e1000e_set_rx_control(E1000ECore *core, int index, uint32_t val)
2003 {
2004 core->mac[RCTL] = val;
2005 trace_e1000e_rx_set_rctl(core->mac[RCTL]);
2006
2007 if (val & E1000_RCTL_EN) {
2008 e1000e_parse_rxbufsize(core);
2009 e1000e_calc_rxdesclen(core);
2010 core->rxbuf_min_shift = ((val / E1000_RCTL_RDMTS_QUAT) & 3) + 1 +
2011 E1000_RING_DESC_LEN_SHIFT;
2012
2013 e1000e_start_recv(core);
2014 }
2015 }
2016
2017 static
2018 void(*e1000e_phyreg_writeops[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE])
2019 (E1000ECore *, int, uint16_t) = {
2020 [0] = {
2021 [MII_BMCR] = e1000e_set_phy_ctrl,
2022 [PHY_PAGE] = e1000e_set_phy_page,
2023 [PHY_OEM_BITS] = e1000e_set_phy_oem_bits
2024 }
2025 };
2026
2027 static inline void
2028 e1000e_clear_ims_bits(E1000ECore *core, uint32_t bits)
2029 {
2030 trace_e1000e_irq_clear_ims(bits, core->mac[IMS], core->mac[IMS] & ~bits);
2031 core->mac[IMS] &= ~bits;
2032 }
2033
2034 static inline bool
2035 e1000e_postpone_interrupt(E1000IntrDelayTimer *timer)
2036 {
2037 if (timer->running) {
2038 trace_e1000e_irq_postponed_by_xitr(timer->delay_reg << 2);
2039
2040 return true;
2041 }
2042
2043 if (timer->core->mac[timer->delay_reg] != 0) {
2044 e1000e_intrmgr_rearm_timer(timer);
2045 }
2046
2047 return false;
2048 }
2049
2050 static inline bool
2051 e1000e_itr_should_postpone(E1000ECore *core)
2052 {
2053 return e1000e_postpone_interrupt(&core->itr);
2054 }
2055
2056 static inline bool
2057 e1000e_eitr_should_postpone(E1000ECore *core, int idx)
2058 {
2059 return e1000e_postpone_interrupt(&core->eitr[idx]);
2060 }
2061
2062 static void
2063 e1000e_msix_notify_one(E1000ECore *core, uint32_t cause, uint32_t int_cfg)
2064 {
2065 uint32_t effective_eiac;
2066
2067 if (E1000_IVAR_ENTRY_VALID(int_cfg)) {
2068 uint32_t vec = E1000_IVAR_ENTRY_VEC(int_cfg);
2069 if (vec < E1000E_MSIX_VEC_NUM) {
2070 if (!e1000e_eitr_should_postpone(core, vec)) {
2071 trace_e1000e_irq_msix_notify_vec(vec);
2072 msix_notify(core->owner, vec);
2073 }
2074 } else {
2075 trace_e1000e_wrn_msix_vec_wrong(cause, int_cfg);
2076 }
2077 } else {
2078 trace_e1000e_wrn_msix_invalid(cause, int_cfg);
2079 }
2080
2081 if (core->mac[CTRL_EXT] & E1000_CTRL_EXT_EIAME) {
2082 trace_e1000e_irq_iam_clear_eiame(core->mac[IAM], cause);
2083 core->mac[IAM] &= ~cause;
2084 }
2085
2086 trace_e1000e_irq_icr_clear_eiac(core->mac[ICR], core->mac[EIAC]);
2087
2088 effective_eiac = core->mac[EIAC] & cause;
2089
2090 core->mac[ICR] &= ~effective_eiac;
2091 core->msi_causes_pending &= ~effective_eiac;
2092
2093 if (!(core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) {
2094 core->mac[IMS] &= ~effective_eiac;
2095 }
2096 }
2097
2098 static void
2099 e1000e_msix_notify(E1000ECore *core, uint32_t causes)
2100 {
2101 if (causes & E1000_ICR_RXQ0) {
2102 e1000e_msix_notify_one(core, E1000_ICR_RXQ0,
2103 E1000_IVAR_RXQ0(core->mac[IVAR]));
2104 }
2105
2106 if (causes & E1000_ICR_RXQ1) {
2107 e1000e_msix_notify_one(core, E1000_ICR_RXQ1,
2108 E1000_IVAR_RXQ1(core->mac[IVAR]));
2109 }
2110
2111 if (causes & E1000_ICR_TXQ0) {
2112 e1000e_msix_notify_one(core, E1000_ICR_TXQ0,
2113 E1000_IVAR_TXQ0(core->mac[IVAR]));
2114 }
2115
2116 if (causes & E1000_ICR_TXQ1) {
2117 e1000e_msix_notify_one(core, E1000_ICR_TXQ1,
2118 E1000_IVAR_TXQ1(core->mac[IVAR]));
2119 }
2120
2121 if (causes & E1000_ICR_OTHER) {
2122 e1000e_msix_notify_one(core, E1000_ICR_OTHER,
2123 E1000_IVAR_OTHER(core->mac[IVAR]));
2124 }
2125 }
2126
2127 static void
2128 e1000e_msix_clear_one(E1000ECore *core, uint32_t cause, uint32_t int_cfg)
2129 {
2130 if (E1000_IVAR_ENTRY_VALID(int_cfg)) {
2131 uint32_t vec = E1000_IVAR_ENTRY_VEC(int_cfg);
2132 if (vec < E1000E_MSIX_VEC_NUM) {
2133 trace_e1000e_irq_msix_pending_clearing(cause, int_cfg, vec);
2134 msix_clr_pending(core->owner, vec);
2135 } else {
2136 trace_e1000e_wrn_msix_vec_wrong(cause, int_cfg);
2137 }
2138 } else {
2139 trace_e1000e_wrn_msix_invalid(cause, int_cfg);
2140 }
2141 }
2142
2143 static void
2144 e1000e_msix_clear(E1000ECore *core, uint32_t causes)
2145 {
2146 if (causes & E1000_ICR_RXQ0) {
2147 e1000e_msix_clear_one(core, E1000_ICR_RXQ0,
2148 E1000_IVAR_RXQ0(core->mac[IVAR]));
2149 }
2150
2151 if (causes & E1000_ICR_RXQ1) {
2152 e1000e_msix_clear_one(core, E1000_ICR_RXQ1,
2153 E1000_IVAR_RXQ1(core->mac[IVAR]));
2154 }
2155
2156 if (causes & E1000_ICR_TXQ0) {
2157 e1000e_msix_clear_one(core, E1000_ICR_TXQ0,
2158 E1000_IVAR_TXQ0(core->mac[IVAR]));
2159 }
2160
2161 if (causes & E1000_ICR_TXQ1) {
2162 e1000e_msix_clear_one(core, E1000_ICR_TXQ1,
2163 E1000_IVAR_TXQ1(core->mac[IVAR]));
2164 }
2165
2166 if (causes & E1000_ICR_OTHER) {
2167 e1000e_msix_clear_one(core, E1000_ICR_OTHER,
2168 E1000_IVAR_OTHER(core->mac[IVAR]));
2169 }
2170 }
2171
2172 static inline void
2173 e1000e_fix_icr_asserted(E1000ECore *core)
2174 {
2175 core->mac[ICR] &= ~E1000_ICR_ASSERTED;
2176 if (core->mac[ICR]) {
2177 core->mac[ICR] |= E1000_ICR_ASSERTED;
2178 }
2179
2180 trace_e1000e_irq_fix_icr_asserted(core->mac[ICR]);
2181 }
2182
2183 static void
2184 e1000e_send_msi(E1000ECore *core, bool msix)
2185 {
2186 uint32_t causes = core->mac[ICR] & core->mac[IMS] & ~E1000_ICR_ASSERTED;
2187
2188 core->msi_causes_pending &= causes;
2189 causes ^= core->msi_causes_pending;
2190 if (causes == 0) {
2191 return;
2192 }
2193 core->msi_causes_pending |= causes;
2194
2195 if (msix) {
2196 e1000e_msix_notify(core, causes);
2197 } else {
2198 if (!e1000e_itr_should_postpone(core)) {
2199 trace_e1000e_irq_msi_notify(causes);
2200 msi_notify(core->owner, 0);
2201 }
2202 }
2203 }
2204
2205 static void
2206 e1000e_update_interrupt_state(E1000ECore *core)
2207 {
2208 bool interrupts_pending;
2209 bool is_msix = msix_enabled(core->owner);
2210
2211 /* Set ICR[OTHER] for MSI-X */
2212 if (is_msix) {
2213 if (core->mac[ICR] & E1000_ICR_OTHER_CAUSES) {
2214 core->mac[ICR] |= E1000_ICR_OTHER;
2215 trace_e1000e_irq_add_msi_other(core->mac[ICR]);
2216 }
2217 }
2218
2219 e1000e_fix_icr_asserted(core);
2220
2221 /*
2222 * Make sure ICR and ICS registers have the same value.
2223 * The spec says that the ICS register is write-only. However in practice,
2224 * on real hardware ICS is readable, and for reads it has the same value as
2225 * ICR (except that ICS does not have the clear on read behaviour of ICR).
2226 *
2227 * The VxWorks PRO/1000 driver uses this behaviour.
2228 */
2229 core->mac[ICS] = core->mac[ICR];
2230
2231 interrupts_pending = (core->mac[IMS] & core->mac[ICR]) ? true : false;
2232 if (!interrupts_pending) {
2233 core->msi_causes_pending = 0;
2234 }
2235
2236 trace_e1000e_irq_pending_interrupts(core->mac[ICR] & core->mac[IMS],
2237 core->mac[ICR], core->mac[IMS]);
2238
2239 if (is_msix || msi_enabled(core->owner)) {
2240 if (interrupts_pending) {
2241 e1000e_send_msi(core, is_msix);
2242 }
2243 } else {
2244 if (interrupts_pending) {
2245 if (!e1000e_itr_should_postpone(core)) {
2246 e1000e_raise_legacy_irq(core);
2247 }
2248 } else {
2249 e1000e_lower_legacy_irq(core);
2250 }
2251 }
2252 }
2253
2254 static void
2255 e1000e_set_interrupt_cause(E1000ECore *core, uint32_t val)
2256 {
2257 trace_e1000e_irq_set_cause_entry(val, core->mac[ICR]);
2258
2259 val |= e1000e_intmgr_collect_delayed_causes(core);
2260 core->mac[ICR] |= val;
2261
2262 trace_e1000e_irq_set_cause_exit(val, core->mac[ICR]);
2263
2264 e1000e_update_interrupt_state(core);
2265 }
2266
2267 static inline void
2268 e1000e_autoneg_timer(void *opaque)
2269 {
2270 E1000ECore *core = opaque;
2271 if (!qemu_get_queue(core->owner_nic)->link_down) {
2272 e1000x_update_regs_on_autoneg_done(core->mac, core->phy[0]);
2273 e1000e_start_recv(core);
2274
2275 e1000e_update_flowctl_status(core);
2276 /* signal link status change to the guest */
2277 e1000e_set_interrupt_cause(core, E1000_ICR_LSC);
2278 }
2279 }
2280
2281 static inline uint16_t
2282 e1000e_get_reg_index_with_offset(const uint16_t *mac_reg_access, hwaddr addr)
2283 {
2284 uint16_t index = (addr & 0x1ffff) >> 2;
2285 return index + (mac_reg_access[index] & 0xfffe);
2286 }
2287
2288 static const char e1000e_phy_regcap[E1000E_PHY_PAGES][0x20] = {
2289 [0] = {
2290 [MII_BMCR] = PHY_ANYPAGE | PHY_RW,
2291 [MII_BMSR] = PHY_ANYPAGE | PHY_R,
2292 [MII_PHYID1] = PHY_ANYPAGE | PHY_R,
2293 [MII_PHYID2] = PHY_ANYPAGE | PHY_R,
2294 [MII_ANAR] = PHY_ANYPAGE | PHY_RW,
2295 [MII_ANLPAR] = PHY_ANYPAGE | PHY_R,
2296 [MII_ANER] = PHY_ANYPAGE | PHY_R,
2297 [MII_ANNP] = PHY_ANYPAGE | PHY_RW,
2298 [MII_ANLPRNP] = PHY_ANYPAGE | PHY_R,
2299 [MII_CTRL1000] = PHY_ANYPAGE | PHY_RW,
2300 [MII_STAT1000] = PHY_ANYPAGE | PHY_R,
2301 [MII_EXTSTAT] = PHY_ANYPAGE | PHY_R,
2302 [PHY_PAGE] = PHY_ANYPAGE | PHY_RW,
2303
2304 [PHY_COPPER_CTRL1] = PHY_RW,
2305 [PHY_COPPER_STAT1] = PHY_R,
2306 [PHY_COPPER_CTRL3] = PHY_RW,
2307 [PHY_RX_ERR_CNTR] = PHY_R,
2308 [PHY_OEM_BITS] = PHY_RW,
2309 [PHY_BIAS_1] = PHY_RW,
2310 [PHY_BIAS_2] = PHY_RW,
2311 [PHY_COPPER_INT_ENABLE] = PHY_RW,
2312 [PHY_COPPER_STAT2] = PHY_R,
2313 [PHY_COPPER_CTRL2] = PHY_RW
2314 },
2315 [2] = {
2316 [PHY_MAC_CTRL1] = PHY_RW,
2317 [PHY_MAC_INT_ENABLE] = PHY_RW,
2318 [PHY_MAC_STAT] = PHY_R,
2319 [PHY_MAC_CTRL2] = PHY_RW
2320 },
2321 [3] = {
2322 [PHY_LED_03_FUNC_CTRL1] = PHY_RW,
2323 [PHY_LED_03_POL_CTRL] = PHY_RW,
2324 [PHY_LED_TIMER_CTRL] = PHY_RW,
2325 [PHY_LED_45_CTRL] = PHY_RW
2326 },
2327 [5] = {
2328 [PHY_1000T_SKEW] = PHY_R,
2329 [PHY_1000T_SWAP] = PHY_R
2330 },
2331 [6] = {
2332 [PHY_CRC_COUNTERS] = PHY_R
2333 }
2334 };
2335
2336 static bool
2337 e1000e_phy_reg_check_cap(E1000ECore *core, uint32_t addr,
2338 char cap, uint8_t *page)
2339 {
2340 *page =
2341 (e1000e_phy_regcap[0][addr] & PHY_ANYPAGE) ? 0
2342 : core->phy[0][PHY_PAGE];
2343
2344 if (*page >= E1000E_PHY_PAGES) {
2345 return false;
2346 }
2347
2348 return e1000e_phy_regcap[*page][addr] & cap;
2349 }
2350
2351 static void
2352 e1000e_phy_reg_write(E1000ECore *core, uint8_t page,
2353 uint32_t addr, uint16_t data)
2354 {
2355 assert(page < E1000E_PHY_PAGES);
2356 assert(addr < E1000E_PHY_PAGE_SIZE);
2357
2358 if (e1000e_phyreg_writeops[page][addr]) {
2359 e1000e_phyreg_writeops[page][addr](core, addr, data);
2360 } else {
2361 core->phy[page][addr] = data;
2362 }
2363 }
2364
2365 static void
2366 e1000e_set_mdic(E1000ECore *core, int index, uint32_t val)
2367 {
2368 uint32_t data = val & E1000_MDIC_DATA_MASK;
2369 uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
2370 uint8_t page;
2371
2372 if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) { /* phy # */
2373 val = core->mac[MDIC] | E1000_MDIC_ERROR;
2374 } else if (val & E1000_MDIC_OP_READ) {
2375 if (!e1000e_phy_reg_check_cap(core, addr, PHY_R, &page)) {
2376 trace_e1000e_core_mdic_read_unhandled(page, addr);
2377 val |= E1000_MDIC_ERROR;
2378 } else {
2379 val = (val ^ data) | core->phy[page][addr];
2380 trace_e1000e_core_mdic_read(page, addr, val);
2381 }
2382 } else if (val & E1000_MDIC_OP_WRITE) {
2383 if (!e1000e_phy_reg_check_cap(core, addr, PHY_W, &page)) {
2384 trace_e1000e_core_mdic_write_unhandled(page, addr);
2385 val |= E1000_MDIC_ERROR;
2386 } else {
2387 trace_e1000e_core_mdic_write(page, addr, data);
2388 e1000e_phy_reg_write(core, page, addr, data);
2389 }
2390 }
2391 core->mac[MDIC] = val | E1000_MDIC_READY;
2392
2393 if (val & E1000_MDIC_INT_EN) {
2394 e1000e_set_interrupt_cause(core, E1000_ICR_MDAC);
2395 }
2396 }
2397
2398 static void
2399 e1000e_set_rdt(E1000ECore *core, int index, uint32_t val)
2400 {
2401 core->mac[index] = val & 0xffff;
2402 trace_e1000e_rx_set_rdt(e1000e_mq_queue_idx(RDT0, index), val);
2403 e1000e_start_recv(core);
2404 }
2405
2406 static void
2407 e1000e_set_status(E1000ECore *core, int index, uint32_t val)
2408 {
2409 if ((val & E1000_STATUS_PHYRA) == 0) {
2410 core->mac[index] &= ~E1000_STATUS_PHYRA;
2411 }
2412 }
2413
2414 static void
2415 e1000e_set_ctrlext(E1000ECore *core, int index, uint32_t val)
2416 {
2417 trace_e1000e_link_set_ext_params(!!(val & E1000_CTRL_EXT_ASDCHK),
2418 !!(val & E1000_CTRL_EXT_SPD_BYPS));
2419
2420 /* Zero self-clearing bits */
2421 val &= ~(E1000_CTRL_EXT_ASDCHK | E1000_CTRL_EXT_EE_RST);
2422 core->mac[CTRL_EXT] = val;
2423 }
2424
2425 static void
2426 e1000e_set_pbaclr(E1000ECore *core, int index, uint32_t val)
2427 {
2428 int i;
2429
2430 core->mac[PBACLR] = val & E1000_PBACLR_VALID_MASK;
2431
2432 if (!msix_enabled(core->owner)) {
2433 return;
2434 }
2435
2436 for (i = 0; i < E1000E_MSIX_VEC_NUM; i++) {
2437 if (core->mac[PBACLR] & BIT(i)) {
2438 msix_clr_pending(core->owner, i);
2439 }
2440 }
2441 }
2442
2443 static void
2444 e1000e_set_fcrth(E1000ECore *core, int index, uint32_t val)
2445 {
2446 core->mac[FCRTH] = val & 0xFFF8;
2447 }
2448
2449 static void
2450 e1000e_set_fcrtl(E1000ECore *core, int index, uint32_t val)
2451 {
2452 core->mac[FCRTL] = val & 0x8000FFF8;
2453 }
2454
2455 #define E1000E_LOW_BITS_SET_FUNC(num) \
2456 static void \
2457 e1000e_set_##num##bit(E1000ECore *core, int index, uint32_t val) \
2458 { \
2459 core->mac[index] = val & (BIT(num) - 1); \
2460 }
2461
2462 E1000E_LOW_BITS_SET_FUNC(4)
2463 E1000E_LOW_BITS_SET_FUNC(6)
2464 E1000E_LOW_BITS_SET_FUNC(11)
2465 E1000E_LOW_BITS_SET_FUNC(12)
2466 E1000E_LOW_BITS_SET_FUNC(13)
2467 E1000E_LOW_BITS_SET_FUNC(16)
2468
2469 static void
2470 e1000e_set_vet(E1000ECore *core, int index, uint32_t val)
2471 {
2472 core->mac[VET] = val & 0xffff;
2473 trace_e1000e_vlan_vet(core->mac[VET]);
2474 }
2475
2476 static void
2477 e1000e_set_dlen(E1000ECore *core, int index, uint32_t val)
2478 {
2479 core->mac[index] = val & E1000_XDLEN_MASK;
2480 }
2481
2482 static void
2483 e1000e_set_dbal(E1000ECore *core, int index, uint32_t val)
2484 {
2485 core->mac[index] = val & E1000_XDBAL_MASK;
2486 }
2487
2488 static void
2489 e1000e_set_tctl(E1000ECore *core, int index, uint32_t val)
2490 {
2491 E1000E_TxRing txr;
2492 core->mac[index] = val;
2493
2494 if (core->mac[TARC0] & E1000_TARC_ENABLE) {
2495 e1000e_tx_ring_init(core, &txr, 0);
2496 e1000e_start_xmit(core, &txr);
2497 }
2498
2499 if (core->mac[TARC1] & E1000_TARC_ENABLE) {
2500 e1000e_tx_ring_init(core, &txr, 1);
2501 e1000e_start_xmit(core, &txr);
2502 }
2503 }
2504
2505 static void
2506 e1000e_set_tdt(E1000ECore *core, int index, uint32_t val)
2507 {
2508 E1000E_TxRing txr;
2509 int qidx = e1000e_mq_queue_idx(TDT, index);
2510 uint32_t tarc_reg = (qidx == 0) ? TARC0 : TARC1;
2511
2512 core->mac[index] = val & 0xffff;
2513
2514 if (core->mac[tarc_reg] & E1000_TARC_ENABLE) {
2515 e1000e_tx_ring_init(core, &txr, qidx);
2516 e1000e_start_xmit(core, &txr);
2517 }
2518 }
2519
2520 static void
2521 e1000e_set_ics(E1000ECore *core, int index, uint32_t val)
2522 {
2523 trace_e1000e_irq_write_ics(val);
2524 e1000e_set_interrupt_cause(core, val);
2525 }
2526
2527 static void
2528 e1000e_set_icr(E1000ECore *core, int index, uint32_t val)
2529 {
2530 uint32_t icr = 0;
2531 if ((core->mac[ICR] & E1000_ICR_ASSERTED) &&
2532 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) {
2533 trace_e1000e_irq_icr_process_iame();
2534 e1000e_clear_ims_bits(core, core->mac[IAM]);
2535 }
2536
2537 icr = core->mac[ICR] & ~val;
2538 /*
2539 * Windows driver expects that the "receive overrun" bit and other
2540 * ones to be cleared when the "Other" bit (#24) is cleared.
2541 */
2542 icr = (val & E1000_ICR_OTHER) ? (icr & ~E1000_ICR_OTHER_CAUSES) : icr;
2543 trace_e1000e_irq_icr_write(val, core->mac[ICR], icr);
2544 core->mac[ICR] = icr;
2545 e1000e_update_interrupt_state(core);
2546 }
2547
2548 static void
2549 e1000e_set_imc(E1000ECore *core, int index, uint32_t val)
2550 {
2551 trace_e1000e_irq_ims_clear_set_imc(val);
2552 e1000e_clear_ims_bits(core, val);
2553 e1000e_update_interrupt_state(core);
2554 }
2555
2556 static void
2557 e1000e_set_ims(E1000ECore *core, int index, uint32_t val)
2558 {
2559 static const uint32_t ims_ext_mask =
2560 E1000_IMS_RXQ0 | E1000_IMS_RXQ1 |
2561 E1000_IMS_TXQ0 | E1000_IMS_TXQ1 |
2562 E1000_IMS_OTHER;
2563
2564 static const uint32_t ims_valid_mask =
2565 E1000_IMS_TXDW | E1000_IMS_TXQE | E1000_IMS_LSC |
2566 E1000_IMS_RXDMT0 | E1000_IMS_RXO | E1000_IMS_RXT0 |
2567 E1000_IMS_MDAC | E1000_IMS_TXD_LOW | E1000_IMS_SRPD |
2568 E1000_IMS_ACK | E1000_IMS_MNG | E1000_IMS_RXQ0 |
2569 E1000_IMS_RXQ1 | E1000_IMS_TXQ0 | E1000_IMS_TXQ1 |
2570 E1000_IMS_OTHER;
2571
2572 uint32_t valid_val = val & ims_valid_mask;
2573
2574 trace_e1000e_irq_set_ims(val, core->mac[IMS], core->mac[IMS] | valid_val);
2575 core->mac[IMS] |= valid_val;
2576
2577 if ((valid_val & ims_ext_mask) &&
2578 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_PBA_CLR) &&
2579 msix_enabled(core->owner)) {
2580 e1000e_msix_clear(core, valid_val);
2581 }
2582
2583 if ((valid_val == ims_valid_mask) &&
2584 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_INT_TIMERS_CLEAR_ENA)) {
2585 trace_e1000e_irq_fire_all_timers(val);
2586 e1000e_intrmgr_fire_all_timers(core);
2587 }
2588
2589 e1000e_update_interrupt_state(core);
2590 }
2591
2592 static void
2593 e1000e_set_rdtr(E1000ECore *core, int index, uint32_t val)
2594 {
2595 e1000e_set_16bit(core, index, val);
2596
2597 if ((val & E1000_RDTR_FPD) && (core->rdtr.running)) {
2598 trace_e1000e_irq_rdtr_fpd_running();
2599 e1000e_intrmgr_fire_delayed_interrupts(core);
2600 } else {
2601 trace_e1000e_irq_rdtr_fpd_not_running();
2602 }
2603 }
2604
2605 static void
2606 e1000e_set_tidv(E1000ECore *core, int index, uint32_t val)
2607 {
2608 e1000e_set_16bit(core, index, val);
2609
2610 if ((val & E1000_TIDV_FPD) && (core->tidv.running)) {
2611 trace_e1000e_irq_tidv_fpd_running();
2612 e1000e_intrmgr_fire_delayed_interrupts(core);
2613 } else {
2614 trace_e1000e_irq_tidv_fpd_not_running();
2615 }
2616 }
2617
2618 static uint32_t
2619 e1000e_mac_readreg(E1000ECore *core, int index)
2620 {
2621 return core->mac[index];
2622 }
2623
2624 static uint32_t
2625 e1000e_mac_ics_read(E1000ECore *core, int index)
2626 {
2627 trace_e1000e_irq_read_ics(core->mac[ICS]);
2628 return core->mac[ICS];
2629 }
2630
2631 static uint32_t
2632 e1000e_mac_ims_read(E1000ECore *core, int index)
2633 {
2634 trace_e1000e_irq_read_ims(core->mac[IMS]);
2635 return core->mac[IMS];
2636 }
2637
2638 static uint32_t
2639 e1000e_mac_swsm_read(E1000ECore *core, int index)
2640 {
2641 uint32_t val = core->mac[SWSM];
2642 core->mac[SWSM] = val | E1000_SWSM_SMBI;
2643 return val;
2644 }
2645
2646 static uint32_t
2647 e1000e_mac_itr_read(E1000ECore *core, int index)
2648 {
2649 return core->itr_guest_value;
2650 }
2651
2652 static uint32_t
2653 e1000e_mac_eitr_read(E1000ECore *core, int index)
2654 {
2655 return core->eitr_guest_value[index - EITR];
2656 }
2657
2658 static uint32_t
2659 e1000e_mac_icr_read(E1000ECore *core, int index)
2660 {
2661 uint32_t ret = core->mac[ICR];
2662 trace_e1000e_irq_icr_read_entry(ret);
2663
2664 if (core->mac[IMS] == 0) {
2665 trace_e1000e_irq_icr_clear_zero_ims();
2666 core->mac[ICR] = 0;
2667 }
2668
2669 if (!msix_enabled(core->owner)) {
2670 trace_e1000e_irq_icr_clear_nonmsix_icr_read();
2671 core->mac[ICR] = 0;
2672 }
2673
2674 if ((core->mac[ICR] & E1000_ICR_ASSERTED) &&
2675 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) {
2676 trace_e1000e_irq_icr_clear_iame();
2677 core->mac[ICR] = 0;
2678 trace_e1000e_irq_icr_process_iame();
2679 e1000e_clear_ims_bits(core, core->mac[IAM]);
2680 }
2681
2682 trace_e1000e_irq_icr_read_exit(core->mac[ICR]);
2683 e1000e_update_interrupt_state(core);
2684 return ret;
2685 }
2686
2687 static uint32_t
2688 e1000e_mac_read_clr4(E1000ECore *core, int index)
2689 {
2690 uint32_t ret = core->mac[index];
2691
2692 core->mac[index] = 0;
2693 return ret;
2694 }
2695
2696 static uint32_t
2697 e1000e_mac_read_clr8(E1000ECore *core, int index)
2698 {
2699 uint32_t ret = core->mac[index];
2700
2701 core->mac[index] = 0;
2702 core->mac[index - 1] = 0;
2703 return ret;
2704 }
2705
2706 static uint32_t
2707 e1000e_get_ctrl(E1000ECore *core, int index)
2708 {
2709 uint32_t val = core->mac[CTRL];
2710
2711 trace_e1000e_link_read_params(
2712 !!(val & E1000_CTRL_ASDE),
2713 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT,
2714 !!(val & E1000_CTRL_FRCSPD),
2715 !!(val & E1000_CTRL_FRCDPX),
2716 !!(val & E1000_CTRL_RFCE),
2717 !!(val & E1000_CTRL_TFCE));
2718
2719 return val;
2720 }
2721
2722 static uint32_t
2723 e1000e_get_status(E1000ECore *core, int index)
2724 {
2725 uint32_t res = core->mac[STATUS];
2726
2727 if (!(core->mac[CTRL] & E1000_CTRL_GIO_MASTER_DISABLE)) {
2728 res |= E1000_STATUS_GIO_MASTER_ENABLE;
2729 }
2730
2731 if (core->mac[CTRL] & E1000_CTRL_FRCDPX) {
2732 res |= (core->mac[CTRL] & E1000_CTRL_FD) ? E1000_STATUS_FD : 0;
2733 } else {
2734 res |= E1000_STATUS_FD;
2735 }
2736
2737 if ((core->mac[CTRL] & E1000_CTRL_FRCSPD) ||
2738 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_SPD_BYPS)) {
2739 switch (core->mac[CTRL] & E1000_CTRL_SPD_SEL) {
2740 case E1000_CTRL_SPD_10:
2741 res |= E1000_STATUS_SPEED_10;
2742 break;
2743 case E1000_CTRL_SPD_100:
2744 res |= E1000_STATUS_SPEED_100;
2745 break;
2746 case E1000_CTRL_SPD_1000:
2747 default:
2748 res |= E1000_STATUS_SPEED_1000;
2749 break;
2750 }
2751 } else {
2752 res |= E1000_STATUS_SPEED_1000;
2753 }
2754
2755 trace_e1000e_link_status(
2756 !!(res & E1000_STATUS_LU),
2757 !!(res & E1000_STATUS_FD),
2758 (res & E1000_STATUS_SPEED_MASK) >> E1000_STATUS_SPEED_SHIFT,
2759 (res & E1000_STATUS_ASDV) >> E1000_STATUS_ASDV_SHIFT);
2760
2761 return res;
2762 }
2763
2764 static uint32_t
2765 e1000e_get_tarc(E1000ECore *core, int index)
2766 {
2767 return core->mac[index] & ((BIT(11) - 1) |
2768 BIT(27) |
2769 BIT(28) |
2770 BIT(29) |
2771 BIT(30));
2772 }
2773
2774 static void
2775 e1000e_mac_writereg(E1000ECore *core, int index, uint32_t val)
2776 {
2777 core->mac[index] = val;
2778 }
2779
2780 static void
2781 e1000e_mac_setmacaddr(E1000ECore *core, int index, uint32_t val)
2782 {
2783 uint32_t macaddr[2];
2784
2785 core->mac[index] = val;
2786
2787 macaddr[0] = cpu_to_le32(core->mac[RA]);
2788 macaddr[1] = cpu_to_le32(core->mac[RA + 1]);
2789 qemu_format_nic_info_str(qemu_get_queue(core->owner_nic),
2790 (uint8_t *) macaddr);
2791
2792 trace_e1000e_mac_set_sw(MAC_ARG(macaddr));
2793 }
2794
2795 static void
2796 e1000e_set_eecd(E1000ECore *core, int index, uint32_t val)
2797 {
2798 static const uint32_t ro_bits = E1000_EECD_PRES |
2799 E1000_EECD_AUTO_RD |
2800 E1000_EECD_SIZE_EX_MASK;
2801
2802 core->mac[EECD] = (core->mac[EECD] & ro_bits) | (val & ~ro_bits);
2803 }
2804
2805 static void
2806 e1000e_set_eerd(E1000ECore *core, int index, uint32_t val)
2807 {
2808 uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK;
2809 uint32_t flags = 0;
2810 uint32_t data = 0;
2811
2812 if ((addr < E1000E_EEPROM_SIZE) && (val & E1000_EERW_START)) {
2813 data = core->eeprom[addr];
2814 flags = E1000_EERW_DONE;
2815 }
2816
2817 core->mac[EERD] = flags |
2818 (addr << E1000_EERW_ADDR_SHIFT) |
2819 (data << E1000_EERW_DATA_SHIFT);
2820 }
2821
2822 static void
2823 e1000e_set_eewr(E1000ECore *core, int index, uint32_t val)
2824 {
2825 uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK;
2826 uint32_t data = (val >> E1000_EERW_DATA_SHIFT) & E1000_EERW_DATA_MASK;
2827 uint32_t flags = 0;
2828
2829 if ((addr < E1000E_EEPROM_SIZE) && (val & E1000_EERW_START)) {
2830 core->eeprom[addr] = data;
2831 flags = E1000_EERW_DONE;
2832 }
2833
2834 core->mac[EERD] = flags |
2835 (addr << E1000_EERW_ADDR_SHIFT) |
2836 (data << E1000_EERW_DATA_SHIFT);
2837 }
2838
2839 static void
2840 e1000e_set_rxdctl(E1000ECore *core, int index, uint32_t val)
2841 {
2842 core->mac[RXDCTL] = core->mac[RXDCTL1] = val;
2843 }
2844
2845 static void
2846 e1000e_set_itr(E1000ECore *core, int index, uint32_t val)
2847 {
2848 uint32_t interval = val & 0xffff;
2849
2850 trace_e1000e_irq_itr_set(val);
2851
2852 core->itr_guest_value = interval;
2853 core->mac[index] = MAX(interval, E1000E_MIN_XITR);
2854 }
2855
2856 static void
2857 e1000e_set_eitr(E1000ECore *core, int index, uint32_t val)
2858 {
2859 uint32_t interval = val & 0xffff;
2860 uint32_t eitr_num = index - EITR;
2861
2862 trace_e1000e_irq_eitr_set(eitr_num, val);
2863
2864 core->eitr_guest_value[eitr_num] = interval;
2865 core->mac[index] = MAX(interval, E1000E_MIN_XITR);
2866 }
2867
2868 static void
2869 e1000e_set_psrctl(E1000ECore *core, int index, uint32_t val)
2870 {
2871 if (core->mac[RCTL] & E1000_RCTL_DTYP_MASK) {
2872
2873 if ((val & E1000_PSRCTL_BSIZE0_MASK) == 0) {
2874 qemu_log_mask(LOG_GUEST_ERROR,
2875 "e1000e: PSRCTL.BSIZE0 cannot be zero");
2876 return;
2877 }
2878
2879 if ((val & E1000_PSRCTL_BSIZE1_MASK) == 0) {
2880 qemu_log_mask(LOG_GUEST_ERROR,
2881 "e1000e: PSRCTL.BSIZE1 cannot be zero");
2882 return;
2883 }
2884 }
2885
2886 core->mac[PSRCTL] = val;
2887 }
2888
2889 static void
2890 e1000e_update_rx_offloads(E1000ECore *core)
2891 {
2892 int cso_state = e1000e_rx_l4_cso_enabled(core);
2893
2894 trace_e1000e_rx_set_cso(cso_state);
2895
2896 if (core->has_vnet) {
2897 qemu_set_offload(qemu_get_queue(core->owner_nic)->peer,
2898 cso_state, 0, 0, 0, 0);
2899 }
2900 }
2901
2902 static void
2903 e1000e_set_rxcsum(E1000ECore *core, int index, uint32_t val)
2904 {
2905 core->mac[RXCSUM] = val;
2906 e1000e_update_rx_offloads(core);
2907 }
2908
2909 static void
2910 e1000e_set_gcr(E1000ECore *core, int index, uint32_t val)
2911 {
2912 uint32_t ro_bits = core->mac[GCR] & E1000_GCR_RO_BITS;
2913 core->mac[GCR] = (val & ~E1000_GCR_RO_BITS) | ro_bits;
2914 }
2915
2916 static uint32_t e1000e_get_systiml(E1000ECore *core, int index)
2917 {
2918 e1000x_timestamp(core->mac, core->timadj, SYSTIML, SYSTIMH);
2919 return core->mac[SYSTIML];
2920 }
2921
2922 static uint32_t e1000e_get_rxsatrh(E1000ECore *core, int index)
2923 {
2924 core->mac[TSYNCRXCTL] &= ~E1000_TSYNCRXCTL_VALID;
2925 return core->mac[RXSATRH];
2926 }
2927
2928 static uint32_t e1000e_get_txstmph(E1000ECore *core, int index)
2929 {
2930 core->mac[TSYNCTXCTL] &= ~E1000_TSYNCTXCTL_VALID;
2931 return core->mac[TXSTMPH];
2932 }
2933
2934 static void e1000e_set_timinca(E1000ECore *core, int index, uint32_t val)
2935 {
2936 e1000x_set_timinca(core->mac, &core->timadj, val);
2937 }
2938
2939 static void e1000e_set_timadjh(E1000ECore *core, int index, uint32_t val)
2940 {
2941 core->mac[TIMADJH] = val;
2942 core->timadj += core->mac[TIMADJL] | ((int64_t)core->mac[TIMADJH] << 32);
2943 }
2944
2945 #define e1000e_getreg(x) [x] = e1000e_mac_readreg
2946 typedef uint32_t (*readops)(E1000ECore *, int);
2947 static const readops e1000e_macreg_readops[] = {
2948 e1000e_getreg(PBA),
2949 e1000e_getreg(WUFC),
2950 e1000e_getreg(MANC),
2951 e1000e_getreg(TOTL),
2952 e1000e_getreg(RDT0),
2953 e1000e_getreg(RDBAH0),
2954 e1000e_getreg(TDBAL1),
2955 e1000e_getreg(RDLEN0),
2956 e1000e_getreg(RDH1),
2957 e1000e_getreg(LATECOL),
2958 e1000e_getreg(SEQEC),
2959 e1000e_getreg(XONTXC),
2960 e1000e_getreg(AIT),
2961 e1000e_getreg(TDFH),
2962 e1000e_getreg(TDFT),
2963 e1000e_getreg(TDFHS),
2964 e1000e_getreg(TDFTS),
2965 e1000e_getreg(TDFPC),
2966 e1000e_getreg(WUS),
2967 e1000e_getreg(PBS),
2968 e1000e_getreg(RDFH),
2969 e1000e_getreg(RDFT),
2970 e1000e_getreg(RDFHS),
2971 e1000e_getreg(RDFTS),
2972 e1000e_getreg(RDFPC),
2973 e1000e_getreg(GORCL),
2974 e1000e_getreg(MGTPRC),
2975 e1000e_getreg(EERD),
2976 e1000e_getreg(EIAC),
2977 e1000e_getreg(PSRCTL),
2978 e1000e_getreg(MANC2H),
2979 e1000e_getreg(RXCSUM),
2980 e1000e_getreg(GSCL_3),
2981 e1000e_getreg(GSCN_2),
2982 e1000e_getreg(RSRPD),
2983 e1000e_getreg(RDBAL1),
2984 e1000e_getreg(FCAH),
2985 e1000e_getreg(FCRTH),
2986 e1000e_getreg(FLOP),
2987 e1000e_getreg(FLASHT),
2988 e1000e_getreg(RXSTMPH),
2989 e1000e_getreg(TXSTMPL),
2990 e1000e_getreg(TIMADJL),
2991 e1000e_getreg(TXDCTL),
2992 e1000e_getreg(RDH0),
2993 e1000e_getreg(TDT1),
2994 e1000e_getreg(TNCRS),
2995 e1000e_getreg(RJC),
2996 e1000e_getreg(IAM),
2997 e1000e_getreg(GSCL_2),
2998 e1000e_getreg(RDBAH1),
2999 e1000e_getreg(FLSWDATA),
3000 e1000e_getreg(TIPG),
3001 e1000e_getreg(FLMNGCTL),
3002 e1000e_getreg(FLMNGCNT),
3003 e1000e_getreg(TSYNCTXCTL),
3004 e1000e_getreg(EXTCNF_SIZE),
3005 e1000e_getreg(EXTCNF_CTRL),
3006 e1000e_getreg(EEMNGDATA),
3007 e1000e_getreg(CTRL_EXT),
3008 e1000e_getreg(SYSTIMH),
3009 e1000e_getreg(EEMNGCTL),
3010 e1000e_getreg(FLMNGDATA),
3011 e1000e_getreg(TSYNCRXCTL),
3012 e1000e_getreg(TDH),
3013 e1000e_getreg(LEDCTL),
3014 e1000e_getreg(TCTL),
3015 e1000e_getreg(TDBAL),
3016 e1000e_getreg(TDLEN),
3017 e1000e_getreg(TDH1),
3018 e1000e_getreg(RADV),
3019 e1000e_getreg(ECOL),
3020 e1000e_getreg(DC),
3021 e1000e_getreg(RLEC),
3022 e1000e_getreg(XOFFTXC),
3023 e1000e_getreg(RFC),
3024 e1000e_getreg(RNBC),
3025 e1000e_getreg(MGTPTC),
3026 e1000e_getreg(TIMINCA),
3027 e1000e_getreg(RXCFGL),
3028 e1000e_getreg(MFUTP01),
3029 e1000e_getreg(FACTPS),
3030 e1000e_getreg(GSCL_1),
3031 e1000e_getreg(GSCN_0),
3032 e1000e_getreg(GCR2),
3033 e1000e_getreg(RDT1),
3034 e1000e_getreg(PBACLR),
3035 e1000e_getreg(FCTTV),
3036 e1000e_getreg(EEWR),
3037 e1000e_getreg(FLSWCTL),
3038 e1000e_getreg(RXDCTL1),
3039 e1000e_getreg(RXSATRL),
3040 e1000e_getreg(RXUDP),
3041 e1000e_getreg(TORL),
3042 e1000e_getreg(TDLEN1),
3043 e1000e_getreg(MCC),
3044 e1000e_getreg(WUC),
3045 e1000e_getreg(EECD),
3046 e1000e_getreg(MFUTP23),
3047 e1000e_getreg(RAID),
3048 e1000e_getreg(FCRTV),
3049 e1000e_getreg(TXDCTL1),
3050 e1000e_getreg(RCTL),
3051 e1000e_getreg(TDT),
3052 e1000e_getreg(MDIC),
3053 e1000e_getreg(FCRUC),
3054 e1000e_getreg(VET),
3055 e1000e_getreg(RDBAL0),
3056 e1000e_getreg(TDBAH1),
3057 e1000e_getreg(RDTR),
3058 e1000e_getreg(SCC),
3059 e1000e_getreg(COLC),
3060 e1000e_getreg(CEXTERR),
3061 e1000e_getreg(XOFFRXC),
3062 e1000e_getreg(IPAV),
3063 e1000e_getreg(GOTCL),
3064 e1000e_getreg(MGTPDC),
3065 e1000e_getreg(GCR),
3066 e1000e_getreg(IVAR),
3067 e1000e_getreg(POEMB),
3068 e1000e_getreg(MFVAL),
3069 e1000e_getreg(FUNCTAG),
3070 e1000e_getreg(GSCL_4),
3071 e1000e_getreg(GSCN_3),
3072 e1000e_getreg(MRQC),
3073 e1000e_getreg(RDLEN1),
3074 e1000e_getreg(FCT),
3075 e1000e_getreg(FLA),
3076 e1000e_getreg(FLOL),
3077 e1000e_getreg(RXDCTL),
3078 e1000e_getreg(RXSTMPL),
3079 e1000e_getreg(TIMADJH),
3080 e1000e_getreg(FCRTL),
3081 e1000e_getreg(TDBAH),
3082 e1000e_getreg(TADV),
3083 e1000e_getreg(XONRXC),
3084 e1000e_getreg(TSCTFC),
3085 e1000e_getreg(RFCTL),
3086 e1000e_getreg(GSCN_1),
3087 e1000e_getreg(FCAL),
3088 e1000e_getreg(FLSWCNT),
3089
3090 [TOTH] = e1000e_mac_read_clr8,
3091 [GOTCH] = e1000e_mac_read_clr8,
3092 [PRC64] = e1000e_mac_read_clr4,
3093 [PRC255] = e1000e_mac_read_clr4,
3094 [PRC1023] = e1000e_mac_read_clr4,
3095 [PTC64] = e1000e_mac_read_clr4,
3096 [PTC255] = e1000e_mac_read_clr4,
3097 [PTC1023] = e1000e_mac_read_clr4,
3098 [GPRC] = e1000e_mac_read_clr4,
3099 [TPT] = e1000e_mac_read_clr4,
3100 [RUC] = e1000e_mac_read_clr4,
3101 [BPRC] = e1000e_mac_read_clr4,
3102 [MPTC] = e1000e_mac_read_clr4,
3103 [IAC] = e1000e_mac_read_clr4,
3104 [ICR] = e1000e_mac_icr_read,
3105 [STATUS] = e1000e_get_status,
3106 [TARC0] = e1000e_get_tarc,
3107 [ICS] = e1000e_mac_ics_read,
3108 [TORH] = e1000e_mac_read_clr8,
3109 [GORCH] = e1000e_mac_read_clr8,
3110 [PRC127] = e1000e_mac_read_clr4,
3111 [PRC511] = e1000e_mac_read_clr4,
3112 [PRC1522] = e1000e_mac_read_clr4,
3113 [PTC127] = e1000e_mac_read_clr4,
3114 [PTC511] = e1000e_mac_read_clr4,
3115 [PTC1522] = e1000e_mac_read_clr4,
3116 [GPTC] = e1000e_mac_read_clr4,
3117 [TPR] = e1000e_mac_read_clr4,
3118 [ROC] = e1000e_mac_read_clr4,
3119 [MPRC] = e1000e_mac_read_clr4,
3120 [BPTC] = e1000e_mac_read_clr4,
3121 [TSCTC] = e1000e_mac_read_clr4,
3122 [ITR] = e1000e_mac_itr_read,
3123 [CTRL] = e1000e_get_ctrl,
3124 [TARC1] = e1000e_get_tarc,
3125 [SWSM] = e1000e_mac_swsm_read,
3126 [IMS] = e1000e_mac_ims_read,
3127 [SYSTIML] = e1000e_get_systiml,
3128 [RXSATRH] = e1000e_get_rxsatrh,
3129 [TXSTMPH] = e1000e_get_txstmph,
3130
3131 [CRCERRS ... MPC] = e1000e_mac_readreg,
3132 [IP6AT ... IP6AT + 3] = e1000e_mac_readreg,
3133 [IP4AT ... IP4AT + 6] = e1000e_mac_readreg,
3134 [RA ... RA + 31] = e1000e_mac_readreg,
3135 [WUPM ... WUPM + 31] = e1000e_mac_readreg,
3136 [MTA ... MTA + E1000_MC_TBL_SIZE - 1] = e1000e_mac_readreg,
3137 [VFTA ... VFTA + E1000_VLAN_FILTER_TBL_SIZE - 1] = e1000e_mac_readreg,
3138 [FFMT ... FFMT + 254] = e1000e_mac_readreg,
3139 [FFVT ... FFVT + 254] = e1000e_mac_readreg,
3140 [MDEF ... MDEF + 7] = e1000e_mac_readreg,
3141 [FFLT ... FFLT + 10] = e1000e_mac_readreg,
3142 [FTFT ... FTFT + 254] = e1000e_mac_readreg,
3143 [PBM ... PBM + 10239] = e1000e_mac_readreg,
3144 [RETA ... RETA + 31] = e1000e_mac_readreg,
3145 [RSSRK ... RSSRK + 31] = e1000e_mac_readreg,
3146 [MAVTV0 ... MAVTV3] = e1000e_mac_readreg,
3147 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = e1000e_mac_eitr_read
3148 };
3149 enum { E1000E_NREADOPS = ARRAY_SIZE(e1000e_macreg_readops) };
3150
3151 #define e1000e_putreg(x) [x] = e1000e_mac_writereg
3152 typedef void (*writeops)(E1000ECore *, int, uint32_t);
3153 static const writeops e1000e_macreg_writeops[] = {
3154 e1000e_putreg(PBA),
3155 e1000e_putreg(SWSM),
3156 e1000e_putreg(WUFC),
3157 e1000e_putreg(RDBAH1),
3158 e1000e_putreg(TDBAH),
3159 e1000e_putreg(TXDCTL),
3160 e1000e_putreg(RDBAH0),
3161 e1000e_putreg(LEDCTL),
3162 e1000e_putreg(FCAL),
3163 e1000e_putreg(FCRUC),
3164 e1000e_putreg(WUC),
3165 e1000e_putreg(WUS),
3166 e1000e_putreg(IPAV),
3167 e1000e_putreg(TDBAH1),
3168 e1000e_putreg(IAM),
3169 e1000e_putreg(EIAC),
3170 e1000e_putreg(IVAR),
3171 e1000e_putreg(TARC0),
3172 e1000e_putreg(TARC1),
3173 e1000e_putreg(FLSWDATA),
3174 e1000e_putreg(POEMB),
3175 e1000e_putreg(MFUTP01),
3176 e1000e_putreg(MFUTP23),
3177 e1000e_putreg(MANC),
3178 e1000e_putreg(MANC2H),
3179 e1000e_putreg(MFVAL),
3180 e1000e_putreg(EXTCNF_CTRL),
3181 e1000e_putreg(FACTPS),
3182 e1000e_putreg(FUNCTAG),
3183 e1000e_putreg(GSCL_1),
3184 e1000e_putreg(GSCL_2),
3185 e1000e_putreg(GSCL_3),
3186 e1000e_putreg(GSCL_4),
3187 e1000e_putreg(GSCN_0),
3188 e1000e_putreg(GSCN_1),
3189 e1000e_putreg(GSCN_2),
3190 e1000e_putreg(GSCN_3),
3191 e1000e_putreg(GCR2),
3192 e1000e_putreg(MRQC),
3193 e1000e_putreg(FLOP),
3194 e1000e_putreg(FLOL),
3195 e1000e_putreg(FLSWCTL),
3196 e1000e_putreg(FLSWCNT),
3197 e1000e_putreg(FLA),
3198 e1000e_putreg(RXDCTL1),
3199 e1000e_putreg(TXDCTL1),
3200 e1000e_putreg(TIPG),
3201 e1000e_putreg(RXSTMPH),
3202 e1000e_putreg(RXSTMPL),
3203 e1000e_putreg(RXSATRL),
3204 e1000e_putreg(RXSATRH),
3205 e1000e_putreg(TXSTMPL),
3206 e1000e_putreg(TXSTMPH),
3207 e1000e_putreg(SYSTIML),
3208 e1000e_putreg(SYSTIMH),
3209 e1000e_putreg(TIMADJL),
3210 e1000e_putreg(RXUDP),
3211 e1000e_putreg(RXCFGL),
3212 e1000e_putreg(TSYNCRXCTL),
3213 e1000e_putreg(TSYNCTXCTL),
3214 e1000e_putreg(EXTCNF_SIZE),
3215 e1000e_putreg(EEMNGCTL),
3216 e1000e_putreg(RA),
3217
3218 [TDH1] = e1000e_set_16bit,
3219 [TDT1] = e1000e_set_tdt,
3220 [TCTL] = e1000e_set_tctl,
3221 [TDT] = e1000e_set_tdt,
3222 [MDIC] = e1000e_set_mdic,
3223 [ICS] = e1000e_set_ics,
3224 [TDH] = e1000e_set_16bit,
3225 [RDH0] = e1000e_set_16bit,
3226 [RDT0] = e1000e_set_rdt,
3227 [IMC] = e1000e_set_imc,
3228 [IMS] = e1000e_set_ims,
3229 [ICR] = e1000e_set_icr,
3230 [EECD] = e1000e_set_eecd,
3231 [RCTL] = e1000e_set_rx_control,
3232 [CTRL] = e1000e_set_ctrl,
3233 [RDTR] = e1000e_set_rdtr,
3234 [RADV] = e1000e_set_16bit,
3235 [TADV] = e1000e_set_16bit,
3236 [ITR] = e1000e_set_itr,
3237 [EERD] = e1000e_set_eerd,
3238 [AIT] = e1000e_set_16bit,
3239 [TDFH] = e1000e_set_13bit,
3240 [TDFT] = e1000e_set_13bit,
3241 [TDFHS] = e1000e_set_13bit,
3242 [TDFTS] = e1000e_set_13bit,
3243 [TDFPC] = e1000e_set_13bit,
3244 [RDFH] = e1000e_set_13bit,
3245 [RDFHS] = e1000e_set_13bit,
3246 [RDFT] = e1000e_set_13bit,
3247 [RDFTS] = e1000e_set_13bit,
3248 [RDFPC] = e1000e_set_13bit,
3249 [PBS] = e1000e_set_6bit,
3250 [GCR] = e1000e_set_gcr,
3251 [PSRCTL] = e1000e_set_psrctl,
3252 [RXCSUM] = e1000e_set_rxcsum,
3253 [RAID] = e1000e_set_16bit,
3254 [RSRPD] = e1000e_set_12bit,
3255 [TIDV] = e1000e_set_tidv,
3256 [TDLEN1] = e1000e_set_dlen,
3257 [TDLEN] = e1000e_set_dlen,
3258 [RDLEN0] = e1000e_set_dlen,
3259 [RDLEN1] = e1000e_set_dlen,
3260 [TDBAL] = e1000e_set_dbal,
3261 [TDBAL1] = e1000e_set_dbal,
3262 [RDBAL0] = e1000e_set_dbal,
3263 [RDBAL1] = e1000e_set_dbal,
3264 [RDH1] = e1000e_set_16bit,
3265 [RDT1] = e1000e_set_rdt,
3266 [STATUS] = e1000e_set_status,
3267 [PBACLR] = e1000e_set_pbaclr,
3268 [CTRL_EXT] = e1000e_set_ctrlext,
3269 [FCAH] = e1000e_set_16bit,
3270 [FCT] = e1000e_set_16bit,
3271 [FCTTV] = e1000e_set_16bit,
3272 [FCRTV] = e1000e_set_16bit,
3273 [FCRTH] = e1000e_set_fcrth,
3274 [FCRTL] = e1000e_set_fcrtl,
3275 [VET] = e1000e_set_vet,
3276 [RXDCTL] = e1000e_set_rxdctl,
3277 [FLASHT] = e1000e_set_16bit,
3278 [EEWR] = e1000e_set_eewr,
3279 [CTRL_DUP] = e1000e_set_ctrl,
3280 [RFCTL] = e1000e_set_rfctl,
3281 [RA + 1] = e1000e_mac_setmacaddr,
3282 [TIMINCA] = e1000e_set_timinca,
3283 [TIMADJH] = e1000e_set_timadjh,
3284
3285 [IP6AT ... IP6AT + 3] = e1000e_mac_writereg,
3286 [IP4AT ... IP4AT + 6] = e1000e_mac_writereg,
3287 [RA + 2 ... RA + 31] = e1000e_mac_writereg,
3288 [WUPM ... WUPM + 31] = e1000e_mac_writereg,
3289 [MTA ... MTA + E1000_MC_TBL_SIZE - 1] = e1000e_mac_writereg,
3290 [VFTA ... VFTA + E1000_VLAN_FILTER_TBL_SIZE - 1] = e1000e_mac_writereg,
3291 [FFMT ... FFMT + 254] = e1000e_set_4bit,
3292 [FFVT ... FFVT + 254] = e1000e_mac_writereg,
3293 [PBM ... PBM + 10239] = e1000e_mac_writereg,
3294 [MDEF ... MDEF + 7] = e1000e_mac_writereg,
3295 [FFLT ... FFLT + 10] = e1000e_set_11bit,
3296 [FTFT ... FTFT + 254] = e1000e_mac_writereg,
3297 [RETA ... RETA + 31] = e1000e_mac_writereg,
3298 [RSSRK ... RSSRK + 31] = e1000e_mac_writereg,
3299 [MAVTV0 ... MAVTV3] = e1000e_mac_writereg,
3300 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = e1000e_set_eitr
3301 };
3302 enum { E1000E_NWRITEOPS = ARRAY_SIZE(e1000e_macreg_writeops) };
3303
3304 enum { MAC_ACCESS_PARTIAL = 1 };
3305
3306 /*
3307 * The array below combines alias offsets of the index values for the
3308 * MAC registers that have aliases, with the indication of not fully
3309 * implemented registers (lowest bit). This combination is possible
3310 * because all of the offsets are even.
3311 */
3312 static const uint16_t mac_reg_access[E1000E_MAC_SIZE] = {
3313 /* Alias index offsets */
3314 [FCRTL_A] = 0x07fe, [FCRTH_A] = 0x0802,
3315 [RDH0_A] = 0x09bc, [RDT0_A] = 0x09bc, [RDTR_A] = 0x09c6,
3316 [RDFH_A] = 0xe904, [RDFT_A] = 0xe904,
3317 [TDH_A] = 0x0cf8, [TDT_A] = 0x0cf8, [TIDV_A] = 0x0cf8,
3318 [TDFH_A] = 0xed00, [TDFT_A] = 0xed00,
3319 [RA_A ... RA_A + 31] = 0x14f0,
3320 [VFTA_A ... VFTA_A + E1000_VLAN_FILTER_TBL_SIZE - 1] = 0x1400,
3321 [RDBAL0_A ... RDLEN0_A] = 0x09bc,
3322 [TDBAL_A ... TDLEN_A] = 0x0cf8,
3323 /* Access options */
3324 [RDFH] = MAC_ACCESS_PARTIAL, [RDFT] = MAC_ACCESS_PARTIAL,
3325 [RDFHS] = MAC_ACCESS_PARTIAL, [RDFTS] = MAC_ACCESS_PARTIAL,
3326 [RDFPC] = MAC_ACCESS_PARTIAL,
3327 [TDFH] = MAC_ACCESS_PARTIAL, [TDFT] = MAC_ACCESS_PARTIAL,
3328 [TDFHS] = MAC_ACCESS_PARTIAL, [TDFTS] = MAC_ACCESS_PARTIAL,
3329 [TDFPC] = MAC_ACCESS_PARTIAL, [EECD] = MAC_ACCESS_PARTIAL,
3330 [PBM] = MAC_ACCESS_PARTIAL, [FLA] = MAC_ACCESS_PARTIAL,
3331 [FCAL] = MAC_ACCESS_PARTIAL, [FCAH] = MAC_ACCESS_PARTIAL,
3332 [FCT] = MAC_ACCESS_PARTIAL, [FCTTV] = MAC_ACCESS_PARTIAL,
3333 [FCRTV] = MAC_ACCESS_PARTIAL, [FCRTL] = MAC_ACCESS_PARTIAL,
3334 [FCRTH] = MAC_ACCESS_PARTIAL, [TXDCTL] = MAC_ACCESS_PARTIAL,
3335 [TXDCTL1] = MAC_ACCESS_PARTIAL,
3336 [MAVTV0 ... MAVTV3] = MAC_ACCESS_PARTIAL
3337 };
3338
3339 void
3340 e1000e_core_write(E1000ECore *core, hwaddr addr, uint64_t val, unsigned size)
3341 {
3342 uint16_t index = e1000e_get_reg_index_with_offset(mac_reg_access, addr);
3343
3344 if (index < E1000E_NWRITEOPS && e1000e_macreg_writeops[index]) {
3345 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) {
3346 trace_e1000e_wrn_regs_write_trivial(index << 2);
3347 }
3348 trace_e1000e_core_write(index << 2, size, val);
3349 e1000e_macreg_writeops[index](core, index, val);
3350 } else if (index < E1000E_NREADOPS && e1000e_macreg_readops[index]) {
3351 trace_e1000e_wrn_regs_write_ro(index << 2, size, val);
3352 } else {
3353 trace_e1000e_wrn_regs_write_unknown(index << 2, size, val);
3354 }
3355 }
3356
3357 uint64_t
3358 e1000e_core_read(E1000ECore *core, hwaddr addr, unsigned size)
3359 {
3360 uint64_t val;
3361 uint16_t index = e1000e_get_reg_index_with_offset(mac_reg_access, addr);
3362
3363 if (index < E1000E_NREADOPS && e1000e_macreg_readops[index]) {
3364 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) {
3365 trace_e1000e_wrn_regs_read_trivial(index << 2);
3366 }
3367 val = e1000e_macreg_readops[index](core, index);
3368 trace_e1000e_core_read(index << 2, size, val);
3369 return val;
3370 } else {
3371 trace_e1000e_wrn_regs_read_unknown(index << 2, size);
3372 }
3373 return 0;
3374 }
3375
3376 static inline void
3377 e1000e_autoneg_pause(E1000ECore *core)
3378 {
3379 timer_del(core->autoneg_timer);
3380 }
3381
3382 static void
3383 e1000e_autoneg_resume(E1000ECore *core)
3384 {
3385 if (e1000e_have_autoneg(core) &&
3386 !(core->phy[0][MII_BMSR] & MII_BMSR_AN_COMP)) {
3387 qemu_get_queue(core->owner_nic)->link_down = false;
3388 timer_mod(core->autoneg_timer,
3389 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 500);
3390 }
3391 }
3392
3393 static void
3394 e1000e_vm_state_change(void *opaque, bool running, RunState state)
3395 {
3396 E1000ECore *core = opaque;
3397
3398 if (running) {
3399 trace_e1000e_vm_state_running();
3400 e1000e_intrmgr_resume(core);
3401 e1000e_autoneg_resume(core);
3402 } else {
3403 trace_e1000e_vm_state_stopped();
3404 e1000e_autoneg_pause(core);
3405 e1000e_intrmgr_pause(core);
3406 }
3407 }
3408
3409 void
3410 e1000e_core_pci_realize(E1000ECore *core,
3411 const uint16_t *eeprom_templ,
3412 uint32_t eeprom_size,
3413 const uint8_t *macaddr)
3414 {
3415 int i;
3416
3417 core->autoneg_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL,
3418 e1000e_autoneg_timer, core);
3419 e1000e_intrmgr_pci_realize(core);
3420
3421 core->vmstate =
3422 qemu_add_vm_change_state_handler(e1000e_vm_state_change, core);
3423
3424 for (i = 0; i < E1000E_NUM_QUEUES; i++) {
3425 net_tx_pkt_init(&core->tx[i].tx_pkt, core->owner, E1000E_MAX_TX_FRAGS);
3426 }
3427
3428 net_rx_pkt_init(&core->rx_pkt);
3429
3430 e1000x_core_prepare_eeprom(core->eeprom,
3431 eeprom_templ,
3432 eeprom_size,
3433 PCI_DEVICE_GET_CLASS(core->owner)->device_id,
3434 macaddr);
3435 e1000e_update_rx_offloads(core);
3436 }
3437
3438 void
3439 e1000e_core_pci_uninit(E1000ECore *core)
3440 {
3441 int i;
3442
3443 timer_free(core->autoneg_timer);
3444
3445 e1000e_intrmgr_pci_unint(core);
3446
3447 qemu_del_vm_change_state_handler(core->vmstate);
3448
3449 for (i = 0; i < E1000E_NUM_QUEUES; i++) {
3450 net_tx_pkt_reset(core->tx[i].tx_pkt, core->owner);
3451 net_tx_pkt_uninit(core->tx[i].tx_pkt);
3452 }
3453
3454 net_rx_pkt_uninit(core->rx_pkt);
3455 }
3456
3457 static const uint16_t
3458 e1000e_phy_reg_init[E1000E_PHY_PAGES][E1000E_PHY_PAGE_SIZE] = {
3459 [0] = {
3460 [MII_BMCR] = MII_BMCR_SPEED1000 |
3461 MII_BMCR_FD |
3462 MII_BMCR_AUTOEN,
3463
3464 [MII_BMSR] = MII_BMSR_EXTCAP |
3465 MII_BMSR_LINK_ST |
3466 MII_BMSR_AUTONEG |
3467 MII_BMSR_MFPS |
3468 MII_BMSR_EXTSTAT |
3469 MII_BMSR_10T_HD |
3470 MII_BMSR_10T_FD |
3471 MII_BMSR_100TX_HD |
3472 MII_BMSR_100TX_FD,
3473
3474 [MII_PHYID1] = 0x141,
3475 [MII_PHYID2] = E1000_PHY_ID2_82574x,
3476 [MII_ANAR] = MII_ANAR_CSMACD | MII_ANAR_10 |
3477 MII_ANAR_10FD | MII_ANAR_TX |
3478 MII_ANAR_TXFD | MII_ANAR_PAUSE |
3479 MII_ANAR_PAUSE_ASYM,
3480 [MII_ANLPAR] = MII_ANLPAR_10 | MII_ANLPAR_10FD |
3481 MII_ANLPAR_TX | MII_ANLPAR_TXFD |
3482 MII_ANLPAR_T4 | MII_ANLPAR_PAUSE,
3483 [MII_ANER] = MII_ANER_NP | MII_ANER_NWAY,
3484 [MII_ANNP] = 1 | MII_ANNP_MP,
3485 [MII_CTRL1000] = MII_CTRL1000_HALF | MII_CTRL1000_FULL |
3486 MII_CTRL1000_PORT | MII_CTRL1000_MASTER,
3487 [MII_STAT1000] = MII_STAT1000_HALF | MII_STAT1000_FULL |
3488 MII_STAT1000_ROK | MII_STAT1000_LOK,
3489 [MII_EXTSTAT] = MII_EXTSTAT_1000T_HD | MII_EXTSTAT_1000T_FD,
3490
3491 [PHY_COPPER_CTRL1] = BIT(5) | BIT(6) | BIT(8) | BIT(9) |
3492 BIT(12) | BIT(13),
3493 [PHY_COPPER_STAT1] = BIT(3) | BIT(10) | BIT(11) | BIT(13) | BIT(15)
3494 },
3495 [2] = {
3496 [PHY_MAC_CTRL1] = BIT(3) | BIT(7),
3497 [PHY_MAC_CTRL2] = BIT(1) | BIT(2) | BIT(6) | BIT(12)
3498 },
3499 [3] = {
3500 [PHY_LED_TIMER_CTRL] = BIT(0) | BIT(2) | BIT(14)
3501 }
3502 };
3503
3504 static const uint32_t e1000e_mac_reg_init[] = {
3505 [PBA] = 0x00140014,
3506 [LEDCTL] = BIT(1) | BIT(8) | BIT(9) | BIT(15) | BIT(17) | BIT(18),
3507 [EXTCNF_CTRL] = BIT(3),
3508 [EEMNGCTL] = BIT(31),
3509 [FLASHT] = 0x2,
3510 [FLSWCTL] = BIT(30) | BIT(31),
3511 [FLOL] = BIT(0),
3512 [RXDCTL] = BIT(16),
3513 [RXDCTL1] = BIT(16),
3514 [TIPG] = 0x8 | (0x8 << 10) | (0x6 << 20),
3515 [RXCFGL] = 0x88F7,
3516 [RXUDP] = 0x319,
3517 [CTRL] = E1000_CTRL_FD | E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN0 |
3518 E1000_CTRL_SPD_1000 | E1000_CTRL_SLU |
3519 E1000_CTRL_ADVD3WUC,
3520 [STATUS] = E1000_STATUS_ASDV_1000 | E1000_STATUS_LU,
3521 [PSRCTL] = (2 << E1000_PSRCTL_BSIZE0_SHIFT) |
3522 (4 << E1000_PSRCTL_BSIZE1_SHIFT) |
3523 (4 << E1000_PSRCTL_BSIZE2_SHIFT),
3524 [TARC0] = 0x3 | E1000_TARC_ENABLE,
3525 [TARC1] = 0x3 | E1000_TARC_ENABLE,
3526 [EECD] = E1000_EECD_AUTO_RD | E1000_EECD_PRES,
3527 [EERD] = E1000_EERW_DONE,
3528 [EEWR] = E1000_EERW_DONE,
3529 [GCR] = E1000_L0S_ADJUST |
3530 E1000_L1_ENTRY_LATENCY_MSB |
3531 E1000_L1_ENTRY_LATENCY_LSB,
3532 [TDFH] = 0x600,
3533 [TDFT] = 0x600,
3534 [TDFHS] = 0x600,
3535 [TDFTS] = 0x600,
3536 [POEMB] = 0x30D,
3537 [PBS] = 0x028,
3538 [MANC] = E1000_MANC_DIS_IP_CHK_ARP,
3539 [FACTPS] = E1000_FACTPS_LAN0_ON | 0x20000000,
3540 [SWSM] = 1,
3541 [RXCSUM] = E1000_RXCSUM_IPOFLD | E1000_RXCSUM_TUOFLD,
3542 [ITR] = E1000E_MIN_XITR,
3543 [EITR...EITR + E1000E_MSIX_VEC_NUM - 1] = E1000E_MIN_XITR,
3544 };
3545
3546 static void e1000e_reset(E1000ECore *core, bool sw)
3547 {
3548 int i;
3549
3550 timer_del(core->autoneg_timer);
3551
3552 e1000e_intrmgr_reset(core);
3553
3554 memset(core->phy, 0, sizeof core->phy);
3555 memcpy(core->phy, e1000e_phy_reg_init, sizeof e1000e_phy_reg_init);
3556
3557 for (i = 0; i < E1000E_MAC_SIZE; i++) {
3558 if (sw && (i == PBA || i == PBS || i == FLA)) {
3559 continue;
3560 }
3561
3562 core->mac[i] = i < ARRAY_SIZE(e1000e_mac_reg_init) ?
3563 e1000e_mac_reg_init[i] : 0;
3564 }
3565
3566 core->rxbuf_min_shift = 1 + E1000_RING_DESC_LEN_SHIFT;
3567
3568 if (qemu_get_queue(core->owner_nic)->link_down) {
3569 e1000e_link_down(core);
3570 }
3571
3572 e1000x_reset_mac_addr(core->owner_nic, core->mac, core->permanent_mac);
3573
3574 for (i = 0; i < ARRAY_SIZE(core->tx); i++) {
3575 net_tx_pkt_reset(core->tx[i].tx_pkt, core->owner);
3576 memset(&core->tx[i].props, 0, sizeof(core->tx[i].props));
3577 core->tx[i].skip_cp = false;
3578 }
3579 }
3580
3581 void
3582 e1000e_core_reset(E1000ECore *core)
3583 {
3584 e1000e_reset(core, false);
3585 }
3586
3587 void e1000e_core_pre_save(E1000ECore *core)
3588 {
3589 int i;
3590 NetClientState *nc = qemu_get_queue(core->owner_nic);
3591
3592 /*
3593 * If link is down and auto-negotiation is supported and ongoing,
3594 * complete auto-negotiation immediately. This allows us to look
3595 * at MII_BMSR_AN_COMP to infer link status on load.
3596 */
3597 if (nc->link_down && e1000e_have_autoneg(core)) {
3598 core->phy[0][MII_BMSR] |= MII_BMSR_AN_COMP;
3599 e1000e_update_flowctl_status(core);
3600 }
3601
3602 for (i = 0; i < ARRAY_SIZE(core->tx); i++) {
3603 if (net_tx_pkt_has_fragments(core->tx[i].tx_pkt)) {
3604 core->tx[i].skip_cp = true;
3605 }
3606 }
3607 }
3608
3609 int
3610 e1000e_core_post_load(E1000ECore *core)
3611 {
3612 NetClientState *nc = qemu_get_queue(core->owner_nic);
3613
3614 /*
3615 * nc.link_down can't be migrated, so infer link_down according
3616 * to link status bit in core.mac[STATUS].
3617 */
3618 nc->link_down = (core->mac[STATUS] & E1000_STATUS_LU) == 0;
3619
3620 return 0;
3621 }
QEMU mirror