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igb: check oversized packets for VMDq
[mirror_qemu.git] / hw / net / igb_core.c
1 /*
2 * Core code for QEMU igb emulation
3 *
4 * Datasheet:
5 * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/82576eg-gbe-datasheet.pdf
6 *
7 * Copyright (c) 2020-2023 Red Hat, Inc.
8 * Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com)
9 * Developed by Daynix Computing LTD (http://www.daynix.com)
10 *
11 * Authors:
12 * Akihiko Odaki <akihiko.odaki@daynix.com>
13 * Gal Hammmer <gal.hammer@sap.com>
14 * Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
15 * Dmitry Fleytman <dmitry@daynix.com>
16 * Leonid Bloch <leonid@daynix.com>
17 * Yan Vugenfirer <yan@daynix.com>
18 *
19 * Based on work done by:
20 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
21 * Copyright (c) 2008 Qumranet
22 * Based on work done by:
23 * Copyright (c) 2007 Dan Aloni
24 * Copyright (c) 2004 Antony T Curtis
25 *
26 * This library is free software; you can redistribute it and/or
27 * modify it under the terms of the GNU Lesser General Public
28 * License as published by the Free Software Foundation; either
29 * version 2.1 of the License, or (at your option) any later version.
30 *
31 * This library is distributed in the hope that it will be useful,
32 * but WITHOUT ANY WARRANTY; without even the implied warranty of
33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
34 * Lesser General Public License for more details.
35 *
36 * You should have received a copy of the GNU Lesser General Public
37 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
38 */
39
40 #include "qemu/osdep.h"
41 #include "qemu/log.h"
42 #include "net/net.h"
43 #include "net/tap.h"
44 #include "hw/net/mii.h"
45 #include "hw/pci/msi.h"
46 #include "hw/pci/msix.h"
47 #include "sysemu/runstate.h"
48
49 #include "net_tx_pkt.h"
50 #include "net_rx_pkt.h"
51
52 #include "igb_common.h"
53 #include "e1000x_common.h"
54 #include "igb_core.h"
55
56 #include "trace.h"
57
58 #define E1000E_MAX_TX_FRAGS (64)
59
60 union e1000_rx_desc_union {
61 struct e1000_rx_desc legacy;
62 union e1000_adv_rx_desc adv;
63 };
64
65 typedef struct IGBTxPktVmdqCallbackContext {
66 IGBCore *core;
67 NetClientState *nc;
68 } IGBTxPktVmdqCallbackContext;
69
70 static ssize_t
71 igb_receive_internal(IGBCore *core, const struct iovec *iov, int iovcnt,
72 bool has_vnet, bool *external_tx);
73
74 static inline void
75 igb_set_interrupt_cause(IGBCore *core, uint32_t val);
76
77 static void igb_update_interrupt_state(IGBCore *core);
78 static void igb_reset(IGBCore *core, bool sw);
79
80 static inline void
81 igb_raise_legacy_irq(IGBCore *core)
82 {
83 trace_e1000e_irq_legacy_notify(true);
84 e1000x_inc_reg_if_not_full(core->mac, IAC);
85 pci_set_irq(core->owner, 1);
86 }
87
88 static inline void
89 igb_lower_legacy_irq(IGBCore *core)
90 {
91 trace_e1000e_irq_legacy_notify(false);
92 pci_set_irq(core->owner, 0);
93 }
94
95 static void igb_msix_notify(IGBCore *core, unsigned int vector)
96 {
97 PCIDevice *dev = core->owner;
98 uint16_t vfn;
99
100 vfn = 8 - (vector + 2) / IGBVF_MSIX_VEC_NUM;
101 if (vfn < pcie_sriov_num_vfs(core->owner)) {
102 dev = pcie_sriov_get_vf_at_index(core->owner, vfn);
103 assert(dev);
104 vector = (vector + 2) % IGBVF_MSIX_VEC_NUM;
105 } else if (vector >= IGB_MSIX_VEC_NUM) {
106 qemu_log_mask(LOG_GUEST_ERROR,
107 "igb: Tried to use vector unavailable for PF");
108 return;
109 }
110
111 msix_notify(dev, vector);
112 }
113
114 static inline void
115 igb_intrmgr_rearm_timer(IGBIntrDelayTimer *timer)
116 {
117 int64_t delay_ns = (int64_t) timer->core->mac[timer->delay_reg] *
118 timer->delay_resolution_ns;
119
120 trace_e1000e_irq_rearm_timer(timer->delay_reg << 2, delay_ns);
121
122 timer_mod(timer->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + delay_ns);
123
124 timer->running = true;
125 }
126
127 static void
128 igb_intmgr_timer_resume(IGBIntrDelayTimer *timer)
129 {
130 if (timer->running) {
131 igb_intrmgr_rearm_timer(timer);
132 }
133 }
134
135 static void
136 igb_intmgr_timer_pause(IGBIntrDelayTimer *timer)
137 {
138 if (timer->running) {
139 timer_del(timer->timer);
140 }
141 }
142
143 static void
144 igb_intrmgr_on_msix_throttling_timer(void *opaque)
145 {
146 IGBIntrDelayTimer *timer = opaque;
147 int idx = timer - &timer->core->eitr[0];
148
149 timer->running = false;
150
151 trace_e1000e_irq_msix_notify_postponed_vec(idx);
152 igb_msix_notify(timer->core, idx);
153 }
154
155 static void
156 igb_intrmgr_initialize_all_timers(IGBCore *core, bool create)
157 {
158 int i;
159
160 for (i = 0; i < IGB_INTR_NUM; i++) {
161 core->eitr[i].core = core;
162 core->eitr[i].delay_reg = EITR0 + i;
163 core->eitr[i].delay_resolution_ns = E1000_INTR_DELAY_NS_RES;
164 }
165
166 if (!create) {
167 return;
168 }
169
170 for (i = 0; i < IGB_INTR_NUM; i++) {
171 core->eitr[i].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
172 igb_intrmgr_on_msix_throttling_timer,
173 &core->eitr[i]);
174 }
175 }
176
177 static void
178 igb_intrmgr_resume(IGBCore *core)
179 {
180 int i;
181
182 for (i = 0; i < IGB_INTR_NUM; i++) {
183 igb_intmgr_timer_resume(&core->eitr[i]);
184 }
185 }
186
187 static void
188 igb_intrmgr_pause(IGBCore *core)
189 {
190 int i;
191
192 for (i = 0; i < IGB_INTR_NUM; i++) {
193 igb_intmgr_timer_pause(&core->eitr[i]);
194 }
195 }
196
197 static void
198 igb_intrmgr_reset(IGBCore *core)
199 {
200 int i;
201
202 for (i = 0; i < IGB_INTR_NUM; i++) {
203 if (core->eitr[i].running) {
204 timer_del(core->eitr[i].timer);
205 igb_intrmgr_on_msix_throttling_timer(&core->eitr[i]);
206 }
207 }
208 }
209
210 static void
211 igb_intrmgr_pci_unint(IGBCore *core)
212 {
213 int i;
214
215 for (i = 0; i < IGB_INTR_NUM; i++) {
216 timer_free(core->eitr[i].timer);
217 }
218 }
219
220 static void
221 igb_intrmgr_pci_realize(IGBCore *core)
222 {
223 igb_intrmgr_initialize_all_timers(core, true);
224 }
225
226 static inline bool
227 igb_rx_csum_enabled(IGBCore *core)
228 {
229 return (core->mac[RXCSUM] & E1000_RXCSUM_PCSD) ? false : true;
230 }
231
232 static inline bool
233 igb_rx_use_legacy_descriptor(IGBCore *core)
234 {
235 /*
236 * TODO: If SRRCTL[n],DESCTYPE = 000b, the 82576 uses the legacy Rx
237 * descriptor.
238 */
239 return false;
240 }
241
242 static inline bool
243 igb_rss_enabled(IGBCore *core)
244 {
245 return (core->mac[MRQC] & 3) == E1000_MRQC_ENABLE_RSS_MQ &&
246 !igb_rx_csum_enabled(core) &&
247 !igb_rx_use_legacy_descriptor(core);
248 }
249
250 typedef struct E1000E_RSSInfo_st {
251 bool enabled;
252 uint32_t hash;
253 uint32_t queue;
254 uint32_t type;
255 } E1000E_RSSInfo;
256
257 static uint32_t
258 igb_rss_get_hash_type(IGBCore *core, struct NetRxPkt *pkt)
259 {
260 bool hasip4, hasip6;
261 EthL4HdrProto l4hdr_proto;
262
263 assert(igb_rss_enabled(core));
264
265 net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto);
266
267 if (hasip4) {
268 trace_e1000e_rx_rss_ip4(l4hdr_proto, core->mac[MRQC],
269 E1000_MRQC_EN_TCPIPV4(core->mac[MRQC]),
270 E1000_MRQC_EN_IPV4(core->mac[MRQC]));
271
272 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP &&
273 E1000_MRQC_EN_TCPIPV4(core->mac[MRQC])) {
274 return E1000_MRQ_RSS_TYPE_IPV4TCP;
275 }
276
277 if (E1000_MRQC_EN_IPV4(core->mac[MRQC])) {
278 return E1000_MRQ_RSS_TYPE_IPV4;
279 }
280 } else if (hasip6) {
281 eth_ip6_hdr_info *ip6info = net_rx_pkt_get_ip6_info(pkt);
282
283 bool ex_dis = core->mac[RFCTL] & E1000_RFCTL_IPV6_EX_DIS;
284 bool new_ex_dis = core->mac[RFCTL] & E1000_RFCTL_NEW_IPV6_EXT_DIS;
285
286 /*
287 * Following two traces must not be combined because resulting
288 * event will have 11 arguments totally and some trace backends
289 * (at least "ust") have limitation of maximum 10 arguments per
290 * event. Events with more arguments fail to compile for
291 * backends like these.
292 */
293 trace_e1000e_rx_rss_ip6_rfctl(core->mac[RFCTL]);
294 trace_e1000e_rx_rss_ip6(ex_dis, new_ex_dis, l4hdr_proto,
295 ip6info->has_ext_hdrs,
296 ip6info->rss_ex_dst_valid,
297 ip6info->rss_ex_src_valid,
298 core->mac[MRQC],
299 E1000_MRQC_EN_TCPIPV6(core->mac[MRQC]),
300 E1000_MRQC_EN_IPV6EX(core->mac[MRQC]),
301 E1000_MRQC_EN_IPV6(core->mac[MRQC]));
302
303 if ((!ex_dis || !ip6info->has_ext_hdrs) &&
304 (!new_ex_dis || !(ip6info->rss_ex_dst_valid ||
305 ip6info->rss_ex_src_valid))) {
306
307 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP &&
308 E1000_MRQC_EN_TCPIPV6(core->mac[MRQC])) {
309 return E1000_MRQ_RSS_TYPE_IPV6TCP;
310 }
311
312 if (E1000_MRQC_EN_IPV6EX(core->mac[MRQC])) {
313 return E1000_MRQ_RSS_TYPE_IPV6EX;
314 }
315
316 }
317
318 if (E1000_MRQC_EN_IPV6(core->mac[MRQC])) {
319 return E1000_MRQ_RSS_TYPE_IPV6;
320 }
321
322 }
323
324 return E1000_MRQ_RSS_TYPE_NONE;
325 }
326
327 static uint32_t
328 igb_rss_calc_hash(IGBCore *core, struct NetRxPkt *pkt, E1000E_RSSInfo *info)
329 {
330 NetRxPktRssType type;
331
332 assert(igb_rss_enabled(core));
333
334 switch (info->type) {
335 case E1000_MRQ_RSS_TYPE_IPV4:
336 type = NetPktRssIpV4;
337 break;
338 case E1000_MRQ_RSS_TYPE_IPV4TCP:
339 type = NetPktRssIpV4Tcp;
340 break;
341 case E1000_MRQ_RSS_TYPE_IPV6TCP:
342 type = NetPktRssIpV6TcpEx;
343 break;
344 case E1000_MRQ_RSS_TYPE_IPV6:
345 type = NetPktRssIpV6;
346 break;
347 case E1000_MRQ_RSS_TYPE_IPV6EX:
348 type = NetPktRssIpV6Ex;
349 break;
350 default:
351 assert(false);
352 return 0;
353 }
354
355 return net_rx_pkt_calc_rss_hash(pkt, type, (uint8_t *) &core->mac[RSSRK]);
356 }
357
358 static void
359 igb_rss_parse_packet(IGBCore *core, struct NetRxPkt *pkt, bool tx,
360 E1000E_RSSInfo *info)
361 {
362 trace_e1000e_rx_rss_started();
363
364 if (tx || !igb_rss_enabled(core)) {
365 info->enabled = false;
366 info->hash = 0;
367 info->queue = 0;
368 info->type = 0;
369 trace_e1000e_rx_rss_disabled();
370 return;
371 }
372
373 info->enabled = true;
374
375 info->type = igb_rss_get_hash_type(core, pkt);
376
377 trace_e1000e_rx_rss_type(info->type);
378
379 if (info->type == E1000_MRQ_RSS_TYPE_NONE) {
380 info->hash = 0;
381 info->queue = 0;
382 return;
383 }
384
385 info->hash = igb_rss_calc_hash(core, pkt, info);
386 info->queue = E1000_RSS_QUEUE(&core->mac[RETA], info->hash);
387 }
388
389 static bool
390 igb_setup_tx_offloads(IGBCore *core, struct igb_tx *tx)
391 {
392 if (tx->first_cmd_type_len & E1000_ADVTXD_DCMD_TSE) {
393 uint32_t idx = (tx->first_olinfo_status >> 4) & 1;
394 uint32_t mss = tx->ctx[idx].mss_l4len_idx >> 16;
395 if (!net_tx_pkt_build_vheader(tx->tx_pkt, true, true, mss)) {
396 return false;
397 }
398
399 net_tx_pkt_update_ip_checksums(tx->tx_pkt);
400 e1000x_inc_reg_if_not_full(core->mac, TSCTC);
401 return true;
402 }
403
404 if (tx->first_olinfo_status & E1000_ADVTXD_POTS_TXSM) {
405 if (!net_tx_pkt_build_vheader(tx->tx_pkt, false, true, 0)) {
406 return false;
407 }
408 }
409
410 if (tx->first_olinfo_status & E1000_ADVTXD_POTS_IXSM) {
411 net_tx_pkt_update_ip_hdr_checksum(tx->tx_pkt);
412 }
413
414 return true;
415 }
416
417 static void igb_tx_pkt_mac_callback(void *core,
418 const struct iovec *iov,
419 int iovcnt,
420 const struct iovec *virt_iov,
421 int virt_iovcnt)
422 {
423 igb_receive_internal(core, virt_iov, virt_iovcnt, true, NULL);
424 }
425
426 static void igb_tx_pkt_vmdq_callback(void *opaque,
427 const struct iovec *iov,
428 int iovcnt,
429 const struct iovec *virt_iov,
430 int virt_iovcnt)
431 {
432 IGBTxPktVmdqCallbackContext *context = opaque;
433 bool external_tx;
434
435 igb_receive_internal(context->core, virt_iov, virt_iovcnt, true,
436 &external_tx);
437
438 if (external_tx) {
439 if (context->core->has_vnet) {
440 qemu_sendv_packet(context->nc, virt_iov, virt_iovcnt);
441 } else {
442 qemu_sendv_packet(context->nc, iov, iovcnt);
443 }
444 }
445 }
446
447 /* TX Packets Switching (7.10.3.6) */
448 static bool igb_tx_pkt_switch(IGBCore *core, struct igb_tx *tx,
449 NetClientState *nc)
450 {
451 IGBTxPktVmdqCallbackContext context;
452
453 /* TX switching is only used to serve VM to VM traffic. */
454 if (!(core->mac[MRQC] & 1)) {
455 goto send_out;
456 }
457
458 /* TX switching requires DTXSWC.Loopback_en bit enabled. */
459 if (!(core->mac[DTXSWC] & E1000_DTXSWC_VMDQ_LOOPBACK_EN)) {
460 goto send_out;
461 }
462
463 context.core = core;
464 context.nc = nc;
465
466 return net_tx_pkt_send_custom(tx->tx_pkt, false,
467 igb_tx_pkt_vmdq_callback, &context);
468
469 send_out:
470 return net_tx_pkt_send(tx->tx_pkt, nc);
471 }
472
473 static bool
474 igb_tx_pkt_send(IGBCore *core, struct igb_tx *tx, int queue_index)
475 {
476 int target_queue = MIN(core->max_queue_num, queue_index);
477 NetClientState *queue = qemu_get_subqueue(core->owner_nic, target_queue);
478
479 if (!igb_setup_tx_offloads(core, tx)) {
480 return false;
481 }
482
483 net_tx_pkt_dump(tx->tx_pkt);
484
485 if ((core->phy[MII_BMCR] & MII_BMCR_LOOPBACK) ||
486 ((core->mac[RCTL] & E1000_RCTL_LBM_MAC) == E1000_RCTL_LBM_MAC)) {
487 return net_tx_pkt_send_custom(tx->tx_pkt, false,
488 igb_tx_pkt_mac_callback, core);
489 } else {
490 return igb_tx_pkt_switch(core, tx, queue);
491 }
492 }
493
494 static void
495 igb_on_tx_done_update_stats(IGBCore *core, struct NetTxPkt *tx_pkt)
496 {
497 static const int PTCregs[6] = { PTC64, PTC127, PTC255, PTC511,
498 PTC1023, PTC1522 };
499
500 size_t tot_len = net_tx_pkt_get_total_len(tx_pkt) + 4;
501
502 e1000x_increase_size_stats(core->mac, PTCregs, tot_len);
503 e1000x_inc_reg_if_not_full(core->mac, TPT);
504 e1000x_grow_8reg_if_not_full(core->mac, TOTL, tot_len);
505
506 switch (net_tx_pkt_get_packet_type(tx_pkt)) {
507 case ETH_PKT_BCAST:
508 e1000x_inc_reg_if_not_full(core->mac, BPTC);
509 break;
510 case ETH_PKT_MCAST:
511 e1000x_inc_reg_if_not_full(core->mac, MPTC);
512 break;
513 case ETH_PKT_UCAST:
514 break;
515 default:
516 g_assert_not_reached();
517 }
518
519 core->mac[GPTC] = core->mac[TPT];
520 core->mac[GOTCL] = core->mac[TOTL];
521 core->mac[GOTCH] = core->mac[TOTH];
522 }
523
524 static void
525 igb_process_tx_desc(IGBCore *core,
526 PCIDevice *dev,
527 struct igb_tx *tx,
528 union e1000_adv_tx_desc *tx_desc,
529 int queue_index)
530 {
531 struct e1000_adv_tx_context_desc *tx_ctx_desc;
532 uint32_t cmd_type_len;
533 uint32_t idx;
534 uint64_t buffer_addr;
535 uint16_t length;
536
537 cmd_type_len = le32_to_cpu(tx_desc->read.cmd_type_len);
538
539 if (cmd_type_len & E1000_ADVTXD_DCMD_DEXT) {
540 if ((cmd_type_len & E1000_ADVTXD_DTYP_DATA) ==
541 E1000_ADVTXD_DTYP_DATA) {
542 /* advanced transmit data descriptor */
543 if (tx->first) {
544 tx->first_cmd_type_len = cmd_type_len;
545 tx->first_olinfo_status = le32_to_cpu(tx_desc->read.olinfo_status);
546 tx->first = false;
547 }
548 } else if ((cmd_type_len & E1000_ADVTXD_DTYP_CTXT) ==
549 E1000_ADVTXD_DTYP_CTXT) {
550 /* advanced transmit context descriptor */
551 tx_ctx_desc = (struct e1000_adv_tx_context_desc *)tx_desc;
552 idx = (le32_to_cpu(tx_ctx_desc->mss_l4len_idx) >> 4) & 1;
553 tx->ctx[idx].vlan_macip_lens = le32_to_cpu(tx_ctx_desc->vlan_macip_lens);
554 tx->ctx[idx].seqnum_seed = le32_to_cpu(tx_ctx_desc->seqnum_seed);
555 tx->ctx[idx].type_tucmd_mlhl = le32_to_cpu(tx_ctx_desc->type_tucmd_mlhl);
556 tx->ctx[idx].mss_l4len_idx = le32_to_cpu(tx_ctx_desc->mss_l4len_idx);
557 return;
558 } else {
559 /* unknown descriptor type */
560 return;
561 }
562 } else {
563 /* legacy descriptor */
564
565 /* TODO: Implement a support for legacy descriptors (7.2.2.1). */
566 }
567
568 buffer_addr = le64_to_cpu(tx_desc->read.buffer_addr);
569 length = cmd_type_len & 0xFFFF;
570
571 if (!tx->skip_cp) {
572 if (!net_tx_pkt_add_raw_fragment(tx->tx_pkt, buffer_addr, length)) {
573 tx->skip_cp = true;
574 }
575 }
576
577 if (cmd_type_len & E1000_TXD_CMD_EOP) {
578 if (!tx->skip_cp && net_tx_pkt_parse(tx->tx_pkt)) {
579 if (cmd_type_len & E1000_TXD_CMD_VLE) {
580 idx = (tx->first_olinfo_status >> 4) & 1;
581 uint16_t vlan = tx->ctx[idx].vlan_macip_lens >> 16;
582 uint16_t vet = core->mac[VET] & 0xffff;
583 net_tx_pkt_setup_vlan_header_ex(tx->tx_pkt, vlan, vet);
584 }
585 if (igb_tx_pkt_send(core, tx, queue_index)) {
586 igb_on_tx_done_update_stats(core, tx->tx_pkt);
587 }
588 }
589
590 tx->first = true;
591 tx->skip_cp = false;
592 net_tx_pkt_reset(tx->tx_pkt, dev);
593 }
594 }
595
596 static uint32_t igb_tx_wb_eic(IGBCore *core, int queue_idx)
597 {
598 uint32_t n, ent = 0;
599
600 n = igb_ivar_entry_tx(queue_idx);
601 ent = (core->mac[IVAR0 + n / 4] >> (8 * (n % 4))) & 0xff;
602
603 return (ent & E1000_IVAR_VALID) ? BIT(ent & 0x1f) : 0;
604 }
605
606 static uint32_t igb_rx_wb_eic(IGBCore *core, int queue_idx)
607 {
608 uint32_t n, ent = 0;
609
610 n = igb_ivar_entry_rx(queue_idx);
611 ent = (core->mac[IVAR0 + n / 4] >> (8 * (n % 4))) & 0xff;
612
613 return (ent & E1000_IVAR_VALID) ? BIT(ent & 0x1f) : 0;
614 }
615
616 typedef struct E1000E_RingInfo_st {
617 int dbah;
618 int dbal;
619 int dlen;
620 int dh;
621 int dt;
622 int idx;
623 } E1000E_RingInfo;
624
625 static inline bool
626 igb_ring_empty(IGBCore *core, const E1000E_RingInfo *r)
627 {
628 return core->mac[r->dh] == core->mac[r->dt] ||
629 core->mac[r->dt] >= core->mac[r->dlen] / E1000_RING_DESC_LEN;
630 }
631
632 static inline uint64_t
633 igb_ring_base(IGBCore *core, const E1000E_RingInfo *r)
634 {
635 uint64_t bah = core->mac[r->dbah];
636 uint64_t bal = core->mac[r->dbal];
637
638 return (bah << 32) + bal;
639 }
640
641 static inline uint64_t
642 igb_ring_head_descr(IGBCore *core, const E1000E_RingInfo *r)
643 {
644 return igb_ring_base(core, r) + E1000_RING_DESC_LEN * core->mac[r->dh];
645 }
646
647 static inline void
648 igb_ring_advance(IGBCore *core, const E1000E_RingInfo *r, uint32_t count)
649 {
650 core->mac[r->dh] += count;
651
652 if (core->mac[r->dh] * E1000_RING_DESC_LEN >= core->mac[r->dlen]) {
653 core->mac[r->dh] = 0;
654 }
655 }
656
657 static inline uint32_t
658 igb_ring_free_descr_num(IGBCore *core, const E1000E_RingInfo *r)
659 {
660 trace_e1000e_ring_free_space(r->idx, core->mac[r->dlen],
661 core->mac[r->dh], core->mac[r->dt]);
662
663 if (core->mac[r->dh] <= core->mac[r->dt]) {
664 return core->mac[r->dt] - core->mac[r->dh];
665 }
666
667 if (core->mac[r->dh] > core->mac[r->dt]) {
668 return core->mac[r->dlen] / E1000_RING_DESC_LEN +
669 core->mac[r->dt] - core->mac[r->dh];
670 }
671
672 g_assert_not_reached();
673 return 0;
674 }
675
676 static inline bool
677 igb_ring_enabled(IGBCore *core, const E1000E_RingInfo *r)
678 {
679 return core->mac[r->dlen] > 0;
680 }
681
682 typedef struct IGB_TxRing_st {
683 const E1000E_RingInfo *i;
684 struct igb_tx *tx;
685 } IGB_TxRing;
686
687 static inline int
688 igb_mq_queue_idx(int base_reg_idx, int reg_idx)
689 {
690 return (reg_idx - base_reg_idx) / 16;
691 }
692
693 static inline void
694 igb_tx_ring_init(IGBCore *core, IGB_TxRing *txr, int idx)
695 {
696 static const E1000E_RingInfo i[IGB_NUM_QUEUES] = {
697 { TDBAH0, TDBAL0, TDLEN0, TDH0, TDT0, 0 },
698 { TDBAH1, TDBAL1, TDLEN1, TDH1, TDT1, 1 },
699 { TDBAH2, TDBAL2, TDLEN2, TDH2, TDT2, 2 },
700 { TDBAH3, TDBAL3, TDLEN3, TDH3, TDT3, 3 },
701 { TDBAH4, TDBAL4, TDLEN4, TDH4, TDT4, 4 },
702 { TDBAH5, TDBAL5, TDLEN5, TDH5, TDT5, 5 },
703 { TDBAH6, TDBAL6, TDLEN6, TDH6, TDT6, 6 },
704 { TDBAH7, TDBAL7, TDLEN7, TDH7, TDT7, 7 },
705 { TDBAH8, TDBAL8, TDLEN8, TDH8, TDT8, 8 },
706 { TDBAH9, TDBAL9, TDLEN9, TDH9, TDT9, 9 },
707 { TDBAH10, TDBAL10, TDLEN10, TDH10, TDT10, 10 },
708 { TDBAH11, TDBAL11, TDLEN11, TDH11, TDT11, 11 },
709 { TDBAH12, TDBAL12, TDLEN12, TDH12, TDT12, 12 },
710 { TDBAH13, TDBAL13, TDLEN13, TDH13, TDT13, 13 },
711 { TDBAH14, TDBAL14, TDLEN14, TDH14, TDT14, 14 },
712 { TDBAH15, TDBAL15, TDLEN15, TDH15, TDT15, 15 }
713 };
714
715 assert(idx < ARRAY_SIZE(i));
716
717 txr->i = &i[idx];
718 txr->tx = &core->tx[idx];
719 }
720
721 typedef struct E1000E_RxRing_st {
722 const E1000E_RingInfo *i;
723 } E1000E_RxRing;
724
725 static inline void
726 igb_rx_ring_init(IGBCore *core, E1000E_RxRing *rxr, int idx)
727 {
728 static const E1000E_RingInfo i[IGB_NUM_QUEUES] = {
729 { RDBAH0, RDBAL0, RDLEN0, RDH0, RDT0, 0 },
730 { RDBAH1, RDBAL1, RDLEN1, RDH1, RDT1, 1 },
731 { RDBAH2, RDBAL2, RDLEN2, RDH2, RDT2, 2 },
732 { RDBAH3, RDBAL3, RDLEN3, RDH3, RDT3, 3 },
733 { RDBAH4, RDBAL4, RDLEN4, RDH4, RDT4, 4 },
734 { RDBAH5, RDBAL5, RDLEN5, RDH5, RDT5, 5 },
735 { RDBAH6, RDBAL6, RDLEN6, RDH6, RDT6, 6 },
736 { RDBAH7, RDBAL7, RDLEN7, RDH7, RDT7, 7 },
737 { RDBAH8, RDBAL8, RDLEN8, RDH8, RDT8, 8 },
738 { RDBAH9, RDBAL9, RDLEN9, RDH9, RDT9, 9 },
739 { RDBAH10, RDBAL10, RDLEN10, RDH10, RDT10, 10 },
740 { RDBAH11, RDBAL11, RDLEN11, RDH11, RDT11, 11 },
741 { RDBAH12, RDBAL12, RDLEN12, RDH12, RDT12, 12 },
742 { RDBAH13, RDBAL13, RDLEN13, RDH13, RDT13, 13 },
743 { RDBAH14, RDBAL14, RDLEN14, RDH14, RDT14, 14 },
744 { RDBAH15, RDBAL15, RDLEN15, RDH15, RDT15, 15 }
745 };
746
747 assert(idx < ARRAY_SIZE(i));
748
749 rxr->i = &i[idx];
750 }
751
752 static uint32_t
753 igb_txdesc_writeback(IGBCore *core, dma_addr_t base,
754 union e1000_adv_tx_desc *tx_desc,
755 const E1000E_RingInfo *txi)
756 {
757 PCIDevice *d;
758 uint32_t cmd_type_len = le32_to_cpu(tx_desc->read.cmd_type_len);
759 uint64_t tdwba;
760
761 tdwba = core->mac[E1000_TDWBAL(txi->idx) >> 2];
762 tdwba |= (uint64_t)core->mac[E1000_TDWBAH(txi->idx) >> 2] << 32;
763
764 if (!(cmd_type_len & E1000_TXD_CMD_RS)) {
765 return 0;
766 }
767
768 d = pcie_sriov_get_vf_at_index(core->owner, txi->idx % 8);
769 if (!d) {
770 d = core->owner;
771 }
772
773 if (tdwba & 1) {
774 uint32_t buffer = cpu_to_le32(core->mac[txi->dh]);
775 pci_dma_write(d, tdwba & ~3, &buffer, sizeof(buffer));
776 } else {
777 uint32_t status = le32_to_cpu(tx_desc->wb.status) | E1000_TXD_STAT_DD;
778
779 tx_desc->wb.status = cpu_to_le32(status);
780 pci_dma_write(d, base + offsetof(union e1000_adv_tx_desc, wb),
781 &tx_desc->wb, sizeof(tx_desc->wb));
782 }
783
784 return igb_tx_wb_eic(core, txi->idx);
785 }
786
787 static inline bool
788 igb_tx_enabled(IGBCore *core, const E1000E_RingInfo *txi)
789 {
790 bool vmdq = core->mac[MRQC] & 1;
791 uint16_t qn = txi->idx;
792 uint16_t pool = qn % IGB_NUM_VM_POOLS;
793
794 return (core->mac[TCTL] & E1000_TCTL_EN) &&
795 (!vmdq || core->mac[VFTE] & BIT(pool)) &&
796 (core->mac[TXDCTL0 + (qn * 16)] & E1000_TXDCTL_QUEUE_ENABLE);
797 }
798
799 static void
800 igb_start_xmit(IGBCore *core, const IGB_TxRing *txr)
801 {
802 PCIDevice *d;
803 dma_addr_t base;
804 union e1000_adv_tx_desc desc;
805 const E1000E_RingInfo *txi = txr->i;
806 uint32_t eic = 0;
807
808 if (!igb_tx_enabled(core, txi)) {
809 trace_e1000e_tx_disabled();
810 return;
811 }
812
813 d = pcie_sriov_get_vf_at_index(core->owner, txi->idx % 8);
814 if (!d) {
815 d = core->owner;
816 }
817
818 net_tx_pkt_reset(txr->tx->tx_pkt, d);
819
820 while (!igb_ring_empty(core, txi)) {
821 base = igb_ring_head_descr(core, txi);
822
823 pci_dma_read(d, base, &desc, sizeof(desc));
824
825 trace_e1000e_tx_descr((void *)(intptr_t)desc.read.buffer_addr,
826 desc.read.cmd_type_len, desc.wb.status);
827
828 igb_process_tx_desc(core, d, txr->tx, &desc, txi->idx);
829 igb_ring_advance(core, txi, 1);
830 eic |= igb_txdesc_writeback(core, base, &desc, txi);
831 }
832
833 if (eic) {
834 core->mac[EICR] |= eic;
835 igb_set_interrupt_cause(core, E1000_ICR_TXDW);
836 }
837 }
838
839 static uint32_t
840 igb_rxbufsize(IGBCore *core, const E1000E_RingInfo *r)
841 {
842 uint32_t srrctl = core->mac[E1000_SRRCTL(r->idx) >> 2];
843 uint32_t bsizepkt = srrctl & E1000_SRRCTL_BSIZEPKT_MASK;
844 if (bsizepkt) {
845 return bsizepkt << E1000_SRRCTL_BSIZEPKT_SHIFT;
846 }
847
848 return e1000x_rxbufsize(core->mac[RCTL]);
849 }
850
851 static bool
852 igb_has_rxbufs(IGBCore *core, const E1000E_RingInfo *r, size_t total_size)
853 {
854 uint32_t bufs = igb_ring_free_descr_num(core, r);
855 uint32_t bufsize = igb_rxbufsize(core, r);
856
857 trace_e1000e_rx_has_buffers(r->idx, bufs, total_size, bufsize);
858
859 return total_size <= bufs / (core->rx_desc_len / E1000_MIN_RX_DESC_LEN) *
860 bufsize;
861 }
862
863 void
864 igb_start_recv(IGBCore *core)
865 {
866 int i;
867
868 trace_e1000e_rx_start_recv();
869
870 for (i = 0; i <= core->max_queue_num; i++) {
871 qemu_flush_queued_packets(qemu_get_subqueue(core->owner_nic, i));
872 }
873 }
874
875 bool
876 igb_can_receive(IGBCore *core)
877 {
878 int i;
879
880 if (!e1000x_rx_ready(core->owner, core->mac)) {
881 return false;
882 }
883
884 for (i = 0; i < IGB_NUM_QUEUES; i++) {
885 E1000E_RxRing rxr;
886 if (!(core->mac[RXDCTL0 + (i * 16)] & E1000_RXDCTL_QUEUE_ENABLE)) {
887 continue;
888 }
889
890 igb_rx_ring_init(core, &rxr, i);
891 if (igb_ring_enabled(core, rxr.i) && igb_has_rxbufs(core, rxr.i, 1)) {
892 trace_e1000e_rx_can_recv();
893 return true;
894 }
895 }
896
897 trace_e1000e_rx_can_recv_rings_full();
898 return false;
899 }
900
901 ssize_t
902 igb_receive(IGBCore *core, const uint8_t *buf, size_t size)
903 {
904 const struct iovec iov = {
905 .iov_base = (uint8_t *)buf,
906 .iov_len = size
907 };
908
909 return igb_receive_iov(core, &iov, 1);
910 }
911
912 static inline bool
913 igb_rx_l3_cso_enabled(IGBCore *core)
914 {
915 return !!(core->mac[RXCSUM] & E1000_RXCSUM_IPOFLD);
916 }
917
918 static inline bool
919 igb_rx_l4_cso_enabled(IGBCore *core)
920 {
921 return !!(core->mac[RXCSUM] & E1000_RXCSUM_TUOFLD);
922 }
923
924 static bool
925 igb_rx_is_oversized(IGBCore *core, uint16_t qn, size_t size)
926 {
927 uint16_t pool = qn % IGB_NUM_VM_POOLS;
928 bool lpe = !!(core->mac[VMOLR0 + pool] & E1000_VMOLR_LPE);
929 int max_ethernet_lpe_size =
930 core->mac[VMOLR0 + pool] & E1000_VMOLR_RLPML_MASK;
931 int max_ethernet_vlan_size = 1522;
932
933 return size > (lpe ? max_ethernet_lpe_size : max_ethernet_vlan_size);
934 }
935
936 static uint16_t igb_receive_assign(IGBCore *core, const struct eth_header *ehdr,
937 size_t size, E1000E_RSSInfo *rss_info,
938 bool *external_tx)
939 {
940 static const int ta_shift[] = { 4, 3, 2, 0 };
941 uint32_t f, ra[2], *macp, rctl = core->mac[RCTL];
942 uint16_t queues = 0;
943 uint16_t oversized = 0;
944 uint16_t vid = lduw_be_p(&PKT_GET_VLAN_HDR(ehdr)->h_tci) & VLAN_VID_MASK;
945 bool accepted = false;
946 int i;
947
948 memset(rss_info, 0, sizeof(E1000E_RSSInfo));
949
950 if (external_tx) {
951 *external_tx = true;
952 }
953
954 if (e1000x_is_vlan_packet(ehdr, core->mac[VET] & 0xffff) &&
955 e1000x_vlan_rx_filter_enabled(core->mac)) {
956 uint32_t vfta =
957 ldl_le_p((uint32_t *)(core->mac + VFTA) +
958 ((vid >> E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK));
959 if ((vfta & (1 << (vid & E1000_VFTA_ENTRY_BIT_SHIFT_MASK))) == 0) {
960 trace_e1000e_rx_flt_vlan_mismatch(vid);
961 return queues;
962 } else {
963 trace_e1000e_rx_flt_vlan_match(vid);
964 }
965 }
966
967 if (core->mac[MRQC] & 1) {
968 if (is_broadcast_ether_addr(ehdr->h_dest)) {
969 for (i = 0; i < IGB_NUM_VM_POOLS; i++) {
970 if (core->mac[VMOLR0 + i] & E1000_VMOLR_BAM) {
971 queues |= BIT(i);
972 }
973 }
974 } else {
975 for (macp = core->mac + RA; macp < core->mac + RA + 32; macp += 2) {
976 if (!(macp[1] & E1000_RAH_AV)) {
977 continue;
978 }
979 ra[0] = cpu_to_le32(macp[0]);
980 ra[1] = cpu_to_le32(macp[1]);
981 if (!memcmp(ehdr->h_dest, (uint8_t *)ra, ETH_ALEN)) {
982 queues |= (macp[1] & E1000_RAH_POOL_MASK) / E1000_RAH_POOL_1;
983 }
984 }
985
986 for (macp = core->mac + RA2; macp < core->mac + RA2 + 16; macp += 2) {
987 if (!(macp[1] & E1000_RAH_AV)) {
988 continue;
989 }
990 ra[0] = cpu_to_le32(macp[0]);
991 ra[1] = cpu_to_le32(macp[1]);
992 if (!memcmp(ehdr->h_dest, (uint8_t *)ra, ETH_ALEN)) {
993 queues |= (macp[1] & E1000_RAH_POOL_MASK) / E1000_RAH_POOL_1;
994 }
995 }
996
997 if (!queues) {
998 macp = core->mac + (is_multicast_ether_addr(ehdr->h_dest) ? MTA : UTA);
999
1000 f = ta_shift[(rctl >> E1000_RCTL_MO_SHIFT) & 3];
1001 f = (((ehdr->h_dest[5] << 8) | ehdr->h_dest[4]) >> f) & 0xfff;
1002 if (macp[f >> 5] & (1 << (f & 0x1f))) {
1003 for (i = 0; i < IGB_NUM_VM_POOLS; i++) {
1004 if (core->mac[VMOLR0 + i] & E1000_VMOLR_ROMPE) {
1005 queues |= BIT(i);
1006 }
1007 }
1008 }
1009 } else if (is_unicast_ether_addr(ehdr->h_dest) && external_tx) {
1010 *external_tx = false;
1011 }
1012 }
1013
1014 if (e1000x_vlan_rx_filter_enabled(core->mac)) {
1015 uint16_t mask = 0;
1016
1017 if (e1000x_is_vlan_packet(ehdr, core->mac[VET] & 0xffff)) {
1018 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
1019 if ((core->mac[VLVF0 + i] & E1000_VLVF_VLANID_MASK) == vid &&
1020 (core->mac[VLVF0 + i] & E1000_VLVF_VLANID_ENABLE)) {
1021 uint32_t poolsel = core->mac[VLVF0 + i] & E1000_VLVF_POOLSEL_MASK;
1022 mask |= poolsel >> E1000_VLVF_POOLSEL_SHIFT;
1023 }
1024 }
1025 } else {
1026 for (i = 0; i < IGB_NUM_VM_POOLS; i++) {
1027 if (core->mac[VMOLR0 + i] & E1000_VMOLR_AUPE) {
1028 mask |= BIT(i);
1029 }
1030 }
1031 }
1032
1033 queues &= mask;
1034 }
1035
1036 if (is_unicast_ether_addr(ehdr->h_dest) && !queues && !external_tx &&
1037 !(core->mac[VT_CTL] & E1000_VT_CTL_DISABLE_DEF_POOL)) {
1038 uint32_t def_pl = core->mac[VT_CTL] & E1000_VT_CTL_DEFAULT_POOL_MASK;
1039 queues = BIT(def_pl >> E1000_VT_CTL_DEFAULT_POOL_SHIFT);
1040 }
1041
1042 queues &= core->mac[VFRE];
1043 if (queues) {
1044 for (i = 0; i < IGB_NUM_VM_POOLS; i++) {
1045 if ((queues & BIT(i)) && igb_rx_is_oversized(core, i, size)) {
1046 oversized |= BIT(i);
1047 }
1048 }
1049 /* 8.19.37 increment ROC if packet is oversized for all queues */
1050 if (oversized == queues) {
1051 trace_e1000x_rx_oversized(size);
1052 e1000x_inc_reg_if_not_full(core->mac, ROC);
1053 }
1054 queues &= ~oversized;
1055 }
1056
1057 if (queues) {
1058 igb_rss_parse_packet(core, core->rx_pkt,
1059 external_tx != NULL, rss_info);
1060 if (rss_info->queue & 1) {
1061 queues <<= 8;
1062 }
1063 }
1064 } else {
1065 switch (net_rx_pkt_get_packet_type(core->rx_pkt)) {
1066 case ETH_PKT_UCAST:
1067 if (rctl & E1000_RCTL_UPE) {
1068 accepted = true; /* promiscuous ucast */
1069 }
1070 break;
1071
1072 case ETH_PKT_BCAST:
1073 if (rctl & E1000_RCTL_BAM) {
1074 accepted = true; /* broadcast enabled */
1075 }
1076 break;
1077
1078 case ETH_PKT_MCAST:
1079 if (rctl & E1000_RCTL_MPE) {
1080 accepted = true; /* promiscuous mcast */
1081 }
1082 break;
1083
1084 default:
1085 g_assert_not_reached();
1086 }
1087
1088 if (!accepted) {
1089 accepted = e1000x_rx_group_filter(core->mac, ehdr->h_dest);
1090 }
1091
1092 if (!accepted) {
1093 for (macp = core->mac + RA2; macp < core->mac + RA2 + 16; macp += 2) {
1094 if (!(macp[1] & E1000_RAH_AV)) {
1095 continue;
1096 }
1097 ra[0] = cpu_to_le32(macp[0]);
1098 ra[1] = cpu_to_le32(macp[1]);
1099 if (!memcmp(ehdr->h_dest, (uint8_t *)ra, ETH_ALEN)) {
1100 trace_e1000x_rx_flt_ucast_match((int)(macp - core->mac - RA2) / 2,
1101 MAC_ARG(ehdr->h_dest));
1102
1103 accepted = true;
1104 break;
1105 }
1106 }
1107 }
1108
1109 if (accepted) {
1110 igb_rss_parse_packet(core, core->rx_pkt, false, rss_info);
1111 queues = BIT(rss_info->queue);
1112 }
1113 }
1114
1115 return queues;
1116 }
1117
1118 static inline void
1119 igb_read_lgcy_rx_descr(IGBCore *core, struct e1000_rx_desc *desc,
1120 hwaddr *buff_addr)
1121 {
1122 *buff_addr = le64_to_cpu(desc->buffer_addr);
1123 }
1124
1125 static inline void
1126 igb_read_adv_rx_descr(IGBCore *core, union e1000_adv_rx_desc *desc,
1127 hwaddr *buff_addr)
1128 {
1129 *buff_addr = le64_to_cpu(desc->read.pkt_addr);
1130 }
1131
1132 static inline void
1133 igb_read_rx_descr(IGBCore *core, union e1000_rx_desc_union *desc,
1134 hwaddr *buff_addr)
1135 {
1136 if (igb_rx_use_legacy_descriptor(core)) {
1137 igb_read_lgcy_rx_descr(core, &desc->legacy, buff_addr);
1138 } else {
1139 igb_read_adv_rx_descr(core, &desc->adv, buff_addr);
1140 }
1141 }
1142
1143 static void
1144 igb_verify_csum_in_sw(IGBCore *core,
1145 struct NetRxPkt *pkt,
1146 uint32_t *status_flags,
1147 EthL4HdrProto l4hdr_proto)
1148 {
1149 bool csum_valid;
1150 uint32_t csum_error;
1151
1152 if (igb_rx_l3_cso_enabled(core)) {
1153 if (!net_rx_pkt_validate_l3_csum(pkt, &csum_valid)) {
1154 trace_e1000e_rx_metadata_l3_csum_validation_failed();
1155 } else {
1156 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_IPE;
1157 *status_flags |= E1000_RXD_STAT_IPCS | csum_error;
1158 }
1159 } else {
1160 trace_e1000e_rx_metadata_l3_cso_disabled();
1161 }
1162
1163 if (!igb_rx_l4_cso_enabled(core)) {
1164 trace_e1000e_rx_metadata_l4_cso_disabled();
1165 return;
1166 }
1167
1168 if (!net_rx_pkt_validate_l4_csum(pkt, &csum_valid)) {
1169 trace_e1000e_rx_metadata_l4_csum_validation_failed();
1170 return;
1171 }
1172
1173 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_TCPE;
1174 *status_flags |= E1000_RXD_STAT_TCPCS | csum_error;
1175
1176 if (l4hdr_proto == ETH_L4_HDR_PROTO_UDP) {
1177 *status_flags |= E1000_RXD_STAT_UDPCS;
1178 }
1179 }
1180
1181 static void
1182 igb_build_rx_metadata(IGBCore *core,
1183 struct NetRxPkt *pkt,
1184 bool is_eop,
1185 const E1000E_RSSInfo *rss_info,
1186 uint16_t *pkt_info, uint16_t *hdr_info,
1187 uint32_t *rss,
1188 uint32_t *status_flags,
1189 uint16_t *ip_id,
1190 uint16_t *vlan_tag)
1191 {
1192 struct virtio_net_hdr *vhdr;
1193 bool hasip4, hasip6;
1194 EthL4HdrProto l4hdr_proto;
1195 uint32_t pkt_type;
1196
1197 *status_flags = E1000_RXD_STAT_DD;
1198
1199 /* No additional metadata needed for non-EOP descriptors */
1200 /* TODO: EOP apply only to status so don't skip whole function. */
1201 if (!is_eop) {
1202 goto func_exit;
1203 }
1204
1205 *status_flags |= E1000_RXD_STAT_EOP;
1206
1207 net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto);
1208 trace_e1000e_rx_metadata_protocols(hasip4, hasip6, l4hdr_proto);
1209
1210 /* VLAN state */
1211 if (net_rx_pkt_is_vlan_stripped(pkt)) {
1212 *status_flags |= E1000_RXD_STAT_VP;
1213 *vlan_tag = cpu_to_le16(net_rx_pkt_get_vlan_tag(pkt));
1214 trace_e1000e_rx_metadata_vlan(*vlan_tag);
1215 }
1216
1217 /* Packet parsing results */
1218 if ((core->mac[RXCSUM] & E1000_RXCSUM_PCSD) != 0) {
1219 if (rss_info->enabled) {
1220 *rss = cpu_to_le32(rss_info->hash);
1221 trace_igb_rx_metadata_rss(*rss);
1222 }
1223 } else if (hasip4) {
1224 *status_flags |= E1000_RXD_STAT_IPIDV;
1225 *ip_id = cpu_to_le16(net_rx_pkt_get_ip_id(pkt));
1226 trace_e1000e_rx_metadata_ip_id(*ip_id);
1227 }
1228
1229 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP && net_rx_pkt_is_tcp_ack(pkt)) {
1230 *status_flags |= E1000_RXD_STAT_ACK;
1231 trace_e1000e_rx_metadata_ack();
1232 }
1233
1234 if (hasip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_DIS)) {
1235 trace_e1000e_rx_metadata_ipv6_filtering_disabled();
1236 pkt_type = E1000_RXD_PKT_MAC;
1237 } else if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP ||
1238 l4hdr_proto == ETH_L4_HDR_PROTO_UDP) {
1239 pkt_type = hasip4 ? E1000_RXD_PKT_IP4_XDP : E1000_RXD_PKT_IP6_XDP;
1240 } else if (hasip4 || hasip6) {
1241 pkt_type = hasip4 ? E1000_RXD_PKT_IP4 : E1000_RXD_PKT_IP6;
1242 } else {
1243 pkt_type = E1000_RXD_PKT_MAC;
1244 }
1245
1246 trace_e1000e_rx_metadata_pkt_type(pkt_type);
1247
1248 if (pkt_info) {
1249 if (rss_info->enabled) {
1250 *pkt_info = rss_info->type;
1251 }
1252
1253 *pkt_info |= (pkt_type << 4);
1254 } else {
1255 *status_flags |= E1000_RXD_PKT_TYPE(pkt_type);
1256 }
1257
1258 if (hdr_info) {
1259 *hdr_info = 0;
1260 }
1261
1262 /* RX CSO information */
1263 if (hasip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_XSUM_DIS)) {
1264 trace_e1000e_rx_metadata_ipv6_sum_disabled();
1265 goto func_exit;
1266 }
1267
1268 vhdr = net_rx_pkt_get_vhdr(pkt);
1269
1270 if (!(vhdr->flags & VIRTIO_NET_HDR_F_DATA_VALID) &&
1271 !(vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM)) {
1272 trace_e1000e_rx_metadata_virthdr_no_csum_info();
1273 igb_verify_csum_in_sw(core, pkt, status_flags, l4hdr_proto);
1274 goto func_exit;
1275 }
1276
1277 if (igb_rx_l3_cso_enabled(core)) {
1278 *status_flags |= hasip4 ? E1000_RXD_STAT_IPCS : 0;
1279 } else {
1280 trace_e1000e_rx_metadata_l3_cso_disabled();
1281 }
1282
1283 if (igb_rx_l4_cso_enabled(core)) {
1284 switch (l4hdr_proto) {
1285 case ETH_L4_HDR_PROTO_TCP:
1286 *status_flags |= E1000_RXD_STAT_TCPCS;
1287 break;
1288
1289 case ETH_L4_HDR_PROTO_UDP:
1290 *status_flags |= E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS;
1291 break;
1292
1293 default:
1294 goto func_exit;
1295 }
1296 } else {
1297 trace_e1000e_rx_metadata_l4_cso_disabled();
1298 }
1299
1300 trace_e1000e_rx_metadata_status_flags(*status_flags);
1301
1302 func_exit:
1303 *status_flags = cpu_to_le32(*status_flags);
1304 }
1305
1306 static inline void
1307 igb_write_lgcy_rx_descr(IGBCore *core, struct e1000_rx_desc *desc,
1308 struct NetRxPkt *pkt,
1309 const E1000E_RSSInfo *rss_info,
1310 uint16_t length)
1311 {
1312 uint32_t status_flags, rss;
1313 uint16_t ip_id;
1314
1315 assert(!rss_info->enabled);
1316 desc->length = cpu_to_le16(length);
1317 desc->csum = 0;
1318
1319 igb_build_rx_metadata(core, pkt, pkt != NULL,
1320 rss_info,
1321 NULL, NULL, &rss,
1322 &status_flags, &ip_id,
1323 &desc->special);
1324 desc->errors = (uint8_t) (le32_to_cpu(status_flags) >> 24);
1325 desc->status = (uint8_t) le32_to_cpu(status_flags);
1326 }
1327
1328 static inline void
1329 igb_write_adv_rx_descr(IGBCore *core, union e1000_adv_rx_desc *desc,
1330 struct NetRxPkt *pkt,
1331 const E1000E_RSSInfo *rss_info,
1332 uint16_t length)
1333 {
1334 memset(&desc->wb, 0, sizeof(desc->wb));
1335
1336 desc->wb.upper.length = cpu_to_le16(length);
1337
1338 igb_build_rx_metadata(core, pkt, pkt != NULL,
1339 rss_info,
1340 &desc->wb.lower.lo_dword.pkt_info,
1341 &desc->wb.lower.lo_dword.hdr_info,
1342 &desc->wb.lower.hi_dword.rss,
1343 &desc->wb.upper.status_error,
1344 &desc->wb.lower.hi_dword.csum_ip.ip_id,
1345 &desc->wb.upper.vlan);
1346 }
1347
1348 static inline void
1349 igb_write_rx_descr(IGBCore *core, union e1000_rx_desc_union *desc,
1350 struct NetRxPkt *pkt, const E1000E_RSSInfo *rss_info, uint16_t length)
1351 {
1352 if (igb_rx_use_legacy_descriptor(core)) {
1353 igb_write_lgcy_rx_descr(core, &desc->legacy, pkt, rss_info, length);
1354 } else {
1355 igb_write_adv_rx_descr(core, &desc->adv, pkt, rss_info, length);
1356 }
1357 }
1358
1359 static inline void
1360 igb_pci_dma_write_rx_desc(IGBCore *core, PCIDevice *dev, dma_addr_t addr,
1361 union e1000_rx_desc_union *desc, dma_addr_t len)
1362 {
1363 if (igb_rx_use_legacy_descriptor(core)) {
1364 struct e1000_rx_desc *d = &desc->legacy;
1365 size_t offset = offsetof(struct e1000_rx_desc, status);
1366 uint8_t status = d->status;
1367
1368 d->status &= ~E1000_RXD_STAT_DD;
1369 pci_dma_write(dev, addr, desc, len);
1370
1371 if (status & E1000_RXD_STAT_DD) {
1372 d->status = status;
1373 pci_dma_write(dev, addr + offset, &status, sizeof(status));
1374 }
1375 } else {
1376 union e1000_adv_rx_desc *d = &desc->adv;
1377 size_t offset =
1378 offsetof(union e1000_adv_rx_desc, wb.upper.status_error);
1379 uint32_t status = d->wb.upper.status_error;
1380
1381 d->wb.upper.status_error &= ~E1000_RXD_STAT_DD;
1382 pci_dma_write(dev, addr, desc, len);
1383
1384 if (status & E1000_RXD_STAT_DD) {
1385 d->wb.upper.status_error = status;
1386 pci_dma_write(dev, addr + offset, &status, sizeof(status));
1387 }
1388 }
1389 }
1390
1391 static void
1392 igb_write_to_rx_buffers(IGBCore *core,
1393 PCIDevice *d,
1394 hwaddr ba,
1395 uint16_t *written,
1396 const char *data,
1397 dma_addr_t data_len)
1398 {
1399 trace_igb_rx_desc_buff_write(ba, *written, data, data_len);
1400 pci_dma_write(d, ba + *written, data, data_len);
1401 *written += data_len;
1402 }
1403
1404 static void
1405 igb_update_rx_stats(IGBCore *core, size_t data_size, size_t data_fcs_size)
1406 {
1407 e1000x_update_rx_total_stats(core->mac, data_size, data_fcs_size);
1408
1409 switch (net_rx_pkt_get_packet_type(core->rx_pkt)) {
1410 case ETH_PKT_BCAST:
1411 e1000x_inc_reg_if_not_full(core->mac, BPRC);
1412 break;
1413
1414 case ETH_PKT_MCAST:
1415 e1000x_inc_reg_if_not_full(core->mac, MPRC);
1416 break;
1417
1418 default:
1419 break;
1420 }
1421 }
1422
1423 static inline bool
1424 igb_rx_descr_threshold_hit(IGBCore *core, const E1000E_RingInfo *rxi)
1425 {
1426 return igb_ring_free_descr_num(core, rxi) ==
1427 ((core->mac[E1000_SRRCTL(rxi->idx) >> 2] >> 20) & 31) * 16;
1428 }
1429
1430 static void
1431 igb_write_packet_to_guest(IGBCore *core, struct NetRxPkt *pkt,
1432 const E1000E_RxRing *rxr,
1433 const E1000E_RSSInfo *rss_info)
1434 {
1435 PCIDevice *d;
1436 dma_addr_t base;
1437 union e1000_rx_desc_union desc;
1438 size_t desc_size;
1439 size_t desc_offset = 0;
1440 size_t iov_ofs = 0;
1441
1442 struct iovec *iov = net_rx_pkt_get_iovec(pkt);
1443 size_t size = net_rx_pkt_get_total_len(pkt);
1444 size_t total_size = size + e1000x_fcs_len(core->mac);
1445 const E1000E_RingInfo *rxi = rxr->i;
1446 size_t bufsize = igb_rxbufsize(core, rxi);
1447
1448 d = pcie_sriov_get_vf_at_index(core->owner, rxi->idx % 8);
1449 if (!d) {
1450 d = core->owner;
1451 }
1452
1453 do {
1454 hwaddr ba;
1455 uint16_t written = 0;
1456 bool is_last = false;
1457
1458 desc_size = total_size - desc_offset;
1459
1460 if (desc_size > bufsize) {
1461 desc_size = bufsize;
1462 }
1463
1464 if (igb_ring_empty(core, rxi)) {
1465 return;
1466 }
1467
1468 base = igb_ring_head_descr(core, rxi);
1469
1470 pci_dma_read(d, base, &desc, core->rx_desc_len);
1471
1472 trace_e1000e_rx_descr(rxi->idx, base, core->rx_desc_len);
1473
1474 igb_read_rx_descr(core, &desc, &ba);
1475
1476 if (ba) {
1477 if (desc_offset < size) {
1478 static const uint32_t fcs_pad;
1479 size_t iov_copy;
1480 size_t copy_size = size - desc_offset;
1481 if (copy_size > bufsize) {
1482 copy_size = bufsize;
1483 }
1484
1485 /* Copy packet payload */
1486 while (copy_size) {
1487 iov_copy = MIN(copy_size, iov->iov_len - iov_ofs);
1488
1489 igb_write_to_rx_buffers(core, d, ba, &written,
1490 iov->iov_base + iov_ofs, iov_copy);
1491
1492 copy_size -= iov_copy;
1493 iov_ofs += iov_copy;
1494 if (iov_ofs == iov->iov_len) {
1495 iov++;
1496 iov_ofs = 0;
1497 }
1498 }
1499
1500 if (desc_offset + desc_size >= total_size) {
1501 /* Simulate FCS checksum presence in the last descriptor */
1502 igb_write_to_rx_buffers(core, d, ba, &written,
1503 (const char *) &fcs_pad, e1000x_fcs_len(core->mac));
1504 }
1505 }
1506 } else { /* as per intel docs; skip descriptors with null buf addr */
1507 trace_e1000e_rx_null_descriptor();
1508 }
1509 desc_offset += desc_size;
1510 if (desc_offset >= total_size) {
1511 is_last = true;
1512 }
1513
1514 igb_write_rx_descr(core, &desc, is_last ? core->rx_pkt : NULL,
1515 rss_info, written);
1516 igb_pci_dma_write_rx_desc(core, d, base, &desc, core->rx_desc_len);
1517
1518 igb_ring_advance(core, rxi, core->rx_desc_len / E1000_MIN_RX_DESC_LEN);
1519
1520 } while (desc_offset < total_size);
1521
1522 igb_update_rx_stats(core, size, total_size);
1523 }
1524
1525 static inline void
1526 igb_rx_fix_l4_csum(IGBCore *core, struct NetRxPkt *pkt)
1527 {
1528 struct virtio_net_hdr *vhdr = net_rx_pkt_get_vhdr(pkt);
1529
1530 if (vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM) {
1531 net_rx_pkt_fix_l4_csum(pkt);
1532 }
1533 }
1534
1535 ssize_t
1536 igb_receive_iov(IGBCore *core, const struct iovec *iov, int iovcnt)
1537 {
1538 return igb_receive_internal(core, iov, iovcnt, core->has_vnet, NULL);
1539 }
1540
1541 static ssize_t
1542 igb_receive_internal(IGBCore *core, const struct iovec *iov, int iovcnt,
1543 bool has_vnet, bool *external_tx)
1544 {
1545 static const int maximum_ethernet_hdr_len = (ETH_HLEN + 4);
1546
1547 uint16_t queues = 0;
1548 uint32_t n = 0;
1549 uint8_t min_buf[ETH_ZLEN];
1550 struct iovec min_iov;
1551 struct eth_header *ehdr;
1552 uint8_t *filter_buf;
1553 size_t size, orig_size;
1554 size_t iov_ofs = 0;
1555 E1000E_RxRing rxr;
1556 E1000E_RSSInfo rss_info;
1557 size_t total_size;
1558 int i;
1559
1560 trace_e1000e_rx_receive_iov(iovcnt);
1561
1562 if (external_tx) {
1563 *external_tx = true;
1564 }
1565
1566 if (!e1000x_hw_rx_enabled(core->mac)) {
1567 return -1;
1568 }
1569
1570 /* Pull virtio header in */
1571 if (has_vnet) {
1572 net_rx_pkt_set_vhdr_iovec(core->rx_pkt, iov, iovcnt);
1573 iov_ofs = sizeof(struct virtio_net_hdr);
1574 } else {
1575 net_rx_pkt_unset_vhdr(core->rx_pkt);
1576 }
1577
1578 filter_buf = iov->iov_base + iov_ofs;
1579 orig_size = iov_size(iov, iovcnt);
1580 size = orig_size - iov_ofs;
1581
1582 /* Pad to minimum Ethernet frame length */
1583 if (size < sizeof(min_buf)) {
1584 iov_to_buf(iov, iovcnt, iov_ofs, min_buf, size);
1585 memset(&min_buf[size], 0, sizeof(min_buf) - size);
1586 e1000x_inc_reg_if_not_full(core->mac, RUC);
1587 min_iov.iov_base = filter_buf = min_buf;
1588 min_iov.iov_len = size = sizeof(min_buf);
1589 iovcnt = 1;
1590 iov = &min_iov;
1591 iov_ofs = 0;
1592 } else if (iov->iov_len < maximum_ethernet_hdr_len) {
1593 /* This is very unlikely, but may happen. */
1594 iov_to_buf(iov, iovcnt, iov_ofs, min_buf, maximum_ethernet_hdr_len);
1595 filter_buf = min_buf;
1596 }
1597
1598 /* Discard oversized packets if !LPE and !SBP. */
1599 if (e1000x_is_oversized(core->mac, size)) {
1600 return orig_size;
1601 }
1602
1603 ehdr = PKT_GET_ETH_HDR(filter_buf);
1604 net_rx_pkt_set_packet_type(core->rx_pkt, get_eth_packet_type(ehdr));
1605
1606 net_rx_pkt_attach_iovec_ex(core->rx_pkt, iov, iovcnt, iov_ofs,
1607 e1000x_vlan_enabled(core->mac),
1608 core->mac[VET] & 0xffff);
1609
1610 queues = igb_receive_assign(core, ehdr, size, &rss_info, external_tx);
1611 if (!queues) {
1612 trace_e1000e_rx_flt_dropped();
1613 return orig_size;
1614 }
1615
1616 total_size = net_rx_pkt_get_total_len(core->rx_pkt) +
1617 e1000x_fcs_len(core->mac);
1618
1619 for (i = 0; i < IGB_NUM_QUEUES; i++) {
1620 if (!(queues & BIT(i)) ||
1621 !(core->mac[RXDCTL0 + (i * 16)] & E1000_RXDCTL_QUEUE_ENABLE)) {
1622 continue;
1623 }
1624
1625 igb_rx_ring_init(core, &rxr, i);
1626
1627 if (!igb_has_rxbufs(core, rxr.i, total_size)) {
1628 n |= E1000_ICS_RXO;
1629 trace_e1000e_rx_not_written_to_guest(rxr.i->idx);
1630 continue;
1631 }
1632
1633 n |= E1000_ICR_RXDW;
1634
1635 igb_rx_fix_l4_csum(core, core->rx_pkt);
1636 igb_write_packet_to_guest(core, core->rx_pkt, &rxr, &rss_info);
1637
1638 /* Check if receive descriptor minimum threshold hit */
1639 if (igb_rx_descr_threshold_hit(core, rxr.i)) {
1640 n |= E1000_ICS_RXDMT0;
1641 }
1642
1643 core->mac[EICR] |= igb_rx_wb_eic(core, rxr.i->idx);
1644
1645 trace_e1000e_rx_written_to_guest(rxr.i->idx);
1646 }
1647
1648 trace_e1000e_rx_interrupt_set(n);
1649 igb_set_interrupt_cause(core, n);
1650
1651 return orig_size;
1652 }
1653
1654 static inline bool
1655 igb_have_autoneg(IGBCore *core)
1656 {
1657 return core->phy[MII_BMCR] & MII_BMCR_AUTOEN;
1658 }
1659
1660 static void igb_update_flowctl_status(IGBCore *core)
1661 {
1662 if (igb_have_autoneg(core) && core->phy[MII_BMSR] & MII_BMSR_AN_COMP) {
1663 trace_e1000e_link_autoneg_flowctl(true);
1664 core->mac[CTRL] |= E1000_CTRL_TFCE | E1000_CTRL_RFCE;
1665 } else {
1666 trace_e1000e_link_autoneg_flowctl(false);
1667 }
1668 }
1669
1670 static inline void
1671 igb_link_down(IGBCore *core)
1672 {
1673 e1000x_update_regs_on_link_down(core->mac, core->phy);
1674 igb_update_flowctl_status(core);
1675 }
1676
1677 static inline void
1678 igb_set_phy_ctrl(IGBCore *core, uint16_t val)
1679 {
1680 /* bits 0-5 reserved; MII_BMCR_[ANRESTART,RESET] are self clearing */
1681 core->phy[MII_BMCR] = val & ~(0x3f | MII_BMCR_RESET | MII_BMCR_ANRESTART);
1682
1683 if ((val & MII_BMCR_ANRESTART) && igb_have_autoneg(core)) {
1684 e1000x_restart_autoneg(core->mac, core->phy, core->autoneg_timer);
1685 }
1686 }
1687
1688 void igb_core_set_link_status(IGBCore *core)
1689 {
1690 NetClientState *nc = qemu_get_queue(core->owner_nic);
1691 uint32_t old_status = core->mac[STATUS];
1692
1693 trace_e1000e_link_status_changed(nc->link_down ? false : true);
1694
1695 if (nc->link_down) {
1696 e1000x_update_regs_on_link_down(core->mac, core->phy);
1697 } else {
1698 if (igb_have_autoneg(core) &&
1699 !(core->phy[MII_BMSR] & MII_BMSR_AN_COMP)) {
1700 e1000x_restart_autoneg(core->mac, core->phy,
1701 core->autoneg_timer);
1702 } else {
1703 e1000x_update_regs_on_link_up(core->mac, core->phy);
1704 igb_start_recv(core);
1705 }
1706 }
1707
1708 if (core->mac[STATUS] != old_status) {
1709 igb_set_interrupt_cause(core, E1000_ICR_LSC);
1710 }
1711 }
1712
1713 static void
1714 igb_set_ctrl(IGBCore *core, int index, uint32_t val)
1715 {
1716 trace_e1000e_core_ctrl_write(index, val);
1717
1718 /* RST is self clearing */
1719 core->mac[CTRL] = val & ~E1000_CTRL_RST;
1720 core->mac[CTRL_DUP] = core->mac[CTRL];
1721
1722 trace_e1000e_link_set_params(
1723 !!(val & E1000_CTRL_ASDE),
1724 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT,
1725 !!(val & E1000_CTRL_FRCSPD),
1726 !!(val & E1000_CTRL_FRCDPX),
1727 !!(val & E1000_CTRL_RFCE),
1728 !!(val & E1000_CTRL_TFCE));
1729
1730 if (val & E1000_CTRL_RST) {
1731 trace_e1000e_core_ctrl_sw_reset();
1732 igb_reset(core, true);
1733 }
1734
1735 if (val & E1000_CTRL_PHY_RST) {
1736 trace_e1000e_core_ctrl_phy_reset();
1737 core->mac[STATUS] |= E1000_STATUS_PHYRA;
1738 }
1739 }
1740
1741 static void
1742 igb_set_rfctl(IGBCore *core, int index, uint32_t val)
1743 {
1744 trace_e1000e_rx_set_rfctl(val);
1745
1746 if (!(val & E1000_RFCTL_ISCSI_DIS)) {
1747 trace_e1000e_wrn_iscsi_filtering_not_supported();
1748 }
1749
1750 if (!(val & E1000_RFCTL_NFSW_DIS)) {
1751 trace_e1000e_wrn_nfsw_filtering_not_supported();
1752 }
1753
1754 if (!(val & E1000_RFCTL_NFSR_DIS)) {
1755 trace_e1000e_wrn_nfsr_filtering_not_supported();
1756 }
1757
1758 core->mac[RFCTL] = val;
1759 }
1760
1761 static void
1762 igb_calc_rxdesclen(IGBCore *core)
1763 {
1764 if (igb_rx_use_legacy_descriptor(core)) {
1765 core->rx_desc_len = sizeof(struct e1000_rx_desc);
1766 } else {
1767 core->rx_desc_len = sizeof(union e1000_adv_rx_desc);
1768 }
1769 trace_e1000e_rx_desc_len(core->rx_desc_len);
1770 }
1771
1772 static void
1773 igb_set_rx_control(IGBCore *core, int index, uint32_t val)
1774 {
1775 core->mac[RCTL] = val;
1776 trace_e1000e_rx_set_rctl(core->mac[RCTL]);
1777
1778 if (val & E1000_RCTL_DTYP_MASK) {
1779 qemu_log_mask(LOG_GUEST_ERROR,
1780 "igb: RCTL.DTYP must be zero for compatibility");
1781 }
1782
1783 if (val & E1000_RCTL_EN) {
1784 igb_calc_rxdesclen(core);
1785 igb_start_recv(core);
1786 }
1787 }
1788
1789 static inline void
1790 igb_clear_ims_bits(IGBCore *core, uint32_t bits)
1791 {
1792 trace_e1000e_irq_clear_ims(bits, core->mac[IMS], core->mac[IMS] & ~bits);
1793 core->mac[IMS] &= ~bits;
1794 }
1795
1796 static inline bool
1797 igb_postpone_interrupt(IGBIntrDelayTimer *timer)
1798 {
1799 if (timer->running) {
1800 trace_e1000e_irq_postponed_by_xitr(timer->delay_reg << 2);
1801
1802 return true;
1803 }
1804
1805 if (timer->core->mac[timer->delay_reg] != 0) {
1806 igb_intrmgr_rearm_timer(timer);
1807 }
1808
1809 return false;
1810 }
1811
1812 static inline bool
1813 igb_eitr_should_postpone(IGBCore *core, int idx)
1814 {
1815 return igb_postpone_interrupt(&core->eitr[idx]);
1816 }
1817
1818 static void igb_send_msix(IGBCore *core)
1819 {
1820 uint32_t causes = core->mac[EICR] & core->mac[EIMS];
1821 uint32_t effective_eiac;
1822 int vector;
1823
1824 for (vector = 0; vector < IGB_INTR_NUM; ++vector) {
1825 if ((causes & BIT(vector)) && !igb_eitr_should_postpone(core, vector)) {
1826
1827 trace_e1000e_irq_msix_notify_vec(vector);
1828 igb_msix_notify(core, vector);
1829
1830 trace_e1000e_irq_icr_clear_eiac(core->mac[EICR], core->mac[EIAC]);
1831 effective_eiac = core->mac[EIAC] & BIT(vector);
1832 core->mac[EICR] &= ~effective_eiac;
1833 }
1834 }
1835 }
1836
1837 static inline void
1838 igb_fix_icr_asserted(IGBCore *core)
1839 {
1840 core->mac[ICR] &= ~E1000_ICR_ASSERTED;
1841 if (core->mac[ICR]) {
1842 core->mac[ICR] |= E1000_ICR_ASSERTED;
1843 }
1844
1845 trace_e1000e_irq_fix_icr_asserted(core->mac[ICR]);
1846 }
1847
1848 static void
1849 igb_update_interrupt_state(IGBCore *core)
1850 {
1851 uint32_t icr;
1852 uint32_t causes;
1853 uint32_t int_alloc;
1854
1855 icr = core->mac[ICR] & core->mac[IMS];
1856
1857 if (msix_enabled(core->owner)) {
1858 if (icr) {
1859 causes = 0;
1860 if (icr & E1000_ICR_DRSTA) {
1861 int_alloc = core->mac[IVAR_MISC] & 0xff;
1862 if (int_alloc & E1000_IVAR_VALID) {
1863 causes |= BIT(int_alloc & 0x1f);
1864 }
1865 }
1866 /* Check if other bits (excluding the TCP Timer) are enabled. */
1867 if (icr & ~E1000_ICR_DRSTA) {
1868 int_alloc = (core->mac[IVAR_MISC] >> 8) & 0xff;
1869 if (int_alloc & E1000_IVAR_VALID) {
1870 causes |= BIT(int_alloc & 0x1f);
1871 }
1872 trace_e1000e_irq_add_msi_other(core->mac[EICR]);
1873 }
1874 core->mac[EICR] |= causes;
1875 }
1876
1877 if ((core->mac[EICR] & core->mac[EIMS])) {
1878 igb_send_msix(core);
1879 }
1880 } else {
1881 igb_fix_icr_asserted(core);
1882
1883 if (icr) {
1884 core->mac[EICR] |= (icr & E1000_ICR_DRSTA) | E1000_EICR_OTHER;
1885 } else {
1886 core->mac[EICR] &= ~E1000_EICR_OTHER;
1887 }
1888
1889 trace_e1000e_irq_pending_interrupts(core->mac[ICR] & core->mac[IMS],
1890 core->mac[ICR], core->mac[IMS]);
1891
1892 if (msi_enabled(core->owner)) {
1893 if (icr) {
1894 msi_notify(core->owner, 0);
1895 }
1896 } else {
1897 if (icr) {
1898 igb_raise_legacy_irq(core);
1899 } else {
1900 igb_lower_legacy_irq(core);
1901 }
1902 }
1903 }
1904 }
1905
1906 static void
1907 igb_set_interrupt_cause(IGBCore *core, uint32_t val)
1908 {
1909 trace_e1000e_irq_set_cause_entry(val, core->mac[ICR]);
1910
1911 core->mac[ICR] |= val;
1912
1913 trace_e1000e_irq_set_cause_exit(val, core->mac[ICR]);
1914
1915 igb_update_interrupt_state(core);
1916 }
1917
1918 static void igb_set_eics(IGBCore *core, int index, uint32_t val)
1919 {
1920 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE);
1921
1922 trace_igb_irq_write_eics(val, msix);
1923
1924 core->mac[EICS] |=
1925 val & (msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK);
1926
1927 /*
1928 * TODO: Move to igb_update_interrupt_state if EICS is modified in other
1929 * places.
1930 */
1931 core->mac[EICR] = core->mac[EICS];
1932
1933 igb_update_interrupt_state(core);
1934 }
1935
1936 static void igb_set_eims(IGBCore *core, int index, uint32_t val)
1937 {
1938 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE);
1939
1940 trace_igb_irq_write_eims(val, msix);
1941
1942 core->mac[EIMS] |=
1943 val & (msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK);
1944
1945 igb_update_interrupt_state(core);
1946 }
1947
1948 static void mailbox_interrupt_to_vf(IGBCore *core, uint16_t vfn)
1949 {
1950 uint32_t ent = core->mac[VTIVAR_MISC + vfn];
1951
1952 if ((ent & E1000_IVAR_VALID)) {
1953 core->mac[EICR] |= (ent & 0x3) << (22 - vfn * IGBVF_MSIX_VEC_NUM);
1954 igb_update_interrupt_state(core);
1955 }
1956 }
1957
1958 static void mailbox_interrupt_to_pf(IGBCore *core)
1959 {
1960 igb_set_interrupt_cause(core, E1000_ICR_VMMB);
1961 }
1962
1963 static void igb_set_pfmailbox(IGBCore *core, int index, uint32_t val)
1964 {
1965 uint16_t vfn = index - P2VMAILBOX0;
1966
1967 trace_igb_set_pfmailbox(vfn, val);
1968
1969 if (val & E1000_P2VMAILBOX_STS) {
1970 core->mac[V2PMAILBOX0 + vfn] |= E1000_V2PMAILBOX_PFSTS;
1971 mailbox_interrupt_to_vf(core, vfn);
1972 }
1973
1974 if (val & E1000_P2VMAILBOX_ACK) {
1975 core->mac[V2PMAILBOX0 + vfn] |= E1000_V2PMAILBOX_PFACK;
1976 mailbox_interrupt_to_vf(core, vfn);
1977 }
1978
1979 /* Buffer Taken by PF (can be set only if the VFU is cleared). */
1980 if (val & E1000_P2VMAILBOX_PFU) {
1981 if (!(core->mac[index] & E1000_P2VMAILBOX_VFU)) {
1982 core->mac[index] |= E1000_P2VMAILBOX_PFU;
1983 core->mac[V2PMAILBOX0 + vfn] |= E1000_V2PMAILBOX_PFU;
1984 }
1985 } else {
1986 core->mac[index] &= ~E1000_P2VMAILBOX_PFU;
1987 core->mac[V2PMAILBOX0 + vfn] &= ~E1000_V2PMAILBOX_PFU;
1988 }
1989
1990 if (val & E1000_P2VMAILBOX_RVFU) {
1991 core->mac[V2PMAILBOX0 + vfn] &= ~E1000_V2PMAILBOX_VFU;
1992 core->mac[MBVFICR] &= ~((E1000_MBVFICR_VFACK_VF1 << vfn) |
1993 (E1000_MBVFICR_VFREQ_VF1 << vfn));
1994 }
1995 }
1996
1997 static void igb_set_vfmailbox(IGBCore *core, int index, uint32_t val)
1998 {
1999 uint16_t vfn = index - V2PMAILBOX0;
2000
2001 trace_igb_set_vfmailbox(vfn, val);
2002
2003 if (val & E1000_V2PMAILBOX_REQ) {
2004 core->mac[MBVFICR] |= E1000_MBVFICR_VFREQ_VF1 << vfn;
2005 mailbox_interrupt_to_pf(core);
2006 }
2007
2008 if (val & E1000_V2PMAILBOX_ACK) {
2009 core->mac[MBVFICR] |= E1000_MBVFICR_VFACK_VF1 << vfn;
2010 mailbox_interrupt_to_pf(core);
2011 }
2012
2013 /* Buffer Taken by VF (can be set only if the PFU is cleared). */
2014 if (val & E1000_V2PMAILBOX_VFU) {
2015 if (!(core->mac[index] & E1000_V2PMAILBOX_PFU)) {
2016 core->mac[index] |= E1000_V2PMAILBOX_VFU;
2017 core->mac[P2VMAILBOX0 + vfn] |= E1000_P2VMAILBOX_VFU;
2018 }
2019 } else {
2020 core->mac[index] &= ~E1000_V2PMAILBOX_VFU;
2021 core->mac[P2VMAILBOX0 + vfn] &= ~E1000_P2VMAILBOX_VFU;
2022 }
2023 }
2024
2025 static void igb_vf_reset(IGBCore *core, uint16_t vfn)
2026 {
2027 uint16_t qn0 = vfn;
2028 uint16_t qn1 = vfn + IGB_NUM_VM_POOLS;
2029
2030 /* disable Rx and Tx for the VF*/
2031 core->mac[RXDCTL0 + (qn0 * 16)] &= ~E1000_RXDCTL_QUEUE_ENABLE;
2032 core->mac[RXDCTL0 + (qn1 * 16)] &= ~E1000_RXDCTL_QUEUE_ENABLE;
2033 core->mac[TXDCTL0 + (qn0 * 16)] &= ~E1000_TXDCTL_QUEUE_ENABLE;
2034 core->mac[TXDCTL0 + (qn1 * 16)] &= ~E1000_TXDCTL_QUEUE_ENABLE;
2035 core->mac[VFRE] &= ~BIT(vfn);
2036 core->mac[VFTE] &= ~BIT(vfn);
2037 /* indicate VF reset to PF */
2038 core->mac[VFLRE] |= BIT(vfn);
2039 /* VFLRE and mailbox use the same interrupt cause */
2040 mailbox_interrupt_to_pf(core);
2041 }
2042
2043 static void igb_w1c(IGBCore *core, int index, uint32_t val)
2044 {
2045 core->mac[index] &= ~val;
2046 }
2047
2048 static void igb_set_eimc(IGBCore *core, int index, uint32_t val)
2049 {
2050 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE);
2051
2052 /* Interrupts are disabled via a write to EIMC and reflected in EIMS. */
2053 core->mac[EIMS] &=
2054 ~(val & (msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK));
2055
2056 trace_igb_irq_write_eimc(val, core->mac[EIMS], msix);
2057 igb_update_interrupt_state(core);
2058 }
2059
2060 static void igb_set_eiac(IGBCore *core, int index, uint32_t val)
2061 {
2062 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE);
2063
2064 if (msix) {
2065 trace_igb_irq_write_eiac(val);
2066
2067 /*
2068 * TODO: When using IOV, the bits that correspond to MSI-X vectors
2069 * that are assigned to a VF are read-only.
2070 */
2071 core->mac[EIAC] |= (val & E1000_EICR_MSIX_MASK);
2072 }
2073 }
2074
2075 static void igb_set_eiam(IGBCore *core, int index, uint32_t val)
2076 {
2077 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE);
2078
2079 /*
2080 * TODO: When using IOV, the bits that correspond to MSI-X vectors that
2081 * are assigned to a VF are read-only.
2082 */
2083 core->mac[EIAM] |=
2084 ~(val & (msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK));
2085
2086 trace_igb_irq_write_eiam(val, msix);
2087 }
2088
2089 static void igb_set_eicr(IGBCore *core, int index, uint32_t val)
2090 {
2091 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE);
2092
2093 /*
2094 * TODO: In IOV mode, only bit zero of this vector is available for the PF
2095 * function.
2096 */
2097 core->mac[EICR] &=
2098 ~(val & (msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK));
2099
2100 trace_igb_irq_write_eicr(val, msix);
2101 igb_update_interrupt_state(core);
2102 }
2103
2104 static void igb_set_vtctrl(IGBCore *core, int index, uint32_t val)
2105 {
2106 uint16_t vfn;
2107
2108 if (val & E1000_CTRL_RST) {
2109 vfn = (index - PVTCTRL0) / 0x40;
2110 igb_vf_reset(core, vfn);
2111 }
2112 }
2113
2114 static void igb_set_vteics(IGBCore *core, int index, uint32_t val)
2115 {
2116 uint16_t vfn = (index - PVTEICS0) / 0x40;
2117
2118 core->mac[index] = val;
2119 igb_set_eics(core, EICS, (val & 0x7) << (22 - vfn * IGBVF_MSIX_VEC_NUM));
2120 }
2121
2122 static void igb_set_vteims(IGBCore *core, int index, uint32_t val)
2123 {
2124 uint16_t vfn = (index - PVTEIMS0) / 0x40;
2125
2126 core->mac[index] = val;
2127 igb_set_eims(core, EIMS, (val & 0x7) << (22 - vfn * IGBVF_MSIX_VEC_NUM));
2128 }
2129
2130 static void igb_set_vteimc(IGBCore *core, int index, uint32_t val)
2131 {
2132 uint16_t vfn = (index - PVTEIMC0) / 0x40;
2133
2134 core->mac[index] = val;
2135 igb_set_eimc(core, EIMC, (val & 0x7) << (22 - vfn * IGBVF_MSIX_VEC_NUM));
2136 }
2137
2138 static void igb_set_vteiac(IGBCore *core, int index, uint32_t val)
2139 {
2140 uint16_t vfn = (index - PVTEIAC0) / 0x40;
2141
2142 core->mac[index] = val;
2143 igb_set_eiac(core, EIAC, (val & 0x7) << (22 - vfn * IGBVF_MSIX_VEC_NUM));
2144 }
2145
2146 static void igb_set_vteiam(IGBCore *core, int index, uint32_t val)
2147 {
2148 uint16_t vfn = (index - PVTEIAM0) / 0x40;
2149
2150 core->mac[index] = val;
2151 igb_set_eiam(core, EIAM, (val & 0x7) << (22 - vfn * IGBVF_MSIX_VEC_NUM));
2152 }
2153
2154 static void igb_set_vteicr(IGBCore *core, int index, uint32_t val)
2155 {
2156 uint16_t vfn = (index - PVTEICR0) / 0x40;
2157
2158 core->mac[index] = val;
2159 igb_set_eicr(core, EICR, (val & 0x7) << (22 - vfn * IGBVF_MSIX_VEC_NUM));
2160 }
2161
2162 static void igb_set_vtivar(IGBCore *core, int index, uint32_t val)
2163 {
2164 uint16_t vfn = (index - VTIVAR);
2165 uint16_t qn = vfn;
2166 uint8_t ent;
2167 int n;
2168
2169 core->mac[index] = val;
2170
2171 /* Get assigned vector associated with queue Rx#0. */
2172 if ((val & E1000_IVAR_VALID)) {
2173 n = igb_ivar_entry_rx(qn);
2174 ent = E1000_IVAR_VALID | (24 - vfn * IGBVF_MSIX_VEC_NUM - (2 - (val & 0x7)));
2175 core->mac[IVAR0 + n / 4] |= ent << 8 * (n % 4);
2176 }
2177
2178 /* Get assigned vector associated with queue Tx#0 */
2179 ent = val >> 8;
2180 if ((ent & E1000_IVAR_VALID)) {
2181 n = igb_ivar_entry_tx(qn);
2182 ent = E1000_IVAR_VALID | (24 - vfn * IGBVF_MSIX_VEC_NUM - (2 - (ent & 0x7)));
2183 core->mac[IVAR0 + n / 4] |= ent << 8 * (n % 4);
2184 }
2185
2186 /*
2187 * Ignoring assigned vectors associated with queues Rx#1 and Tx#1 for now.
2188 */
2189 }
2190
2191 static inline void
2192 igb_autoneg_timer(void *opaque)
2193 {
2194 IGBCore *core = opaque;
2195 if (!qemu_get_queue(core->owner_nic)->link_down) {
2196 e1000x_update_regs_on_autoneg_done(core->mac, core->phy);
2197 igb_start_recv(core);
2198
2199 igb_update_flowctl_status(core);
2200 /* signal link status change to the guest */
2201 igb_set_interrupt_cause(core, E1000_ICR_LSC);
2202 }
2203 }
2204
2205 static inline uint16_t
2206 igb_get_reg_index_with_offset(const uint16_t *mac_reg_access, hwaddr addr)
2207 {
2208 uint16_t index = (addr & 0x1ffff) >> 2;
2209 return index + (mac_reg_access[index] & 0xfffe);
2210 }
2211
2212 static const char igb_phy_regcap[MAX_PHY_REG_ADDRESS + 1] = {
2213 [MII_BMCR] = PHY_RW,
2214 [MII_BMSR] = PHY_R,
2215 [MII_PHYID1] = PHY_R,
2216 [MII_PHYID2] = PHY_R,
2217 [MII_ANAR] = PHY_RW,
2218 [MII_ANLPAR] = PHY_R,
2219 [MII_ANER] = PHY_R,
2220 [MII_ANNP] = PHY_RW,
2221 [MII_ANLPRNP] = PHY_R,
2222 [MII_CTRL1000] = PHY_RW,
2223 [MII_STAT1000] = PHY_R,
2224 [MII_EXTSTAT] = PHY_R,
2225
2226 [IGP01E1000_PHY_PORT_CONFIG] = PHY_RW,
2227 [IGP01E1000_PHY_PORT_STATUS] = PHY_R,
2228 [IGP01E1000_PHY_PORT_CTRL] = PHY_RW,
2229 [IGP01E1000_PHY_LINK_HEALTH] = PHY_R,
2230 [IGP02E1000_PHY_POWER_MGMT] = PHY_RW,
2231 [IGP01E1000_PHY_PAGE_SELECT] = PHY_W
2232 };
2233
2234 static void
2235 igb_phy_reg_write(IGBCore *core, uint32_t addr, uint16_t data)
2236 {
2237 assert(addr <= MAX_PHY_REG_ADDRESS);
2238
2239 if (addr == MII_BMCR) {
2240 igb_set_phy_ctrl(core, data);
2241 } else {
2242 core->phy[addr] = data;
2243 }
2244 }
2245
2246 static void
2247 igb_set_mdic(IGBCore *core, int index, uint32_t val)
2248 {
2249 uint32_t data = val & E1000_MDIC_DATA_MASK;
2250 uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
2251
2252 if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) { /* phy # */
2253 val = core->mac[MDIC] | E1000_MDIC_ERROR;
2254 } else if (val & E1000_MDIC_OP_READ) {
2255 if (!(igb_phy_regcap[addr] & PHY_R)) {
2256 trace_igb_core_mdic_read_unhandled(addr);
2257 val |= E1000_MDIC_ERROR;
2258 } else {
2259 val = (val ^ data) | core->phy[addr];
2260 trace_igb_core_mdic_read(addr, val);
2261 }
2262 } else if (val & E1000_MDIC_OP_WRITE) {
2263 if (!(igb_phy_regcap[addr] & PHY_W)) {
2264 trace_igb_core_mdic_write_unhandled(addr);
2265 val |= E1000_MDIC_ERROR;
2266 } else {
2267 trace_igb_core_mdic_write(addr, data);
2268 igb_phy_reg_write(core, addr, data);
2269 }
2270 }
2271 core->mac[MDIC] = val | E1000_MDIC_READY;
2272
2273 if (val & E1000_MDIC_INT_EN) {
2274 igb_set_interrupt_cause(core, E1000_ICR_MDAC);
2275 }
2276 }
2277
2278 static void
2279 igb_set_rdt(IGBCore *core, int index, uint32_t val)
2280 {
2281 core->mac[index] = val & 0xffff;
2282 trace_e1000e_rx_set_rdt(igb_mq_queue_idx(RDT0, index), val);
2283 igb_start_recv(core);
2284 }
2285
2286 static void
2287 igb_set_status(IGBCore *core, int index, uint32_t val)
2288 {
2289 if ((val & E1000_STATUS_PHYRA) == 0) {
2290 core->mac[index] &= ~E1000_STATUS_PHYRA;
2291 }
2292 }
2293
2294 static void
2295 igb_set_ctrlext(IGBCore *core, int index, uint32_t val)
2296 {
2297 trace_igb_link_set_ext_params(!!(val & E1000_CTRL_EXT_ASDCHK),
2298 !!(val & E1000_CTRL_EXT_SPD_BYPS),
2299 !!(val & E1000_CTRL_EXT_PFRSTD));
2300
2301 /* Zero self-clearing bits */
2302 val &= ~(E1000_CTRL_EXT_ASDCHK | E1000_CTRL_EXT_EE_RST);
2303 core->mac[CTRL_EXT] = val;
2304
2305 if (core->mac[CTRL_EXT] & E1000_CTRL_EXT_PFRSTD) {
2306 for (int vfn = 0; vfn < IGB_MAX_VF_FUNCTIONS; vfn++) {
2307 core->mac[V2PMAILBOX0 + vfn] &= ~E1000_V2PMAILBOX_RSTI;
2308 core->mac[V2PMAILBOX0 + vfn] |= E1000_V2PMAILBOX_RSTD;
2309 }
2310 }
2311 }
2312
2313 static void
2314 igb_set_pbaclr(IGBCore *core, int index, uint32_t val)
2315 {
2316 int i;
2317
2318 core->mac[PBACLR] = val & E1000_PBACLR_VALID_MASK;
2319
2320 if (!msix_enabled(core->owner)) {
2321 return;
2322 }
2323
2324 for (i = 0; i < IGB_INTR_NUM; i++) {
2325 if (core->mac[PBACLR] & BIT(i)) {
2326 msix_clr_pending(core->owner, i);
2327 }
2328 }
2329 }
2330
2331 static void
2332 igb_set_fcrth(IGBCore *core, int index, uint32_t val)
2333 {
2334 core->mac[FCRTH] = val & 0xFFF8;
2335 }
2336
2337 static void
2338 igb_set_fcrtl(IGBCore *core, int index, uint32_t val)
2339 {
2340 core->mac[FCRTL] = val & 0x8000FFF8;
2341 }
2342
2343 #define IGB_LOW_BITS_SET_FUNC(num) \
2344 static void \
2345 igb_set_##num##bit(IGBCore *core, int index, uint32_t val) \
2346 { \
2347 core->mac[index] = val & (BIT(num) - 1); \
2348 }
2349
2350 IGB_LOW_BITS_SET_FUNC(4)
2351 IGB_LOW_BITS_SET_FUNC(13)
2352 IGB_LOW_BITS_SET_FUNC(16)
2353
2354 static void
2355 igb_set_dlen(IGBCore *core, int index, uint32_t val)
2356 {
2357 core->mac[index] = val & 0xffff0;
2358 }
2359
2360 static void
2361 igb_set_dbal(IGBCore *core, int index, uint32_t val)
2362 {
2363 core->mac[index] = val & E1000_XDBAL_MASK;
2364 }
2365
2366 static void
2367 igb_set_tdt(IGBCore *core, int index, uint32_t val)
2368 {
2369 IGB_TxRing txr;
2370 int qn = igb_mq_queue_idx(TDT0, index);
2371
2372 core->mac[index] = val & 0xffff;
2373
2374 igb_tx_ring_init(core, &txr, qn);
2375 igb_start_xmit(core, &txr);
2376 }
2377
2378 static void
2379 igb_set_ics(IGBCore *core, int index, uint32_t val)
2380 {
2381 trace_e1000e_irq_write_ics(val);
2382 igb_set_interrupt_cause(core, val);
2383 }
2384
2385 static void
2386 igb_set_imc(IGBCore *core, int index, uint32_t val)
2387 {
2388 trace_e1000e_irq_ims_clear_set_imc(val);
2389 igb_clear_ims_bits(core, val);
2390 igb_update_interrupt_state(core);
2391 }
2392
2393 static void
2394 igb_set_ims(IGBCore *core, int index, uint32_t val)
2395 {
2396 uint32_t valid_val = val & 0x77D4FBFD;
2397
2398 trace_e1000e_irq_set_ims(val, core->mac[IMS], core->mac[IMS] | valid_val);
2399 core->mac[IMS] |= valid_val;
2400 igb_update_interrupt_state(core);
2401 }
2402
2403 static void igb_commit_icr(IGBCore *core)
2404 {
2405 /*
2406 * If GPIE.NSICR = 0, then the copy of IAM to IMS will occur only if at
2407 * least one bit is set in the IMS and there is a true interrupt as
2408 * reflected in ICR.INTA.
2409 */
2410 if ((core->mac[GPIE] & E1000_GPIE_NSICR) ||
2411 (core->mac[IMS] && (core->mac[ICR] & E1000_ICR_INT_ASSERTED))) {
2412 igb_set_ims(core, IMS, core->mac[IAM]);
2413 } else {
2414 igb_update_interrupt_state(core);
2415 }
2416 }
2417
2418 static void igb_set_icr(IGBCore *core, int index, uint32_t val)
2419 {
2420 uint32_t icr = core->mac[ICR] & ~val;
2421
2422 trace_igb_irq_icr_write(val, core->mac[ICR], icr);
2423 core->mac[ICR] = icr;
2424 igb_commit_icr(core);
2425 }
2426
2427 static uint32_t
2428 igb_mac_readreg(IGBCore *core, int index)
2429 {
2430 return core->mac[index];
2431 }
2432
2433 static uint32_t
2434 igb_mac_ics_read(IGBCore *core, int index)
2435 {
2436 trace_e1000e_irq_read_ics(core->mac[ICS]);
2437 return core->mac[ICS];
2438 }
2439
2440 static uint32_t
2441 igb_mac_ims_read(IGBCore *core, int index)
2442 {
2443 trace_e1000e_irq_read_ims(core->mac[IMS]);
2444 return core->mac[IMS];
2445 }
2446
2447 static uint32_t
2448 igb_mac_swsm_read(IGBCore *core, int index)
2449 {
2450 uint32_t val = core->mac[SWSM];
2451 core->mac[SWSM] = val | E1000_SWSM_SMBI;
2452 return val;
2453 }
2454
2455 static uint32_t
2456 igb_mac_eitr_read(IGBCore *core, int index)
2457 {
2458 return core->eitr_guest_value[index - EITR0];
2459 }
2460
2461 static uint32_t igb_mac_vfmailbox_read(IGBCore *core, int index)
2462 {
2463 uint32_t val = core->mac[index];
2464
2465 core->mac[index] &= ~(E1000_V2PMAILBOX_PFSTS | E1000_V2PMAILBOX_PFACK |
2466 E1000_V2PMAILBOX_RSTD);
2467
2468 return val;
2469 }
2470
2471 static uint32_t
2472 igb_mac_icr_read(IGBCore *core, int index)
2473 {
2474 uint32_t ret = core->mac[ICR];
2475 trace_e1000e_irq_icr_read_entry(ret);
2476
2477 if (core->mac[GPIE] & E1000_GPIE_NSICR) {
2478 trace_igb_irq_icr_clear_gpie_nsicr();
2479 core->mac[ICR] = 0;
2480 } else if (core->mac[IMS] == 0) {
2481 trace_e1000e_irq_icr_clear_zero_ims();
2482 core->mac[ICR] = 0;
2483 } else if (!msix_enabled(core->owner)) {
2484 trace_e1000e_irq_icr_clear_nonmsix_icr_read();
2485 core->mac[ICR] = 0;
2486 }
2487
2488 trace_e1000e_irq_icr_read_exit(core->mac[ICR]);
2489 igb_commit_icr(core);
2490 return ret;
2491 }
2492
2493 static uint32_t
2494 igb_mac_read_clr4(IGBCore *core, int index)
2495 {
2496 uint32_t ret = core->mac[index];
2497
2498 core->mac[index] = 0;
2499 return ret;
2500 }
2501
2502 static uint32_t
2503 igb_mac_read_clr8(IGBCore *core, int index)
2504 {
2505 uint32_t ret = core->mac[index];
2506
2507 core->mac[index] = 0;
2508 core->mac[index - 1] = 0;
2509 return ret;
2510 }
2511
2512 static uint32_t
2513 igb_get_ctrl(IGBCore *core, int index)
2514 {
2515 uint32_t val = core->mac[CTRL];
2516
2517 trace_e1000e_link_read_params(
2518 !!(val & E1000_CTRL_ASDE),
2519 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT,
2520 !!(val & E1000_CTRL_FRCSPD),
2521 !!(val & E1000_CTRL_FRCDPX),
2522 !!(val & E1000_CTRL_RFCE),
2523 !!(val & E1000_CTRL_TFCE));
2524
2525 return val;
2526 }
2527
2528 static uint32_t igb_get_status(IGBCore *core, int index)
2529 {
2530 uint32_t res = core->mac[STATUS];
2531 uint16_t num_vfs = pcie_sriov_num_vfs(core->owner);
2532
2533 if (core->mac[CTRL] & E1000_CTRL_FRCDPX) {
2534 res |= (core->mac[CTRL] & E1000_CTRL_FD) ? E1000_STATUS_FD : 0;
2535 } else {
2536 res |= E1000_STATUS_FD;
2537 }
2538
2539 if ((core->mac[CTRL] & E1000_CTRL_FRCSPD) ||
2540 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_SPD_BYPS)) {
2541 switch (core->mac[CTRL] & E1000_CTRL_SPD_SEL) {
2542 case E1000_CTRL_SPD_10:
2543 res |= E1000_STATUS_SPEED_10;
2544 break;
2545 case E1000_CTRL_SPD_100:
2546 res |= E1000_STATUS_SPEED_100;
2547 break;
2548 case E1000_CTRL_SPD_1000:
2549 default:
2550 res |= E1000_STATUS_SPEED_1000;
2551 break;
2552 }
2553 } else {
2554 res |= E1000_STATUS_SPEED_1000;
2555 }
2556
2557 if (num_vfs) {
2558 res |= num_vfs << E1000_STATUS_NUM_VFS_SHIFT;
2559 res |= E1000_STATUS_IOV_MODE;
2560 }
2561
2562 /*
2563 * Windows driver 12.18.9.23 resets if E1000_STATUS_GIO_MASTER_ENABLE is
2564 * left set after E1000_CTRL_LRST is set.
2565 */
2566 if (!(core->mac[CTRL] & E1000_CTRL_GIO_MASTER_DISABLE) &&
2567 !(core->mac[CTRL] & E1000_CTRL_LRST)) {
2568 res |= E1000_STATUS_GIO_MASTER_ENABLE;
2569 }
2570
2571 return res;
2572 }
2573
2574 static void
2575 igb_mac_writereg(IGBCore *core, int index, uint32_t val)
2576 {
2577 core->mac[index] = val;
2578 }
2579
2580 static void
2581 igb_mac_setmacaddr(IGBCore *core, int index, uint32_t val)
2582 {
2583 uint32_t macaddr[2];
2584
2585 core->mac[index] = val;
2586
2587 macaddr[0] = cpu_to_le32(core->mac[RA]);
2588 macaddr[1] = cpu_to_le32(core->mac[RA + 1]);
2589 qemu_format_nic_info_str(qemu_get_queue(core->owner_nic),
2590 (uint8_t *) macaddr);
2591
2592 trace_e1000e_mac_set_sw(MAC_ARG(macaddr));
2593 }
2594
2595 static void
2596 igb_set_eecd(IGBCore *core, int index, uint32_t val)
2597 {
2598 static const uint32_t ro_bits = E1000_EECD_PRES |
2599 E1000_EECD_AUTO_RD |
2600 E1000_EECD_SIZE_EX_MASK;
2601
2602 core->mac[EECD] = (core->mac[EECD] & ro_bits) | (val & ~ro_bits);
2603 }
2604
2605 static void
2606 igb_set_eerd(IGBCore *core, int index, uint32_t val)
2607 {
2608 uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK;
2609 uint32_t flags = 0;
2610 uint32_t data = 0;
2611
2612 if ((addr < IGB_EEPROM_SIZE) && (val & E1000_EERW_START)) {
2613 data = core->eeprom[addr];
2614 flags = E1000_EERW_DONE;
2615 }
2616
2617 core->mac[EERD] = flags |
2618 (addr << E1000_EERW_ADDR_SHIFT) |
2619 (data << E1000_EERW_DATA_SHIFT);
2620 }
2621
2622 static void
2623 igb_set_eitr(IGBCore *core, int index, uint32_t val)
2624 {
2625 uint32_t eitr_num = index - EITR0;
2626
2627 trace_igb_irq_eitr_set(eitr_num, val);
2628
2629 core->eitr_guest_value[eitr_num] = val & ~E1000_EITR_CNT_IGNR;
2630 core->mac[index] = val & 0x7FFE;
2631 }
2632
2633 static void
2634 igb_update_rx_offloads(IGBCore *core)
2635 {
2636 int cso_state = igb_rx_l4_cso_enabled(core);
2637
2638 trace_e1000e_rx_set_cso(cso_state);
2639
2640 if (core->has_vnet) {
2641 qemu_set_offload(qemu_get_queue(core->owner_nic)->peer,
2642 cso_state, 0, 0, 0, 0);
2643 }
2644 }
2645
2646 static void
2647 igb_set_rxcsum(IGBCore *core, int index, uint32_t val)
2648 {
2649 core->mac[RXCSUM] = val;
2650 igb_update_rx_offloads(core);
2651 }
2652
2653 static void
2654 igb_set_gcr(IGBCore *core, int index, uint32_t val)
2655 {
2656 uint32_t ro_bits = core->mac[GCR] & E1000_GCR_RO_BITS;
2657 core->mac[GCR] = (val & ~E1000_GCR_RO_BITS) | ro_bits;
2658 }
2659
2660 static uint32_t igb_get_systiml(IGBCore *core, int index)
2661 {
2662 e1000x_timestamp(core->mac, core->timadj, SYSTIML, SYSTIMH);
2663 return core->mac[SYSTIML];
2664 }
2665
2666 static uint32_t igb_get_rxsatrh(IGBCore *core, int index)
2667 {
2668 core->mac[TSYNCRXCTL] &= ~E1000_TSYNCRXCTL_VALID;
2669 return core->mac[RXSATRH];
2670 }
2671
2672 static uint32_t igb_get_txstmph(IGBCore *core, int index)
2673 {
2674 core->mac[TSYNCTXCTL] &= ~E1000_TSYNCTXCTL_VALID;
2675 return core->mac[TXSTMPH];
2676 }
2677
2678 static void igb_set_timinca(IGBCore *core, int index, uint32_t val)
2679 {
2680 e1000x_set_timinca(core->mac, &core->timadj, val);
2681 }
2682
2683 static void igb_set_timadjh(IGBCore *core, int index, uint32_t val)
2684 {
2685 core->mac[TIMADJH] = val;
2686 core->timadj += core->mac[TIMADJL] | ((int64_t)core->mac[TIMADJH] << 32);
2687 }
2688
2689 #define igb_getreg(x) [x] = igb_mac_readreg
2690 typedef uint32_t (*readops)(IGBCore *, int);
2691 static const readops igb_macreg_readops[] = {
2692 igb_getreg(WUFC),
2693 igb_getreg(MANC),
2694 igb_getreg(TOTL),
2695 igb_getreg(RDT0),
2696 igb_getreg(RDT1),
2697 igb_getreg(RDT2),
2698 igb_getreg(RDT3),
2699 igb_getreg(RDT4),
2700 igb_getreg(RDT5),
2701 igb_getreg(RDT6),
2702 igb_getreg(RDT7),
2703 igb_getreg(RDT8),
2704 igb_getreg(RDT9),
2705 igb_getreg(RDT10),
2706 igb_getreg(RDT11),
2707 igb_getreg(RDT12),
2708 igb_getreg(RDT13),
2709 igb_getreg(RDT14),
2710 igb_getreg(RDT15),
2711 igb_getreg(RDBAH0),
2712 igb_getreg(RDBAH1),
2713 igb_getreg(RDBAH2),
2714 igb_getreg(RDBAH3),
2715 igb_getreg(RDBAH4),
2716 igb_getreg(RDBAH5),
2717 igb_getreg(RDBAH6),
2718 igb_getreg(RDBAH7),
2719 igb_getreg(RDBAH8),
2720 igb_getreg(RDBAH9),
2721 igb_getreg(RDBAH10),
2722 igb_getreg(RDBAH11),
2723 igb_getreg(RDBAH12),
2724 igb_getreg(RDBAH13),
2725 igb_getreg(RDBAH14),
2726 igb_getreg(RDBAH15),
2727 igb_getreg(TDBAL0),
2728 igb_getreg(TDBAL1),
2729 igb_getreg(TDBAL2),
2730 igb_getreg(TDBAL3),
2731 igb_getreg(TDBAL4),
2732 igb_getreg(TDBAL5),
2733 igb_getreg(TDBAL6),
2734 igb_getreg(TDBAL7),
2735 igb_getreg(TDBAL8),
2736 igb_getreg(TDBAL9),
2737 igb_getreg(TDBAL10),
2738 igb_getreg(TDBAL11),
2739 igb_getreg(TDBAL12),
2740 igb_getreg(TDBAL13),
2741 igb_getreg(TDBAL14),
2742 igb_getreg(TDBAL15),
2743 igb_getreg(RDLEN0),
2744 igb_getreg(RDLEN1),
2745 igb_getreg(RDLEN2),
2746 igb_getreg(RDLEN3),
2747 igb_getreg(RDLEN4),
2748 igb_getreg(RDLEN5),
2749 igb_getreg(RDLEN6),
2750 igb_getreg(RDLEN7),
2751 igb_getreg(RDLEN8),
2752 igb_getreg(RDLEN9),
2753 igb_getreg(RDLEN10),
2754 igb_getreg(RDLEN11),
2755 igb_getreg(RDLEN12),
2756 igb_getreg(RDLEN13),
2757 igb_getreg(RDLEN14),
2758 igb_getreg(RDLEN15),
2759 igb_getreg(SRRCTL0),
2760 igb_getreg(SRRCTL1),
2761 igb_getreg(SRRCTL2),
2762 igb_getreg(SRRCTL3),
2763 igb_getreg(SRRCTL4),
2764 igb_getreg(SRRCTL5),
2765 igb_getreg(SRRCTL6),
2766 igb_getreg(SRRCTL7),
2767 igb_getreg(SRRCTL8),
2768 igb_getreg(SRRCTL9),
2769 igb_getreg(SRRCTL10),
2770 igb_getreg(SRRCTL11),
2771 igb_getreg(SRRCTL12),
2772 igb_getreg(SRRCTL13),
2773 igb_getreg(SRRCTL14),
2774 igb_getreg(SRRCTL15),
2775 igb_getreg(LATECOL),
2776 igb_getreg(XONTXC),
2777 igb_getreg(TDFH),
2778 igb_getreg(TDFT),
2779 igb_getreg(TDFHS),
2780 igb_getreg(TDFTS),
2781 igb_getreg(TDFPC),
2782 igb_getreg(WUS),
2783 igb_getreg(RDFH),
2784 igb_getreg(RDFT),
2785 igb_getreg(RDFHS),
2786 igb_getreg(RDFTS),
2787 igb_getreg(RDFPC),
2788 igb_getreg(GORCL),
2789 igb_getreg(MGTPRC),
2790 igb_getreg(EERD),
2791 igb_getreg(EIAC),
2792 igb_getreg(MANC2H),
2793 igb_getreg(RXCSUM),
2794 igb_getreg(GSCL_3),
2795 igb_getreg(GSCN_2),
2796 igb_getreg(FCAH),
2797 igb_getreg(FCRTH),
2798 igb_getreg(FLOP),
2799 igb_getreg(RXSTMPH),
2800 igb_getreg(TXSTMPL),
2801 igb_getreg(TIMADJL),
2802 igb_getreg(RDH0),
2803 igb_getreg(RDH1),
2804 igb_getreg(RDH2),
2805 igb_getreg(RDH3),
2806 igb_getreg(RDH4),
2807 igb_getreg(RDH5),
2808 igb_getreg(RDH6),
2809 igb_getreg(RDH7),
2810 igb_getreg(RDH8),
2811 igb_getreg(RDH9),
2812 igb_getreg(RDH10),
2813 igb_getreg(RDH11),
2814 igb_getreg(RDH12),
2815 igb_getreg(RDH13),
2816 igb_getreg(RDH14),
2817 igb_getreg(RDH15),
2818 igb_getreg(TDT0),
2819 igb_getreg(TDT1),
2820 igb_getreg(TDT2),
2821 igb_getreg(TDT3),
2822 igb_getreg(TDT4),
2823 igb_getreg(TDT5),
2824 igb_getreg(TDT6),
2825 igb_getreg(TDT7),
2826 igb_getreg(TDT8),
2827 igb_getreg(TDT9),
2828 igb_getreg(TDT10),
2829 igb_getreg(TDT11),
2830 igb_getreg(TDT12),
2831 igb_getreg(TDT13),
2832 igb_getreg(TDT14),
2833 igb_getreg(TDT15),
2834 igb_getreg(TNCRS),
2835 igb_getreg(RJC),
2836 igb_getreg(IAM),
2837 igb_getreg(GSCL_2),
2838 igb_getreg(TIPG),
2839 igb_getreg(FLMNGCTL),
2840 igb_getreg(FLMNGCNT),
2841 igb_getreg(TSYNCTXCTL),
2842 igb_getreg(EEMNGDATA),
2843 igb_getreg(CTRL_EXT),
2844 igb_getreg(SYSTIMH),
2845 igb_getreg(EEMNGCTL),
2846 igb_getreg(FLMNGDATA),
2847 igb_getreg(TSYNCRXCTL),
2848 igb_getreg(LEDCTL),
2849 igb_getreg(TCTL),
2850 igb_getreg(TCTL_EXT),
2851 igb_getreg(DTXCTL),
2852 igb_getreg(RXPBS),
2853 igb_getreg(TDH0),
2854 igb_getreg(TDH1),
2855 igb_getreg(TDH2),
2856 igb_getreg(TDH3),
2857 igb_getreg(TDH4),
2858 igb_getreg(TDH5),
2859 igb_getreg(TDH6),
2860 igb_getreg(TDH7),
2861 igb_getreg(TDH8),
2862 igb_getreg(TDH9),
2863 igb_getreg(TDH10),
2864 igb_getreg(TDH11),
2865 igb_getreg(TDH12),
2866 igb_getreg(TDH13),
2867 igb_getreg(TDH14),
2868 igb_getreg(TDH15),
2869 igb_getreg(ECOL),
2870 igb_getreg(DC),
2871 igb_getreg(RLEC),
2872 igb_getreg(XOFFTXC),
2873 igb_getreg(RFC),
2874 igb_getreg(RNBC),
2875 igb_getreg(MGTPTC),
2876 igb_getreg(TIMINCA),
2877 igb_getreg(FACTPS),
2878 igb_getreg(GSCL_1),
2879 igb_getreg(GSCN_0),
2880 igb_getreg(PBACLR),
2881 igb_getreg(FCTTV),
2882 igb_getreg(RXSATRL),
2883 igb_getreg(TORL),
2884 igb_getreg(TDLEN0),
2885 igb_getreg(TDLEN1),
2886 igb_getreg(TDLEN2),
2887 igb_getreg(TDLEN3),
2888 igb_getreg(TDLEN4),
2889 igb_getreg(TDLEN5),
2890 igb_getreg(TDLEN6),
2891 igb_getreg(TDLEN7),
2892 igb_getreg(TDLEN8),
2893 igb_getreg(TDLEN9),
2894 igb_getreg(TDLEN10),
2895 igb_getreg(TDLEN11),
2896 igb_getreg(TDLEN12),
2897 igb_getreg(TDLEN13),
2898 igb_getreg(TDLEN14),
2899 igb_getreg(TDLEN15),
2900 igb_getreg(MCC),
2901 igb_getreg(WUC),
2902 igb_getreg(EECD),
2903 igb_getreg(FCRTV),
2904 igb_getreg(TXDCTL0),
2905 igb_getreg(TXDCTL1),
2906 igb_getreg(TXDCTL2),
2907 igb_getreg(TXDCTL3),
2908 igb_getreg(TXDCTL4),
2909 igb_getreg(TXDCTL5),
2910 igb_getreg(TXDCTL6),
2911 igb_getreg(TXDCTL7),
2912 igb_getreg(TXDCTL8),
2913 igb_getreg(TXDCTL9),
2914 igb_getreg(TXDCTL10),
2915 igb_getreg(TXDCTL11),
2916 igb_getreg(TXDCTL12),
2917 igb_getreg(TXDCTL13),
2918 igb_getreg(TXDCTL14),
2919 igb_getreg(TXDCTL15),
2920 igb_getreg(TXCTL0),
2921 igb_getreg(TXCTL1),
2922 igb_getreg(TXCTL2),
2923 igb_getreg(TXCTL3),
2924 igb_getreg(TXCTL4),
2925 igb_getreg(TXCTL5),
2926 igb_getreg(TXCTL6),
2927 igb_getreg(TXCTL7),
2928 igb_getreg(TXCTL8),
2929 igb_getreg(TXCTL9),
2930 igb_getreg(TXCTL10),
2931 igb_getreg(TXCTL11),
2932 igb_getreg(TXCTL12),
2933 igb_getreg(TXCTL13),
2934 igb_getreg(TXCTL14),
2935 igb_getreg(TXCTL15),
2936 igb_getreg(TDWBAL0),
2937 igb_getreg(TDWBAL1),
2938 igb_getreg(TDWBAL2),
2939 igb_getreg(TDWBAL3),
2940 igb_getreg(TDWBAL4),
2941 igb_getreg(TDWBAL5),
2942 igb_getreg(TDWBAL6),
2943 igb_getreg(TDWBAL7),
2944 igb_getreg(TDWBAL8),
2945 igb_getreg(TDWBAL9),
2946 igb_getreg(TDWBAL10),
2947 igb_getreg(TDWBAL11),
2948 igb_getreg(TDWBAL12),
2949 igb_getreg(TDWBAL13),
2950 igb_getreg(TDWBAL14),
2951 igb_getreg(TDWBAL15),
2952 igb_getreg(TDWBAH0),
2953 igb_getreg(TDWBAH1),
2954 igb_getreg(TDWBAH2),
2955 igb_getreg(TDWBAH3),
2956 igb_getreg(TDWBAH4),
2957 igb_getreg(TDWBAH5),
2958 igb_getreg(TDWBAH6),
2959 igb_getreg(TDWBAH7),
2960 igb_getreg(TDWBAH8),
2961 igb_getreg(TDWBAH9),
2962 igb_getreg(TDWBAH10),
2963 igb_getreg(TDWBAH11),
2964 igb_getreg(TDWBAH12),
2965 igb_getreg(TDWBAH13),
2966 igb_getreg(TDWBAH14),
2967 igb_getreg(TDWBAH15),
2968 igb_getreg(PVTCTRL0),
2969 igb_getreg(PVTCTRL1),
2970 igb_getreg(PVTCTRL2),
2971 igb_getreg(PVTCTRL3),
2972 igb_getreg(PVTCTRL4),
2973 igb_getreg(PVTCTRL5),
2974 igb_getreg(PVTCTRL6),
2975 igb_getreg(PVTCTRL7),
2976 igb_getreg(PVTEIMS0),
2977 igb_getreg(PVTEIMS1),
2978 igb_getreg(PVTEIMS2),
2979 igb_getreg(PVTEIMS3),
2980 igb_getreg(PVTEIMS4),
2981 igb_getreg(PVTEIMS5),
2982 igb_getreg(PVTEIMS6),
2983 igb_getreg(PVTEIMS7),
2984 igb_getreg(PVTEIAC0),
2985 igb_getreg(PVTEIAC1),
2986 igb_getreg(PVTEIAC2),
2987 igb_getreg(PVTEIAC3),
2988 igb_getreg(PVTEIAC4),
2989 igb_getreg(PVTEIAC5),
2990 igb_getreg(PVTEIAC6),
2991 igb_getreg(PVTEIAC7),
2992 igb_getreg(PVTEIAM0),
2993 igb_getreg(PVTEIAM1),
2994 igb_getreg(PVTEIAM2),
2995 igb_getreg(PVTEIAM3),
2996 igb_getreg(PVTEIAM4),
2997 igb_getreg(PVTEIAM5),
2998 igb_getreg(PVTEIAM6),
2999 igb_getreg(PVTEIAM7),
3000 igb_getreg(PVFGPRC0),
3001 igb_getreg(PVFGPRC1),
3002 igb_getreg(PVFGPRC2),
3003 igb_getreg(PVFGPRC3),
3004 igb_getreg(PVFGPRC4),
3005 igb_getreg(PVFGPRC5),
3006 igb_getreg(PVFGPRC6),
3007 igb_getreg(PVFGPRC7),
3008 igb_getreg(PVFGPTC0),
3009 igb_getreg(PVFGPTC1),
3010 igb_getreg(PVFGPTC2),
3011 igb_getreg(PVFGPTC3),
3012 igb_getreg(PVFGPTC4),
3013 igb_getreg(PVFGPTC5),
3014 igb_getreg(PVFGPTC6),
3015 igb_getreg(PVFGPTC7),
3016 igb_getreg(PVFGORC0),
3017 igb_getreg(PVFGORC1),
3018 igb_getreg(PVFGORC2),
3019 igb_getreg(PVFGORC3),
3020 igb_getreg(PVFGORC4),
3021 igb_getreg(PVFGORC5),
3022 igb_getreg(PVFGORC6),
3023 igb_getreg(PVFGORC7),
3024 igb_getreg(PVFGOTC0),
3025 igb_getreg(PVFGOTC1),
3026 igb_getreg(PVFGOTC2),
3027 igb_getreg(PVFGOTC3),
3028 igb_getreg(PVFGOTC4),
3029 igb_getreg(PVFGOTC5),
3030 igb_getreg(PVFGOTC6),
3031 igb_getreg(PVFGOTC7),
3032 igb_getreg(PVFMPRC0),
3033 igb_getreg(PVFMPRC1),
3034 igb_getreg(PVFMPRC2),
3035 igb_getreg(PVFMPRC3),
3036 igb_getreg(PVFMPRC4),
3037 igb_getreg(PVFMPRC5),
3038 igb_getreg(PVFMPRC6),
3039 igb_getreg(PVFMPRC7),
3040 igb_getreg(PVFGPRLBC0),
3041 igb_getreg(PVFGPRLBC1),
3042 igb_getreg(PVFGPRLBC2),
3043 igb_getreg(PVFGPRLBC3),
3044 igb_getreg(PVFGPRLBC4),
3045 igb_getreg(PVFGPRLBC5),
3046 igb_getreg(PVFGPRLBC6),
3047 igb_getreg(PVFGPRLBC7),
3048 igb_getreg(PVFGPTLBC0),
3049 igb_getreg(PVFGPTLBC1),
3050 igb_getreg(PVFGPTLBC2),
3051 igb_getreg(PVFGPTLBC3),
3052 igb_getreg(PVFGPTLBC4),
3053 igb_getreg(PVFGPTLBC5),
3054 igb_getreg(PVFGPTLBC6),
3055 igb_getreg(PVFGPTLBC7),
3056 igb_getreg(PVFGORLBC0),
3057 igb_getreg(PVFGORLBC1),
3058 igb_getreg(PVFGORLBC2),
3059 igb_getreg(PVFGORLBC3),
3060 igb_getreg(PVFGORLBC4),
3061 igb_getreg(PVFGORLBC5),
3062 igb_getreg(PVFGORLBC6),
3063 igb_getreg(PVFGORLBC7),
3064 igb_getreg(PVFGOTLBC0),
3065 igb_getreg(PVFGOTLBC1),
3066 igb_getreg(PVFGOTLBC2),
3067 igb_getreg(PVFGOTLBC3),
3068 igb_getreg(PVFGOTLBC4),
3069 igb_getreg(PVFGOTLBC5),
3070 igb_getreg(PVFGOTLBC6),
3071 igb_getreg(PVFGOTLBC7),
3072 igb_getreg(RCTL),
3073 igb_getreg(MDIC),
3074 igb_getreg(FCRUC),
3075 igb_getreg(VET),
3076 igb_getreg(RDBAL0),
3077 igb_getreg(RDBAL1),
3078 igb_getreg(RDBAL2),
3079 igb_getreg(RDBAL3),
3080 igb_getreg(RDBAL4),
3081 igb_getreg(RDBAL5),
3082 igb_getreg(RDBAL6),
3083 igb_getreg(RDBAL7),
3084 igb_getreg(RDBAL8),
3085 igb_getreg(RDBAL9),
3086 igb_getreg(RDBAL10),
3087 igb_getreg(RDBAL11),
3088 igb_getreg(RDBAL12),
3089 igb_getreg(RDBAL13),
3090 igb_getreg(RDBAL14),
3091 igb_getreg(RDBAL15),
3092 igb_getreg(TDBAH0),
3093 igb_getreg(TDBAH1),
3094 igb_getreg(TDBAH2),
3095 igb_getreg(TDBAH3),
3096 igb_getreg(TDBAH4),
3097 igb_getreg(TDBAH5),
3098 igb_getreg(TDBAH6),
3099 igb_getreg(TDBAH7),
3100 igb_getreg(TDBAH8),
3101 igb_getreg(TDBAH9),
3102 igb_getreg(TDBAH10),
3103 igb_getreg(TDBAH11),
3104 igb_getreg(TDBAH12),
3105 igb_getreg(TDBAH13),
3106 igb_getreg(TDBAH14),
3107 igb_getreg(TDBAH15),
3108 igb_getreg(SCC),
3109 igb_getreg(COLC),
3110 igb_getreg(XOFFRXC),
3111 igb_getreg(IPAV),
3112 igb_getreg(GOTCL),
3113 igb_getreg(MGTPDC),
3114 igb_getreg(GCR),
3115 igb_getreg(MFVAL),
3116 igb_getreg(FUNCTAG),
3117 igb_getreg(GSCL_4),
3118 igb_getreg(GSCN_3),
3119 igb_getreg(MRQC),
3120 igb_getreg(FCT),
3121 igb_getreg(FLA),
3122 igb_getreg(RXDCTL0),
3123 igb_getreg(RXDCTL1),
3124 igb_getreg(RXDCTL2),
3125 igb_getreg(RXDCTL3),
3126 igb_getreg(RXDCTL4),
3127 igb_getreg(RXDCTL5),
3128 igb_getreg(RXDCTL6),
3129 igb_getreg(RXDCTL7),
3130 igb_getreg(RXDCTL8),
3131 igb_getreg(RXDCTL9),
3132 igb_getreg(RXDCTL10),
3133 igb_getreg(RXDCTL11),
3134 igb_getreg(RXDCTL12),
3135 igb_getreg(RXDCTL13),
3136 igb_getreg(RXDCTL14),
3137 igb_getreg(RXDCTL15),
3138 igb_getreg(RXSTMPL),
3139 igb_getreg(TIMADJH),
3140 igb_getreg(FCRTL),
3141 igb_getreg(XONRXC),
3142 igb_getreg(RFCTL),
3143 igb_getreg(GSCN_1),
3144 igb_getreg(FCAL),
3145 igb_getreg(GPIE),
3146 igb_getreg(TXPBS),
3147 igb_getreg(RLPML),
3148
3149 [TOTH] = igb_mac_read_clr8,
3150 [GOTCH] = igb_mac_read_clr8,
3151 [PRC64] = igb_mac_read_clr4,
3152 [PRC255] = igb_mac_read_clr4,
3153 [PRC1023] = igb_mac_read_clr4,
3154 [PTC64] = igb_mac_read_clr4,
3155 [PTC255] = igb_mac_read_clr4,
3156 [PTC1023] = igb_mac_read_clr4,
3157 [GPRC] = igb_mac_read_clr4,
3158 [TPT] = igb_mac_read_clr4,
3159 [RUC] = igb_mac_read_clr4,
3160 [BPRC] = igb_mac_read_clr4,
3161 [MPTC] = igb_mac_read_clr4,
3162 [IAC] = igb_mac_read_clr4,
3163 [ICR] = igb_mac_icr_read,
3164 [STATUS] = igb_get_status,
3165 [ICS] = igb_mac_ics_read,
3166 /*
3167 * 8.8.10: Reading the IMC register returns the value of the IMS register.
3168 */
3169 [IMC] = igb_mac_ims_read,
3170 [TORH] = igb_mac_read_clr8,
3171 [GORCH] = igb_mac_read_clr8,
3172 [PRC127] = igb_mac_read_clr4,
3173 [PRC511] = igb_mac_read_clr4,
3174 [PRC1522] = igb_mac_read_clr4,
3175 [PTC127] = igb_mac_read_clr4,
3176 [PTC511] = igb_mac_read_clr4,
3177 [PTC1522] = igb_mac_read_clr4,
3178 [GPTC] = igb_mac_read_clr4,
3179 [TPR] = igb_mac_read_clr4,
3180 [ROC] = igb_mac_read_clr4,
3181 [MPRC] = igb_mac_read_clr4,
3182 [BPTC] = igb_mac_read_clr4,
3183 [TSCTC] = igb_mac_read_clr4,
3184 [CTRL] = igb_get_ctrl,
3185 [SWSM] = igb_mac_swsm_read,
3186 [IMS] = igb_mac_ims_read,
3187 [SYSTIML] = igb_get_systiml,
3188 [RXSATRH] = igb_get_rxsatrh,
3189 [TXSTMPH] = igb_get_txstmph,
3190
3191 [CRCERRS ... MPC] = igb_mac_readreg,
3192 [IP6AT ... IP6AT + 3] = igb_mac_readreg,
3193 [IP4AT ... IP4AT + 6] = igb_mac_readreg,
3194 [RA ... RA + 31] = igb_mac_readreg,
3195 [RA2 ... RA2 + 31] = igb_mac_readreg,
3196 [WUPM ... WUPM + 31] = igb_mac_readreg,
3197 [MTA ... MTA + E1000_MC_TBL_SIZE - 1] = igb_mac_readreg,
3198 [VFTA ... VFTA + E1000_VLAN_FILTER_TBL_SIZE - 1] = igb_mac_readreg,
3199 [FFMT ... FFMT + 254] = igb_mac_readreg,
3200 [MDEF ... MDEF + 7] = igb_mac_readreg,
3201 [FTFT ... FTFT + 254] = igb_mac_readreg,
3202 [RETA ... RETA + 31] = igb_mac_readreg,
3203 [RSSRK ... RSSRK + 9] = igb_mac_readreg,
3204 [MAVTV0 ... MAVTV3] = igb_mac_readreg,
3205 [EITR0 ... EITR0 + IGB_INTR_NUM - 1] = igb_mac_eitr_read,
3206 [PVTEICR0] = igb_mac_read_clr4,
3207 [PVTEICR1] = igb_mac_read_clr4,
3208 [PVTEICR2] = igb_mac_read_clr4,
3209 [PVTEICR3] = igb_mac_read_clr4,
3210 [PVTEICR4] = igb_mac_read_clr4,
3211 [PVTEICR5] = igb_mac_read_clr4,
3212 [PVTEICR6] = igb_mac_read_clr4,
3213 [PVTEICR7] = igb_mac_read_clr4,
3214
3215 /* IGB specific: */
3216 [FWSM] = igb_mac_readreg,
3217 [SW_FW_SYNC] = igb_mac_readreg,
3218 [HTCBDPC] = igb_mac_read_clr4,
3219 [EICR] = igb_mac_read_clr4,
3220 [EIMS] = igb_mac_readreg,
3221 [EIAM] = igb_mac_readreg,
3222 [IVAR0 ... IVAR0 + 7] = igb_mac_readreg,
3223 igb_getreg(IVAR_MISC),
3224 igb_getreg(VT_CTL),
3225 [P2VMAILBOX0 ... P2VMAILBOX7] = igb_mac_readreg,
3226 [V2PMAILBOX0 ... V2PMAILBOX7] = igb_mac_vfmailbox_read,
3227 igb_getreg(MBVFICR),
3228 [VMBMEM0 ... VMBMEM0 + 127] = igb_mac_readreg,
3229 igb_getreg(MBVFIMR),
3230 igb_getreg(VFLRE),
3231 igb_getreg(VFRE),
3232 igb_getreg(VFTE),
3233 igb_getreg(QDE),
3234 igb_getreg(DTXSWC),
3235 igb_getreg(RPLOLR),
3236 [VLVF0 ... VLVF0 + E1000_VLVF_ARRAY_SIZE - 1] = igb_mac_readreg,
3237 [VMVIR0 ... VMVIR7] = igb_mac_readreg,
3238 [VMOLR0 ... VMOLR7] = igb_mac_readreg,
3239 [WVBR] = igb_mac_read_clr4,
3240 [RQDPC0] = igb_mac_read_clr4,
3241 [RQDPC1] = igb_mac_read_clr4,
3242 [RQDPC2] = igb_mac_read_clr4,
3243 [RQDPC3] = igb_mac_read_clr4,
3244 [RQDPC4] = igb_mac_read_clr4,
3245 [RQDPC5] = igb_mac_read_clr4,
3246 [RQDPC6] = igb_mac_read_clr4,
3247 [RQDPC7] = igb_mac_read_clr4,
3248 [RQDPC8] = igb_mac_read_clr4,
3249 [RQDPC9] = igb_mac_read_clr4,
3250 [RQDPC10] = igb_mac_read_clr4,
3251 [RQDPC11] = igb_mac_read_clr4,
3252 [RQDPC12] = igb_mac_read_clr4,
3253 [RQDPC13] = igb_mac_read_clr4,
3254 [RQDPC14] = igb_mac_read_clr4,
3255 [RQDPC15] = igb_mac_read_clr4,
3256 [VTIVAR ... VTIVAR + 7] = igb_mac_readreg,
3257 [VTIVAR_MISC ... VTIVAR_MISC + 7] = igb_mac_readreg,
3258 };
3259 enum { IGB_NREADOPS = ARRAY_SIZE(igb_macreg_readops) };
3260
3261 #define igb_putreg(x) [x] = igb_mac_writereg
3262 typedef void (*writeops)(IGBCore *, int, uint32_t);
3263 static const writeops igb_macreg_writeops[] = {
3264 igb_putreg(SWSM),
3265 igb_putreg(WUFC),
3266 igb_putreg(RDBAH0),
3267 igb_putreg(RDBAH1),
3268 igb_putreg(RDBAH2),
3269 igb_putreg(RDBAH3),
3270 igb_putreg(RDBAH4),
3271 igb_putreg(RDBAH5),
3272 igb_putreg(RDBAH6),
3273 igb_putreg(RDBAH7),
3274 igb_putreg(RDBAH8),
3275 igb_putreg(RDBAH9),
3276 igb_putreg(RDBAH10),
3277 igb_putreg(RDBAH11),
3278 igb_putreg(RDBAH12),
3279 igb_putreg(RDBAH13),
3280 igb_putreg(RDBAH14),
3281 igb_putreg(RDBAH15),
3282 igb_putreg(SRRCTL0),
3283 igb_putreg(SRRCTL1),
3284 igb_putreg(SRRCTL2),
3285 igb_putreg(SRRCTL3),
3286 igb_putreg(SRRCTL4),
3287 igb_putreg(SRRCTL5),
3288 igb_putreg(SRRCTL6),
3289 igb_putreg(SRRCTL7),
3290 igb_putreg(SRRCTL8),
3291 igb_putreg(SRRCTL9),
3292 igb_putreg(SRRCTL10),
3293 igb_putreg(SRRCTL11),
3294 igb_putreg(SRRCTL12),
3295 igb_putreg(SRRCTL13),
3296 igb_putreg(SRRCTL14),
3297 igb_putreg(SRRCTL15),
3298 igb_putreg(RXDCTL0),
3299 igb_putreg(RXDCTL1),
3300 igb_putreg(RXDCTL2),
3301 igb_putreg(RXDCTL3),
3302 igb_putreg(RXDCTL4),
3303 igb_putreg(RXDCTL5),
3304 igb_putreg(RXDCTL6),
3305 igb_putreg(RXDCTL7),
3306 igb_putreg(RXDCTL8),
3307 igb_putreg(RXDCTL9),
3308 igb_putreg(RXDCTL10),
3309 igb_putreg(RXDCTL11),
3310 igb_putreg(RXDCTL12),
3311 igb_putreg(RXDCTL13),
3312 igb_putreg(RXDCTL14),
3313 igb_putreg(RXDCTL15),
3314 igb_putreg(LEDCTL),
3315 igb_putreg(TCTL),
3316 igb_putreg(TCTL_EXT),
3317 igb_putreg(DTXCTL),
3318 igb_putreg(RXPBS),
3319 igb_putreg(RQDPC0),
3320 igb_putreg(FCAL),
3321 igb_putreg(FCRUC),
3322 igb_putreg(WUC),
3323 igb_putreg(WUS),
3324 igb_putreg(IPAV),
3325 igb_putreg(TDBAH0),
3326 igb_putreg(TDBAH1),
3327 igb_putreg(TDBAH2),
3328 igb_putreg(TDBAH3),
3329 igb_putreg(TDBAH4),
3330 igb_putreg(TDBAH5),
3331 igb_putreg(TDBAH6),
3332 igb_putreg(TDBAH7),
3333 igb_putreg(TDBAH8),
3334 igb_putreg(TDBAH9),
3335 igb_putreg(TDBAH10),
3336 igb_putreg(TDBAH11),
3337 igb_putreg(TDBAH12),
3338 igb_putreg(TDBAH13),
3339 igb_putreg(TDBAH14),
3340 igb_putreg(TDBAH15),
3341 igb_putreg(IAM),
3342 igb_putreg(MANC),
3343 igb_putreg(MANC2H),
3344 igb_putreg(MFVAL),
3345 igb_putreg(FACTPS),
3346 igb_putreg(FUNCTAG),
3347 igb_putreg(GSCL_1),
3348 igb_putreg(GSCL_2),
3349 igb_putreg(GSCL_3),
3350 igb_putreg(GSCL_4),
3351 igb_putreg(GSCN_0),
3352 igb_putreg(GSCN_1),
3353 igb_putreg(GSCN_2),
3354 igb_putreg(GSCN_3),
3355 igb_putreg(MRQC),
3356 igb_putreg(FLOP),
3357 igb_putreg(FLA),
3358 igb_putreg(TXDCTL0),
3359 igb_putreg(TXDCTL1),
3360 igb_putreg(TXDCTL2),
3361 igb_putreg(TXDCTL3),
3362 igb_putreg(TXDCTL4),
3363 igb_putreg(TXDCTL5),
3364 igb_putreg(TXDCTL6),
3365 igb_putreg(TXDCTL7),
3366 igb_putreg(TXDCTL8),
3367 igb_putreg(TXDCTL9),
3368 igb_putreg(TXDCTL10),
3369 igb_putreg(TXDCTL11),
3370 igb_putreg(TXDCTL12),
3371 igb_putreg(TXDCTL13),
3372 igb_putreg(TXDCTL14),
3373 igb_putreg(TXDCTL15),
3374 igb_putreg(TXCTL0),
3375 igb_putreg(TXCTL1),
3376 igb_putreg(TXCTL2),
3377 igb_putreg(TXCTL3),
3378 igb_putreg(TXCTL4),
3379 igb_putreg(TXCTL5),
3380 igb_putreg(TXCTL6),
3381 igb_putreg(TXCTL7),
3382 igb_putreg(TXCTL8),
3383 igb_putreg(TXCTL9),
3384 igb_putreg(TXCTL10),
3385 igb_putreg(TXCTL11),
3386 igb_putreg(TXCTL12),
3387 igb_putreg(TXCTL13),
3388 igb_putreg(TXCTL14),
3389 igb_putreg(TXCTL15),
3390 igb_putreg(TDWBAL0),
3391 igb_putreg(TDWBAL1),
3392 igb_putreg(TDWBAL2),
3393 igb_putreg(TDWBAL3),
3394 igb_putreg(TDWBAL4),
3395 igb_putreg(TDWBAL5),
3396 igb_putreg(TDWBAL6),
3397 igb_putreg(TDWBAL7),
3398 igb_putreg(TDWBAL8),
3399 igb_putreg(TDWBAL9),
3400 igb_putreg(TDWBAL10),
3401 igb_putreg(TDWBAL11),
3402 igb_putreg(TDWBAL12),
3403 igb_putreg(TDWBAL13),
3404 igb_putreg(TDWBAL14),
3405 igb_putreg(TDWBAL15),
3406 igb_putreg(TDWBAH0),
3407 igb_putreg(TDWBAH1),
3408 igb_putreg(TDWBAH2),
3409 igb_putreg(TDWBAH3),
3410 igb_putreg(TDWBAH4),
3411 igb_putreg(TDWBAH5),
3412 igb_putreg(TDWBAH6),
3413 igb_putreg(TDWBAH7),
3414 igb_putreg(TDWBAH8),
3415 igb_putreg(TDWBAH9),
3416 igb_putreg(TDWBAH10),
3417 igb_putreg(TDWBAH11),
3418 igb_putreg(TDWBAH12),
3419 igb_putreg(TDWBAH13),
3420 igb_putreg(TDWBAH14),
3421 igb_putreg(TDWBAH15),
3422 igb_putreg(TIPG),
3423 igb_putreg(RXSTMPH),
3424 igb_putreg(RXSTMPL),
3425 igb_putreg(RXSATRL),
3426 igb_putreg(RXSATRH),
3427 igb_putreg(TXSTMPL),
3428 igb_putreg(TXSTMPH),
3429 igb_putreg(SYSTIML),
3430 igb_putreg(SYSTIMH),
3431 igb_putreg(TIMADJL),
3432 igb_putreg(TSYNCRXCTL),
3433 igb_putreg(TSYNCTXCTL),
3434 igb_putreg(EEMNGCTL),
3435 igb_putreg(GPIE),
3436 igb_putreg(TXPBS),
3437 igb_putreg(RLPML),
3438 igb_putreg(VET),
3439
3440 [TDH0] = igb_set_16bit,
3441 [TDH1] = igb_set_16bit,
3442 [TDH2] = igb_set_16bit,
3443 [TDH3] = igb_set_16bit,
3444 [TDH4] = igb_set_16bit,
3445 [TDH5] = igb_set_16bit,
3446 [TDH6] = igb_set_16bit,
3447 [TDH7] = igb_set_16bit,
3448 [TDH8] = igb_set_16bit,
3449 [TDH9] = igb_set_16bit,
3450 [TDH10] = igb_set_16bit,
3451 [TDH11] = igb_set_16bit,
3452 [TDH12] = igb_set_16bit,
3453 [TDH13] = igb_set_16bit,
3454 [TDH14] = igb_set_16bit,
3455 [TDH15] = igb_set_16bit,
3456 [TDT0] = igb_set_tdt,
3457 [TDT1] = igb_set_tdt,
3458 [TDT2] = igb_set_tdt,
3459 [TDT3] = igb_set_tdt,
3460 [TDT4] = igb_set_tdt,
3461 [TDT5] = igb_set_tdt,
3462 [TDT6] = igb_set_tdt,
3463 [TDT7] = igb_set_tdt,
3464 [TDT8] = igb_set_tdt,
3465 [TDT9] = igb_set_tdt,
3466 [TDT10] = igb_set_tdt,
3467 [TDT11] = igb_set_tdt,
3468 [TDT12] = igb_set_tdt,
3469 [TDT13] = igb_set_tdt,
3470 [TDT14] = igb_set_tdt,
3471 [TDT15] = igb_set_tdt,
3472 [MDIC] = igb_set_mdic,
3473 [ICS] = igb_set_ics,
3474 [RDH0] = igb_set_16bit,
3475 [RDH1] = igb_set_16bit,
3476 [RDH2] = igb_set_16bit,
3477 [RDH3] = igb_set_16bit,
3478 [RDH4] = igb_set_16bit,
3479 [RDH5] = igb_set_16bit,
3480 [RDH6] = igb_set_16bit,
3481 [RDH7] = igb_set_16bit,
3482 [RDH8] = igb_set_16bit,
3483 [RDH9] = igb_set_16bit,
3484 [RDH10] = igb_set_16bit,
3485 [RDH11] = igb_set_16bit,
3486 [RDH12] = igb_set_16bit,
3487 [RDH13] = igb_set_16bit,
3488 [RDH14] = igb_set_16bit,
3489 [RDH15] = igb_set_16bit,
3490 [RDT0] = igb_set_rdt,
3491 [RDT1] = igb_set_rdt,
3492 [RDT2] = igb_set_rdt,
3493 [RDT3] = igb_set_rdt,
3494 [RDT4] = igb_set_rdt,
3495 [RDT5] = igb_set_rdt,
3496 [RDT6] = igb_set_rdt,
3497 [RDT7] = igb_set_rdt,
3498 [RDT8] = igb_set_rdt,
3499 [RDT9] = igb_set_rdt,
3500 [RDT10] = igb_set_rdt,
3501 [RDT11] = igb_set_rdt,
3502 [RDT12] = igb_set_rdt,
3503 [RDT13] = igb_set_rdt,
3504 [RDT14] = igb_set_rdt,
3505 [RDT15] = igb_set_rdt,
3506 [IMC] = igb_set_imc,
3507 [IMS] = igb_set_ims,
3508 [ICR] = igb_set_icr,
3509 [EECD] = igb_set_eecd,
3510 [RCTL] = igb_set_rx_control,
3511 [CTRL] = igb_set_ctrl,
3512 [EERD] = igb_set_eerd,
3513 [TDFH] = igb_set_13bit,
3514 [TDFT] = igb_set_13bit,
3515 [TDFHS] = igb_set_13bit,
3516 [TDFTS] = igb_set_13bit,
3517 [TDFPC] = igb_set_13bit,
3518 [RDFH] = igb_set_13bit,
3519 [RDFT] = igb_set_13bit,
3520 [RDFHS] = igb_set_13bit,
3521 [RDFTS] = igb_set_13bit,
3522 [RDFPC] = igb_set_13bit,
3523 [GCR] = igb_set_gcr,
3524 [RXCSUM] = igb_set_rxcsum,
3525 [TDLEN0] = igb_set_dlen,
3526 [TDLEN1] = igb_set_dlen,
3527 [TDLEN2] = igb_set_dlen,
3528 [TDLEN3] = igb_set_dlen,
3529 [TDLEN4] = igb_set_dlen,
3530 [TDLEN5] = igb_set_dlen,
3531 [TDLEN6] = igb_set_dlen,
3532 [TDLEN7] = igb_set_dlen,
3533 [TDLEN8] = igb_set_dlen,
3534 [TDLEN9] = igb_set_dlen,
3535 [TDLEN10] = igb_set_dlen,
3536 [TDLEN11] = igb_set_dlen,
3537 [TDLEN12] = igb_set_dlen,
3538 [TDLEN13] = igb_set_dlen,
3539 [TDLEN14] = igb_set_dlen,
3540 [TDLEN15] = igb_set_dlen,
3541 [RDLEN0] = igb_set_dlen,
3542 [RDLEN1] = igb_set_dlen,
3543 [RDLEN2] = igb_set_dlen,
3544 [RDLEN3] = igb_set_dlen,
3545 [RDLEN4] = igb_set_dlen,
3546 [RDLEN5] = igb_set_dlen,
3547 [RDLEN6] = igb_set_dlen,
3548 [RDLEN7] = igb_set_dlen,
3549 [RDLEN8] = igb_set_dlen,
3550 [RDLEN9] = igb_set_dlen,
3551 [RDLEN10] = igb_set_dlen,
3552 [RDLEN11] = igb_set_dlen,
3553 [RDLEN12] = igb_set_dlen,
3554 [RDLEN13] = igb_set_dlen,
3555 [RDLEN14] = igb_set_dlen,
3556 [RDLEN15] = igb_set_dlen,
3557 [TDBAL0] = igb_set_dbal,
3558 [TDBAL1] = igb_set_dbal,
3559 [TDBAL2] = igb_set_dbal,
3560 [TDBAL3] = igb_set_dbal,
3561 [TDBAL4] = igb_set_dbal,
3562 [TDBAL5] = igb_set_dbal,
3563 [TDBAL6] = igb_set_dbal,
3564 [TDBAL7] = igb_set_dbal,
3565 [TDBAL8] = igb_set_dbal,
3566 [TDBAL9] = igb_set_dbal,
3567 [TDBAL10] = igb_set_dbal,
3568 [TDBAL11] = igb_set_dbal,
3569 [TDBAL12] = igb_set_dbal,
3570 [TDBAL13] = igb_set_dbal,
3571 [TDBAL14] = igb_set_dbal,
3572 [TDBAL15] = igb_set_dbal,
3573 [RDBAL0] = igb_set_dbal,
3574 [RDBAL1] = igb_set_dbal,
3575 [RDBAL2] = igb_set_dbal,
3576 [RDBAL3] = igb_set_dbal,
3577 [RDBAL4] = igb_set_dbal,
3578 [RDBAL5] = igb_set_dbal,
3579 [RDBAL6] = igb_set_dbal,
3580 [RDBAL7] = igb_set_dbal,
3581 [RDBAL8] = igb_set_dbal,
3582 [RDBAL9] = igb_set_dbal,
3583 [RDBAL10] = igb_set_dbal,
3584 [RDBAL11] = igb_set_dbal,
3585 [RDBAL12] = igb_set_dbal,
3586 [RDBAL13] = igb_set_dbal,
3587 [RDBAL14] = igb_set_dbal,
3588 [RDBAL15] = igb_set_dbal,
3589 [STATUS] = igb_set_status,
3590 [PBACLR] = igb_set_pbaclr,
3591 [CTRL_EXT] = igb_set_ctrlext,
3592 [FCAH] = igb_set_16bit,
3593 [FCT] = igb_set_16bit,
3594 [FCTTV] = igb_set_16bit,
3595 [FCRTV] = igb_set_16bit,
3596 [FCRTH] = igb_set_fcrth,
3597 [FCRTL] = igb_set_fcrtl,
3598 [CTRL_DUP] = igb_set_ctrl,
3599 [RFCTL] = igb_set_rfctl,
3600 [TIMINCA] = igb_set_timinca,
3601 [TIMADJH] = igb_set_timadjh,
3602
3603 [IP6AT ... IP6AT + 3] = igb_mac_writereg,
3604 [IP4AT ... IP4AT + 6] = igb_mac_writereg,
3605 [RA] = igb_mac_writereg,
3606 [RA + 1] = igb_mac_setmacaddr,
3607 [RA + 2 ... RA + 31] = igb_mac_writereg,
3608 [RA2 ... RA2 + 31] = igb_mac_writereg,
3609 [WUPM ... WUPM + 31] = igb_mac_writereg,
3610 [MTA ... MTA + E1000_MC_TBL_SIZE - 1] = igb_mac_writereg,
3611 [VFTA ... VFTA + E1000_VLAN_FILTER_TBL_SIZE - 1] = igb_mac_writereg,
3612 [FFMT ... FFMT + 254] = igb_set_4bit,
3613 [MDEF ... MDEF + 7] = igb_mac_writereg,
3614 [FTFT ... FTFT + 254] = igb_mac_writereg,
3615 [RETA ... RETA + 31] = igb_mac_writereg,
3616 [RSSRK ... RSSRK + 9] = igb_mac_writereg,
3617 [MAVTV0 ... MAVTV3] = igb_mac_writereg,
3618 [EITR0 ... EITR0 + IGB_INTR_NUM - 1] = igb_set_eitr,
3619
3620 /* IGB specific: */
3621 [FWSM] = igb_mac_writereg,
3622 [SW_FW_SYNC] = igb_mac_writereg,
3623 [EICR] = igb_set_eicr,
3624 [EICS] = igb_set_eics,
3625 [EIAC] = igb_set_eiac,
3626 [EIAM] = igb_set_eiam,
3627 [EIMC] = igb_set_eimc,
3628 [EIMS] = igb_set_eims,
3629 [IVAR0 ... IVAR0 + 7] = igb_mac_writereg,
3630 igb_putreg(IVAR_MISC),
3631 igb_putreg(VT_CTL),
3632 [P2VMAILBOX0 ... P2VMAILBOX7] = igb_set_pfmailbox,
3633 [V2PMAILBOX0 ... V2PMAILBOX7] = igb_set_vfmailbox,
3634 [MBVFICR] = igb_w1c,
3635 [VMBMEM0 ... VMBMEM0 + 127] = igb_mac_writereg,
3636 igb_putreg(MBVFIMR),
3637 [VFLRE] = igb_w1c,
3638 igb_putreg(VFRE),
3639 igb_putreg(VFTE),
3640 igb_putreg(QDE),
3641 igb_putreg(DTXSWC),
3642 igb_putreg(RPLOLR),
3643 [VLVF0 ... VLVF0 + E1000_VLVF_ARRAY_SIZE - 1] = igb_mac_writereg,
3644 [VMVIR0 ... VMVIR7] = igb_mac_writereg,
3645 [VMOLR0 ... VMOLR7] = igb_mac_writereg,
3646 [UTA ... UTA + E1000_MC_TBL_SIZE - 1] = igb_mac_writereg,
3647 [PVTCTRL0] = igb_set_vtctrl,
3648 [PVTCTRL1] = igb_set_vtctrl,
3649 [PVTCTRL2] = igb_set_vtctrl,
3650 [PVTCTRL3] = igb_set_vtctrl,
3651 [PVTCTRL4] = igb_set_vtctrl,
3652 [PVTCTRL5] = igb_set_vtctrl,
3653 [PVTCTRL6] = igb_set_vtctrl,
3654 [PVTCTRL7] = igb_set_vtctrl,
3655 [PVTEICS0] = igb_set_vteics,
3656 [PVTEICS1] = igb_set_vteics,
3657 [PVTEICS2] = igb_set_vteics,
3658 [PVTEICS3] = igb_set_vteics,
3659 [PVTEICS4] = igb_set_vteics,
3660 [PVTEICS5] = igb_set_vteics,
3661 [PVTEICS6] = igb_set_vteics,
3662 [PVTEICS7] = igb_set_vteics,
3663 [PVTEIMS0] = igb_set_vteims,
3664 [PVTEIMS1] = igb_set_vteims,
3665 [PVTEIMS2] = igb_set_vteims,
3666 [PVTEIMS3] = igb_set_vteims,
3667 [PVTEIMS4] = igb_set_vteims,
3668 [PVTEIMS5] = igb_set_vteims,
3669 [PVTEIMS6] = igb_set_vteims,
3670 [PVTEIMS7] = igb_set_vteims,
3671 [PVTEIMC0] = igb_set_vteimc,
3672 [PVTEIMC1] = igb_set_vteimc,
3673 [PVTEIMC2] = igb_set_vteimc,
3674 [PVTEIMC3] = igb_set_vteimc,
3675 [PVTEIMC4] = igb_set_vteimc,
3676 [PVTEIMC5] = igb_set_vteimc,
3677 [PVTEIMC6] = igb_set_vteimc,
3678 [PVTEIMC7] = igb_set_vteimc,
3679 [PVTEIAC0] = igb_set_vteiac,
3680 [PVTEIAC1] = igb_set_vteiac,
3681 [PVTEIAC2] = igb_set_vteiac,
3682 [PVTEIAC3] = igb_set_vteiac,
3683 [PVTEIAC4] = igb_set_vteiac,
3684 [PVTEIAC5] = igb_set_vteiac,
3685 [PVTEIAC6] = igb_set_vteiac,
3686 [PVTEIAC7] = igb_set_vteiac,
3687 [PVTEIAM0] = igb_set_vteiam,
3688 [PVTEIAM1] = igb_set_vteiam,
3689 [PVTEIAM2] = igb_set_vteiam,
3690 [PVTEIAM3] = igb_set_vteiam,
3691 [PVTEIAM4] = igb_set_vteiam,
3692 [PVTEIAM5] = igb_set_vteiam,
3693 [PVTEIAM6] = igb_set_vteiam,
3694 [PVTEIAM7] = igb_set_vteiam,
3695 [PVTEICR0] = igb_set_vteicr,
3696 [PVTEICR1] = igb_set_vteicr,
3697 [PVTEICR2] = igb_set_vteicr,
3698 [PVTEICR3] = igb_set_vteicr,
3699 [PVTEICR4] = igb_set_vteicr,
3700 [PVTEICR5] = igb_set_vteicr,
3701 [PVTEICR6] = igb_set_vteicr,
3702 [PVTEICR7] = igb_set_vteicr,
3703 [VTIVAR ... VTIVAR + 7] = igb_set_vtivar,
3704 [VTIVAR_MISC ... VTIVAR_MISC + 7] = igb_mac_writereg
3705 };
3706 enum { IGB_NWRITEOPS = ARRAY_SIZE(igb_macreg_writeops) };
3707
3708 enum { MAC_ACCESS_PARTIAL = 1 };
3709
3710 /*
3711 * The array below combines alias offsets of the index values for the
3712 * MAC registers that have aliases, with the indication of not fully
3713 * implemented registers (lowest bit). This combination is possible
3714 * because all of the offsets are even.
3715 */
3716 static const uint16_t mac_reg_access[E1000E_MAC_SIZE] = {
3717 /* Alias index offsets */
3718 [FCRTL_A] = 0x07fe,
3719 [RDFH_A] = 0xe904, [RDFT_A] = 0xe904,
3720 [TDFH_A] = 0xed00, [TDFT_A] = 0xed00,
3721 [RA_A ... RA_A + 31] = 0x14f0,
3722 [VFTA_A ... VFTA_A + E1000_VLAN_FILTER_TBL_SIZE - 1] = 0x1400,
3723
3724 [RDBAL0_A] = 0x2600,
3725 [RDBAH0_A] = 0x2600,
3726 [RDLEN0_A] = 0x2600,
3727 [SRRCTL0_A] = 0x2600,
3728 [RDH0_A] = 0x2600,
3729 [RDT0_A] = 0x2600,
3730 [RXDCTL0_A] = 0x2600,
3731 [RXCTL0_A] = 0x2600,
3732 [RQDPC0_A] = 0x2600,
3733 [RDBAL1_A] = 0x25D0,
3734 [RDBAL2_A] = 0x25A0,
3735 [RDBAL3_A] = 0x2570,
3736 [RDBAH1_A] = 0x25D0,
3737 [RDBAH2_A] = 0x25A0,
3738 [RDBAH3_A] = 0x2570,
3739 [RDLEN1_A] = 0x25D0,
3740 [RDLEN2_A] = 0x25A0,
3741 [RDLEN3_A] = 0x2570,
3742 [SRRCTL1_A] = 0x25D0,
3743 [SRRCTL2_A] = 0x25A0,
3744 [SRRCTL3_A] = 0x2570,
3745 [RDH1_A] = 0x25D0,
3746 [RDH2_A] = 0x25A0,
3747 [RDH3_A] = 0x2570,
3748 [RDT1_A] = 0x25D0,
3749 [RDT2_A] = 0x25A0,
3750 [RDT3_A] = 0x2570,
3751 [RXDCTL1_A] = 0x25D0,
3752 [RXDCTL2_A] = 0x25A0,
3753 [RXDCTL3_A] = 0x2570,
3754 [RXCTL1_A] = 0x25D0,
3755 [RXCTL2_A] = 0x25A0,
3756 [RXCTL3_A] = 0x2570,
3757 [RQDPC1_A] = 0x25D0,
3758 [RQDPC2_A] = 0x25A0,
3759 [RQDPC3_A] = 0x2570,
3760 [TDBAL0_A] = 0x2A00,
3761 [TDBAH0_A] = 0x2A00,
3762 [TDLEN0_A] = 0x2A00,
3763 [TDH0_A] = 0x2A00,
3764 [TDT0_A] = 0x2A00,
3765 [TXCTL0_A] = 0x2A00,
3766 [TDWBAL0_A] = 0x2A00,
3767 [TDWBAH0_A] = 0x2A00,
3768 [TDBAL1_A] = 0x29D0,
3769 [TDBAL2_A] = 0x29A0,
3770 [TDBAL3_A] = 0x2970,
3771 [TDBAH1_A] = 0x29D0,
3772 [TDBAH2_A] = 0x29A0,
3773 [TDBAH3_A] = 0x2970,
3774 [TDLEN1_A] = 0x29D0,
3775 [TDLEN2_A] = 0x29A0,
3776 [TDLEN3_A] = 0x2970,
3777 [TDH1_A] = 0x29D0,
3778 [TDH2_A] = 0x29A0,
3779 [TDH3_A] = 0x2970,
3780 [TDT1_A] = 0x29D0,
3781 [TDT2_A] = 0x29A0,
3782 [TDT3_A] = 0x2970,
3783 [TXDCTL0_A] = 0x2A00,
3784 [TXDCTL1_A] = 0x29D0,
3785 [TXDCTL2_A] = 0x29A0,
3786 [TXDCTL3_A] = 0x2970,
3787 [TXCTL1_A] = 0x29D0,
3788 [TXCTL2_A] = 0x29A0,
3789 [TXCTL3_A] = 0x29D0,
3790 [TDWBAL1_A] = 0x29D0,
3791 [TDWBAL2_A] = 0x29A0,
3792 [TDWBAL3_A] = 0x2970,
3793 [TDWBAH1_A] = 0x29D0,
3794 [TDWBAH2_A] = 0x29A0,
3795 [TDWBAH3_A] = 0x2970,
3796
3797 /* Access options */
3798 [RDFH] = MAC_ACCESS_PARTIAL, [RDFT] = MAC_ACCESS_PARTIAL,
3799 [RDFHS] = MAC_ACCESS_PARTIAL, [RDFTS] = MAC_ACCESS_PARTIAL,
3800 [RDFPC] = MAC_ACCESS_PARTIAL,
3801 [TDFH] = MAC_ACCESS_PARTIAL, [TDFT] = MAC_ACCESS_PARTIAL,
3802 [TDFHS] = MAC_ACCESS_PARTIAL, [TDFTS] = MAC_ACCESS_PARTIAL,
3803 [TDFPC] = MAC_ACCESS_PARTIAL, [EECD] = MAC_ACCESS_PARTIAL,
3804 [FLA] = MAC_ACCESS_PARTIAL,
3805 [FCAL] = MAC_ACCESS_PARTIAL, [FCAH] = MAC_ACCESS_PARTIAL,
3806 [FCT] = MAC_ACCESS_PARTIAL, [FCTTV] = MAC_ACCESS_PARTIAL,
3807 [FCRTV] = MAC_ACCESS_PARTIAL, [FCRTL] = MAC_ACCESS_PARTIAL,
3808 [FCRTH] = MAC_ACCESS_PARTIAL,
3809 [MAVTV0 ... MAVTV3] = MAC_ACCESS_PARTIAL
3810 };
3811
3812 void
3813 igb_core_write(IGBCore *core, hwaddr addr, uint64_t val, unsigned size)
3814 {
3815 uint16_t index = igb_get_reg_index_with_offset(mac_reg_access, addr);
3816
3817 if (index < IGB_NWRITEOPS && igb_macreg_writeops[index]) {
3818 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) {
3819 trace_e1000e_wrn_regs_write_trivial(index << 2);
3820 }
3821 trace_e1000e_core_write(index << 2, size, val);
3822 igb_macreg_writeops[index](core, index, val);
3823 } else if (index < IGB_NREADOPS && igb_macreg_readops[index]) {
3824 trace_e1000e_wrn_regs_write_ro(index << 2, size, val);
3825 } else {
3826 trace_e1000e_wrn_regs_write_unknown(index << 2, size, val);
3827 }
3828 }
3829
3830 uint64_t
3831 igb_core_read(IGBCore *core, hwaddr addr, unsigned size)
3832 {
3833 uint64_t val;
3834 uint16_t index = igb_get_reg_index_with_offset(mac_reg_access, addr);
3835
3836 if (index < IGB_NREADOPS && igb_macreg_readops[index]) {
3837 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) {
3838 trace_e1000e_wrn_regs_read_trivial(index << 2);
3839 }
3840 val = igb_macreg_readops[index](core, index);
3841 trace_e1000e_core_read(index << 2, size, val);
3842 return val;
3843 } else {
3844 trace_e1000e_wrn_regs_read_unknown(index << 2, size);
3845 }
3846 return 0;
3847 }
3848
3849 static inline void
3850 igb_autoneg_pause(IGBCore *core)
3851 {
3852 timer_del(core->autoneg_timer);
3853 }
3854
3855 static void
3856 igb_autoneg_resume(IGBCore *core)
3857 {
3858 if (igb_have_autoneg(core) &&
3859 !(core->phy[MII_BMSR] & MII_BMSR_AN_COMP)) {
3860 qemu_get_queue(core->owner_nic)->link_down = false;
3861 timer_mod(core->autoneg_timer,
3862 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 500);
3863 }
3864 }
3865
3866 static void
3867 igb_vm_state_change(void *opaque, bool running, RunState state)
3868 {
3869 IGBCore *core = opaque;
3870
3871 if (running) {
3872 trace_e1000e_vm_state_running();
3873 igb_intrmgr_resume(core);
3874 igb_autoneg_resume(core);
3875 } else {
3876 trace_e1000e_vm_state_stopped();
3877 igb_autoneg_pause(core);
3878 igb_intrmgr_pause(core);
3879 }
3880 }
3881
3882 void
3883 igb_core_pci_realize(IGBCore *core,
3884 const uint16_t *eeprom_templ,
3885 uint32_t eeprom_size,
3886 const uint8_t *macaddr)
3887 {
3888 int i;
3889
3890 core->autoneg_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL,
3891 igb_autoneg_timer, core);
3892 igb_intrmgr_pci_realize(core);
3893
3894 core->vmstate = qemu_add_vm_change_state_handler(igb_vm_state_change, core);
3895
3896 for (i = 0; i < IGB_NUM_QUEUES; i++) {
3897 net_tx_pkt_init(&core->tx[i].tx_pkt, NULL, E1000E_MAX_TX_FRAGS);
3898 }
3899
3900 net_rx_pkt_init(&core->rx_pkt);
3901
3902 e1000x_core_prepare_eeprom(core->eeprom,
3903 eeprom_templ,
3904 eeprom_size,
3905 PCI_DEVICE_GET_CLASS(core->owner)->device_id,
3906 macaddr);
3907 igb_update_rx_offloads(core);
3908 }
3909
3910 void
3911 igb_core_pci_uninit(IGBCore *core)
3912 {
3913 int i;
3914
3915 timer_free(core->autoneg_timer);
3916
3917 igb_intrmgr_pci_unint(core);
3918
3919 qemu_del_vm_change_state_handler(core->vmstate);
3920
3921 for (i = 0; i < IGB_NUM_QUEUES; i++) {
3922 net_tx_pkt_reset(core->tx[i].tx_pkt, NULL);
3923 net_tx_pkt_uninit(core->tx[i].tx_pkt);
3924 }
3925
3926 net_rx_pkt_uninit(core->rx_pkt);
3927 }
3928
3929 static const uint16_t
3930 igb_phy_reg_init[] = {
3931 [MII_BMCR] = MII_BMCR_SPEED1000 |
3932 MII_BMCR_FD |
3933 MII_BMCR_AUTOEN,
3934
3935 [MII_BMSR] = MII_BMSR_EXTCAP |
3936 MII_BMSR_LINK_ST |
3937 MII_BMSR_AUTONEG |
3938 MII_BMSR_MFPS |
3939 MII_BMSR_EXTSTAT |
3940 MII_BMSR_10T_HD |
3941 MII_BMSR_10T_FD |
3942 MII_BMSR_100TX_HD |
3943 MII_BMSR_100TX_FD,
3944
3945 [MII_PHYID1] = IGP03E1000_E_PHY_ID >> 16,
3946 [MII_PHYID2] = (IGP03E1000_E_PHY_ID & 0xfff0) | 1,
3947 [MII_ANAR] = MII_ANAR_CSMACD | MII_ANAR_10 |
3948 MII_ANAR_10FD | MII_ANAR_TX |
3949 MII_ANAR_TXFD | MII_ANAR_PAUSE |
3950 MII_ANAR_PAUSE_ASYM,
3951 [MII_ANLPAR] = MII_ANLPAR_10 | MII_ANLPAR_10FD |
3952 MII_ANLPAR_TX | MII_ANLPAR_TXFD |
3953 MII_ANLPAR_T4 | MII_ANLPAR_PAUSE,
3954 [MII_ANER] = MII_ANER_NP | MII_ANER_NWAY,
3955 [MII_ANNP] = 0x1 | MII_ANNP_MP,
3956 [MII_CTRL1000] = MII_CTRL1000_HALF | MII_CTRL1000_FULL |
3957 MII_CTRL1000_PORT | MII_CTRL1000_MASTER,
3958 [MII_STAT1000] = MII_STAT1000_HALF | MII_STAT1000_FULL |
3959 MII_STAT1000_ROK | MII_STAT1000_LOK,
3960 [MII_EXTSTAT] = MII_EXTSTAT_1000T_HD | MII_EXTSTAT_1000T_FD,
3961
3962 [IGP01E1000_PHY_PORT_CONFIG] = BIT(5) | BIT(8),
3963 [IGP01E1000_PHY_PORT_STATUS] = IGP01E1000_PSSR_SPEED_1000MBPS,
3964 [IGP02E1000_PHY_POWER_MGMT] = BIT(0) | BIT(3) | IGP02E1000_PM_D3_LPLU |
3965 IGP01E1000_PSCFR_SMART_SPEED
3966 };
3967
3968 static const uint32_t igb_mac_reg_init[] = {
3969 [LEDCTL] = 2 | (3 << 8) | BIT(15) | (6 << 16) | (7 << 24),
3970 [EEMNGCTL] = BIT(31),
3971 [TXDCTL0] = E1000_TXDCTL_QUEUE_ENABLE,
3972 [RXDCTL0] = E1000_RXDCTL_QUEUE_ENABLE | (1 << 16),
3973 [RXDCTL1] = 1 << 16,
3974 [RXDCTL2] = 1 << 16,
3975 [RXDCTL3] = 1 << 16,
3976 [RXDCTL4] = 1 << 16,
3977 [RXDCTL5] = 1 << 16,
3978 [RXDCTL6] = 1 << 16,
3979 [RXDCTL7] = 1 << 16,
3980 [RXDCTL8] = 1 << 16,
3981 [RXDCTL9] = 1 << 16,
3982 [RXDCTL10] = 1 << 16,
3983 [RXDCTL11] = 1 << 16,
3984 [RXDCTL12] = 1 << 16,
3985 [RXDCTL13] = 1 << 16,
3986 [RXDCTL14] = 1 << 16,
3987 [RXDCTL15] = 1 << 16,
3988 [TIPG] = 0x08 | (0x04 << 10) | (0x06 << 20),
3989 [CTRL] = E1000_CTRL_FD | E1000_CTRL_LRST | E1000_CTRL_SPD_1000 |
3990 E1000_CTRL_ADVD3WUC,
3991 [STATUS] = E1000_STATUS_PHYRA | BIT(31),
3992 [EECD] = E1000_EECD_FWE_DIS | E1000_EECD_PRES |
3993 (2 << E1000_EECD_SIZE_EX_SHIFT),
3994 [GCR] = E1000_L0S_ADJUST |
3995 E1000_GCR_CMPL_TMOUT_RESEND |
3996 E1000_GCR_CAP_VER2 |
3997 E1000_L1_ENTRY_LATENCY_MSB |
3998 E1000_L1_ENTRY_LATENCY_LSB,
3999 [RXCSUM] = E1000_RXCSUM_IPOFLD | E1000_RXCSUM_TUOFLD,
4000 [TXPBS] = 0x28,
4001 [RXPBS] = 0x40,
4002 [TCTL] = E1000_TCTL_PSP | (0xF << E1000_CT_SHIFT) |
4003 (0x40 << E1000_COLD_SHIFT) | (0x1 << 26) | (0xA << 28),
4004 [TCTL_EXT] = 0x40 | (0x42 << 10),
4005 [DTXCTL] = E1000_DTXCTL_8023LL | E1000_DTXCTL_SPOOF_INT,
4006 [VET] = ETH_P_VLAN | (ETH_P_VLAN << 16),
4007
4008 [V2PMAILBOX0 ... V2PMAILBOX0 + IGB_MAX_VF_FUNCTIONS - 1] = E1000_V2PMAILBOX_RSTI,
4009 [MBVFIMR] = 0xFF,
4010 [VFRE] = 0xFF,
4011 [VFTE] = 0xFF,
4012 [VMOLR0 ... VMOLR0 + 7] = 0x2600 | E1000_VMOLR_STRCRC,
4013 [RPLOLR] = E1000_RPLOLR_STRCRC,
4014 [RLPML] = 0x2600,
4015 [TXCTL0] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4016 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4017 E1000_DCA_TXCTRL_DESC_RRO_EN,
4018 [TXCTL1] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4019 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4020 E1000_DCA_TXCTRL_DESC_RRO_EN,
4021 [TXCTL2] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4022 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4023 E1000_DCA_TXCTRL_DESC_RRO_EN,
4024 [TXCTL3] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4025 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4026 E1000_DCA_TXCTRL_DESC_RRO_EN,
4027 [TXCTL4] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4028 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4029 E1000_DCA_TXCTRL_DESC_RRO_EN,
4030 [TXCTL5] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4031 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4032 E1000_DCA_TXCTRL_DESC_RRO_EN,
4033 [TXCTL6] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4034 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4035 E1000_DCA_TXCTRL_DESC_RRO_EN,
4036 [TXCTL7] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4037 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4038 E1000_DCA_TXCTRL_DESC_RRO_EN,
4039 [TXCTL8] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4040 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4041 E1000_DCA_TXCTRL_DESC_RRO_EN,
4042 [TXCTL9] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4043 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4044 E1000_DCA_TXCTRL_DESC_RRO_EN,
4045 [TXCTL10] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4046 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4047 E1000_DCA_TXCTRL_DESC_RRO_EN,
4048 [TXCTL11] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4049 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4050 E1000_DCA_TXCTRL_DESC_RRO_EN,
4051 [TXCTL12] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4052 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4053 E1000_DCA_TXCTRL_DESC_RRO_EN,
4054 [TXCTL13] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4055 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4056 E1000_DCA_TXCTRL_DESC_RRO_EN,
4057 [TXCTL14] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4058 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4059 E1000_DCA_TXCTRL_DESC_RRO_EN,
4060 [TXCTL15] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4061 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4062 E1000_DCA_TXCTRL_DESC_RRO_EN,
4063 };
4064
4065 static void igb_reset(IGBCore *core, bool sw)
4066 {
4067 struct igb_tx *tx;
4068 int i;
4069
4070 timer_del(core->autoneg_timer);
4071
4072 igb_intrmgr_reset(core);
4073
4074 memset(core->phy, 0, sizeof core->phy);
4075 memcpy(core->phy, igb_phy_reg_init, sizeof igb_phy_reg_init);
4076
4077 for (i = 0; i < E1000E_MAC_SIZE; i++) {
4078 if (sw &&
4079 (i == RXPBS || i == TXPBS ||
4080 (i >= EITR0 && i < EITR0 + IGB_INTR_NUM))) {
4081 continue;
4082 }
4083
4084 core->mac[i] = i < ARRAY_SIZE(igb_mac_reg_init) ?
4085 igb_mac_reg_init[i] : 0;
4086 }
4087
4088 if (qemu_get_queue(core->owner_nic)->link_down) {
4089 igb_link_down(core);
4090 }
4091
4092 e1000x_reset_mac_addr(core->owner_nic, core->mac, core->permanent_mac);
4093
4094 for (int vfn = 0; vfn < IGB_MAX_VF_FUNCTIONS; vfn++) {
4095 /* Set RSTI, so VF can identify a PF reset is in progress */
4096 core->mac[V2PMAILBOX0 + vfn] |= E1000_V2PMAILBOX_RSTI;
4097 }
4098
4099 for (i = 0; i < ARRAY_SIZE(core->tx); i++) {
4100 tx = &core->tx[i];
4101 net_tx_pkt_reset(tx->tx_pkt, NULL);
4102 memset(tx->ctx, 0, sizeof(tx->ctx));
4103 tx->first = true;
4104 tx->skip_cp = false;
4105 }
4106 }
4107
4108 void
4109 igb_core_reset(IGBCore *core)
4110 {
4111 igb_reset(core, false);
4112 }
4113
4114 void igb_core_pre_save(IGBCore *core)
4115 {
4116 int i;
4117 NetClientState *nc = qemu_get_queue(core->owner_nic);
4118
4119 /*
4120 * If link is down and auto-negotiation is supported and ongoing,
4121 * complete auto-negotiation immediately. This allows us to look
4122 * at MII_BMSR_AN_COMP to infer link status on load.
4123 */
4124 if (nc->link_down && igb_have_autoneg(core)) {
4125 core->phy[MII_BMSR] |= MII_BMSR_AN_COMP;
4126 igb_update_flowctl_status(core);
4127 }
4128
4129 for (i = 0; i < ARRAY_SIZE(core->tx); i++) {
4130 if (net_tx_pkt_has_fragments(core->tx[i].tx_pkt)) {
4131 core->tx[i].skip_cp = true;
4132 }
4133 }
4134 }
4135
4136 int
4137 igb_core_post_load(IGBCore *core)
4138 {
4139 NetClientState *nc = qemu_get_queue(core->owner_nic);
4140
4141 /*
4142 * nc.link_down can't be migrated, so infer link_down according
4143 * to link status bit in core.mac[STATUS].
4144 */
4145 nc->link_down = (core->mac[STATUS] & E1000_STATUS_LU) == 0;
4146
4147 return 0;
4148 }
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