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igb: Strip the second VLAN tag for extended VLAN
[mirror_qemu.git] / hw / net / igb_core.c
1 /*
2 * Core code for QEMU igb emulation
3 *
4 * Datasheet:
5 * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/82576eg-gbe-datasheet.pdf
6 *
7 * Copyright (c) 2020-2023 Red Hat, Inc.
8 * Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com)
9 * Developed by Daynix Computing LTD (http://www.daynix.com)
10 *
11 * Authors:
12 * Akihiko Odaki <akihiko.odaki@daynix.com>
13 * Gal Hammmer <gal.hammer@sap.com>
14 * Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
15 * Dmitry Fleytman <dmitry@daynix.com>
16 * Leonid Bloch <leonid@daynix.com>
17 * Yan Vugenfirer <yan@daynix.com>
18 *
19 * Based on work done by:
20 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
21 * Copyright (c) 2008 Qumranet
22 * Based on work done by:
23 * Copyright (c) 2007 Dan Aloni
24 * Copyright (c) 2004 Antony T Curtis
25 *
26 * This library is free software; you can redistribute it and/or
27 * modify it under the terms of the GNU Lesser General Public
28 * License as published by the Free Software Foundation; either
29 * version 2.1 of the License, or (at your option) any later version.
30 *
31 * This library is distributed in the hope that it will be useful,
32 * but WITHOUT ANY WARRANTY; without even the implied warranty of
33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
34 * Lesser General Public License for more details.
35 *
36 * You should have received a copy of the GNU Lesser General Public
37 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
38 */
39
40 #include "qemu/osdep.h"
41 #include "qemu/log.h"
42 #include "net/net.h"
43 #include "net/tap.h"
44 #include "hw/net/mii.h"
45 #include "hw/pci/msi.h"
46 #include "hw/pci/msix.h"
47 #include "sysemu/runstate.h"
48
49 #include "net_tx_pkt.h"
50 #include "net_rx_pkt.h"
51
52 #include "igb_common.h"
53 #include "e1000x_common.h"
54 #include "igb_core.h"
55
56 #include "trace.h"
57
58 #define E1000E_MAX_TX_FRAGS (64)
59
60 union e1000_rx_desc_union {
61 struct e1000_rx_desc legacy;
62 union e1000_adv_rx_desc adv;
63 };
64
65 typedef struct IGBTxPktVmdqCallbackContext {
66 IGBCore *core;
67 NetClientState *nc;
68 } IGBTxPktVmdqCallbackContext;
69
70 typedef struct L2Header {
71 struct eth_header eth;
72 struct vlan_header vlan;
73 } L2Header;
74
75 static ssize_t
76 igb_receive_internal(IGBCore *core, const struct iovec *iov, int iovcnt,
77 bool has_vnet, bool *external_tx);
78
79 static inline void
80 igb_set_interrupt_cause(IGBCore *core, uint32_t val);
81
82 static void igb_update_interrupt_state(IGBCore *core);
83 static void igb_reset(IGBCore *core, bool sw);
84
85 static inline void
86 igb_raise_legacy_irq(IGBCore *core)
87 {
88 trace_e1000e_irq_legacy_notify(true);
89 e1000x_inc_reg_if_not_full(core->mac, IAC);
90 pci_set_irq(core->owner, 1);
91 }
92
93 static inline void
94 igb_lower_legacy_irq(IGBCore *core)
95 {
96 trace_e1000e_irq_legacy_notify(false);
97 pci_set_irq(core->owner, 0);
98 }
99
100 static void igb_msix_notify(IGBCore *core, unsigned int cause)
101 {
102 PCIDevice *dev = core->owner;
103 uint16_t vfn;
104 uint32_t effective_eiac;
105 unsigned int vector;
106
107 vfn = 8 - (cause + 2) / IGBVF_MSIX_VEC_NUM;
108 if (vfn < pcie_sriov_num_vfs(core->owner)) {
109 dev = pcie_sriov_get_vf_at_index(core->owner, vfn);
110 assert(dev);
111 vector = (cause + 2) % IGBVF_MSIX_VEC_NUM;
112 } else if (cause >= IGB_MSIX_VEC_NUM) {
113 qemu_log_mask(LOG_GUEST_ERROR,
114 "igb: Tried to use vector unavailable for PF");
115 return;
116 } else {
117 vector = cause;
118 }
119
120 msix_notify(dev, vector);
121
122 trace_e1000e_irq_icr_clear_eiac(core->mac[EICR], core->mac[EIAC]);
123 effective_eiac = core->mac[EIAC] & BIT(cause);
124 core->mac[EICR] &= ~effective_eiac;
125 }
126
127 static inline void
128 igb_intrmgr_rearm_timer(IGBIntrDelayTimer *timer)
129 {
130 int64_t delay_ns = (int64_t) timer->core->mac[timer->delay_reg] *
131 timer->delay_resolution_ns;
132
133 trace_e1000e_irq_rearm_timer(timer->delay_reg << 2, delay_ns);
134
135 timer_mod(timer->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + delay_ns);
136
137 timer->running = true;
138 }
139
140 static void
141 igb_intmgr_timer_resume(IGBIntrDelayTimer *timer)
142 {
143 if (timer->running) {
144 igb_intrmgr_rearm_timer(timer);
145 }
146 }
147
148 static void
149 igb_intmgr_timer_pause(IGBIntrDelayTimer *timer)
150 {
151 if (timer->running) {
152 timer_del(timer->timer);
153 }
154 }
155
156 static void
157 igb_intrmgr_on_msix_throttling_timer(void *opaque)
158 {
159 IGBIntrDelayTimer *timer = opaque;
160 int idx = timer - &timer->core->eitr[0];
161
162 timer->running = false;
163
164 trace_e1000e_irq_msix_notify_postponed_vec(idx);
165 igb_msix_notify(timer->core, idx);
166 }
167
168 static void
169 igb_intrmgr_initialize_all_timers(IGBCore *core, bool create)
170 {
171 int i;
172
173 for (i = 0; i < IGB_INTR_NUM; i++) {
174 core->eitr[i].core = core;
175 core->eitr[i].delay_reg = EITR0 + i;
176 core->eitr[i].delay_resolution_ns = E1000_INTR_DELAY_NS_RES;
177 }
178
179 if (!create) {
180 return;
181 }
182
183 for (i = 0; i < IGB_INTR_NUM; i++) {
184 core->eitr[i].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
185 igb_intrmgr_on_msix_throttling_timer,
186 &core->eitr[i]);
187 }
188 }
189
190 static void
191 igb_intrmgr_resume(IGBCore *core)
192 {
193 int i;
194
195 for (i = 0; i < IGB_INTR_NUM; i++) {
196 igb_intmgr_timer_resume(&core->eitr[i]);
197 }
198 }
199
200 static void
201 igb_intrmgr_pause(IGBCore *core)
202 {
203 int i;
204
205 for (i = 0; i < IGB_INTR_NUM; i++) {
206 igb_intmgr_timer_pause(&core->eitr[i]);
207 }
208 }
209
210 static void
211 igb_intrmgr_reset(IGBCore *core)
212 {
213 int i;
214
215 for (i = 0; i < IGB_INTR_NUM; i++) {
216 if (core->eitr[i].running) {
217 timer_del(core->eitr[i].timer);
218 igb_intrmgr_on_msix_throttling_timer(&core->eitr[i]);
219 }
220 }
221 }
222
223 static void
224 igb_intrmgr_pci_unint(IGBCore *core)
225 {
226 int i;
227
228 for (i = 0; i < IGB_INTR_NUM; i++) {
229 timer_free(core->eitr[i].timer);
230 }
231 }
232
233 static void
234 igb_intrmgr_pci_realize(IGBCore *core)
235 {
236 igb_intrmgr_initialize_all_timers(core, true);
237 }
238
239 static inline bool
240 igb_rx_csum_enabled(IGBCore *core)
241 {
242 return (core->mac[RXCSUM] & E1000_RXCSUM_PCSD) ? false : true;
243 }
244
245 static inline bool
246 igb_rx_use_legacy_descriptor(IGBCore *core)
247 {
248 /*
249 * TODO: If SRRCTL[n],DESCTYPE = 000b, the 82576 uses the legacy Rx
250 * descriptor.
251 */
252 return false;
253 }
254
255 static inline bool
256 igb_rss_enabled(IGBCore *core)
257 {
258 return (core->mac[MRQC] & 3) == E1000_MRQC_ENABLE_RSS_MQ &&
259 !igb_rx_csum_enabled(core) &&
260 !igb_rx_use_legacy_descriptor(core);
261 }
262
263 typedef struct E1000E_RSSInfo_st {
264 bool enabled;
265 uint32_t hash;
266 uint32_t queue;
267 uint32_t type;
268 } E1000E_RSSInfo;
269
270 static uint32_t
271 igb_rss_get_hash_type(IGBCore *core, struct NetRxPkt *pkt)
272 {
273 bool hasip4, hasip6;
274 EthL4HdrProto l4hdr_proto;
275
276 assert(igb_rss_enabled(core));
277
278 net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto);
279
280 if (hasip4) {
281 trace_e1000e_rx_rss_ip4(l4hdr_proto, core->mac[MRQC],
282 E1000_MRQC_EN_TCPIPV4(core->mac[MRQC]),
283 E1000_MRQC_EN_IPV4(core->mac[MRQC]));
284
285 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP &&
286 E1000_MRQC_EN_TCPIPV4(core->mac[MRQC])) {
287 return E1000_MRQ_RSS_TYPE_IPV4TCP;
288 }
289
290 if (l4hdr_proto == ETH_L4_HDR_PROTO_UDP &&
291 (core->mac[MRQC] & E1000_MRQC_RSS_FIELD_IPV4_UDP)) {
292 return E1000_MRQ_RSS_TYPE_IPV4UDP;
293 }
294
295 if (E1000_MRQC_EN_IPV4(core->mac[MRQC])) {
296 return E1000_MRQ_RSS_TYPE_IPV4;
297 }
298 } else if (hasip6) {
299 eth_ip6_hdr_info *ip6info = net_rx_pkt_get_ip6_info(pkt);
300
301 bool ex_dis = core->mac[RFCTL] & E1000_RFCTL_IPV6_EX_DIS;
302 bool new_ex_dis = core->mac[RFCTL] & E1000_RFCTL_NEW_IPV6_EXT_DIS;
303
304 /*
305 * Following two traces must not be combined because resulting
306 * event will have 11 arguments totally and some trace backends
307 * (at least "ust") have limitation of maximum 10 arguments per
308 * event. Events with more arguments fail to compile for
309 * backends like these.
310 */
311 trace_e1000e_rx_rss_ip6_rfctl(core->mac[RFCTL]);
312 trace_e1000e_rx_rss_ip6(ex_dis, new_ex_dis, l4hdr_proto,
313 ip6info->has_ext_hdrs,
314 ip6info->rss_ex_dst_valid,
315 ip6info->rss_ex_src_valid,
316 core->mac[MRQC],
317 E1000_MRQC_EN_TCPIPV6EX(core->mac[MRQC]),
318 E1000_MRQC_EN_IPV6EX(core->mac[MRQC]),
319 E1000_MRQC_EN_IPV6(core->mac[MRQC]));
320
321 if ((!ex_dis || !ip6info->has_ext_hdrs) &&
322 (!new_ex_dis || !(ip6info->rss_ex_dst_valid ||
323 ip6info->rss_ex_src_valid))) {
324
325 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP &&
326 E1000_MRQC_EN_TCPIPV6EX(core->mac[MRQC])) {
327 return E1000_MRQ_RSS_TYPE_IPV6TCPEX;
328 }
329
330 if (l4hdr_proto == ETH_L4_HDR_PROTO_UDP &&
331 (core->mac[MRQC] & E1000_MRQC_RSS_FIELD_IPV6_UDP)) {
332 return E1000_MRQ_RSS_TYPE_IPV6UDP;
333 }
334
335 if (E1000_MRQC_EN_IPV6EX(core->mac[MRQC])) {
336 return E1000_MRQ_RSS_TYPE_IPV6EX;
337 }
338
339 }
340
341 if (E1000_MRQC_EN_IPV6(core->mac[MRQC])) {
342 return E1000_MRQ_RSS_TYPE_IPV6;
343 }
344
345 }
346
347 return E1000_MRQ_RSS_TYPE_NONE;
348 }
349
350 static uint32_t
351 igb_rss_calc_hash(IGBCore *core, struct NetRxPkt *pkt, E1000E_RSSInfo *info)
352 {
353 NetRxPktRssType type;
354
355 assert(igb_rss_enabled(core));
356
357 switch (info->type) {
358 case E1000_MRQ_RSS_TYPE_IPV4:
359 type = NetPktRssIpV4;
360 break;
361 case E1000_MRQ_RSS_TYPE_IPV4TCP:
362 type = NetPktRssIpV4Tcp;
363 break;
364 case E1000_MRQ_RSS_TYPE_IPV6TCPEX:
365 type = NetPktRssIpV6TcpEx;
366 break;
367 case E1000_MRQ_RSS_TYPE_IPV6:
368 type = NetPktRssIpV6;
369 break;
370 case E1000_MRQ_RSS_TYPE_IPV6EX:
371 type = NetPktRssIpV6Ex;
372 break;
373 case E1000_MRQ_RSS_TYPE_IPV4UDP:
374 type = NetPktRssIpV4Udp;
375 break;
376 case E1000_MRQ_RSS_TYPE_IPV6UDP:
377 type = NetPktRssIpV6Udp;
378 break;
379 default:
380 assert(false);
381 return 0;
382 }
383
384 return net_rx_pkt_calc_rss_hash(pkt, type, (uint8_t *) &core->mac[RSSRK]);
385 }
386
387 static void
388 igb_rss_parse_packet(IGBCore *core, struct NetRxPkt *pkt, bool tx,
389 E1000E_RSSInfo *info)
390 {
391 trace_e1000e_rx_rss_started();
392
393 if (tx || !igb_rss_enabled(core)) {
394 info->enabled = false;
395 info->hash = 0;
396 info->queue = 0;
397 info->type = 0;
398 trace_e1000e_rx_rss_disabled();
399 return;
400 }
401
402 info->enabled = true;
403
404 info->type = igb_rss_get_hash_type(core, pkt);
405
406 trace_e1000e_rx_rss_type(info->type);
407
408 if (info->type == E1000_MRQ_RSS_TYPE_NONE) {
409 info->hash = 0;
410 info->queue = 0;
411 return;
412 }
413
414 info->hash = igb_rss_calc_hash(core, pkt, info);
415 info->queue = E1000_RSS_QUEUE(&core->mac[RETA], info->hash);
416 }
417
418 static void
419 igb_tx_insert_vlan(IGBCore *core, uint16_t qn, struct igb_tx *tx,
420 uint16_t vlan, bool insert_vlan)
421 {
422 if (core->mac[MRQC] & 1) {
423 uint16_t pool = qn % IGB_NUM_VM_POOLS;
424
425 if (core->mac[VMVIR0 + pool] & E1000_VMVIR_VLANA_DEFAULT) {
426 /* always insert default VLAN */
427 insert_vlan = true;
428 vlan = core->mac[VMVIR0 + pool] & 0xffff;
429 } else if (core->mac[VMVIR0 + pool] & E1000_VMVIR_VLANA_NEVER) {
430 insert_vlan = false;
431 }
432 }
433
434 if (insert_vlan) {
435 net_tx_pkt_setup_vlan_header_ex(tx->tx_pkt, vlan,
436 core->mac[VET] & 0xffff);
437 }
438 }
439
440 static bool
441 igb_setup_tx_offloads(IGBCore *core, struct igb_tx *tx)
442 {
443 uint32_t idx = (tx->first_olinfo_status >> 4) & 1;
444
445 if (tx->first_cmd_type_len & E1000_ADVTXD_DCMD_TSE) {
446 uint32_t mss = tx->ctx[idx].mss_l4len_idx >> E1000_ADVTXD_MSS_SHIFT;
447 if (!net_tx_pkt_build_vheader(tx->tx_pkt, true, true, mss)) {
448 return false;
449 }
450
451 net_tx_pkt_update_ip_checksums(tx->tx_pkt);
452 e1000x_inc_reg_if_not_full(core->mac, TSCTC);
453 return true;
454 }
455
456 if ((tx->first_olinfo_status & E1000_ADVTXD_POTS_TXSM) &&
457 !((tx->ctx[idx].type_tucmd_mlhl & E1000_ADVTXD_TUCMD_L4T_SCTP) ?
458 net_tx_pkt_update_sctp_checksum(tx->tx_pkt) :
459 net_tx_pkt_build_vheader(tx->tx_pkt, false, true, 0))) {
460 return false;
461 }
462
463 if (tx->first_olinfo_status & E1000_ADVTXD_POTS_IXSM) {
464 net_tx_pkt_update_ip_hdr_checksum(tx->tx_pkt);
465 }
466
467 return true;
468 }
469
470 static void igb_tx_pkt_mac_callback(void *core,
471 const struct iovec *iov,
472 int iovcnt,
473 const struct iovec *virt_iov,
474 int virt_iovcnt)
475 {
476 igb_receive_internal(core, virt_iov, virt_iovcnt, true, NULL);
477 }
478
479 static void igb_tx_pkt_vmdq_callback(void *opaque,
480 const struct iovec *iov,
481 int iovcnt,
482 const struct iovec *virt_iov,
483 int virt_iovcnt)
484 {
485 IGBTxPktVmdqCallbackContext *context = opaque;
486 bool external_tx;
487
488 igb_receive_internal(context->core, virt_iov, virt_iovcnt, true,
489 &external_tx);
490
491 if (external_tx) {
492 if (context->core->has_vnet) {
493 qemu_sendv_packet(context->nc, virt_iov, virt_iovcnt);
494 } else {
495 qemu_sendv_packet(context->nc, iov, iovcnt);
496 }
497 }
498 }
499
500 /* TX Packets Switching (7.10.3.6) */
501 static bool igb_tx_pkt_switch(IGBCore *core, struct igb_tx *tx,
502 NetClientState *nc)
503 {
504 IGBTxPktVmdqCallbackContext context;
505
506 /* TX switching is only used to serve VM to VM traffic. */
507 if (!(core->mac[MRQC] & 1)) {
508 goto send_out;
509 }
510
511 /* TX switching requires DTXSWC.Loopback_en bit enabled. */
512 if (!(core->mac[DTXSWC] & E1000_DTXSWC_VMDQ_LOOPBACK_EN)) {
513 goto send_out;
514 }
515
516 context.core = core;
517 context.nc = nc;
518
519 return net_tx_pkt_send_custom(tx->tx_pkt, false,
520 igb_tx_pkt_vmdq_callback, &context);
521
522 send_out:
523 return net_tx_pkt_send(tx->tx_pkt, nc);
524 }
525
526 static bool
527 igb_tx_pkt_send(IGBCore *core, struct igb_tx *tx, int queue_index)
528 {
529 int target_queue = MIN(core->max_queue_num, queue_index);
530 NetClientState *queue = qemu_get_subqueue(core->owner_nic, target_queue);
531
532 if (!igb_setup_tx_offloads(core, tx)) {
533 return false;
534 }
535
536 net_tx_pkt_dump(tx->tx_pkt);
537
538 if ((core->phy[MII_BMCR] & MII_BMCR_LOOPBACK) ||
539 ((core->mac[RCTL] & E1000_RCTL_LBM_MAC) == E1000_RCTL_LBM_MAC)) {
540 return net_tx_pkt_send_custom(tx->tx_pkt, false,
541 igb_tx_pkt_mac_callback, core);
542 } else {
543 return igb_tx_pkt_switch(core, tx, queue);
544 }
545 }
546
547 static void
548 igb_on_tx_done_update_stats(IGBCore *core, struct NetTxPkt *tx_pkt, int qn)
549 {
550 static const int PTCregs[6] = { PTC64, PTC127, PTC255, PTC511,
551 PTC1023, PTC1522 };
552
553 size_t tot_len = net_tx_pkt_get_total_len(tx_pkt) + 4;
554
555 e1000x_increase_size_stats(core->mac, PTCregs, tot_len);
556 e1000x_inc_reg_if_not_full(core->mac, TPT);
557 e1000x_grow_8reg_if_not_full(core->mac, TOTL, tot_len);
558
559 switch (net_tx_pkt_get_packet_type(tx_pkt)) {
560 case ETH_PKT_BCAST:
561 e1000x_inc_reg_if_not_full(core->mac, BPTC);
562 break;
563 case ETH_PKT_MCAST:
564 e1000x_inc_reg_if_not_full(core->mac, MPTC);
565 break;
566 case ETH_PKT_UCAST:
567 break;
568 default:
569 g_assert_not_reached();
570 }
571
572 e1000x_inc_reg_if_not_full(core->mac, GPTC);
573 e1000x_grow_8reg_if_not_full(core->mac, GOTCL, tot_len);
574
575 if (core->mac[MRQC] & 1) {
576 uint16_t pool = qn % IGB_NUM_VM_POOLS;
577
578 core->mac[PVFGOTC0 + (pool * 64)] += tot_len;
579 core->mac[PVFGPTC0 + (pool * 64)]++;
580 }
581 }
582
583 static void
584 igb_process_tx_desc(IGBCore *core,
585 PCIDevice *dev,
586 struct igb_tx *tx,
587 union e1000_adv_tx_desc *tx_desc,
588 int queue_index)
589 {
590 struct e1000_adv_tx_context_desc *tx_ctx_desc;
591 uint32_t cmd_type_len;
592 uint32_t idx;
593 uint64_t buffer_addr;
594 uint16_t length;
595
596 cmd_type_len = le32_to_cpu(tx_desc->read.cmd_type_len);
597
598 if (cmd_type_len & E1000_ADVTXD_DCMD_DEXT) {
599 if ((cmd_type_len & E1000_ADVTXD_DTYP_DATA) ==
600 E1000_ADVTXD_DTYP_DATA) {
601 /* advanced transmit data descriptor */
602 if (tx->first) {
603 tx->first_cmd_type_len = cmd_type_len;
604 tx->first_olinfo_status = le32_to_cpu(tx_desc->read.olinfo_status);
605 tx->first = false;
606 }
607 } else if ((cmd_type_len & E1000_ADVTXD_DTYP_CTXT) ==
608 E1000_ADVTXD_DTYP_CTXT) {
609 /* advanced transmit context descriptor */
610 tx_ctx_desc = (struct e1000_adv_tx_context_desc *)tx_desc;
611 idx = (le32_to_cpu(tx_ctx_desc->mss_l4len_idx) >> 4) & 1;
612 tx->ctx[idx].vlan_macip_lens = le32_to_cpu(tx_ctx_desc->vlan_macip_lens);
613 tx->ctx[idx].seqnum_seed = le32_to_cpu(tx_ctx_desc->seqnum_seed);
614 tx->ctx[idx].type_tucmd_mlhl = le32_to_cpu(tx_ctx_desc->type_tucmd_mlhl);
615 tx->ctx[idx].mss_l4len_idx = le32_to_cpu(tx_ctx_desc->mss_l4len_idx);
616 return;
617 } else {
618 /* unknown descriptor type */
619 return;
620 }
621 } else {
622 /* legacy descriptor */
623
624 /* TODO: Implement a support for legacy descriptors (7.2.2.1). */
625 }
626
627 buffer_addr = le64_to_cpu(tx_desc->read.buffer_addr);
628 length = cmd_type_len & 0xFFFF;
629
630 if (!tx->skip_cp) {
631 if (!net_tx_pkt_add_raw_fragment_pci(tx->tx_pkt, dev,
632 buffer_addr, length)) {
633 tx->skip_cp = true;
634 }
635 }
636
637 if (cmd_type_len & E1000_TXD_CMD_EOP) {
638 if (!tx->skip_cp && net_tx_pkt_parse(tx->tx_pkt)) {
639 idx = (tx->first_olinfo_status >> 4) & 1;
640 igb_tx_insert_vlan(core, queue_index, tx,
641 tx->ctx[idx].vlan_macip_lens >> IGB_TX_FLAGS_VLAN_SHIFT,
642 !!(tx->first_cmd_type_len & E1000_TXD_CMD_VLE));
643
644 if (igb_tx_pkt_send(core, tx, queue_index)) {
645 igb_on_tx_done_update_stats(core, tx->tx_pkt, queue_index);
646 }
647 }
648
649 tx->first = true;
650 tx->skip_cp = false;
651 net_tx_pkt_reset(tx->tx_pkt, net_tx_pkt_unmap_frag_pci, dev);
652 }
653 }
654
655 static uint32_t igb_tx_wb_eic(IGBCore *core, int queue_idx)
656 {
657 uint32_t n, ent = 0;
658
659 n = igb_ivar_entry_tx(queue_idx);
660 ent = (core->mac[IVAR0 + n / 4] >> (8 * (n % 4))) & 0xff;
661
662 return (ent & E1000_IVAR_VALID) ? BIT(ent & 0x1f) : 0;
663 }
664
665 static uint32_t igb_rx_wb_eic(IGBCore *core, int queue_idx)
666 {
667 uint32_t n, ent = 0;
668
669 n = igb_ivar_entry_rx(queue_idx);
670 ent = (core->mac[IVAR0 + n / 4] >> (8 * (n % 4))) & 0xff;
671
672 return (ent & E1000_IVAR_VALID) ? BIT(ent & 0x1f) : 0;
673 }
674
675 typedef struct E1000E_RingInfo_st {
676 int dbah;
677 int dbal;
678 int dlen;
679 int dh;
680 int dt;
681 int idx;
682 } E1000E_RingInfo;
683
684 static inline bool
685 igb_ring_empty(IGBCore *core, const E1000E_RingInfo *r)
686 {
687 return core->mac[r->dh] == core->mac[r->dt] ||
688 core->mac[r->dt] >= core->mac[r->dlen] / E1000_RING_DESC_LEN;
689 }
690
691 static inline uint64_t
692 igb_ring_base(IGBCore *core, const E1000E_RingInfo *r)
693 {
694 uint64_t bah = core->mac[r->dbah];
695 uint64_t bal = core->mac[r->dbal];
696
697 return (bah << 32) + bal;
698 }
699
700 static inline uint64_t
701 igb_ring_head_descr(IGBCore *core, const E1000E_RingInfo *r)
702 {
703 return igb_ring_base(core, r) + E1000_RING_DESC_LEN * core->mac[r->dh];
704 }
705
706 static inline void
707 igb_ring_advance(IGBCore *core, const E1000E_RingInfo *r, uint32_t count)
708 {
709 core->mac[r->dh] += count;
710
711 if (core->mac[r->dh] * E1000_RING_DESC_LEN >= core->mac[r->dlen]) {
712 core->mac[r->dh] = 0;
713 }
714 }
715
716 static inline uint32_t
717 igb_ring_free_descr_num(IGBCore *core, const E1000E_RingInfo *r)
718 {
719 trace_e1000e_ring_free_space(r->idx, core->mac[r->dlen],
720 core->mac[r->dh], core->mac[r->dt]);
721
722 if (core->mac[r->dh] <= core->mac[r->dt]) {
723 return core->mac[r->dt] - core->mac[r->dh];
724 }
725
726 if (core->mac[r->dh] > core->mac[r->dt]) {
727 return core->mac[r->dlen] / E1000_RING_DESC_LEN +
728 core->mac[r->dt] - core->mac[r->dh];
729 }
730
731 g_assert_not_reached();
732 return 0;
733 }
734
735 static inline bool
736 igb_ring_enabled(IGBCore *core, const E1000E_RingInfo *r)
737 {
738 return core->mac[r->dlen] > 0;
739 }
740
741 typedef struct IGB_TxRing_st {
742 const E1000E_RingInfo *i;
743 struct igb_tx *tx;
744 } IGB_TxRing;
745
746 static inline int
747 igb_mq_queue_idx(int base_reg_idx, int reg_idx)
748 {
749 return (reg_idx - base_reg_idx) / 16;
750 }
751
752 static inline void
753 igb_tx_ring_init(IGBCore *core, IGB_TxRing *txr, int idx)
754 {
755 static const E1000E_RingInfo i[IGB_NUM_QUEUES] = {
756 { TDBAH0, TDBAL0, TDLEN0, TDH0, TDT0, 0 },
757 { TDBAH1, TDBAL1, TDLEN1, TDH1, TDT1, 1 },
758 { TDBAH2, TDBAL2, TDLEN2, TDH2, TDT2, 2 },
759 { TDBAH3, TDBAL3, TDLEN3, TDH3, TDT3, 3 },
760 { TDBAH4, TDBAL4, TDLEN4, TDH4, TDT4, 4 },
761 { TDBAH5, TDBAL5, TDLEN5, TDH5, TDT5, 5 },
762 { TDBAH6, TDBAL6, TDLEN6, TDH6, TDT6, 6 },
763 { TDBAH7, TDBAL7, TDLEN7, TDH7, TDT7, 7 },
764 { TDBAH8, TDBAL8, TDLEN8, TDH8, TDT8, 8 },
765 { TDBAH9, TDBAL9, TDLEN9, TDH9, TDT9, 9 },
766 { TDBAH10, TDBAL10, TDLEN10, TDH10, TDT10, 10 },
767 { TDBAH11, TDBAL11, TDLEN11, TDH11, TDT11, 11 },
768 { TDBAH12, TDBAL12, TDLEN12, TDH12, TDT12, 12 },
769 { TDBAH13, TDBAL13, TDLEN13, TDH13, TDT13, 13 },
770 { TDBAH14, TDBAL14, TDLEN14, TDH14, TDT14, 14 },
771 { TDBAH15, TDBAL15, TDLEN15, TDH15, TDT15, 15 }
772 };
773
774 assert(idx < ARRAY_SIZE(i));
775
776 txr->i = &i[idx];
777 txr->tx = &core->tx[idx];
778 }
779
780 typedef struct E1000E_RxRing_st {
781 const E1000E_RingInfo *i;
782 } E1000E_RxRing;
783
784 static inline void
785 igb_rx_ring_init(IGBCore *core, E1000E_RxRing *rxr, int idx)
786 {
787 static const E1000E_RingInfo i[IGB_NUM_QUEUES] = {
788 { RDBAH0, RDBAL0, RDLEN0, RDH0, RDT0, 0 },
789 { RDBAH1, RDBAL1, RDLEN1, RDH1, RDT1, 1 },
790 { RDBAH2, RDBAL2, RDLEN2, RDH2, RDT2, 2 },
791 { RDBAH3, RDBAL3, RDLEN3, RDH3, RDT3, 3 },
792 { RDBAH4, RDBAL4, RDLEN4, RDH4, RDT4, 4 },
793 { RDBAH5, RDBAL5, RDLEN5, RDH5, RDT5, 5 },
794 { RDBAH6, RDBAL6, RDLEN6, RDH6, RDT6, 6 },
795 { RDBAH7, RDBAL7, RDLEN7, RDH7, RDT7, 7 },
796 { RDBAH8, RDBAL8, RDLEN8, RDH8, RDT8, 8 },
797 { RDBAH9, RDBAL9, RDLEN9, RDH9, RDT9, 9 },
798 { RDBAH10, RDBAL10, RDLEN10, RDH10, RDT10, 10 },
799 { RDBAH11, RDBAL11, RDLEN11, RDH11, RDT11, 11 },
800 { RDBAH12, RDBAL12, RDLEN12, RDH12, RDT12, 12 },
801 { RDBAH13, RDBAL13, RDLEN13, RDH13, RDT13, 13 },
802 { RDBAH14, RDBAL14, RDLEN14, RDH14, RDT14, 14 },
803 { RDBAH15, RDBAL15, RDLEN15, RDH15, RDT15, 15 }
804 };
805
806 assert(idx < ARRAY_SIZE(i));
807
808 rxr->i = &i[idx];
809 }
810
811 static uint32_t
812 igb_txdesc_writeback(IGBCore *core, dma_addr_t base,
813 union e1000_adv_tx_desc *tx_desc,
814 const E1000E_RingInfo *txi)
815 {
816 PCIDevice *d;
817 uint32_t cmd_type_len = le32_to_cpu(tx_desc->read.cmd_type_len);
818 uint64_t tdwba;
819
820 tdwba = core->mac[E1000_TDWBAL(txi->idx) >> 2];
821 tdwba |= (uint64_t)core->mac[E1000_TDWBAH(txi->idx) >> 2] << 32;
822
823 if (!(cmd_type_len & E1000_TXD_CMD_RS)) {
824 return 0;
825 }
826
827 d = pcie_sriov_get_vf_at_index(core->owner, txi->idx % 8);
828 if (!d) {
829 d = core->owner;
830 }
831
832 if (tdwba & 1) {
833 uint32_t buffer = cpu_to_le32(core->mac[txi->dh]);
834 pci_dma_write(d, tdwba & ~3, &buffer, sizeof(buffer));
835 } else {
836 uint32_t status = le32_to_cpu(tx_desc->wb.status) | E1000_TXD_STAT_DD;
837
838 tx_desc->wb.status = cpu_to_le32(status);
839 pci_dma_write(d, base + offsetof(union e1000_adv_tx_desc, wb),
840 &tx_desc->wb, sizeof(tx_desc->wb));
841 }
842
843 return igb_tx_wb_eic(core, txi->idx);
844 }
845
846 static inline bool
847 igb_tx_enabled(IGBCore *core, const E1000E_RingInfo *txi)
848 {
849 bool vmdq = core->mac[MRQC] & 1;
850 uint16_t qn = txi->idx;
851 uint16_t pool = qn % IGB_NUM_VM_POOLS;
852
853 return (core->mac[TCTL] & E1000_TCTL_EN) &&
854 (!vmdq || core->mac[VFTE] & BIT(pool)) &&
855 (core->mac[TXDCTL0 + (qn * 16)] & E1000_TXDCTL_QUEUE_ENABLE);
856 }
857
858 static void
859 igb_start_xmit(IGBCore *core, const IGB_TxRing *txr)
860 {
861 PCIDevice *d;
862 dma_addr_t base;
863 union e1000_adv_tx_desc desc;
864 const E1000E_RingInfo *txi = txr->i;
865 uint32_t eic = 0;
866
867 if (!igb_tx_enabled(core, txi)) {
868 trace_e1000e_tx_disabled();
869 return;
870 }
871
872 d = pcie_sriov_get_vf_at_index(core->owner, txi->idx % 8);
873 if (!d) {
874 d = core->owner;
875 }
876
877 while (!igb_ring_empty(core, txi)) {
878 base = igb_ring_head_descr(core, txi);
879
880 pci_dma_read(d, base, &desc, sizeof(desc));
881
882 trace_e1000e_tx_descr((void *)(intptr_t)desc.read.buffer_addr,
883 desc.read.cmd_type_len, desc.wb.status);
884
885 igb_process_tx_desc(core, d, txr->tx, &desc, txi->idx);
886 igb_ring_advance(core, txi, 1);
887 eic |= igb_txdesc_writeback(core, base, &desc, txi);
888 }
889
890 if (eic) {
891 core->mac[EICR] |= eic;
892 igb_set_interrupt_cause(core, E1000_ICR_TXDW);
893 }
894
895 net_tx_pkt_reset(txr->tx->tx_pkt, net_tx_pkt_unmap_frag_pci, d);
896 }
897
898 static uint32_t
899 igb_rxbufsize(IGBCore *core, const E1000E_RingInfo *r)
900 {
901 uint32_t srrctl = core->mac[E1000_SRRCTL(r->idx) >> 2];
902 uint32_t bsizepkt = srrctl & E1000_SRRCTL_BSIZEPKT_MASK;
903 if (bsizepkt) {
904 return bsizepkt << E1000_SRRCTL_BSIZEPKT_SHIFT;
905 }
906
907 return e1000x_rxbufsize(core->mac[RCTL]);
908 }
909
910 static bool
911 igb_has_rxbufs(IGBCore *core, const E1000E_RingInfo *r, size_t total_size)
912 {
913 uint32_t bufs = igb_ring_free_descr_num(core, r);
914 uint32_t bufsize = igb_rxbufsize(core, r);
915
916 trace_e1000e_rx_has_buffers(r->idx, bufs, total_size, bufsize);
917
918 return total_size <= bufs / (core->rx_desc_len / E1000_MIN_RX_DESC_LEN) *
919 bufsize;
920 }
921
922 void
923 igb_start_recv(IGBCore *core)
924 {
925 int i;
926
927 trace_e1000e_rx_start_recv();
928
929 for (i = 0; i <= core->max_queue_num; i++) {
930 qemu_flush_queued_packets(qemu_get_subqueue(core->owner_nic, i));
931 }
932 }
933
934 bool
935 igb_can_receive(IGBCore *core)
936 {
937 int i;
938
939 if (!e1000x_rx_ready(core->owner, core->mac)) {
940 return false;
941 }
942
943 for (i = 0; i < IGB_NUM_QUEUES; i++) {
944 E1000E_RxRing rxr;
945 if (!(core->mac[RXDCTL0 + (i * 16)] & E1000_RXDCTL_QUEUE_ENABLE)) {
946 continue;
947 }
948
949 igb_rx_ring_init(core, &rxr, i);
950 if (igb_ring_enabled(core, rxr.i) && igb_has_rxbufs(core, rxr.i, 1)) {
951 trace_e1000e_rx_can_recv();
952 return true;
953 }
954 }
955
956 trace_e1000e_rx_can_recv_rings_full();
957 return false;
958 }
959
960 ssize_t
961 igb_receive(IGBCore *core, const uint8_t *buf, size_t size)
962 {
963 const struct iovec iov = {
964 .iov_base = (uint8_t *)buf,
965 .iov_len = size
966 };
967
968 return igb_receive_iov(core, &iov, 1);
969 }
970
971 static inline bool
972 igb_rx_l3_cso_enabled(IGBCore *core)
973 {
974 return !!(core->mac[RXCSUM] & E1000_RXCSUM_IPOFLD);
975 }
976
977 static inline bool
978 igb_rx_l4_cso_enabled(IGBCore *core)
979 {
980 return !!(core->mac[RXCSUM] & E1000_RXCSUM_TUOFLD);
981 }
982
983 static bool
984 igb_rx_is_oversized(IGBCore *core, uint16_t qn, size_t size)
985 {
986 uint16_t pool = qn % IGB_NUM_VM_POOLS;
987 bool lpe = !!(core->mac[VMOLR0 + pool] & E1000_VMOLR_LPE);
988 int max_ethernet_lpe_size =
989 core->mac[VMOLR0 + pool] & E1000_VMOLR_RLPML_MASK;
990 int max_ethernet_vlan_size = 1522;
991
992 return size > (lpe ? max_ethernet_lpe_size : max_ethernet_vlan_size);
993 }
994
995 static uint16_t igb_receive_assign(IGBCore *core, const L2Header *l2_header,
996 size_t size, E1000E_RSSInfo *rss_info,
997 bool *external_tx)
998 {
999 static const int ta_shift[] = { 4, 3, 2, 0 };
1000 const struct eth_header *ehdr = &l2_header->eth;
1001 uint32_t f, ra[2], *macp, rctl = core->mac[RCTL];
1002 uint16_t queues = 0;
1003 uint16_t oversized = 0;
1004 uint16_t vid = be16_to_cpu(l2_header->vlan.h_tci) & VLAN_VID_MASK;
1005 int i;
1006
1007 memset(rss_info, 0, sizeof(E1000E_RSSInfo));
1008
1009 if (external_tx) {
1010 *external_tx = true;
1011 }
1012
1013 if (e1000x_is_vlan_packet(ehdr, core->mac[VET] & 0xffff) &&
1014 !e1000x_rx_vlan_filter(core->mac, PKT_GET_VLAN_HDR(ehdr))) {
1015 return queues;
1016 }
1017
1018 if (core->mac[MRQC] & 1) {
1019 if (is_broadcast_ether_addr(ehdr->h_dest)) {
1020 for (i = 0; i < IGB_NUM_VM_POOLS; i++) {
1021 if (core->mac[VMOLR0 + i] & E1000_VMOLR_BAM) {
1022 queues |= BIT(i);
1023 }
1024 }
1025 } else {
1026 for (macp = core->mac + RA; macp < core->mac + RA + 32; macp += 2) {
1027 if (!(macp[1] & E1000_RAH_AV)) {
1028 continue;
1029 }
1030 ra[0] = cpu_to_le32(macp[0]);
1031 ra[1] = cpu_to_le32(macp[1]);
1032 if (!memcmp(ehdr->h_dest, (uint8_t *)ra, ETH_ALEN)) {
1033 queues |= (macp[1] & E1000_RAH_POOL_MASK) / E1000_RAH_POOL_1;
1034 }
1035 }
1036
1037 for (macp = core->mac + RA2; macp < core->mac + RA2 + 16; macp += 2) {
1038 if (!(macp[1] & E1000_RAH_AV)) {
1039 continue;
1040 }
1041 ra[0] = cpu_to_le32(macp[0]);
1042 ra[1] = cpu_to_le32(macp[1]);
1043 if (!memcmp(ehdr->h_dest, (uint8_t *)ra, ETH_ALEN)) {
1044 queues |= (macp[1] & E1000_RAH_POOL_MASK) / E1000_RAH_POOL_1;
1045 }
1046 }
1047
1048 if (!queues) {
1049 macp = core->mac + (is_multicast_ether_addr(ehdr->h_dest) ? MTA : UTA);
1050
1051 f = ta_shift[(rctl >> E1000_RCTL_MO_SHIFT) & 3];
1052 f = (((ehdr->h_dest[5] << 8) | ehdr->h_dest[4]) >> f) & 0xfff;
1053 if (macp[f >> 5] & (1 << (f & 0x1f))) {
1054 for (i = 0; i < IGB_NUM_VM_POOLS; i++) {
1055 if (core->mac[VMOLR0 + i] & E1000_VMOLR_ROMPE) {
1056 queues |= BIT(i);
1057 }
1058 }
1059 }
1060 } else if (is_unicast_ether_addr(ehdr->h_dest) && external_tx) {
1061 *external_tx = false;
1062 }
1063 }
1064
1065 if (e1000x_vlan_rx_filter_enabled(core->mac)) {
1066 uint16_t mask = 0;
1067
1068 if (e1000x_is_vlan_packet(ehdr, core->mac[VET] & 0xffff)) {
1069 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
1070 if ((core->mac[VLVF0 + i] & E1000_VLVF_VLANID_MASK) == vid &&
1071 (core->mac[VLVF0 + i] & E1000_VLVF_VLANID_ENABLE)) {
1072 uint32_t poolsel = core->mac[VLVF0 + i] & E1000_VLVF_POOLSEL_MASK;
1073 mask |= poolsel >> E1000_VLVF_POOLSEL_SHIFT;
1074 }
1075 }
1076 } else {
1077 for (i = 0; i < IGB_NUM_VM_POOLS; i++) {
1078 if (core->mac[VMOLR0 + i] & E1000_VMOLR_AUPE) {
1079 mask |= BIT(i);
1080 }
1081 }
1082 }
1083
1084 queues &= mask;
1085 }
1086
1087 if (is_unicast_ether_addr(ehdr->h_dest) && !queues && !external_tx &&
1088 !(core->mac[VT_CTL] & E1000_VT_CTL_DISABLE_DEF_POOL)) {
1089 uint32_t def_pl = core->mac[VT_CTL] & E1000_VT_CTL_DEFAULT_POOL_MASK;
1090 queues = BIT(def_pl >> E1000_VT_CTL_DEFAULT_POOL_SHIFT);
1091 }
1092
1093 queues &= core->mac[VFRE];
1094 if (queues) {
1095 for (i = 0; i < IGB_NUM_VM_POOLS; i++) {
1096 if ((queues & BIT(i)) && igb_rx_is_oversized(core, i, size)) {
1097 oversized |= BIT(i);
1098 }
1099 }
1100 /* 8.19.37 increment ROC if packet is oversized for all queues */
1101 if (oversized == queues) {
1102 trace_e1000x_rx_oversized(size);
1103 e1000x_inc_reg_if_not_full(core->mac, ROC);
1104 }
1105 queues &= ~oversized;
1106 }
1107
1108 if (queues) {
1109 igb_rss_parse_packet(core, core->rx_pkt,
1110 external_tx != NULL, rss_info);
1111 /* Sec 8.26.1: PQn = VFn + VQn*8 */
1112 if (rss_info->queue & 1) {
1113 for (i = 0; i < IGB_NUM_VM_POOLS; i++) {
1114 if ((queues & BIT(i)) &&
1115 (core->mac[VMOLR0 + i] & E1000_VMOLR_RSSE)) {
1116 queues |= BIT(i + IGB_NUM_VM_POOLS);
1117 queues &= ~BIT(i);
1118 }
1119 }
1120 }
1121 }
1122 } else {
1123 bool accepted = e1000x_rx_group_filter(core->mac, ehdr);
1124 if (!accepted) {
1125 for (macp = core->mac + RA2; macp < core->mac + RA2 + 16; macp += 2) {
1126 if (!(macp[1] & E1000_RAH_AV)) {
1127 continue;
1128 }
1129 ra[0] = cpu_to_le32(macp[0]);
1130 ra[1] = cpu_to_le32(macp[1]);
1131 if (!memcmp(ehdr->h_dest, (uint8_t *)ra, ETH_ALEN)) {
1132 trace_e1000x_rx_flt_ucast_match((int)(macp - core->mac - RA2) / 2,
1133 MAC_ARG(ehdr->h_dest));
1134
1135 accepted = true;
1136 break;
1137 }
1138 }
1139 }
1140
1141 if (accepted) {
1142 igb_rss_parse_packet(core, core->rx_pkt, false, rss_info);
1143 queues = BIT(rss_info->queue);
1144 }
1145 }
1146
1147 return queues;
1148 }
1149
1150 static inline void
1151 igb_read_lgcy_rx_descr(IGBCore *core, struct e1000_rx_desc *desc,
1152 hwaddr *buff_addr)
1153 {
1154 *buff_addr = le64_to_cpu(desc->buffer_addr);
1155 }
1156
1157 static inline void
1158 igb_read_adv_rx_descr(IGBCore *core, union e1000_adv_rx_desc *desc,
1159 hwaddr *buff_addr)
1160 {
1161 *buff_addr = le64_to_cpu(desc->read.pkt_addr);
1162 }
1163
1164 static inline void
1165 igb_read_rx_descr(IGBCore *core, union e1000_rx_desc_union *desc,
1166 hwaddr *buff_addr)
1167 {
1168 if (igb_rx_use_legacy_descriptor(core)) {
1169 igb_read_lgcy_rx_descr(core, &desc->legacy, buff_addr);
1170 } else {
1171 igb_read_adv_rx_descr(core, &desc->adv, buff_addr);
1172 }
1173 }
1174
1175 static void
1176 igb_verify_csum_in_sw(IGBCore *core,
1177 struct NetRxPkt *pkt,
1178 uint32_t *status_flags,
1179 EthL4HdrProto l4hdr_proto)
1180 {
1181 bool csum_valid;
1182 uint32_t csum_error;
1183
1184 if (igb_rx_l3_cso_enabled(core)) {
1185 if (!net_rx_pkt_validate_l3_csum(pkt, &csum_valid)) {
1186 trace_e1000e_rx_metadata_l3_csum_validation_failed();
1187 } else {
1188 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_IPE;
1189 *status_flags |= E1000_RXD_STAT_IPCS | csum_error;
1190 }
1191 } else {
1192 trace_e1000e_rx_metadata_l3_cso_disabled();
1193 }
1194
1195 if (!igb_rx_l4_cso_enabled(core)) {
1196 trace_e1000e_rx_metadata_l4_cso_disabled();
1197 return;
1198 }
1199
1200 if (!net_rx_pkt_validate_l4_csum(pkt, &csum_valid)) {
1201 trace_e1000e_rx_metadata_l4_csum_validation_failed();
1202 return;
1203 }
1204
1205 csum_error = csum_valid ? 0 : E1000_RXDEXT_STATERR_TCPE;
1206 *status_flags |= E1000_RXD_STAT_TCPCS | csum_error;
1207
1208 if (l4hdr_proto == ETH_L4_HDR_PROTO_UDP) {
1209 *status_flags |= E1000_RXD_STAT_UDPCS;
1210 }
1211 }
1212
1213 static void
1214 igb_build_rx_metadata(IGBCore *core,
1215 struct NetRxPkt *pkt,
1216 bool is_eop,
1217 const E1000E_RSSInfo *rss_info,
1218 uint16_t *pkt_info, uint16_t *hdr_info,
1219 uint32_t *rss,
1220 uint32_t *status_flags,
1221 uint16_t *ip_id,
1222 uint16_t *vlan_tag)
1223 {
1224 struct virtio_net_hdr *vhdr;
1225 bool hasip4, hasip6, csum_valid;
1226 EthL4HdrProto l4hdr_proto;
1227
1228 *status_flags = E1000_RXD_STAT_DD;
1229
1230 /* No additional metadata needed for non-EOP descriptors */
1231 /* TODO: EOP apply only to status so don't skip whole function. */
1232 if (!is_eop) {
1233 goto func_exit;
1234 }
1235
1236 *status_flags |= E1000_RXD_STAT_EOP;
1237
1238 net_rx_pkt_get_protocols(pkt, &hasip4, &hasip6, &l4hdr_proto);
1239 trace_e1000e_rx_metadata_protocols(hasip4, hasip6, l4hdr_proto);
1240
1241 /* VLAN state */
1242 if (net_rx_pkt_is_vlan_stripped(pkt)) {
1243 *status_flags |= E1000_RXD_STAT_VP;
1244 *vlan_tag = cpu_to_le16(net_rx_pkt_get_vlan_tag(pkt));
1245 trace_e1000e_rx_metadata_vlan(*vlan_tag);
1246 }
1247
1248 /* Packet parsing results */
1249 if ((core->mac[RXCSUM] & E1000_RXCSUM_PCSD) != 0) {
1250 if (rss_info->enabled) {
1251 *rss = cpu_to_le32(rss_info->hash);
1252 trace_igb_rx_metadata_rss(*rss);
1253 }
1254 } else if (hasip4) {
1255 *status_flags |= E1000_RXD_STAT_IPIDV;
1256 *ip_id = cpu_to_le16(net_rx_pkt_get_ip_id(pkt));
1257 trace_e1000e_rx_metadata_ip_id(*ip_id);
1258 }
1259
1260 if (l4hdr_proto == ETH_L4_HDR_PROTO_TCP && net_rx_pkt_is_tcp_ack(pkt)) {
1261 *status_flags |= E1000_RXD_STAT_ACK;
1262 trace_e1000e_rx_metadata_ack();
1263 }
1264
1265 if (pkt_info) {
1266 *pkt_info = rss_info->enabled ? rss_info->type : 0;
1267
1268 if (hasip4) {
1269 *pkt_info |= E1000_ADVRXD_PKT_IP4;
1270 }
1271
1272 if (hasip6) {
1273 *pkt_info |= E1000_ADVRXD_PKT_IP6;
1274 }
1275
1276 switch (l4hdr_proto) {
1277 case ETH_L4_HDR_PROTO_TCP:
1278 *pkt_info |= E1000_ADVRXD_PKT_TCP;
1279 break;
1280
1281 case ETH_L4_HDR_PROTO_UDP:
1282 *pkt_info |= E1000_ADVRXD_PKT_UDP;
1283 break;
1284
1285 case ETH_L4_HDR_PROTO_SCTP:
1286 *pkt_info |= E1000_ADVRXD_PKT_SCTP;
1287 break;
1288
1289 default:
1290 break;
1291 }
1292 }
1293
1294 if (hdr_info) {
1295 *hdr_info = 0;
1296 }
1297
1298 /* RX CSO information */
1299 if (hasip6 && (core->mac[RFCTL] & E1000_RFCTL_IPV6_XSUM_DIS)) {
1300 trace_e1000e_rx_metadata_ipv6_sum_disabled();
1301 goto func_exit;
1302 }
1303
1304 vhdr = net_rx_pkt_get_vhdr(pkt);
1305
1306 if (!(vhdr->flags & VIRTIO_NET_HDR_F_DATA_VALID) &&
1307 !(vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM)) {
1308 trace_e1000e_rx_metadata_virthdr_no_csum_info();
1309 igb_verify_csum_in_sw(core, pkt, status_flags, l4hdr_proto);
1310 goto func_exit;
1311 }
1312
1313 if (igb_rx_l3_cso_enabled(core)) {
1314 *status_flags |= hasip4 ? E1000_RXD_STAT_IPCS : 0;
1315 } else {
1316 trace_e1000e_rx_metadata_l3_cso_disabled();
1317 }
1318
1319 if (igb_rx_l4_cso_enabled(core)) {
1320 switch (l4hdr_proto) {
1321 case ETH_L4_HDR_PROTO_SCTP:
1322 if (!net_rx_pkt_validate_l4_csum(pkt, &csum_valid)) {
1323 trace_e1000e_rx_metadata_l4_csum_validation_failed();
1324 goto func_exit;
1325 }
1326 if (!csum_valid) {
1327 *status_flags |= E1000_RXDEXT_STATERR_TCPE;
1328 }
1329 /* fall through */
1330 case ETH_L4_HDR_PROTO_TCP:
1331 *status_flags |= E1000_RXD_STAT_TCPCS;
1332 break;
1333
1334 case ETH_L4_HDR_PROTO_UDP:
1335 *status_flags |= E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS;
1336 break;
1337
1338 default:
1339 break;
1340 }
1341 } else {
1342 trace_e1000e_rx_metadata_l4_cso_disabled();
1343 }
1344
1345 func_exit:
1346 trace_e1000e_rx_metadata_status_flags(*status_flags);
1347 *status_flags = cpu_to_le32(*status_flags);
1348 }
1349
1350 static inline void
1351 igb_write_lgcy_rx_descr(IGBCore *core, struct e1000_rx_desc *desc,
1352 struct NetRxPkt *pkt,
1353 const E1000E_RSSInfo *rss_info,
1354 uint16_t length)
1355 {
1356 uint32_t status_flags, rss;
1357 uint16_t ip_id;
1358
1359 assert(!rss_info->enabled);
1360 desc->length = cpu_to_le16(length);
1361 desc->csum = 0;
1362
1363 igb_build_rx_metadata(core, pkt, pkt != NULL,
1364 rss_info,
1365 NULL, NULL, &rss,
1366 &status_flags, &ip_id,
1367 &desc->special);
1368 desc->errors = (uint8_t) (le32_to_cpu(status_flags) >> 24);
1369 desc->status = (uint8_t) le32_to_cpu(status_flags);
1370 }
1371
1372 static inline void
1373 igb_write_adv_rx_descr(IGBCore *core, union e1000_adv_rx_desc *desc,
1374 struct NetRxPkt *pkt,
1375 const E1000E_RSSInfo *rss_info,
1376 uint16_t length)
1377 {
1378 memset(&desc->wb, 0, sizeof(desc->wb));
1379
1380 desc->wb.upper.length = cpu_to_le16(length);
1381
1382 igb_build_rx_metadata(core, pkt, pkt != NULL,
1383 rss_info,
1384 &desc->wb.lower.lo_dword.pkt_info,
1385 &desc->wb.lower.lo_dword.hdr_info,
1386 &desc->wb.lower.hi_dword.rss,
1387 &desc->wb.upper.status_error,
1388 &desc->wb.lower.hi_dword.csum_ip.ip_id,
1389 &desc->wb.upper.vlan);
1390 }
1391
1392 static inline void
1393 igb_write_rx_descr(IGBCore *core, union e1000_rx_desc_union *desc,
1394 struct NetRxPkt *pkt, const E1000E_RSSInfo *rss_info, uint16_t length)
1395 {
1396 if (igb_rx_use_legacy_descriptor(core)) {
1397 igb_write_lgcy_rx_descr(core, &desc->legacy, pkt, rss_info, length);
1398 } else {
1399 igb_write_adv_rx_descr(core, &desc->adv, pkt, rss_info, length);
1400 }
1401 }
1402
1403 static inline void
1404 igb_pci_dma_write_rx_desc(IGBCore *core, PCIDevice *dev, dma_addr_t addr,
1405 union e1000_rx_desc_union *desc, dma_addr_t len)
1406 {
1407 if (igb_rx_use_legacy_descriptor(core)) {
1408 struct e1000_rx_desc *d = &desc->legacy;
1409 size_t offset = offsetof(struct e1000_rx_desc, status);
1410 uint8_t status = d->status;
1411
1412 d->status &= ~E1000_RXD_STAT_DD;
1413 pci_dma_write(dev, addr, desc, len);
1414
1415 if (status & E1000_RXD_STAT_DD) {
1416 d->status = status;
1417 pci_dma_write(dev, addr + offset, &status, sizeof(status));
1418 }
1419 } else {
1420 union e1000_adv_rx_desc *d = &desc->adv;
1421 size_t offset =
1422 offsetof(union e1000_adv_rx_desc, wb.upper.status_error);
1423 uint32_t status = d->wb.upper.status_error;
1424
1425 d->wb.upper.status_error &= ~E1000_RXD_STAT_DD;
1426 pci_dma_write(dev, addr, desc, len);
1427
1428 if (status & E1000_RXD_STAT_DD) {
1429 d->wb.upper.status_error = status;
1430 pci_dma_write(dev, addr + offset, &status, sizeof(status));
1431 }
1432 }
1433 }
1434
1435 static void
1436 igb_write_to_rx_buffers(IGBCore *core,
1437 PCIDevice *d,
1438 hwaddr ba,
1439 uint16_t *written,
1440 const char *data,
1441 dma_addr_t data_len)
1442 {
1443 trace_igb_rx_desc_buff_write(ba, *written, data, data_len);
1444 pci_dma_write(d, ba + *written, data, data_len);
1445 *written += data_len;
1446 }
1447
1448 static void
1449 igb_update_rx_stats(IGBCore *core, const E1000E_RingInfo *rxi,
1450 size_t pkt_size, size_t pkt_fcs_size)
1451 {
1452 eth_pkt_types_e pkt_type = net_rx_pkt_get_packet_type(core->rx_pkt);
1453 e1000x_update_rx_total_stats(core->mac, pkt_type, pkt_size, pkt_fcs_size);
1454
1455 if (core->mac[MRQC] & 1) {
1456 uint16_t pool = rxi->idx % IGB_NUM_VM_POOLS;
1457
1458 core->mac[PVFGORC0 + (pool * 64)] += pkt_size + 4;
1459 core->mac[PVFGPRC0 + (pool * 64)]++;
1460 if (pkt_type == ETH_PKT_MCAST) {
1461 core->mac[PVFMPRC0 + (pool * 64)]++;
1462 }
1463 }
1464 }
1465
1466 static inline bool
1467 igb_rx_descr_threshold_hit(IGBCore *core, const E1000E_RingInfo *rxi)
1468 {
1469 return igb_ring_free_descr_num(core, rxi) ==
1470 ((core->mac[E1000_SRRCTL(rxi->idx) >> 2] >> 20) & 31) * 16;
1471 }
1472
1473 static void
1474 igb_write_packet_to_guest(IGBCore *core, struct NetRxPkt *pkt,
1475 const E1000E_RxRing *rxr,
1476 const E1000E_RSSInfo *rss_info)
1477 {
1478 PCIDevice *d;
1479 dma_addr_t base;
1480 union e1000_rx_desc_union desc;
1481 size_t desc_size;
1482 size_t desc_offset = 0;
1483 size_t iov_ofs = 0;
1484
1485 struct iovec *iov = net_rx_pkt_get_iovec(pkt);
1486 size_t size = net_rx_pkt_get_total_len(pkt);
1487 size_t total_size = size + e1000x_fcs_len(core->mac);
1488 const E1000E_RingInfo *rxi = rxr->i;
1489 size_t bufsize = igb_rxbufsize(core, rxi);
1490
1491 d = pcie_sriov_get_vf_at_index(core->owner, rxi->idx % 8);
1492 if (!d) {
1493 d = core->owner;
1494 }
1495
1496 do {
1497 hwaddr ba;
1498 uint16_t written = 0;
1499 bool is_last = false;
1500
1501 desc_size = total_size - desc_offset;
1502
1503 if (desc_size > bufsize) {
1504 desc_size = bufsize;
1505 }
1506
1507 if (igb_ring_empty(core, rxi)) {
1508 return;
1509 }
1510
1511 base = igb_ring_head_descr(core, rxi);
1512
1513 pci_dma_read(d, base, &desc, core->rx_desc_len);
1514
1515 trace_e1000e_rx_descr(rxi->idx, base, core->rx_desc_len);
1516
1517 igb_read_rx_descr(core, &desc, &ba);
1518
1519 if (ba) {
1520 if (desc_offset < size) {
1521 static const uint32_t fcs_pad;
1522 size_t iov_copy;
1523 size_t copy_size = size - desc_offset;
1524 if (copy_size > bufsize) {
1525 copy_size = bufsize;
1526 }
1527
1528 /* Copy packet payload */
1529 while (copy_size) {
1530 iov_copy = MIN(copy_size, iov->iov_len - iov_ofs);
1531
1532 igb_write_to_rx_buffers(core, d, ba, &written,
1533 iov->iov_base + iov_ofs, iov_copy);
1534
1535 copy_size -= iov_copy;
1536 iov_ofs += iov_copy;
1537 if (iov_ofs == iov->iov_len) {
1538 iov++;
1539 iov_ofs = 0;
1540 }
1541 }
1542
1543 if (desc_offset + desc_size >= total_size) {
1544 /* Simulate FCS checksum presence in the last descriptor */
1545 igb_write_to_rx_buffers(core, d, ba, &written,
1546 (const char *) &fcs_pad, e1000x_fcs_len(core->mac));
1547 }
1548 }
1549 } else { /* as per intel docs; skip descriptors with null buf addr */
1550 trace_e1000e_rx_null_descriptor();
1551 }
1552 desc_offset += desc_size;
1553 if (desc_offset >= total_size) {
1554 is_last = true;
1555 }
1556
1557 igb_write_rx_descr(core, &desc, is_last ? core->rx_pkt : NULL,
1558 rss_info, written);
1559 igb_pci_dma_write_rx_desc(core, d, base, &desc, core->rx_desc_len);
1560
1561 igb_ring_advance(core, rxi, core->rx_desc_len / E1000_MIN_RX_DESC_LEN);
1562
1563 } while (desc_offset < total_size);
1564
1565 igb_update_rx_stats(core, rxi, size, total_size);
1566 }
1567
1568 static bool
1569 igb_rx_strip_vlan(IGBCore *core, const E1000E_RingInfo *rxi)
1570 {
1571 if (core->mac[MRQC] & 1) {
1572 uint16_t pool = rxi->idx % IGB_NUM_VM_POOLS;
1573 /* Sec 7.10.3.8: CTRL.VME is ignored, only VMOLR/RPLOLR is used */
1574 return (net_rx_pkt_get_packet_type(core->rx_pkt) == ETH_PKT_MCAST) ?
1575 core->mac[RPLOLR] & E1000_RPLOLR_STRVLAN :
1576 core->mac[VMOLR0 + pool] & E1000_VMOLR_STRVLAN;
1577 }
1578
1579 return e1000x_vlan_enabled(core->mac);
1580 }
1581
1582 static inline void
1583 igb_rx_fix_l4_csum(IGBCore *core, struct NetRxPkt *pkt)
1584 {
1585 struct virtio_net_hdr *vhdr = net_rx_pkt_get_vhdr(pkt);
1586
1587 if (vhdr->flags & VIRTIO_NET_HDR_F_NEEDS_CSUM) {
1588 net_rx_pkt_fix_l4_csum(pkt);
1589 }
1590 }
1591
1592 ssize_t
1593 igb_receive_iov(IGBCore *core, const struct iovec *iov, int iovcnt)
1594 {
1595 return igb_receive_internal(core, iov, iovcnt, core->has_vnet, NULL);
1596 }
1597
1598 static ssize_t
1599 igb_receive_internal(IGBCore *core, const struct iovec *iov, int iovcnt,
1600 bool has_vnet, bool *external_tx)
1601 {
1602 uint16_t queues = 0;
1603 uint32_t causes = 0;
1604 union {
1605 L2Header l2_header;
1606 uint8_t octets[ETH_ZLEN];
1607 } buf;
1608 struct iovec min_iov;
1609 size_t size, orig_size;
1610 size_t iov_ofs = 0;
1611 E1000E_RxRing rxr;
1612 E1000E_RSSInfo rss_info;
1613 size_t total_size;
1614 int strip_vlan_index;
1615 int i;
1616
1617 trace_e1000e_rx_receive_iov(iovcnt);
1618
1619 if (external_tx) {
1620 *external_tx = true;
1621 }
1622
1623 if (!e1000x_hw_rx_enabled(core->mac)) {
1624 return -1;
1625 }
1626
1627 /* Pull virtio header in */
1628 if (has_vnet) {
1629 net_rx_pkt_set_vhdr_iovec(core->rx_pkt, iov, iovcnt);
1630 iov_ofs = sizeof(struct virtio_net_hdr);
1631 } else {
1632 net_rx_pkt_unset_vhdr(core->rx_pkt);
1633 }
1634
1635 orig_size = iov_size(iov, iovcnt);
1636 size = orig_size - iov_ofs;
1637
1638 /* Pad to minimum Ethernet frame length */
1639 if (size < sizeof(buf)) {
1640 iov_to_buf(iov, iovcnt, iov_ofs, &buf, size);
1641 memset(&buf.octets[size], 0, sizeof(buf) - size);
1642 e1000x_inc_reg_if_not_full(core->mac, RUC);
1643 min_iov.iov_base = &buf;
1644 min_iov.iov_len = size = sizeof(buf);
1645 iovcnt = 1;
1646 iov = &min_iov;
1647 iov_ofs = 0;
1648 } else {
1649 iov_to_buf(iov, iovcnt, iov_ofs, &buf, sizeof(buf.l2_header));
1650 }
1651
1652 /* Discard oversized packets if !LPE and !SBP. */
1653 if (e1000x_is_oversized(core->mac, size)) {
1654 return orig_size;
1655 }
1656
1657 net_rx_pkt_set_packet_type(core->rx_pkt,
1658 get_eth_packet_type(&buf.l2_header.eth));
1659 net_rx_pkt_set_protocols(core->rx_pkt, iov, iovcnt, iov_ofs);
1660
1661 queues = igb_receive_assign(core, &buf.l2_header, size,
1662 &rss_info, external_tx);
1663 if (!queues) {
1664 trace_e1000e_rx_flt_dropped();
1665 return orig_size;
1666 }
1667
1668 for (i = 0; i < IGB_NUM_QUEUES; i++) {
1669 if (!(queues & BIT(i)) ||
1670 !(core->mac[RXDCTL0 + (i * 16)] & E1000_RXDCTL_QUEUE_ENABLE)) {
1671 continue;
1672 }
1673
1674 igb_rx_ring_init(core, &rxr, i);
1675
1676 if (!igb_rx_strip_vlan(core, rxr.i)) {
1677 strip_vlan_index = -1;
1678 } else if (core->mac[CTRL_EXT] & BIT(26)) {
1679 strip_vlan_index = 1;
1680 } else {
1681 strip_vlan_index = 0;
1682 }
1683
1684 net_rx_pkt_attach_iovec_ex(core->rx_pkt, iov, iovcnt, iov_ofs,
1685 strip_vlan_index,
1686 core->mac[VET] & 0xffff,
1687 core->mac[VET] >> 16);
1688
1689 total_size = net_rx_pkt_get_total_len(core->rx_pkt) +
1690 e1000x_fcs_len(core->mac);
1691
1692 if (!igb_has_rxbufs(core, rxr.i, total_size)) {
1693 causes |= E1000_ICS_RXO;
1694 trace_e1000e_rx_not_written_to_guest(rxr.i->idx);
1695 continue;
1696 }
1697
1698 causes |= E1000_ICR_RXDW;
1699
1700 igb_rx_fix_l4_csum(core, core->rx_pkt);
1701 igb_write_packet_to_guest(core, core->rx_pkt, &rxr, &rss_info);
1702
1703 /* Check if receive descriptor minimum threshold hit */
1704 if (igb_rx_descr_threshold_hit(core, rxr.i)) {
1705 causes |= E1000_ICS_RXDMT0;
1706 }
1707
1708 core->mac[EICR] |= igb_rx_wb_eic(core, rxr.i->idx);
1709
1710 trace_e1000e_rx_written_to_guest(rxr.i->idx);
1711 }
1712
1713 trace_e1000e_rx_interrupt_set(causes);
1714 igb_set_interrupt_cause(core, causes);
1715
1716 return orig_size;
1717 }
1718
1719 static inline bool
1720 igb_have_autoneg(IGBCore *core)
1721 {
1722 return core->phy[MII_BMCR] & MII_BMCR_AUTOEN;
1723 }
1724
1725 static void igb_update_flowctl_status(IGBCore *core)
1726 {
1727 if (igb_have_autoneg(core) && core->phy[MII_BMSR] & MII_BMSR_AN_COMP) {
1728 trace_e1000e_link_autoneg_flowctl(true);
1729 core->mac[CTRL] |= E1000_CTRL_TFCE | E1000_CTRL_RFCE;
1730 } else {
1731 trace_e1000e_link_autoneg_flowctl(false);
1732 }
1733 }
1734
1735 static inline void
1736 igb_link_down(IGBCore *core)
1737 {
1738 e1000x_update_regs_on_link_down(core->mac, core->phy);
1739 igb_update_flowctl_status(core);
1740 }
1741
1742 static inline void
1743 igb_set_phy_ctrl(IGBCore *core, uint16_t val)
1744 {
1745 /* bits 0-5 reserved; MII_BMCR_[ANRESTART,RESET] are self clearing */
1746 core->phy[MII_BMCR] = val & ~(0x3f | MII_BMCR_RESET | MII_BMCR_ANRESTART);
1747
1748 if ((val & MII_BMCR_ANRESTART) && igb_have_autoneg(core)) {
1749 e1000x_restart_autoneg(core->mac, core->phy, core->autoneg_timer);
1750 }
1751 }
1752
1753 void igb_core_set_link_status(IGBCore *core)
1754 {
1755 NetClientState *nc = qemu_get_queue(core->owner_nic);
1756 uint32_t old_status = core->mac[STATUS];
1757
1758 trace_e1000e_link_status_changed(nc->link_down ? false : true);
1759
1760 if (nc->link_down) {
1761 e1000x_update_regs_on_link_down(core->mac, core->phy);
1762 } else {
1763 if (igb_have_autoneg(core) &&
1764 !(core->phy[MII_BMSR] & MII_BMSR_AN_COMP)) {
1765 e1000x_restart_autoneg(core->mac, core->phy,
1766 core->autoneg_timer);
1767 } else {
1768 e1000x_update_regs_on_link_up(core->mac, core->phy);
1769 igb_start_recv(core);
1770 }
1771 }
1772
1773 if (core->mac[STATUS] != old_status) {
1774 igb_set_interrupt_cause(core, E1000_ICR_LSC);
1775 }
1776 }
1777
1778 static void
1779 igb_set_ctrl(IGBCore *core, int index, uint32_t val)
1780 {
1781 trace_e1000e_core_ctrl_write(index, val);
1782
1783 /* RST is self clearing */
1784 core->mac[CTRL] = val & ~E1000_CTRL_RST;
1785 core->mac[CTRL_DUP] = core->mac[CTRL];
1786
1787 trace_e1000e_link_set_params(
1788 !!(val & E1000_CTRL_ASDE),
1789 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT,
1790 !!(val & E1000_CTRL_FRCSPD),
1791 !!(val & E1000_CTRL_FRCDPX),
1792 !!(val & E1000_CTRL_RFCE),
1793 !!(val & E1000_CTRL_TFCE));
1794
1795 if (val & E1000_CTRL_RST) {
1796 trace_e1000e_core_ctrl_sw_reset();
1797 igb_reset(core, true);
1798 }
1799
1800 if (val & E1000_CTRL_PHY_RST) {
1801 trace_e1000e_core_ctrl_phy_reset();
1802 core->mac[STATUS] |= E1000_STATUS_PHYRA;
1803 }
1804 }
1805
1806 static void
1807 igb_set_rfctl(IGBCore *core, int index, uint32_t val)
1808 {
1809 trace_e1000e_rx_set_rfctl(val);
1810
1811 if (!(val & E1000_RFCTL_ISCSI_DIS)) {
1812 trace_e1000e_wrn_iscsi_filtering_not_supported();
1813 }
1814
1815 if (!(val & E1000_RFCTL_NFSW_DIS)) {
1816 trace_e1000e_wrn_nfsw_filtering_not_supported();
1817 }
1818
1819 if (!(val & E1000_RFCTL_NFSR_DIS)) {
1820 trace_e1000e_wrn_nfsr_filtering_not_supported();
1821 }
1822
1823 core->mac[RFCTL] = val;
1824 }
1825
1826 static void
1827 igb_calc_rxdesclen(IGBCore *core)
1828 {
1829 if (igb_rx_use_legacy_descriptor(core)) {
1830 core->rx_desc_len = sizeof(struct e1000_rx_desc);
1831 } else {
1832 core->rx_desc_len = sizeof(union e1000_adv_rx_desc);
1833 }
1834 trace_e1000e_rx_desc_len(core->rx_desc_len);
1835 }
1836
1837 static void
1838 igb_set_rx_control(IGBCore *core, int index, uint32_t val)
1839 {
1840 core->mac[RCTL] = val;
1841 trace_e1000e_rx_set_rctl(core->mac[RCTL]);
1842
1843 if (val & E1000_RCTL_DTYP_MASK) {
1844 qemu_log_mask(LOG_GUEST_ERROR,
1845 "igb: RCTL.DTYP must be zero for compatibility");
1846 }
1847
1848 if (val & E1000_RCTL_EN) {
1849 igb_calc_rxdesclen(core);
1850 igb_start_recv(core);
1851 }
1852 }
1853
1854 static inline void
1855 igb_clear_ims_bits(IGBCore *core, uint32_t bits)
1856 {
1857 trace_e1000e_irq_clear_ims(bits, core->mac[IMS], core->mac[IMS] & ~bits);
1858 core->mac[IMS] &= ~bits;
1859 }
1860
1861 static inline bool
1862 igb_postpone_interrupt(IGBIntrDelayTimer *timer)
1863 {
1864 if (timer->running) {
1865 trace_e1000e_irq_postponed_by_xitr(timer->delay_reg << 2);
1866
1867 return true;
1868 }
1869
1870 if (timer->core->mac[timer->delay_reg] != 0) {
1871 igb_intrmgr_rearm_timer(timer);
1872 }
1873
1874 return false;
1875 }
1876
1877 static inline bool
1878 igb_eitr_should_postpone(IGBCore *core, int idx)
1879 {
1880 return igb_postpone_interrupt(&core->eitr[idx]);
1881 }
1882
1883 static void igb_send_msix(IGBCore *core)
1884 {
1885 uint32_t causes = core->mac[EICR] & core->mac[EIMS];
1886 int vector;
1887
1888 for (vector = 0; vector < IGB_INTR_NUM; ++vector) {
1889 if ((causes & BIT(vector)) && !igb_eitr_should_postpone(core, vector)) {
1890
1891 trace_e1000e_irq_msix_notify_vec(vector);
1892 igb_msix_notify(core, vector);
1893 }
1894 }
1895 }
1896
1897 static inline void
1898 igb_fix_icr_asserted(IGBCore *core)
1899 {
1900 core->mac[ICR] &= ~E1000_ICR_ASSERTED;
1901 if (core->mac[ICR]) {
1902 core->mac[ICR] |= E1000_ICR_ASSERTED;
1903 }
1904
1905 trace_e1000e_irq_fix_icr_asserted(core->mac[ICR]);
1906 }
1907
1908 static void
1909 igb_update_interrupt_state(IGBCore *core)
1910 {
1911 uint32_t icr;
1912 uint32_t causes;
1913 uint32_t int_alloc;
1914
1915 icr = core->mac[ICR] & core->mac[IMS];
1916
1917 if (core->mac[GPIE] & E1000_GPIE_MSIX_MODE) {
1918 if (icr) {
1919 causes = 0;
1920 if (icr & E1000_ICR_DRSTA) {
1921 int_alloc = core->mac[IVAR_MISC] & 0xff;
1922 if (int_alloc & E1000_IVAR_VALID) {
1923 causes |= BIT(int_alloc & 0x1f);
1924 }
1925 }
1926 /* Check if other bits (excluding the TCP Timer) are enabled. */
1927 if (icr & ~E1000_ICR_DRSTA) {
1928 int_alloc = (core->mac[IVAR_MISC] >> 8) & 0xff;
1929 if (int_alloc & E1000_IVAR_VALID) {
1930 causes |= BIT(int_alloc & 0x1f);
1931 }
1932 trace_e1000e_irq_add_msi_other(core->mac[EICR]);
1933 }
1934 core->mac[EICR] |= causes;
1935 }
1936
1937 if ((core->mac[EICR] & core->mac[EIMS])) {
1938 igb_send_msix(core);
1939 }
1940 } else {
1941 igb_fix_icr_asserted(core);
1942
1943 if (icr) {
1944 core->mac[EICR] |= (icr & E1000_ICR_DRSTA) | E1000_EICR_OTHER;
1945 } else {
1946 core->mac[EICR] &= ~E1000_EICR_OTHER;
1947 }
1948
1949 trace_e1000e_irq_pending_interrupts(core->mac[ICR] & core->mac[IMS],
1950 core->mac[ICR], core->mac[IMS]);
1951
1952 if (msix_enabled(core->owner)) {
1953 if (icr) {
1954 trace_e1000e_irq_msix_notify_vec(0);
1955 msix_notify(core->owner, 0);
1956 }
1957 } else if (msi_enabled(core->owner)) {
1958 if (icr) {
1959 msi_notify(core->owner, 0);
1960 }
1961 } else {
1962 if (icr) {
1963 igb_raise_legacy_irq(core);
1964 } else {
1965 igb_lower_legacy_irq(core);
1966 }
1967 }
1968 }
1969 }
1970
1971 static void
1972 igb_set_interrupt_cause(IGBCore *core, uint32_t val)
1973 {
1974 trace_e1000e_irq_set_cause_entry(val, core->mac[ICR]);
1975
1976 core->mac[ICR] |= val;
1977
1978 trace_e1000e_irq_set_cause_exit(val, core->mac[ICR]);
1979
1980 igb_update_interrupt_state(core);
1981 }
1982
1983 static void igb_set_eics(IGBCore *core, int index, uint32_t val)
1984 {
1985 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE);
1986
1987 trace_igb_irq_write_eics(val, msix);
1988
1989 core->mac[EICS] |=
1990 val & (msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK);
1991
1992 /*
1993 * TODO: Move to igb_update_interrupt_state if EICS is modified in other
1994 * places.
1995 */
1996 core->mac[EICR] = core->mac[EICS];
1997
1998 igb_update_interrupt_state(core);
1999 }
2000
2001 static void igb_set_eims(IGBCore *core, int index, uint32_t val)
2002 {
2003 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE);
2004
2005 trace_igb_irq_write_eims(val, msix);
2006
2007 core->mac[EIMS] |=
2008 val & (msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK);
2009
2010 igb_update_interrupt_state(core);
2011 }
2012
2013 static void mailbox_interrupt_to_vf(IGBCore *core, uint16_t vfn)
2014 {
2015 uint32_t ent = core->mac[VTIVAR_MISC + vfn];
2016
2017 if ((ent & E1000_IVAR_VALID)) {
2018 core->mac[EICR] |= (ent & 0x3) << (22 - vfn * IGBVF_MSIX_VEC_NUM);
2019 igb_update_interrupt_state(core);
2020 }
2021 }
2022
2023 static void mailbox_interrupt_to_pf(IGBCore *core)
2024 {
2025 igb_set_interrupt_cause(core, E1000_ICR_VMMB);
2026 }
2027
2028 static void igb_set_pfmailbox(IGBCore *core, int index, uint32_t val)
2029 {
2030 uint16_t vfn = index - P2VMAILBOX0;
2031
2032 trace_igb_set_pfmailbox(vfn, val);
2033
2034 if (val & E1000_P2VMAILBOX_STS) {
2035 core->mac[V2PMAILBOX0 + vfn] |= E1000_V2PMAILBOX_PFSTS;
2036 mailbox_interrupt_to_vf(core, vfn);
2037 }
2038
2039 if (val & E1000_P2VMAILBOX_ACK) {
2040 core->mac[V2PMAILBOX0 + vfn] |= E1000_V2PMAILBOX_PFACK;
2041 mailbox_interrupt_to_vf(core, vfn);
2042 }
2043
2044 /* Buffer Taken by PF (can be set only if the VFU is cleared). */
2045 if (val & E1000_P2VMAILBOX_PFU) {
2046 if (!(core->mac[index] & E1000_P2VMAILBOX_VFU)) {
2047 core->mac[index] |= E1000_P2VMAILBOX_PFU;
2048 core->mac[V2PMAILBOX0 + vfn] |= E1000_V2PMAILBOX_PFU;
2049 }
2050 } else {
2051 core->mac[index] &= ~E1000_P2VMAILBOX_PFU;
2052 core->mac[V2PMAILBOX0 + vfn] &= ~E1000_V2PMAILBOX_PFU;
2053 }
2054
2055 if (val & E1000_P2VMAILBOX_RVFU) {
2056 core->mac[V2PMAILBOX0 + vfn] &= ~E1000_V2PMAILBOX_VFU;
2057 core->mac[MBVFICR] &= ~((E1000_MBVFICR_VFACK_VF1 << vfn) |
2058 (E1000_MBVFICR_VFREQ_VF1 << vfn));
2059 }
2060 }
2061
2062 static void igb_set_vfmailbox(IGBCore *core, int index, uint32_t val)
2063 {
2064 uint16_t vfn = index - V2PMAILBOX0;
2065
2066 trace_igb_set_vfmailbox(vfn, val);
2067
2068 if (val & E1000_V2PMAILBOX_REQ) {
2069 core->mac[MBVFICR] |= E1000_MBVFICR_VFREQ_VF1 << vfn;
2070 mailbox_interrupt_to_pf(core);
2071 }
2072
2073 if (val & E1000_V2PMAILBOX_ACK) {
2074 core->mac[MBVFICR] |= E1000_MBVFICR_VFACK_VF1 << vfn;
2075 mailbox_interrupt_to_pf(core);
2076 }
2077
2078 /* Buffer Taken by VF (can be set only if the PFU is cleared). */
2079 if (val & E1000_V2PMAILBOX_VFU) {
2080 if (!(core->mac[index] & E1000_V2PMAILBOX_PFU)) {
2081 core->mac[index] |= E1000_V2PMAILBOX_VFU;
2082 core->mac[P2VMAILBOX0 + vfn] |= E1000_P2VMAILBOX_VFU;
2083 }
2084 } else {
2085 core->mac[index] &= ~E1000_V2PMAILBOX_VFU;
2086 core->mac[P2VMAILBOX0 + vfn] &= ~E1000_P2VMAILBOX_VFU;
2087 }
2088 }
2089
2090 static void igb_vf_reset(IGBCore *core, uint16_t vfn)
2091 {
2092 uint16_t qn0 = vfn;
2093 uint16_t qn1 = vfn + IGB_NUM_VM_POOLS;
2094
2095 /* disable Rx and Tx for the VF*/
2096 core->mac[RXDCTL0 + (qn0 * 16)] &= ~E1000_RXDCTL_QUEUE_ENABLE;
2097 core->mac[RXDCTL0 + (qn1 * 16)] &= ~E1000_RXDCTL_QUEUE_ENABLE;
2098 core->mac[TXDCTL0 + (qn0 * 16)] &= ~E1000_TXDCTL_QUEUE_ENABLE;
2099 core->mac[TXDCTL0 + (qn1 * 16)] &= ~E1000_TXDCTL_QUEUE_ENABLE;
2100 core->mac[VFRE] &= ~BIT(vfn);
2101 core->mac[VFTE] &= ~BIT(vfn);
2102 /* indicate VF reset to PF */
2103 core->mac[VFLRE] |= BIT(vfn);
2104 /* VFLRE and mailbox use the same interrupt cause */
2105 mailbox_interrupt_to_pf(core);
2106 }
2107
2108 static void igb_w1c(IGBCore *core, int index, uint32_t val)
2109 {
2110 core->mac[index] &= ~val;
2111 }
2112
2113 static void igb_set_eimc(IGBCore *core, int index, uint32_t val)
2114 {
2115 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE);
2116
2117 /* Interrupts are disabled via a write to EIMC and reflected in EIMS. */
2118 core->mac[EIMS] &=
2119 ~(val & (msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK));
2120
2121 trace_igb_irq_write_eimc(val, core->mac[EIMS], msix);
2122 igb_update_interrupt_state(core);
2123 }
2124
2125 static void igb_set_eiac(IGBCore *core, int index, uint32_t val)
2126 {
2127 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE);
2128
2129 if (msix) {
2130 trace_igb_irq_write_eiac(val);
2131
2132 /*
2133 * TODO: When using IOV, the bits that correspond to MSI-X vectors
2134 * that are assigned to a VF are read-only.
2135 */
2136 core->mac[EIAC] |= (val & E1000_EICR_MSIX_MASK);
2137 }
2138 }
2139
2140 static void igb_set_eiam(IGBCore *core, int index, uint32_t val)
2141 {
2142 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE);
2143
2144 /*
2145 * TODO: When using IOV, the bits that correspond to MSI-X vectors that
2146 * are assigned to a VF are read-only.
2147 */
2148 core->mac[EIAM] |=
2149 ~(val & (msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK));
2150
2151 trace_igb_irq_write_eiam(val, msix);
2152 }
2153
2154 static void igb_set_eicr(IGBCore *core, int index, uint32_t val)
2155 {
2156 bool msix = !!(core->mac[GPIE] & E1000_GPIE_MSIX_MODE);
2157
2158 /*
2159 * TODO: In IOV mode, only bit zero of this vector is available for the PF
2160 * function.
2161 */
2162 core->mac[EICR] &=
2163 ~(val & (msix ? E1000_EICR_MSIX_MASK : E1000_EICR_LEGACY_MASK));
2164
2165 trace_igb_irq_write_eicr(val, msix);
2166 igb_update_interrupt_state(core);
2167 }
2168
2169 static void igb_set_vtctrl(IGBCore *core, int index, uint32_t val)
2170 {
2171 uint16_t vfn;
2172
2173 if (val & E1000_CTRL_RST) {
2174 vfn = (index - PVTCTRL0) / 0x40;
2175 igb_vf_reset(core, vfn);
2176 }
2177 }
2178
2179 static void igb_set_vteics(IGBCore *core, int index, uint32_t val)
2180 {
2181 uint16_t vfn = (index - PVTEICS0) / 0x40;
2182
2183 core->mac[index] = val;
2184 igb_set_eics(core, EICS, (val & 0x7) << (22 - vfn * IGBVF_MSIX_VEC_NUM));
2185 }
2186
2187 static void igb_set_vteims(IGBCore *core, int index, uint32_t val)
2188 {
2189 uint16_t vfn = (index - PVTEIMS0) / 0x40;
2190
2191 core->mac[index] = val;
2192 igb_set_eims(core, EIMS, (val & 0x7) << (22 - vfn * IGBVF_MSIX_VEC_NUM));
2193 }
2194
2195 static void igb_set_vteimc(IGBCore *core, int index, uint32_t val)
2196 {
2197 uint16_t vfn = (index - PVTEIMC0) / 0x40;
2198
2199 core->mac[index] = val;
2200 igb_set_eimc(core, EIMC, (val & 0x7) << (22 - vfn * IGBVF_MSIX_VEC_NUM));
2201 }
2202
2203 static void igb_set_vteiac(IGBCore *core, int index, uint32_t val)
2204 {
2205 uint16_t vfn = (index - PVTEIAC0) / 0x40;
2206
2207 core->mac[index] = val;
2208 igb_set_eiac(core, EIAC, (val & 0x7) << (22 - vfn * IGBVF_MSIX_VEC_NUM));
2209 }
2210
2211 static void igb_set_vteiam(IGBCore *core, int index, uint32_t val)
2212 {
2213 uint16_t vfn = (index - PVTEIAM0) / 0x40;
2214
2215 core->mac[index] = val;
2216 igb_set_eiam(core, EIAM, (val & 0x7) << (22 - vfn * IGBVF_MSIX_VEC_NUM));
2217 }
2218
2219 static void igb_set_vteicr(IGBCore *core, int index, uint32_t val)
2220 {
2221 uint16_t vfn = (index - PVTEICR0) / 0x40;
2222
2223 core->mac[index] = val;
2224 igb_set_eicr(core, EICR, (val & 0x7) << (22 - vfn * IGBVF_MSIX_VEC_NUM));
2225 }
2226
2227 static void igb_set_vtivar(IGBCore *core, int index, uint32_t val)
2228 {
2229 uint16_t vfn = (index - VTIVAR);
2230 uint16_t qn = vfn;
2231 uint8_t ent;
2232 int n;
2233
2234 core->mac[index] = val;
2235
2236 /* Get assigned vector associated with queue Rx#0. */
2237 if ((val & E1000_IVAR_VALID)) {
2238 n = igb_ivar_entry_rx(qn);
2239 ent = E1000_IVAR_VALID | (24 - vfn * IGBVF_MSIX_VEC_NUM - (2 - (val & 0x7)));
2240 core->mac[IVAR0 + n / 4] |= ent << 8 * (n % 4);
2241 }
2242
2243 /* Get assigned vector associated with queue Tx#0 */
2244 ent = val >> 8;
2245 if ((ent & E1000_IVAR_VALID)) {
2246 n = igb_ivar_entry_tx(qn);
2247 ent = E1000_IVAR_VALID | (24 - vfn * IGBVF_MSIX_VEC_NUM - (2 - (ent & 0x7)));
2248 core->mac[IVAR0 + n / 4] |= ent << 8 * (n % 4);
2249 }
2250
2251 /*
2252 * Ignoring assigned vectors associated with queues Rx#1 and Tx#1 for now.
2253 */
2254 }
2255
2256 static inline void
2257 igb_autoneg_timer(void *opaque)
2258 {
2259 IGBCore *core = opaque;
2260 if (!qemu_get_queue(core->owner_nic)->link_down) {
2261 e1000x_update_regs_on_autoneg_done(core->mac, core->phy);
2262 igb_start_recv(core);
2263
2264 igb_update_flowctl_status(core);
2265 /* signal link status change to the guest */
2266 igb_set_interrupt_cause(core, E1000_ICR_LSC);
2267 }
2268 }
2269
2270 static inline uint16_t
2271 igb_get_reg_index_with_offset(const uint16_t *mac_reg_access, hwaddr addr)
2272 {
2273 uint16_t index = (addr & 0x1ffff) >> 2;
2274 return index + (mac_reg_access[index] & 0xfffe);
2275 }
2276
2277 static const char igb_phy_regcap[MAX_PHY_REG_ADDRESS + 1] = {
2278 [MII_BMCR] = PHY_RW,
2279 [MII_BMSR] = PHY_R,
2280 [MII_PHYID1] = PHY_R,
2281 [MII_PHYID2] = PHY_R,
2282 [MII_ANAR] = PHY_RW,
2283 [MII_ANLPAR] = PHY_R,
2284 [MII_ANER] = PHY_R,
2285 [MII_ANNP] = PHY_RW,
2286 [MII_ANLPRNP] = PHY_R,
2287 [MII_CTRL1000] = PHY_RW,
2288 [MII_STAT1000] = PHY_R,
2289 [MII_EXTSTAT] = PHY_R,
2290
2291 [IGP01E1000_PHY_PORT_CONFIG] = PHY_RW,
2292 [IGP01E1000_PHY_PORT_STATUS] = PHY_R,
2293 [IGP01E1000_PHY_PORT_CTRL] = PHY_RW,
2294 [IGP01E1000_PHY_LINK_HEALTH] = PHY_R,
2295 [IGP02E1000_PHY_POWER_MGMT] = PHY_RW,
2296 [IGP01E1000_PHY_PAGE_SELECT] = PHY_W
2297 };
2298
2299 static void
2300 igb_phy_reg_write(IGBCore *core, uint32_t addr, uint16_t data)
2301 {
2302 assert(addr <= MAX_PHY_REG_ADDRESS);
2303
2304 if (addr == MII_BMCR) {
2305 igb_set_phy_ctrl(core, data);
2306 } else {
2307 core->phy[addr] = data;
2308 }
2309 }
2310
2311 static void
2312 igb_set_mdic(IGBCore *core, int index, uint32_t val)
2313 {
2314 uint32_t data = val & E1000_MDIC_DATA_MASK;
2315 uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
2316
2317 if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) { /* phy # */
2318 val = core->mac[MDIC] | E1000_MDIC_ERROR;
2319 } else if (val & E1000_MDIC_OP_READ) {
2320 if (!(igb_phy_regcap[addr] & PHY_R)) {
2321 trace_igb_core_mdic_read_unhandled(addr);
2322 val |= E1000_MDIC_ERROR;
2323 } else {
2324 val = (val ^ data) | core->phy[addr];
2325 trace_igb_core_mdic_read(addr, val);
2326 }
2327 } else if (val & E1000_MDIC_OP_WRITE) {
2328 if (!(igb_phy_regcap[addr] & PHY_W)) {
2329 trace_igb_core_mdic_write_unhandled(addr);
2330 val |= E1000_MDIC_ERROR;
2331 } else {
2332 trace_igb_core_mdic_write(addr, data);
2333 igb_phy_reg_write(core, addr, data);
2334 }
2335 }
2336 core->mac[MDIC] = val | E1000_MDIC_READY;
2337
2338 if (val & E1000_MDIC_INT_EN) {
2339 igb_set_interrupt_cause(core, E1000_ICR_MDAC);
2340 }
2341 }
2342
2343 static void
2344 igb_set_rdt(IGBCore *core, int index, uint32_t val)
2345 {
2346 core->mac[index] = val & 0xffff;
2347 trace_e1000e_rx_set_rdt(igb_mq_queue_idx(RDT0, index), val);
2348 igb_start_recv(core);
2349 }
2350
2351 static void
2352 igb_set_status(IGBCore *core, int index, uint32_t val)
2353 {
2354 if ((val & E1000_STATUS_PHYRA) == 0) {
2355 core->mac[index] &= ~E1000_STATUS_PHYRA;
2356 }
2357 }
2358
2359 static void
2360 igb_set_ctrlext(IGBCore *core, int index, uint32_t val)
2361 {
2362 trace_igb_link_set_ext_params(!!(val & E1000_CTRL_EXT_ASDCHK),
2363 !!(val & E1000_CTRL_EXT_SPD_BYPS),
2364 !!(val & E1000_CTRL_EXT_PFRSTD));
2365
2366 /* Zero self-clearing bits */
2367 val &= ~(E1000_CTRL_EXT_ASDCHK | E1000_CTRL_EXT_EE_RST);
2368 core->mac[CTRL_EXT] = val;
2369
2370 if (core->mac[CTRL_EXT] & E1000_CTRL_EXT_PFRSTD) {
2371 for (int vfn = 0; vfn < IGB_MAX_VF_FUNCTIONS; vfn++) {
2372 core->mac[V2PMAILBOX0 + vfn] &= ~E1000_V2PMAILBOX_RSTI;
2373 core->mac[V2PMAILBOX0 + vfn] |= E1000_V2PMAILBOX_RSTD;
2374 }
2375 }
2376 }
2377
2378 static void
2379 igb_set_pbaclr(IGBCore *core, int index, uint32_t val)
2380 {
2381 int i;
2382
2383 core->mac[PBACLR] = val & E1000_PBACLR_VALID_MASK;
2384
2385 if (!msix_enabled(core->owner)) {
2386 return;
2387 }
2388
2389 for (i = 0; i < IGB_INTR_NUM; i++) {
2390 if (core->mac[PBACLR] & BIT(i)) {
2391 msix_clr_pending(core->owner, i);
2392 }
2393 }
2394 }
2395
2396 static void
2397 igb_set_fcrth(IGBCore *core, int index, uint32_t val)
2398 {
2399 core->mac[FCRTH] = val & 0xFFF8;
2400 }
2401
2402 static void
2403 igb_set_fcrtl(IGBCore *core, int index, uint32_t val)
2404 {
2405 core->mac[FCRTL] = val & 0x8000FFF8;
2406 }
2407
2408 #define IGB_LOW_BITS_SET_FUNC(num) \
2409 static void \
2410 igb_set_##num##bit(IGBCore *core, int index, uint32_t val) \
2411 { \
2412 core->mac[index] = val & (BIT(num) - 1); \
2413 }
2414
2415 IGB_LOW_BITS_SET_FUNC(4)
2416 IGB_LOW_BITS_SET_FUNC(13)
2417 IGB_LOW_BITS_SET_FUNC(16)
2418
2419 static void
2420 igb_set_dlen(IGBCore *core, int index, uint32_t val)
2421 {
2422 core->mac[index] = val & 0xffff0;
2423 }
2424
2425 static void
2426 igb_set_dbal(IGBCore *core, int index, uint32_t val)
2427 {
2428 core->mac[index] = val & E1000_XDBAL_MASK;
2429 }
2430
2431 static void
2432 igb_set_tdt(IGBCore *core, int index, uint32_t val)
2433 {
2434 IGB_TxRing txr;
2435 int qn = igb_mq_queue_idx(TDT0, index);
2436
2437 core->mac[index] = val & 0xffff;
2438
2439 igb_tx_ring_init(core, &txr, qn);
2440 igb_start_xmit(core, &txr);
2441 }
2442
2443 static void
2444 igb_set_ics(IGBCore *core, int index, uint32_t val)
2445 {
2446 trace_e1000e_irq_write_ics(val);
2447 igb_set_interrupt_cause(core, val);
2448 }
2449
2450 static void
2451 igb_set_imc(IGBCore *core, int index, uint32_t val)
2452 {
2453 trace_e1000e_irq_ims_clear_set_imc(val);
2454 igb_clear_ims_bits(core, val);
2455 igb_update_interrupt_state(core);
2456 }
2457
2458 static void
2459 igb_set_ims(IGBCore *core, int index, uint32_t val)
2460 {
2461 uint32_t valid_val = val & 0x77D4FBFD;
2462
2463 trace_e1000e_irq_set_ims(val, core->mac[IMS], core->mac[IMS] | valid_val);
2464 core->mac[IMS] |= valid_val;
2465 igb_update_interrupt_state(core);
2466 }
2467
2468 static void igb_commit_icr(IGBCore *core)
2469 {
2470 /*
2471 * If GPIE.NSICR = 0, then the clear of IMS will occur only if at
2472 * least one bit is set in the IMS and there is a true interrupt as
2473 * reflected in ICR.INTA.
2474 */
2475 if ((core->mac[GPIE] & E1000_GPIE_NSICR) ||
2476 (core->mac[IMS] && (core->mac[ICR] & E1000_ICR_INT_ASSERTED))) {
2477 igb_clear_ims_bits(core, core->mac[IAM]);
2478 }
2479
2480 igb_update_interrupt_state(core);
2481 }
2482
2483 static void igb_set_icr(IGBCore *core, int index, uint32_t val)
2484 {
2485 uint32_t icr = core->mac[ICR] & ~val;
2486
2487 trace_igb_irq_icr_write(val, core->mac[ICR], icr);
2488 core->mac[ICR] = icr;
2489 igb_commit_icr(core);
2490 }
2491
2492 static uint32_t
2493 igb_mac_readreg(IGBCore *core, int index)
2494 {
2495 return core->mac[index];
2496 }
2497
2498 static uint32_t
2499 igb_mac_ics_read(IGBCore *core, int index)
2500 {
2501 trace_e1000e_irq_read_ics(core->mac[ICS]);
2502 return core->mac[ICS];
2503 }
2504
2505 static uint32_t
2506 igb_mac_ims_read(IGBCore *core, int index)
2507 {
2508 trace_e1000e_irq_read_ims(core->mac[IMS]);
2509 return core->mac[IMS];
2510 }
2511
2512 static uint32_t
2513 igb_mac_swsm_read(IGBCore *core, int index)
2514 {
2515 uint32_t val = core->mac[SWSM];
2516 core->mac[SWSM] = val | E1000_SWSM_SMBI;
2517 return val;
2518 }
2519
2520 static uint32_t
2521 igb_mac_eitr_read(IGBCore *core, int index)
2522 {
2523 return core->eitr_guest_value[index - EITR0];
2524 }
2525
2526 static uint32_t igb_mac_vfmailbox_read(IGBCore *core, int index)
2527 {
2528 uint32_t val = core->mac[index];
2529
2530 core->mac[index] &= ~(E1000_V2PMAILBOX_PFSTS | E1000_V2PMAILBOX_PFACK |
2531 E1000_V2PMAILBOX_RSTD);
2532
2533 return val;
2534 }
2535
2536 static uint32_t
2537 igb_mac_icr_read(IGBCore *core, int index)
2538 {
2539 uint32_t ret = core->mac[ICR];
2540 trace_e1000e_irq_icr_read_entry(ret);
2541
2542 if (core->mac[GPIE] & E1000_GPIE_NSICR) {
2543 trace_igb_irq_icr_clear_gpie_nsicr();
2544 core->mac[ICR] = 0;
2545 } else if (core->mac[IMS] == 0) {
2546 trace_e1000e_irq_icr_clear_zero_ims();
2547 core->mac[ICR] = 0;
2548 } else if (!msix_enabled(core->owner)) {
2549 trace_e1000e_irq_icr_clear_nonmsix_icr_read();
2550 core->mac[ICR] = 0;
2551 }
2552
2553 trace_e1000e_irq_icr_read_exit(core->mac[ICR]);
2554 igb_commit_icr(core);
2555 return ret;
2556 }
2557
2558 static uint32_t
2559 igb_mac_read_clr4(IGBCore *core, int index)
2560 {
2561 uint32_t ret = core->mac[index];
2562
2563 core->mac[index] = 0;
2564 return ret;
2565 }
2566
2567 static uint32_t
2568 igb_mac_read_clr8(IGBCore *core, int index)
2569 {
2570 uint32_t ret = core->mac[index];
2571
2572 core->mac[index] = 0;
2573 core->mac[index - 1] = 0;
2574 return ret;
2575 }
2576
2577 static uint32_t
2578 igb_get_ctrl(IGBCore *core, int index)
2579 {
2580 uint32_t val = core->mac[CTRL];
2581
2582 trace_e1000e_link_read_params(
2583 !!(val & E1000_CTRL_ASDE),
2584 (val & E1000_CTRL_SPD_SEL) >> E1000_CTRL_SPD_SHIFT,
2585 !!(val & E1000_CTRL_FRCSPD),
2586 !!(val & E1000_CTRL_FRCDPX),
2587 !!(val & E1000_CTRL_RFCE),
2588 !!(val & E1000_CTRL_TFCE));
2589
2590 return val;
2591 }
2592
2593 static uint32_t igb_get_status(IGBCore *core, int index)
2594 {
2595 uint32_t res = core->mac[STATUS];
2596 uint16_t num_vfs = pcie_sriov_num_vfs(core->owner);
2597
2598 if (core->mac[CTRL] & E1000_CTRL_FRCDPX) {
2599 res |= (core->mac[CTRL] & E1000_CTRL_FD) ? E1000_STATUS_FD : 0;
2600 } else {
2601 res |= E1000_STATUS_FD;
2602 }
2603
2604 if ((core->mac[CTRL] & E1000_CTRL_FRCSPD) ||
2605 (core->mac[CTRL_EXT] & E1000_CTRL_EXT_SPD_BYPS)) {
2606 switch (core->mac[CTRL] & E1000_CTRL_SPD_SEL) {
2607 case E1000_CTRL_SPD_10:
2608 res |= E1000_STATUS_SPEED_10;
2609 break;
2610 case E1000_CTRL_SPD_100:
2611 res |= E1000_STATUS_SPEED_100;
2612 break;
2613 case E1000_CTRL_SPD_1000:
2614 default:
2615 res |= E1000_STATUS_SPEED_1000;
2616 break;
2617 }
2618 } else {
2619 res |= E1000_STATUS_SPEED_1000;
2620 }
2621
2622 if (num_vfs) {
2623 res |= num_vfs << E1000_STATUS_NUM_VFS_SHIFT;
2624 res |= E1000_STATUS_IOV_MODE;
2625 }
2626
2627 /*
2628 * Windows driver 12.18.9.23 resets if E1000_STATUS_GIO_MASTER_ENABLE is
2629 * left set after E1000_CTRL_LRST is set.
2630 */
2631 if (!(core->mac[CTRL] & E1000_CTRL_GIO_MASTER_DISABLE) &&
2632 !(core->mac[CTRL] & E1000_CTRL_LRST)) {
2633 res |= E1000_STATUS_GIO_MASTER_ENABLE;
2634 }
2635
2636 return res;
2637 }
2638
2639 static void
2640 igb_mac_writereg(IGBCore *core, int index, uint32_t val)
2641 {
2642 core->mac[index] = val;
2643 }
2644
2645 static void
2646 igb_mac_setmacaddr(IGBCore *core, int index, uint32_t val)
2647 {
2648 uint32_t macaddr[2];
2649
2650 core->mac[index] = val;
2651
2652 macaddr[0] = cpu_to_le32(core->mac[RA]);
2653 macaddr[1] = cpu_to_le32(core->mac[RA + 1]);
2654 qemu_format_nic_info_str(qemu_get_queue(core->owner_nic),
2655 (uint8_t *) macaddr);
2656
2657 trace_e1000e_mac_set_sw(MAC_ARG(macaddr));
2658 }
2659
2660 static void
2661 igb_set_eecd(IGBCore *core, int index, uint32_t val)
2662 {
2663 static const uint32_t ro_bits = E1000_EECD_PRES |
2664 E1000_EECD_AUTO_RD |
2665 E1000_EECD_SIZE_EX_MASK;
2666
2667 core->mac[EECD] = (core->mac[EECD] & ro_bits) | (val & ~ro_bits);
2668 }
2669
2670 static void
2671 igb_set_eerd(IGBCore *core, int index, uint32_t val)
2672 {
2673 uint32_t addr = (val >> E1000_EERW_ADDR_SHIFT) & E1000_EERW_ADDR_MASK;
2674 uint32_t flags = 0;
2675 uint32_t data = 0;
2676
2677 if ((addr < IGB_EEPROM_SIZE) && (val & E1000_EERW_START)) {
2678 data = core->eeprom[addr];
2679 flags = E1000_EERW_DONE;
2680 }
2681
2682 core->mac[EERD] = flags |
2683 (addr << E1000_EERW_ADDR_SHIFT) |
2684 (data << E1000_EERW_DATA_SHIFT);
2685 }
2686
2687 static void
2688 igb_set_eitr(IGBCore *core, int index, uint32_t val)
2689 {
2690 uint32_t eitr_num = index - EITR0;
2691
2692 trace_igb_irq_eitr_set(eitr_num, val);
2693
2694 core->eitr_guest_value[eitr_num] = val & ~E1000_EITR_CNT_IGNR;
2695 core->mac[index] = val & 0x7FFE;
2696 }
2697
2698 static void
2699 igb_update_rx_offloads(IGBCore *core)
2700 {
2701 int cso_state = igb_rx_l4_cso_enabled(core);
2702
2703 trace_e1000e_rx_set_cso(cso_state);
2704
2705 if (core->has_vnet) {
2706 qemu_set_offload(qemu_get_queue(core->owner_nic)->peer,
2707 cso_state, 0, 0, 0, 0);
2708 }
2709 }
2710
2711 static void
2712 igb_set_rxcsum(IGBCore *core, int index, uint32_t val)
2713 {
2714 core->mac[RXCSUM] = val;
2715 igb_update_rx_offloads(core);
2716 }
2717
2718 static void
2719 igb_set_gcr(IGBCore *core, int index, uint32_t val)
2720 {
2721 uint32_t ro_bits = core->mac[GCR] & E1000_GCR_RO_BITS;
2722 core->mac[GCR] = (val & ~E1000_GCR_RO_BITS) | ro_bits;
2723 }
2724
2725 static uint32_t igb_get_systiml(IGBCore *core, int index)
2726 {
2727 e1000x_timestamp(core->mac, core->timadj, SYSTIML, SYSTIMH);
2728 return core->mac[SYSTIML];
2729 }
2730
2731 static uint32_t igb_get_rxsatrh(IGBCore *core, int index)
2732 {
2733 core->mac[TSYNCRXCTL] &= ~E1000_TSYNCRXCTL_VALID;
2734 return core->mac[RXSATRH];
2735 }
2736
2737 static uint32_t igb_get_txstmph(IGBCore *core, int index)
2738 {
2739 core->mac[TSYNCTXCTL] &= ~E1000_TSYNCTXCTL_VALID;
2740 return core->mac[TXSTMPH];
2741 }
2742
2743 static void igb_set_timinca(IGBCore *core, int index, uint32_t val)
2744 {
2745 e1000x_set_timinca(core->mac, &core->timadj, val);
2746 }
2747
2748 static void igb_set_timadjh(IGBCore *core, int index, uint32_t val)
2749 {
2750 core->mac[TIMADJH] = val;
2751 core->timadj += core->mac[TIMADJL] | ((int64_t)core->mac[TIMADJH] << 32);
2752 }
2753
2754 #define igb_getreg(x) [x] = igb_mac_readreg
2755 typedef uint32_t (*readops)(IGBCore *, int);
2756 static const readops igb_macreg_readops[] = {
2757 igb_getreg(WUFC),
2758 igb_getreg(MANC),
2759 igb_getreg(TOTL),
2760 igb_getreg(RDT0),
2761 igb_getreg(RDT1),
2762 igb_getreg(RDT2),
2763 igb_getreg(RDT3),
2764 igb_getreg(RDT4),
2765 igb_getreg(RDT5),
2766 igb_getreg(RDT6),
2767 igb_getreg(RDT7),
2768 igb_getreg(RDT8),
2769 igb_getreg(RDT9),
2770 igb_getreg(RDT10),
2771 igb_getreg(RDT11),
2772 igb_getreg(RDT12),
2773 igb_getreg(RDT13),
2774 igb_getreg(RDT14),
2775 igb_getreg(RDT15),
2776 igb_getreg(RDBAH0),
2777 igb_getreg(RDBAH1),
2778 igb_getreg(RDBAH2),
2779 igb_getreg(RDBAH3),
2780 igb_getreg(RDBAH4),
2781 igb_getreg(RDBAH5),
2782 igb_getreg(RDBAH6),
2783 igb_getreg(RDBAH7),
2784 igb_getreg(RDBAH8),
2785 igb_getreg(RDBAH9),
2786 igb_getreg(RDBAH10),
2787 igb_getreg(RDBAH11),
2788 igb_getreg(RDBAH12),
2789 igb_getreg(RDBAH13),
2790 igb_getreg(RDBAH14),
2791 igb_getreg(RDBAH15),
2792 igb_getreg(TDBAL0),
2793 igb_getreg(TDBAL1),
2794 igb_getreg(TDBAL2),
2795 igb_getreg(TDBAL3),
2796 igb_getreg(TDBAL4),
2797 igb_getreg(TDBAL5),
2798 igb_getreg(TDBAL6),
2799 igb_getreg(TDBAL7),
2800 igb_getreg(TDBAL8),
2801 igb_getreg(TDBAL9),
2802 igb_getreg(TDBAL10),
2803 igb_getreg(TDBAL11),
2804 igb_getreg(TDBAL12),
2805 igb_getreg(TDBAL13),
2806 igb_getreg(TDBAL14),
2807 igb_getreg(TDBAL15),
2808 igb_getreg(RDLEN0),
2809 igb_getreg(RDLEN1),
2810 igb_getreg(RDLEN2),
2811 igb_getreg(RDLEN3),
2812 igb_getreg(RDLEN4),
2813 igb_getreg(RDLEN5),
2814 igb_getreg(RDLEN6),
2815 igb_getreg(RDLEN7),
2816 igb_getreg(RDLEN8),
2817 igb_getreg(RDLEN9),
2818 igb_getreg(RDLEN10),
2819 igb_getreg(RDLEN11),
2820 igb_getreg(RDLEN12),
2821 igb_getreg(RDLEN13),
2822 igb_getreg(RDLEN14),
2823 igb_getreg(RDLEN15),
2824 igb_getreg(SRRCTL0),
2825 igb_getreg(SRRCTL1),
2826 igb_getreg(SRRCTL2),
2827 igb_getreg(SRRCTL3),
2828 igb_getreg(SRRCTL4),
2829 igb_getreg(SRRCTL5),
2830 igb_getreg(SRRCTL6),
2831 igb_getreg(SRRCTL7),
2832 igb_getreg(SRRCTL8),
2833 igb_getreg(SRRCTL9),
2834 igb_getreg(SRRCTL10),
2835 igb_getreg(SRRCTL11),
2836 igb_getreg(SRRCTL12),
2837 igb_getreg(SRRCTL13),
2838 igb_getreg(SRRCTL14),
2839 igb_getreg(SRRCTL15),
2840 igb_getreg(LATECOL),
2841 igb_getreg(XONTXC),
2842 igb_getreg(TDFH),
2843 igb_getreg(TDFT),
2844 igb_getreg(TDFHS),
2845 igb_getreg(TDFTS),
2846 igb_getreg(TDFPC),
2847 igb_getreg(WUS),
2848 igb_getreg(RDFH),
2849 igb_getreg(RDFT),
2850 igb_getreg(RDFHS),
2851 igb_getreg(RDFTS),
2852 igb_getreg(RDFPC),
2853 igb_getreg(GORCL),
2854 igb_getreg(MGTPRC),
2855 igb_getreg(EERD),
2856 igb_getreg(EIAC),
2857 igb_getreg(MANC2H),
2858 igb_getreg(RXCSUM),
2859 igb_getreg(GSCL_3),
2860 igb_getreg(GSCN_2),
2861 igb_getreg(FCAH),
2862 igb_getreg(FCRTH),
2863 igb_getreg(FLOP),
2864 igb_getreg(RXSTMPH),
2865 igb_getreg(TXSTMPL),
2866 igb_getreg(TIMADJL),
2867 igb_getreg(RDH0),
2868 igb_getreg(RDH1),
2869 igb_getreg(RDH2),
2870 igb_getreg(RDH3),
2871 igb_getreg(RDH4),
2872 igb_getreg(RDH5),
2873 igb_getreg(RDH6),
2874 igb_getreg(RDH7),
2875 igb_getreg(RDH8),
2876 igb_getreg(RDH9),
2877 igb_getreg(RDH10),
2878 igb_getreg(RDH11),
2879 igb_getreg(RDH12),
2880 igb_getreg(RDH13),
2881 igb_getreg(RDH14),
2882 igb_getreg(RDH15),
2883 igb_getreg(TDT0),
2884 igb_getreg(TDT1),
2885 igb_getreg(TDT2),
2886 igb_getreg(TDT3),
2887 igb_getreg(TDT4),
2888 igb_getreg(TDT5),
2889 igb_getreg(TDT6),
2890 igb_getreg(TDT7),
2891 igb_getreg(TDT8),
2892 igb_getreg(TDT9),
2893 igb_getreg(TDT10),
2894 igb_getreg(TDT11),
2895 igb_getreg(TDT12),
2896 igb_getreg(TDT13),
2897 igb_getreg(TDT14),
2898 igb_getreg(TDT15),
2899 igb_getreg(TNCRS),
2900 igb_getreg(RJC),
2901 igb_getreg(IAM),
2902 igb_getreg(GSCL_2),
2903 igb_getreg(TIPG),
2904 igb_getreg(FLMNGCTL),
2905 igb_getreg(FLMNGCNT),
2906 igb_getreg(TSYNCTXCTL),
2907 igb_getreg(EEMNGDATA),
2908 igb_getreg(CTRL_EXT),
2909 igb_getreg(SYSTIMH),
2910 igb_getreg(EEMNGCTL),
2911 igb_getreg(FLMNGDATA),
2912 igb_getreg(TSYNCRXCTL),
2913 igb_getreg(LEDCTL),
2914 igb_getreg(TCTL),
2915 igb_getreg(TCTL_EXT),
2916 igb_getreg(DTXCTL),
2917 igb_getreg(RXPBS),
2918 igb_getreg(TDH0),
2919 igb_getreg(TDH1),
2920 igb_getreg(TDH2),
2921 igb_getreg(TDH3),
2922 igb_getreg(TDH4),
2923 igb_getreg(TDH5),
2924 igb_getreg(TDH6),
2925 igb_getreg(TDH7),
2926 igb_getreg(TDH8),
2927 igb_getreg(TDH9),
2928 igb_getreg(TDH10),
2929 igb_getreg(TDH11),
2930 igb_getreg(TDH12),
2931 igb_getreg(TDH13),
2932 igb_getreg(TDH14),
2933 igb_getreg(TDH15),
2934 igb_getreg(ECOL),
2935 igb_getreg(DC),
2936 igb_getreg(RLEC),
2937 igb_getreg(XOFFTXC),
2938 igb_getreg(RFC),
2939 igb_getreg(RNBC),
2940 igb_getreg(MGTPTC),
2941 igb_getreg(TIMINCA),
2942 igb_getreg(FACTPS),
2943 igb_getreg(GSCL_1),
2944 igb_getreg(GSCN_0),
2945 igb_getreg(PBACLR),
2946 igb_getreg(FCTTV),
2947 igb_getreg(RXSATRL),
2948 igb_getreg(TORL),
2949 igb_getreg(TDLEN0),
2950 igb_getreg(TDLEN1),
2951 igb_getreg(TDLEN2),
2952 igb_getreg(TDLEN3),
2953 igb_getreg(TDLEN4),
2954 igb_getreg(TDLEN5),
2955 igb_getreg(TDLEN6),
2956 igb_getreg(TDLEN7),
2957 igb_getreg(TDLEN8),
2958 igb_getreg(TDLEN9),
2959 igb_getreg(TDLEN10),
2960 igb_getreg(TDLEN11),
2961 igb_getreg(TDLEN12),
2962 igb_getreg(TDLEN13),
2963 igb_getreg(TDLEN14),
2964 igb_getreg(TDLEN15),
2965 igb_getreg(MCC),
2966 igb_getreg(WUC),
2967 igb_getreg(EECD),
2968 igb_getreg(FCRTV),
2969 igb_getreg(TXDCTL0),
2970 igb_getreg(TXDCTL1),
2971 igb_getreg(TXDCTL2),
2972 igb_getreg(TXDCTL3),
2973 igb_getreg(TXDCTL4),
2974 igb_getreg(TXDCTL5),
2975 igb_getreg(TXDCTL6),
2976 igb_getreg(TXDCTL7),
2977 igb_getreg(TXDCTL8),
2978 igb_getreg(TXDCTL9),
2979 igb_getreg(TXDCTL10),
2980 igb_getreg(TXDCTL11),
2981 igb_getreg(TXDCTL12),
2982 igb_getreg(TXDCTL13),
2983 igb_getreg(TXDCTL14),
2984 igb_getreg(TXDCTL15),
2985 igb_getreg(TXCTL0),
2986 igb_getreg(TXCTL1),
2987 igb_getreg(TXCTL2),
2988 igb_getreg(TXCTL3),
2989 igb_getreg(TXCTL4),
2990 igb_getreg(TXCTL5),
2991 igb_getreg(TXCTL6),
2992 igb_getreg(TXCTL7),
2993 igb_getreg(TXCTL8),
2994 igb_getreg(TXCTL9),
2995 igb_getreg(TXCTL10),
2996 igb_getreg(TXCTL11),
2997 igb_getreg(TXCTL12),
2998 igb_getreg(TXCTL13),
2999 igb_getreg(TXCTL14),
3000 igb_getreg(TXCTL15),
3001 igb_getreg(TDWBAL0),
3002 igb_getreg(TDWBAL1),
3003 igb_getreg(TDWBAL2),
3004 igb_getreg(TDWBAL3),
3005 igb_getreg(TDWBAL4),
3006 igb_getreg(TDWBAL5),
3007 igb_getreg(TDWBAL6),
3008 igb_getreg(TDWBAL7),
3009 igb_getreg(TDWBAL8),
3010 igb_getreg(TDWBAL9),
3011 igb_getreg(TDWBAL10),
3012 igb_getreg(TDWBAL11),
3013 igb_getreg(TDWBAL12),
3014 igb_getreg(TDWBAL13),
3015 igb_getreg(TDWBAL14),
3016 igb_getreg(TDWBAL15),
3017 igb_getreg(TDWBAH0),
3018 igb_getreg(TDWBAH1),
3019 igb_getreg(TDWBAH2),
3020 igb_getreg(TDWBAH3),
3021 igb_getreg(TDWBAH4),
3022 igb_getreg(TDWBAH5),
3023 igb_getreg(TDWBAH6),
3024 igb_getreg(TDWBAH7),
3025 igb_getreg(TDWBAH8),
3026 igb_getreg(TDWBAH9),
3027 igb_getreg(TDWBAH10),
3028 igb_getreg(TDWBAH11),
3029 igb_getreg(TDWBAH12),
3030 igb_getreg(TDWBAH13),
3031 igb_getreg(TDWBAH14),
3032 igb_getreg(TDWBAH15),
3033 igb_getreg(PVTCTRL0),
3034 igb_getreg(PVTCTRL1),
3035 igb_getreg(PVTCTRL2),
3036 igb_getreg(PVTCTRL3),
3037 igb_getreg(PVTCTRL4),
3038 igb_getreg(PVTCTRL5),
3039 igb_getreg(PVTCTRL6),
3040 igb_getreg(PVTCTRL7),
3041 igb_getreg(PVTEIMS0),
3042 igb_getreg(PVTEIMS1),
3043 igb_getreg(PVTEIMS2),
3044 igb_getreg(PVTEIMS3),
3045 igb_getreg(PVTEIMS4),
3046 igb_getreg(PVTEIMS5),
3047 igb_getreg(PVTEIMS6),
3048 igb_getreg(PVTEIMS7),
3049 igb_getreg(PVTEIAC0),
3050 igb_getreg(PVTEIAC1),
3051 igb_getreg(PVTEIAC2),
3052 igb_getreg(PVTEIAC3),
3053 igb_getreg(PVTEIAC4),
3054 igb_getreg(PVTEIAC5),
3055 igb_getreg(PVTEIAC6),
3056 igb_getreg(PVTEIAC7),
3057 igb_getreg(PVTEIAM0),
3058 igb_getreg(PVTEIAM1),
3059 igb_getreg(PVTEIAM2),
3060 igb_getreg(PVTEIAM3),
3061 igb_getreg(PVTEIAM4),
3062 igb_getreg(PVTEIAM5),
3063 igb_getreg(PVTEIAM6),
3064 igb_getreg(PVTEIAM7),
3065 igb_getreg(PVFGPRC0),
3066 igb_getreg(PVFGPRC1),
3067 igb_getreg(PVFGPRC2),
3068 igb_getreg(PVFGPRC3),
3069 igb_getreg(PVFGPRC4),
3070 igb_getreg(PVFGPRC5),
3071 igb_getreg(PVFGPRC6),
3072 igb_getreg(PVFGPRC7),
3073 igb_getreg(PVFGPTC0),
3074 igb_getreg(PVFGPTC1),
3075 igb_getreg(PVFGPTC2),
3076 igb_getreg(PVFGPTC3),
3077 igb_getreg(PVFGPTC4),
3078 igb_getreg(PVFGPTC5),
3079 igb_getreg(PVFGPTC6),
3080 igb_getreg(PVFGPTC7),
3081 igb_getreg(PVFGORC0),
3082 igb_getreg(PVFGORC1),
3083 igb_getreg(PVFGORC2),
3084 igb_getreg(PVFGORC3),
3085 igb_getreg(PVFGORC4),
3086 igb_getreg(PVFGORC5),
3087 igb_getreg(PVFGORC6),
3088 igb_getreg(PVFGORC7),
3089 igb_getreg(PVFGOTC0),
3090 igb_getreg(PVFGOTC1),
3091 igb_getreg(PVFGOTC2),
3092 igb_getreg(PVFGOTC3),
3093 igb_getreg(PVFGOTC4),
3094 igb_getreg(PVFGOTC5),
3095 igb_getreg(PVFGOTC6),
3096 igb_getreg(PVFGOTC7),
3097 igb_getreg(PVFMPRC0),
3098 igb_getreg(PVFMPRC1),
3099 igb_getreg(PVFMPRC2),
3100 igb_getreg(PVFMPRC3),
3101 igb_getreg(PVFMPRC4),
3102 igb_getreg(PVFMPRC5),
3103 igb_getreg(PVFMPRC6),
3104 igb_getreg(PVFMPRC7),
3105 igb_getreg(PVFGPRLBC0),
3106 igb_getreg(PVFGPRLBC1),
3107 igb_getreg(PVFGPRLBC2),
3108 igb_getreg(PVFGPRLBC3),
3109 igb_getreg(PVFGPRLBC4),
3110 igb_getreg(PVFGPRLBC5),
3111 igb_getreg(PVFGPRLBC6),
3112 igb_getreg(PVFGPRLBC7),
3113 igb_getreg(PVFGPTLBC0),
3114 igb_getreg(PVFGPTLBC1),
3115 igb_getreg(PVFGPTLBC2),
3116 igb_getreg(PVFGPTLBC3),
3117 igb_getreg(PVFGPTLBC4),
3118 igb_getreg(PVFGPTLBC5),
3119 igb_getreg(PVFGPTLBC6),
3120 igb_getreg(PVFGPTLBC7),
3121 igb_getreg(PVFGORLBC0),
3122 igb_getreg(PVFGORLBC1),
3123 igb_getreg(PVFGORLBC2),
3124 igb_getreg(PVFGORLBC3),
3125 igb_getreg(PVFGORLBC4),
3126 igb_getreg(PVFGORLBC5),
3127 igb_getreg(PVFGORLBC6),
3128 igb_getreg(PVFGORLBC7),
3129 igb_getreg(PVFGOTLBC0),
3130 igb_getreg(PVFGOTLBC1),
3131 igb_getreg(PVFGOTLBC2),
3132 igb_getreg(PVFGOTLBC3),
3133 igb_getreg(PVFGOTLBC4),
3134 igb_getreg(PVFGOTLBC5),
3135 igb_getreg(PVFGOTLBC6),
3136 igb_getreg(PVFGOTLBC7),
3137 igb_getreg(RCTL),
3138 igb_getreg(MDIC),
3139 igb_getreg(FCRUC),
3140 igb_getreg(VET),
3141 igb_getreg(RDBAL0),
3142 igb_getreg(RDBAL1),
3143 igb_getreg(RDBAL2),
3144 igb_getreg(RDBAL3),
3145 igb_getreg(RDBAL4),
3146 igb_getreg(RDBAL5),
3147 igb_getreg(RDBAL6),
3148 igb_getreg(RDBAL7),
3149 igb_getreg(RDBAL8),
3150 igb_getreg(RDBAL9),
3151 igb_getreg(RDBAL10),
3152 igb_getreg(RDBAL11),
3153 igb_getreg(RDBAL12),
3154 igb_getreg(RDBAL13),
3155 igb_getreg(RDBAL14),
3156 igb_getreg(RDBAL15),
3157 igb_getreg(TDBAH0),
3158 igb_getreg(TDBAH1),
3159 igb_getreg(TDBAH2),
3160 igb_getreg(TDBAH3),
3161 igb_getreg(TDBAH4),
3162 igb_getreg(TDBAH5),
3163 igb_getreg(TDBAH6),
3164 igb_getreg(TDBAH7),
3165 igb_getreg(TDBAH8),
3166 igb_getreg(TDBAH9),
3167 igb_getreg(TDBAH10),
3168 igb_getreg(TDBAH11),
3169 igb_getreg(TDBAH12),
3170 igb_getreg(TDBAH13),
3171 igb_getreg(TDBAH14),
3172 igb_getreg(TDBAH15),
3173 igb_getreg(SCC),
3174 igb_getreg(COLC),
3175 igb_getreg(XOFFRXC),
3176 igb_getreg(IPAV),
3177 igb_getreg(GOTCL),
3178 igb_getreg(MGTPDC),
3179 igb_getreg(GCR),
3180 igb_getreg(MFVAL),
3181 igb_getreg(FUNCTAG),
3182 igb_getreg(GSCL_4),
3183 igb_getreg(GSCN_3),
3184 igb_getreg(MRQC),
3185 igb_getreg(FCT),
3186 igb_getreg(FLA),
3187 igb_getreg(RXDCTL0),
3188 igb_getreg(RXDCTL1),
3189 igb_getreg(RXDCTL2),
3190 igb_getreg(RXDCTL3),
3191 igb_getreg(RXDCTL4),
3192 igb_getreg(RXDCTL5),
3193 igb_getreg(RXDCTL6),
3194 igb_getreg(RXDCTL7),
3195 igb_getreg(RXDCTL8),
3196 igb_getreg(RXDCTL9),
3197 igb_getreg(RXDCTL10),
3198 igb_getreg(RXDCTL11),
3199 igb_getreg(RXDCTL12),
3200 igb_getreg(RXDCTL13),
3201 igb_getreg(RXDCTL14),
3202 igb_getreg(RXDCTL15),
3203 igb_getreg(RXSTMPL),
3204 igb_getreg(TIMADJH),
3205 igb_getreg(FCRTL),
3206 igb_getreg(XONRXC),
3207 igb_getreg(RFCTL),
3208 igb_getreg(GSCN_1),
3209 igb_getreg(FCAL),
3210 igb_getreg(GPIE),
3211 igb_getreg(TXPBS),
3212 igb_getreg(RLPML),
3213
3214 [TOTH] = igb_mac_read_clr8,
3215 [GOTCH] = igb_mac_read_clr8,
3216 [PRC64] = igb_mac_read_clr4,
3217 [PRC255] = igb_mac_read_clr4,
3218 [PRC1023] = igb_mac_read_clr4,
3219 [PTC64] = igb_mac_read_clr4,
3220 [PTC255] = igb_mac_read_clr4,
3221 [PTC1023] = igb_mac_read_clr4,
3222 [GPRC] = igb_mac_read_clr4,
3223 [TPT] = igb_mac_read_clr4,
3224 [RUC] = igb_mac_read_clr4,
3225 [BPRC] = igb_mac_read_clr4,
3226 [MPTC] = igb_mac_read_clr4,
3227 [IAC] = igb_mac_read_clr4,
3228 [ICR] = igb_mac_icr_read,
3229 [STATUS] = igb_get_status,
3230 [ICS] = igb_mac_ics_read,
3231 /*
3232 * 8.8.10: Reading the IMC register returns the value of the IMS register.
3233 */
3234 [IMC] = igb_mac_ims_read,
3235 [TORH] = igb_mac_read_clr8,
3236 [GORCH] = igb_mac_read_clr8,
3237 [PRC127] = igb_mac_read_clr4,
3238 [PRC511] = igb_mac_read_clr4,
3239 [PRC1522] = igb_mac_read_clr4,
3240 [PTC127] = igb_mac_read_clr4,
3241 [PTC511] = igb_mac_read_clr4,
3242 [PTC1522] = igb_mac_read_clr4,
3243 [GPTC] = igb_mac_read_clr4,
3244 [TPR] = igb_mac_read_clr4,
3245 [ROC] = igb_mac_read_clr4,
3246 [MPRC] = igb_mac_read_clr4,
3247 [BPTC] = igb_mac_read_clr4,
3248 [TSCTC] = igb_mac_read_clr4,
3249 [CTRL] = igb_get_ctrl,
3250 [SWSM] = igb_mac_swsm_read,
3251 [IMS] = igb_mac_ims_read,
3252 [SYSTIML] = igb_get_systiml,
3253 [RXSATRH] = igb_get_rxsatrh,
3254 [TXSTMPH] = igb_get_txstmph,
3255
3256 [CRCERRS ... MPC] = igb_mac_readreg,
3257 [IP6AT ... IP6AT + 3] = igb_mac_readreg,
3258 [IP4AT ... IP4AT + 6] = igb_mac_readreg,
3259 [RA ... RA + 31] = igb_mac_readreg,
3260 [RA2 ... RA2 + 31] = igb_mac_readreg,
3261 [WUPM ... WUPM + 31] = igb_mac_readreg,
3262 [MTA ... MTA + E1000_MC_TBL_SIZE - 1] = igb_mac_readreg,
3263 [VFTA ... VFTA + E1000_VLAN_FILTER_TBL_SIZE - 1] = igb_mac_readreg,
3264 [FFMT ... FFMT + 254] = igb_mac_readreg,
3265 [MDEF ... MDEF + 7] = igb_mac_readreg,
3266 [FTFT ... FTFT + 254] = igb_mac_readreg,
3267 [RETA ... RETA + 31] = igb_mac_readreg,
3268 [RSSRK ... RSSRK + 9] = igb_mac_readreg,
3269 [MAVTV0 ... MAVTV3] = igb_mac_readreg,
3270 [EITR0 ... EITR0 + IGB_INTR_NUM - 1] = igb_mac_eitr_read,
3271 [PVTEICR0] = igb_mac_read_clr4,
3272 [PVTEICR1] = igb_mac_read_clr4,
3273 [PVTEICR2] = igb_mac_read_clr4,
3274 [PVTEICR3] = igb_mac_read_clr4,
3275 [PVTEICR4] = igb_mac_read_clr4,
3276 [PVTEICR5] = igb_mac_read_clr4,
3277 [PVTEICR6] = igb_mac_read_clr4,
3278 [PVTEICR7] = igb_mac_read_clr4,
3279
3280 /* IGB specific: */
3281 [FWSM] = igb_mac_readreg,
3282 [SW_FW_SYNC] = igb_mac_readreg,
3283 [HTCBDPC] = igb_mac_read_clr4,
3284 [EICR] = igb_mac_read_clr4,
3285 [EIMS] = igb_mac_readreg,
3286 [EIAM] = igb_mac_readreg,
3287 [IVAR0 ... IVAR0 + 7] = igb_mac_readreg,
3288 igb_getreg(IVAR_MISC),
3289 igb_getreg(VT_CTL),
3290 [P2VMAILBOX0 ... P2VMAILBOX7] = igb_mac_readreg,
3291 [V2PMAILBOX0 ... V2PMAILBOX7] = igb_mac_vfmailbox_read,
3292 igb_getreg(MBVFICR),
3293 [VMBMEM0 ... VMBMEM0 + 127] = igb_mac_readreg,
3294 igb_getreg(MBVFIMR),
3295 igb_getreg(VFLRE),
3296 igb_getreg(VFRE),
3297 igb_getreg(VFTE),
3298 igb_getreg(QDE),
3299 igb_getreg(DTXSWC),
3300 igb_getreg(RPLOLR),
3301 [VLVF0 ... VLVF0 + E1000_VLVF_ARRAY_SIZE - 1] = igb_mac_readreg,
3302 [VMVIR0 ... VMVIR7] = igb_mac_readreg,
3303 [VMOLR0 ... VMOLR7] = igb_mac_readreg,
3304 [WVBR] = igb_mac_read_clr4,
3305 [RQDPC0] = igb_mac_read_clr4,
3306 [RQDPC1] = igb_mac_read_clr4,
3307 [RQDPC2] = igb_mac_read_clr4,
3308 [RQDPC3] = igb_mac_read_clr4,
3309 [RQDPC4] = igb_mac_read_clr4,
3310 [RQDPC5] = igb_mac_read_clr4,
3311 [RQDPC6] = igb_mac_read_clr4,
3312 [RQDPC7] = igb_mac_read_clr4,
3313 [RQDPC8] = igb_mac_read_clr4,
3314 [RQDPC9] = igb_mac_read_clr4,
3315 [RQDPC10] = igb_mac_read_clr4,
3316 [RQDPC11] = igb_mac_read_clr4,
3317 [RQDPC12] = igb_mac_read_clr4,
3318 [RQDPC13] = igb_mac_read_clr4,
3319 [RQDPC14] = igb_mac_read_clr4,
3320 [RQDPC15] = igb_mac_read_clr4,
3321 [VTIVAR ... VTIVAR + 7] = igb_mac_readreg,
3322 [VTIVAR_MISC ... VTIVAR_MISC + 7] = igb_mac_readreg,
3323 };
3324 enum { IGB_NREADOPS = ARRAY_SIZE(igb_macreg_readops) };
3325
3326 #define igb_putreg(x) [x] = igb_mac_writereg
3327 typedef void (*writeops)(IGBCore *, int, uint32_t);
3328 static const writeops igb_macreg_writeops[] = {
3329 igb_putreg(SWSM),
3330 igb_putreg(WUFC),
3331 igb_putreg(RDBAH0),
3332 igb_putreg(RDBAH1),
3333 igb_putreg(RDBAH2),
3334 igb_putreg(RDBAH3),
3335 igb_putreg(RDBAH4),
3336 igb_putreg(RDBAH5),
3337 igb_putreg(RDBAH6),
3338 igb_putreg(RDBAH7),
3339 igb_putreg(RDBAH8),
3340 igb_putreg(RDBAH9),
3341 igb_putreg(RDBAH10),
3342 igb_putreg(RDBAH11),
3343 igb_putreg(RDBAH12),
3344 igb_putreg(RDBAH13),
3345 igb_putreg(RDBAH14),
3346 igb_putreg(RDBAH15),
3347 igb_putreg(SRRCTL0),
3348 igb_putreg(SRRCTL1),
3349 igb_putreg(SRRCTL2),
3350 igb_putreg(SRRCTL3),
3351 igb_putreg(SRRCTL4),
3352 igb_putreg(SRRCTL5),
3353 igb_putreg(SRRCTL6),
3354 igb_putreg(SRRCTL7),
3355 igb_putreg(SRRCTL8),
3356 igb_putreg(SRRCTL9),
3357 igb_putreg(SRRCTL10),
3358 igb_putreg(SRRCTL11),
3359 igb_putreg(SRRCTL12),
3360 igb_putreg(SRRCTL13),
3361 igb_putreg(SRRCTL14),
3362 igb_putreg(SRRCTL15),
3363 igb_putreg(RXDCTL0),
3364 igb_putreg(RXDCTL1),
3365 igb_putreg(RXDCTL2),
3366 igb_putreg(RXDCTL3),
3367 igb_putreg(RXDCTL4),
3368 igb_putreg(RXDCTL5),
3369 igb_putreg(RXDCTL6),
3370 igb_putreg(RXDCTL7),
3371 igb_putreg(RXDCTL8),
3372 igb_putreg(RXDCTL9),
3373 igb_putreg(RXDCTL10),
3374 igb_putreg(RXDCTL11),
3375 igb_putreg(RXDCTL12),
3376 igb_putreg(RXDCTL13),
3377 igb_putreg(RXDCTL14),
3378 igb_putreg(RXDCTL15),
3379 igb_putreg(LEDCTL),
3380 igb_putreg(TCTL),
3381 igb_putreg(TCTL_EXT),
3382 igb_putreg(DTXCTL),
3383 igb_putreg(RXPBS),
3384 igb_putreg(RQDPC0),
3385 igb_putreg(FCAL),
3386 igb_putreg(FCRUC),
3387 igb_putreg(WUC),
3388 igb_putreg(WUS),
3389 igb_putreg(IPAV),
3390 igb_putreg(TDBAH0),
3391 igb_putreg(TDBAH1),
3392 igb_putreg(TDBAH2),
3393 igb_putreg(TDBAH3),
3394 igb_putreg(TDBAH4),
3395 igb_putreg(TDBAH5),
3396 igb_putreg(TDBAH6),
3397 igb_putreg(TDBAH7),
3398 igb_putreg(TDBAH8),
3399 igb_putreg(TDBAH9),
3400 igb_putreg(TDBAH10),
3401 igb_putreg(TDBAH11),
3402 igb_putreg(TDBAH12),
3403 igb_putreg(TDBAH13),
3404 igb_putreg(TDBAH14),
3405 igb_putreg(TDBAH15),
3406 igb_putreg(IAM),
3407 igb_putreg(MANC),
3408 igb_putreg(MANC2H),
3409 igb_putreg(MFVAL),
3410 igb_putreg(FACTPS),
3411 igb_putreg(FUNCTAG),
3412 igb_putreg(GSCL_1),
3413 igb_putreg(GSCL_2),
3414 igb_putreg(GSCL_3),
3415 igb_putreg(GSCL_4),
3416 igb_putreg(GSCN_0),
3417 igb_putreg(GSCN_1),
3418 igb_putreg(GSCN_2),
3419 igb_putreg(GSCN_3),
3420 igb_putreg(MRQC),
3421 igb_putreg(FLOP),
3422 igb_putreg(FLA),
3423 igb_putreg(TXDCTL0),
3424 igb_putreg(TXDCTL1),
3425 igb_putreg(TXDCTL2),
3426 igb_putreg(TXDCTL3),
3427 igb_putreg(TXDCTL4),
3428 igb_putreg(TXDCTL5),
3429 igb_putreg(TXDCTL6),
3430 igb_putreg(TXDCTL7),
3431 igb_putreg(TXDCTL8),
3432 igb_putreg(TXDCTL9),
3433 igb_putreg(TXDCTL10),
3434 igb_putreg(TXDCTL11),
3435 igb_putreg(TXDCTL12),
3436 igb_putreg(TXDCTL13),
3437 igb_putreg(TXDCTL14),
3438 igb_putreg(TXDCTL15),
3439 igb_putreg(TXCTL0),
3440 igb_putreg(TXCTL1),
3441 igb_putreg(TXCTL2),
3442 igb_putreg(TXCTL3),
3443 igb_putreg(TXCTL4),
3444 igb_putreg(TXCTL5),
3445 igb_putreg(TXCTL6),
3446 igb_putreg(TXCTL7),
3447 igb_putreg(TXCTL8),
3448 igb_putreg(TXCTL9),
3449 igb_putreg(TXCTL10),
3450 igb_putreg(TXCTL11),
3451 igb_putreg(TXCTL12),
3452 igb_putreg(TXCTL13),
3453 igb_putreg(TXCTL14),
3454 igb_putreg(TXCTL15),
3455 igb_putreg(TDWBAL0),
3456 igb_putreg(TDWBAL1),
3457 igb_putreg(TDWBAL2),
3458 igb_putreg(TDWBAL3),
3459 igb_putreg(TDWBAL4),
3460 igb_putreg(TDWBAL5),
3461 igb_putreg(TDWBAL6),
3462 igb_putreg(TDWBAL7),
3463 igb_putreg(TDWBAL8),
3464 igb_putreg(TDWBAL9),
3465 igb_putreg(TDWBAL10),
3466 igb_putreg(TDWBAL11),
3467 igb_putreg(TDWBAL12),
3468 igb_putreg(TDWBAL13),
3469 igb_putreg(TDWBAL14),
3470 igb_putreg(TDWBAL15),
3471 igb_putreg(TDWBAH0),
3472 igb_putreg(TDWBAH1),
3473 igb_putreg(TDWBAH2),
3474 igb_putreg(TDWBAH3),
3475 igb_putreg(TDWBAH4),
3476 igb_putreg(TDWBAH5),
3477 igb_putreg(TDWBAH6),
3478 igb_putreg(TDWBAH7),
3479 igb_putreg(TDWBAH8),
3480 igb_putreg(TDWBAH9),
3481 igb_putreg(TDWBAH10),
3482 igb_putreg(TDWBAH11),
3483 igb_putreg(TDWBAH12),
3484 igb_putreg(TDWBAH13),
3485 igb_putreg(TDWBAH14),
3486 igb_putreg(TDWBAH15),
3487 igb_putreg(TIPG),
3488 igb_putreg(RXSTMPH),
3489 igb_putreg(RXSTMPL),
3490 igb_putreg(RXSATRL),
3491 igb_putreg(RXSATRH),
3492 igb_putreg(TXSTMPL),
3493 igb_putreg(TXSTMPH),
3494 igb_putreg(SYSTIML),
3495 igb_putreg(SYSTIMH),
3496 igb_putreg(TIMADJL),
3497 igb_putreg(TSYNCRXCTL),
3498 igb_putreg(TSYNCTXCTL),
3499 igb_putreg(EEMNGCTL),
3500 igb_putreg(GPIE),
3501 igb_putreg(TXPBS),
3502 igb_putreg(RLPML),
3503 igb_putreg(VET),
3504
3505 [TDH0] = igb_set_16bit,
3506 [TDH1] = igb_set_16bit,
3507 [TDH2] = igb_set_16bit,
3508 [TDH3] = igb_set_16bit,
3509 [TDH4] = igb_set_16bit,
3510 [TDH5] = igb_set_16bit,
3511 [TDH6] = igb_set_16bit,
3512 [TDH7] = igb_set_16bit,
3513 [TDH8] = igb_set_16bit,
3514 [TDH9] = igb_set_16bit,
3515 [TDH10] = igb_set_16bit,
3516 [TDH11] = igb_set_16bit,
3517 [TDH12] = igb_set_16bit,
3518 [TDH13] = igb_set_16bit,
3519 [TDH14] = igb_set_16bit,
3520 [TDH15] = igb_set_16bit,
3521 [TDT0] = igb_set_tdt,
3522 [TDT1] = igb_set_tdt,
3523 [TDT2] = igb_set_tdt,
3524 [TDT3] = igb_set_tdt,
3525 [TDT4] = igb_set_tdt,
3526 [TDT5] = igb_set_tdt,
3527 [TDT6] = igb_set_tdt,
3528 [TDT7] = igb_set_tdt,
3529 [TDT8] = igb_set_tdt,
3530 [TDT9] = igb_set_tdt,
3531 [TDT10] = igb_set_tdt,
3532 [TDT11] = igb_set_tdt,
3533 [TDT12] = igb_set_tdt,
3534 [TDT13] = igb_set_tdt,
3535 [TDT14] = igb_set_tdt,
3536 [TDT15] = igb_set_tdt,
3537 [MDIC] = igb_set_mdic,
3538 [ICS] = igb_set_ics,
3539 [RDH0] = igb_set_16bit,
3540 [RDH1] = igb_set_16bit,
3541 [RDH2] = igb_set_16bit,
3542 [RDH3] = igb_set_16bit,
3543 [RDH4] = igb_set_16bit,
3544 [RDH5] = igb_set_16bit,
3545 [RDH6] = igb_set_16bit,
3546 [RDH7] = igb_set_16bit,
3547 [RDH8] = igb_set_16bit,
3548 [RDH9] = igb_set_16bit,
3549 [RDH10] = igb_set_16bit,
3550 [RDH11] = igb_set_16bit,
3551 [RDH12] = igb_set_16bit,
3552 [RDH13] = igb_set_16bit,
3553 [RDH14] = igb_set_16bit,
3554 [RDH15] = igb_set_16bit,
3555 [RDT0] = igb_set_rdt,
3556 [RDT1] = igb_set_rdt,
3557 [RDT2] = igb_set_rdt,
3558 [RDT3] = igb_set_rdt,
3559 [RDT4] = igb_set_rdt,
3560 [RDT5] = igb_set_rdt,
3561 [RDT6] = igb_set_rdt,
3562 [RDT7] = igb_set_rdt,
3563 [RDT8] = igb_set_rdt,
3564 [RDT9] = igb_set_rdt,
3565 [RDT10] = igb_set_rdt,
3566 [RDT11] = igb_set_rdt,
3567 [RDT12] = igb_set_rdt,
3568 [RDT13] = igb_set_rdt,
3569 [RDT14] = igb_set_rdt,
3570 [RDT15] = igb_set_rdt,
3571 [IMC] = igb_set_imc,
3572 [IMS] = igb_set_ims,
3573 [ICR] = igb_set_icr,
3574 [EECD] = igb_set_eecd,
3575 [RCTL] = igb_set_rx_control,
3576 [CTRL] = igb_set_ctrl,
3577 [EERD] = igb_set_eerd,
3578 [TDFH] = igb_set_13bit,
3579 [TDFT] = igb_set_13bit,
3580 [TDFHS] = igb_set_13bit,
3581 [TDFTS] = igb_set_13bit,
3582 [TDFPC] = igb_set_13bit,
3583 [RDFH] = igb_set_13bit,
3584 [RDFT] = igb_set_13bit,
3585 [RDFHS] = igb_set_13bit,
3586 [RDFTS] = igb_set_13bit,
3587 [RDFPC] = igb_set_13bit,
3588 [GCR] = igb_set_gcr,
3589 [RXCSUM] = igb_set_rxcsum,
3590 [TDLEN0] = igb_set_dlen,
3591 [TDLEN1] = igb_set_dlen,
3592 [TDLEN2] = igb_set_dlen,
3593 [TDLEN3] = igb_set_dlen,
3594 [TDLEN4] = igb_set_dlen,
3595 [TDLEN5] = igb_set_dlen,
3596 [TDLEN6] = igb_set_dlen,
3597 [TDLEN7] = igb_set_dlen,
3598 [TDLEN8] = igb_set_dlen,
3599 [TDLEN9] = igb_set_dlen,
3600 [TDLEN10] = igb_set_dlen,
3601 [TDLEN11] = igb_set_dlen,
3602 [TDLEN12] = igb_set_dlen,
3603 [TDLEN13] = igb_set_dlen,
3604 [TDLEN14] = igb_set_dlen,
3605 [TDLEN15] = igb_set_dlen,
3606 [RDLEN0] = igb_set_dlen,
3607 [RDLEN1] = igb_set_dlen,
3608 [RDLEN2] = igb_set_dlen,
3609 [RDLEN3] = igb_set_dlen,
3610 [RDLEN4] = igb_set_dlen,
3611 [RDLEN5] = igb_set_dlen,
3612 [RDLEN6] = igb_set_dlen,
3613 [RDLEN7] = igb_set_dlen,
3614 [RDLEN8] = igb_set_dlen,
3615 [RDLEN9] = igb_set_dlen,
3616 [RDLEN10] = igb_set_dlen,
3617 [RDLEN11] = igb_set_dlen,
3618 [RDLEN12] = igb_set_dlen,
3619 [RDLEN13] = igb_set_dlen,
3620 [RDLEN14] = igb_set_dlen,
3621 [RDLEN15] = igb_set_dlen,
3622 [TDBAL0] = igb_set_dbal,
3623 [TDBAL1] = igb_set_dbal,
3624 [TDBAL2] = igb_set_dbal,
3625 [TDBAL3] = igb_set_dbal,
3626 [TDBAL4] = igb_set_dbal,
3627 [TDBAL5] = igb_set_dbal,
3628 [TDBAL6] = igb_set_dbal,
3629 [TDBAL7] = igb_set_dbal,
3630 [TDBAL8] = igb_set_dbal,
3631 [TDBAL9] = igb_set_dbal,
3632 [TDBAL10] = igb_set_dbal,
3633 [TDBAL11] = igb_set_dbal,
3634 [TDBAL12] = igb_set_dbal,
3635 [TDBAL13] = igb_set_dbal,
3636 [TDBAL14] = igb_set_dbal,
3637 [TDBAL15] = igb_set_dbal,
3638 [RDBAL0] = igb_set_dbal,
3639 [RDBAL1] = igb_set_dbal,
3640 [RDBAL2] = igb_set_dbal,
3641 [RDBAL3] = igb_set_dbal,
3642 [RDBAL4] = igb_set_dbal,
3643 [RDBAL5] = igb_set_dbal,
3644 [RDBAL6] = igb_set_dbal,
3645 [RDBAL7] = igb_set_dbal,
3646 [RDBAL8] = igb_set_dbal,
3647 [RDBAL9] = igb_set_dbal,
3648 [RDBAL10] = igb_set_dbal,
3649 [RDBAL11] = igb_set_dbal,
3650 [RDBAL12] = igb_set_dbal,
3651 [RDBAL13] = igb_set_dbal,
3652 [RDBAL14] = igb_set_dbal,
3653 [RDBAL15] = igb_set_dbal,
3654 [STATUS] = igb_set_status,
3655 [PBACLR] = igb_set_pbaclr,
3656 [CTRL_EXT] = igb_set_ctrlext,
3657 [FCAH] = igb_set_16bit,
3658 [FCT] = igb_set_16bit,
3659 [FCTTV] = igb_set_16bit,
3660 [FCRTV] = igb_set_16bit,
3661 [FCRTH] = igb_set_fcrth,
3662 [FCRTL] = igb_set_fcrtl,
3663 [CTRL_DUP] = igb_set_ctrl,
3664 [RFCTL] = igb_set_rfctl,
3665 [TIMINCA] = igb_set_timinca,
3666 [TIMADJH] = igb_set_timadjh,
3667
3668 [IP6AT ... IP6AT + 3] = igb_mac_writereg,
3669 [IP4AT ... IP4AT + 6] = igb_mac_writereg,
3670 [RA] = igb_mac_writereg,
3671 [RA + 1] = igb_mac_setmacaddr,
3672 [RA + 2 ... RA + 31] = igb_mac_writereg,
3673 [RA2 ... RA2 + 31] = igb_mac_writereg,
3674 [WUPM ... WUPM + 31] = igb_mac_writereg,
3675 [MTA ... MTA + E1000_MC_TBL_SIZE - 1] = igb_mac_writereg,
3676 [VFTA ... VFTA + E1000_VLAN_FILTER_TBL_SIZE - 1] = igb_mac_writereg,
3677 [FFMT ... FFMT + 254] = igb_set_4bit,
3678 [MDEF ... MDEF + 7] = igb_mac_writereg,
3679 [FTFT ... FTFT + 254] = igb_mac_writereg,
3680 [RETA ... RETA + 31] = igb_mac_writereg,
3681 [RSSRK ... RSSRK + 9] = igb_mac_writereg,
3682 [MAVTV0 ... MAVTV3] = igb_mac_writereg,
3683 [EITR0 ... EITR0 + IGB_INTR_NUM - 1] = igb_set_eitr,
3684
3685 /* IGB specific: */
3686 [FWSM] = igb_mac_writereg,
3687 [SW_FW_SYNC] = igb_mac_writereg,
3688 [EICR] = igb_set_eicr,
3689 [EICS] = igb_set_eics,
3690 [EIAC] = igb_set_eiac,
3691 [EIAM] = igb_set_eiam,
3692 [EIMC] = igb_set_eimc,
3693 [EIMS] = igb_set_eims,
3694 [IVAR0 ... IVAR0 + 7] = igb_mac_writereg,
3695 igb_putreg(IVAR_MISC),
3696 igb_putreg(VT_CTL),
3697 [P2VMAILBOX0 ... P2VMAILBOX7] = igb_set_pfmailbox,
3698 [V2PMAILBOX0 ... V2PMAILBOX7] = igb_set_vfmailbox,
3699 [MBVFICR] = igb_w1c,
3700 [VMBMEM0 ... VMBMEM0 + 127] = igb_mac_writereg,
3701 igb_putreg(MBVFIMR),
3702 [VFLRE] = igb_w1c,
3703 igb_putreg(VFRE),
3704 igb_putreg(VFTE),
3705 igb_putreg(QDE),
3706 igb_putreg(DTXSWC),
3707 igb_putreg(RPLOLR),
3708 [VLVF0 ... VLVF0 + E1000_VLVF_ARRAY_SIZE - 1] = igb_mac_writereg,
3709 [VMVIR0 ... VMVIR7] = igb_mac_writereg,
3710 [VMOLR0 ... VMOLR7] = igb_mac_writereg,
3711 [UTA ... UTA + E1000_MC_TBL_SIZE - 1] = igb_mac_writereg,
3712 [PVTCTRL0] = igb_set_vtctrl,
3713 [PVTCTRL1] = igb_set_vtctrl,
3714 [PVTCTRL2] = igb_set_vtctrl,
3715 [PVTCTRL3] = igb_set_vtctrl,
3716 [PVTCTRL4] = igb_set_vtctrl,
3717 [PVTCTRL5] = igb_set_vtctrl,
3718 [PVTCTRL6] = igb_set_vtctrl,
3719 [PVTCTRL7] = igb_set_vtctrl,
3720 [PVTEICS0] = igb_set_vteics,
3721 [PVTEICS1] = igb_set_vteics,
3722 [PVTEICS2] = igb_set_vteics,
3723 [PVTEICS3] = igb_set_vteics,
3724 [PVTEICS4] = igb_set_vteics,
3725 [PVTEICS5] = igb_set_vteics,
3726 [PVTEICS6] = igb_set_vteics,
3727 [PVTEICS7] = igb_set_vteics,
3728 [PVTEIMS0] = igb_set_vteims,
3729 [PVTEIMS1] = igb_set_vteims,
3730 [PVTEIMS2] = igb_set_vteims,
3731 [PVTEIMS3] = igb_set_vteims,
3732 [PVTEIMS4] = igb_set_vteims,
3733 [PVTEIMS5] = igb_set_vteims,
3734 [PVTEIMS6] = igb_set_vteims,
3735 [PVTEIMS7] = igb_set_vteims,
3736 [PVTEIMC0] = igb_set_vteimc,
3737 [PVTEIMC1] = igb_set_vteimc,
3738 [PVTEIMC2] = igb_set_vteimc,
3739 [PVTEIMC3] = igb_set_vteimc,
3740 [PVTEIMC4] = igb_set_vteimc,
3741 [PVTEIMC5] = igb_set_vteimc,
3742 [PVTEIMC6] = igb_set_vteimc,
3743 [PVTEIMC7] = igb_set_vteimc,
3744 [PVTEIAC0] = igb_set_vteiac,
3745 [PVTEIAC1] = igb_set_vteiac,
3746 [PVTEIAC2] = igb_set_vteiac,
3747 [PVTEIAC3] = igb_set_vteiac,
3748 [PVTEIAC4] = igb_set_vteiac,
3749 [PVTEIAC5] = igb_set_vteiac,
3750 [PVTEIAC6] = igb_set_vteiac,
3751 [PVTEIAC7] = igb_set_vteiac,
3752 [PVTEIAM0] = igb_set_vteiam,
3753 [PVTEIAM1] = igb_set_vteiam,
3754 [PVTEIAM2] = igb_set_vteiam,
3755 [PVTEIAM3] = igb_set_vteiam,
3756 [PVTEIAM4] = igb_set_vteiam,
3757 [PVTEIAM5] = igb_set_vteiam,
3758 [PVTEIAM6] = igb_set_vteiam,
3759 [PVTEIAM7] = igb_set_vteiam,
3760 [PVTEICR0] = igb_set_vteicr,
3761 [PVTEICR1] = igb_set_vteicr,
3762 [PVTEICR2] = igb_set_vteicr,
3763 [PVTEICR3] = igb_set_vteicr,
3764 [PVTEICR4] = igb_set_vteicr,
3765 [PVTEICR5] = igb_set_vteicr,
3766 [PVTEICR6] = igb_set_vteicr,
3767 [PVTEICR7] = igb_set_vteicr,
3768 [VTIVAR ... VTIVAR + 7] = igb_set_vtivar,
3769 [VTIVAR_MISC ... VTIVAR_MISC + 7] = igb_mac_writereg
3770 };
3771 enum { IGB_NWRITEOPS = ARRAY_SIZE(igb_macreg_writeops) };
3772
3773 enum { MAC_ACCESS_PARTIAL = 1 };
3774
3775 /*
3776 * The array below combines alias offsets of the index values for the
3777 * MAC registers that have aliases, with the indication of not fully
3778 * implemented registers (lowest bit). This combination is possible
3779 * because all of the offsets are even.
3780 */
3781 static const uint16_t mac_reg_access[E1000E_MAC_SIZE] = {
3782 /* Alias index offsets */
3783 [FCRTL_A] = 0x07fe,
3784 [RDFH_A] = 0xe904, [RDFT_A] = 0xe904,
3785 [TDFH_A] = 0xed00, [TDFT_A] = 0xed00,
3786 [RA_A ... RA_A + 31] = 0x14f0,
3787 [VFTA_A ... VFTA_A + E1000_VLAN_FILTER_TBL_SIZE - 1] = 0x1400,
3788
3789 [RDBAL0_A] = 0x2600,
3790 [RDBAH0_A] = 0x2600,
3791 [RDLEN0_A] = 0x2600,
3792 [SRRCTL0_A] = 0x2600,
3793 [RDH0_A] = 0x2600,
3794 [RDT0_A] = 0x2600,
3795 [RXDCTL0_A] = 0x2600,
3796 [RXCTL0_A] = 0x2600,
3797 [RQDPC0_A] = 0x2600,
3798 [RDBAL1_A] = 0x25D0,
3799 [RDBAL2_A] = 0x25A0,
3800 [RDBAL3_A] = 0x2570,
3801 [RDBAH1_A] = 0x25D0,
3802 [RDBAH2_A] = 0x25A0,
3803 [RDBAH3_A] = 0x2570,
3804 [RDLEN1_A] = 0x25D0,
3805 [RDLEN2_A] = 0x25A0,
3806 [RDLEN3_A] = 0x2570,
3807 [SRRCTL1_A] = 0x25D0,
3808 [SRRCTL2_A] = 0x25A0,
3809 [SRRCTL3_A] = 0x2570,
3810 [RDH1_A] = 0x25D0,
3811 [RDH2_A] = 0x25A0,
3812 [RDH3_A] = 0x2570,
3813 [RDT1_A] = 0x25D0,
3814 [RDT2_A] = 0x25A0,
3815 [RDT3_A] = 0x2570,
3816 [RXDCTL1_A] = 0x25D0,
3817 [RXDCTL2_A] = 0x25A0,
3818 [RXDCTL3_A] = 0x2570,
3819 [RXCTL1_A] = 0x25D0,
3820 [RXCTL2_A] = 0x25A0,
3821 [RXCTL3_A] = 0x2570,
3822 [RQDPC1_A] = 0x25D0,
3823 [RQDPC2_A] = 0x25A0,
3824 [RQDPC3_A] = 0x2570,
3825 [TDBAL0_A] = 0x2A00,
3826 [TDBAH0_A] = 0x2A00,
3827 [TDLEN0_A] = 0x2A00,
3828 [TDH0_A] = 0x2A00,
3829 [TDT0_A] = 0x2A00,
3830 [TXCTL0_A] = 0x2A00,
3831 [TDWBAL0_A] = 0x2A00,
3832 [TDWBAH0_A] = 0x2A00,
3833 [TDBAL1_A] = 0x29D0,
3834 [TDBAL2_A] = 0x29A0,
3835 [TDBAL3_A] = 0x2970,
3836 [TDBAH1_A] = 0x29D0,
3837 [TDBAH2_A] = 0x29A0,
3838 [TDBAH3_A] = 0x2970,
3839 [TDLEN1_A] = 0x29D0,
3840 [TDLEN2_A] = 0x29A0,
3841 [TDLEN3_A] = 0x2970,
3842 [TDH1_A] = 0x29D0,
3843 [TDH2_A] = 0x29A0,
3844 [TDH3_A] = 0x2970,
3845 [TDT1_A] = 0x29D0,
3846 [TDT2_A] = 0x29A0,
3847 [TDT3_A] = 0x2970,
3848 [TXDCTL0_A] = 0x2A00,
3849 [TXDCTL1_A] = 0x29D0,
3850 [TXDCTL2_A] = 0x29A0,
3851 [TXDCTL3_A] = 0x2970,
3852 [TXCTL1_A] = 0x29D0,
3853 [TXCTL2_A] = 0x29A0,
3854 [TXCTL3_A] = 0x29D0,
3855 [TDWBAL1_A] = 0x29D0,
3856 [TDWBAL2_A] = 0x29A0,
3857 [TDWBAL3_A] = 0x2970,
3858 [TDWBAH1_A] = 0x29D0,
3859 [TDWBAH2_A] = 0x29A0,
3860 [TDWBAH3_A] = 0x2970,
3861
3862 /* Access options */
3863 [RDFH] = MAC_ACCESS_PARTIAL, [RDFT] = MAC_ACCESS_PARTIAL,
3864 [RDFHS] = MAC_ACCESS_PARTIAL, [RDFTS] = MAC_ACCESS_PARTIAL,
3865 [RDFPC] = MAC_ACCESS_PARTIAL,
3866 [TDFH] = MAC_ACCESS_PARTIAL, [TDFT] = MAC_ACCESS_PARTIAL,
3867 [TDFHS] = MAC_ACCESS_PARTIAL, [TDFTS] = MAC_ACCESS_PARTIAL,
3868 [TDFPC] = MAC_ACCESS_PARTIAL, [EECD] = MAC_ACCESS_PARTIAL,
3869 [FLA] = MAC_ACCESS_PARTIAL,
3870 [FCAL] = MAC_ACCESS_PARTIAL, [FCAH] = MAC_ACCESS_PARTIAL,
3871 [FCT] = MAC_ACCESS_PARTIAL, [FCTTV] = MAC_ACCESS_PARTIAL,
3872 [FCRTV] = MAC_ACCESS_PARTIAL, [FCRTL] = MAC_ACCESS_PARTIAL,
3873 [FCRTH] = MAC_ACCESS_PARTIAL,
3874 [MAVTV0 ... MAVTV3] = MAC_ACCESS_PARTIAL
3875 };
3876
3877 void
3878 igb_core_write(IGBCore *core, hwaddr addr, uint64_t val, unsigned size)
3879 {
3880 uint16_t index = igb_get_reg_index_with_offset(mac_reg_access, addr);
3881
3882 if (index < IGB_NWRITEOPS && igb_macreg_writeops[index]) {
3883 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) {
3884 trace_e1000e_wrn_regs_write_trivial(index << 2);
3885 }
3886 trace_e1000e_core_write(index << 2, size, val);
3887 igb_macreg_writeops[index](core, index, val);
3888 } else if (index < IGB_NREADOPS && igb_macreg_readops[index]) {
3889 trace_e1000e_wrn_regs_write_ro(index << 2, size, val);
3890 } else {
3891 trace_e1000e_wrn_regs_write_unknown(index << 2, size, val);
3892 }
3893 }
3894
3895 uint64_t
3896 igb_core_read(IGBCore *core, hwaddr addr, unsigned size)
3897 {
3898 uint64_t val;
3899 uint16_t index = igb_get_reg_index_with_offset(mac_reg_access, addr);
3900
3901 if (index < IGB_NREADOPS && igb_macreg_readops[index]) {
3902 if (mac_reg_access[index] & MAC_ACCESS_PARTIAL) {
3903 trace_e1000e_wrn_regs_read_trivial(index << 2);
3904 }
3905 val = igb_macreg_readops[index](core, index);
3906 trace_e1000e_core_read(index << 2, size, val);
3907 return val;
3908 } else {
3909 trace_e1000e_wrn_regs_read_unknown(index << 2, size);
3910 }
3911 return 0;
3912 }
3913
3914 static inline void
3915 igb_autoneg_pause(IGBCore *core)
3916 {
3917 timer_del(core->autoneg_timer);
3918 }
3919
3920 static void
3921 igb_autoneg_resume(IGBCore *core)
3922 {
3923 if (igb_have_autoneg(core) &&
3924 !(core->phy[MII_BMSR] & MII_BMSR_AN_COMP)) {
3925 qemu_get_queue(core->owner_nic)->link_down = false;
3926 timer_mod(core->autoneg_timer,
3927 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 500);
3928 }
3929 }
3930
3931 static void
3932 igb_vm_state_change(void *opaque, bool running, RunState state)
3933 {
3934 IGBCore *core = opaque;
3935
3936 if (running) {
3937 trace_e1000e_vm_state_running();
3938 igb_intrmgr_resume(core);
3939 igb_autoneg_resume(core);
3940 } else {
3941 trace_e1000e_vm_state_stopped();
3942 igb_autoneg_pause(core);
3943 igb_intrmgr_pause(core);
3944 }
3945 }
3946
3947 void
3948 igb_core_pci_realize(IGBCore *core,
3949 const uint16_t *eeprom_templ,
3950 uint32_t eeprom_size,
3951 const uint8_t *macaddr)
3952 {
3953 int i;
3954
3955 core->autoneg_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL,
3956 igb_autoneg_timer, core);
3957 igb_intrmgr_pci_realize(core);
3958
3959 core->vmstate = qemu_add_vm_change_state_handler(igb_vm_state_change, core);
3960
3961 for (i = 0; i < IGB_NUM_QUEUES; i++) {
3962 net_tx_pkt_init(&core->tx[i].tx_pkt, E1000E_MAX_TX_FRAGS);
3963 }
3964
3965 net_rx_pkt_init(&core->rx_pkt);
3966
3967 e1000x_core_prepare_eeprom(core->eeprom,
3968 eeprom_templ,
3969 eeprom_size,
3970 PCI_DEVICE_GET_CLASS(core->owner)->device_id,
3971 macaddr);
3972 igb_update_rx_offloads(core);
3973 }
3974
3975 void
3976 igb_core_pci_uninit(IGBCore *core)
3977 {
3978 int i;
3979
3980 timer_free(core->autoneg_timer);
3981
3982 igb_intrmgr_pci_unint(core);
3983
3984 qemu_del_vm_change_state_handler(core->vmstate);
3985
3986 for (i = 0; i < IGB_NUM_QUEUES; i++) {
3987 net_tx_pkt_uninit(core->tx[i].tx_pkt);
3988 }
3989
3990 net_rx_pkt_uninit(core->rx_pkt);
3991 }
3992
3993 static const uint16_t
3994 igb_phy_reg_init[] = {
3995 [MII_BMCR] = MII_BMCR_SPEED1000 |
3996 MII_BMCR_FD |
3997 MII_BMCR_AUTOEN,
3998
3999 [MII_BMSR] = MII_BMSR_EXTCAP |
4000 MII_BMSR_LINK_ST |
4001 MII_BMSR_AUTONEG |
4002 MII_BMSR_MFPS |
4003 MII_BMSR_EXTSTAT |
4004 MII_BMSR_10T_HD |
4005 MII_BMSR_10T_FD |
4006 MII_BMSR_100TX_HD |
4007 MII_BMSR_100TX_FD,
4008
4009 [MII_PHYID1] = IGP03E1000_E_PHY_ID >> 16,
4010 [MII_PHYID2] = (IGP03E1000_E_PHY_ID & 0xfff0) | 1,
4011 [MII_ANAR] = MII_ANAR_CSMACD | MII_ANAR_10 |
4012 MII_ANAR_10FD | MII_ANAR_TX |
4013 MII_ANAR_TXFD | MII_ANAR_PAUSE |
4014 MII_ANAR_PAUSE_ASYM,
4015 [MII_ANLPAR] = MII_ANLPAR_10 | MII_ANLPAR_10FD |
4016 MII_ANLPAR_TX | MII_ANLPAR_TXFD |
4017 MII_ANLPAR_T4 | MII_ANLPAR_PAUSE,
4018 [MII_ANER] = MII_ANER_NP | MII_ANER_NWAY,
4019 [MII_ANNP] = 0x1 | MII_ANNP_MP,
4020 [MII_CTRL1000] = MII_CTRL1000_HALF | MII_CTRL1000_FULL |
4021 MII_CTRL1000_PORT | MII_CTRL1000_MASTER,
4022 [MII_STAT1000] = MII_STAT1000_HALF | MII_STAT1000_FULL |
4023 MII_STAT1000_ROK | MII_STAT1000_LOK,
4024 [MII_EXTSTAT] = MII_EXTSTAT_1000T_HD | MII_EXTSTAT_1000T_FD,
4025
4026 [IGP01E1000_PHY_PORT_CONFIG] = BIT(5) | BIT(8),
4027 [IGP01E1000_PHY_PORT_STATUS] = IGP01E1000_PSSR_SPEED_1000MBPS,
4028 [IGP02E1000_PHY_POWER_MGMT] = BIT(0) | BIT(3) | IGP02E1000_PM_D3_LPLU |
4029 IGP01E1000_PSCFR_SMART_SPEED
4030 };
4031
4032 static const uint32_t igb_mac_reg_init[] = {
4033 [LEDCTL] = 2 | (3 << 8) | BIT(15) | (6 << 16) | (7 << 24),
4034 [EEMNGCTL] = BIT(31),
4035 [TXDCTL0] = E1000_TXDCTL_QUEUE_ENABLE,
4036 [RXDCTL0] = E1000_RXDCTL_QUEUE_ENABLE | (1 << 16),
4037 [RXDCTL1] = 1 << 16,
4038 [RXDCTL2] = 1 << 16,
4039 [RXDCTL3] = 1 << 16,
4040 [RXDCTL4] = 1 << 16,
4041 [RXDCTL5] = 1 << 16,
4042 [RXDCTL6] = 1 << 16,
4043 [RXDCTL7] = 1 << 16,
4044 [RXDCTL8] = 1 << 16,
4045 [RXDCTL9] = 1 << 16,
4046 [RXDCTL10] = 1 << 16,
4047 [RXDCTL11] = 1 << 16,
4048 [RXDCTL12] = 1 << 16,
4049 [RXDCTL13] = 1 << 16,
4050 [RXDCTL14] = 1 << 16,
4051 [RXDCTL15] = 1 << 16,
4052 [TIPG] = 0x08 | (0x04 << 10) | (0x06 << 20),
4053 [CTRL] = E1000_CTRL_FD | E1000_CTRL_LRST | E1000_CTRL_SPD_1000 |
4054 E1000_CTRL_ADVD3WUC,
4055 [STATUS] = E1000_STATUS_PHYRA | BIT(31),
4056 [EECD] = E1000_EECD_FWE_DIS | E1000_EECD_PRES |
4057 (2 << E1000_EECD_SIZE_EX_SHIFT),
4058 [GCR] = E1000_L0S_ADJUST |
4059 E1000_GCR_CMPL_TMOUT_RESEND |
4060 E1000_GCR_CAP_VER2 |
4061 E1000_L1_ENTRY_LATENCY_MSB |
4062 E1000_L1_ENTRY_LATENCY_LSB,
4063 [RXCSUM] = E1000_RXCSUM_IPOFLD | E1000_RXCSUM_TUOFLD,
4064 [TXPBS] = 0x28,
4065 [RXPBS] = 0x40,
4066 [TCTL] = E1000_TCTL_PSP | (0xF << E1000_CT_SHIFT) |
4067 (0x40 << E1000_COLD_SHIFT) | (0x1 << 26) | (0xA << 28),
4068 [TCTL_EXT] = 0x40 | (0x42 << 10),
4069 [DTXCTL] = E1000_DTXCTL_8023LL | E1000_DTXCTL_SPOOF_INT,
4070 [VET] = ETH_P_VLAN | (ETH_P_VLAN << 16),
4071
4072 [V2PMAILBOX0 ... V2PMAILBOX0 + IGB_MAX_VF_FUNCTIONS - 1] = E1000_V2PMAILBOX_RSTI,
4073 [MBVFIMR] = 0xFF,
4074 [VFRE] = 0xFF,
4075 [VFTE] = 0xFF,
4076 [VMOLR0 ... VMOLR0 + 7] = 0x2600 | E1000_VMOLR_STRCRC,
4077 [RPLOLR] = E1000_RPLOLR_STRCRC,
4078 [RLPML] = 0x2600,
4079 [TXCTL0] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4080 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4081 E1000_DCA_TXCTRL_DESC_RRO_EN,
4082 [TXCTL1] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4083 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4084 E1000_DCA_TXCTRL_DESC_RRO_EN,
4085 [TXCTL2] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4086 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4087 E1000_DCA_TXCTRL_DESC_RRO_EN,
4088 [TXCTL3] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4089 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4090 E1000_DCA_TXCTRL_DESC_RRO_EN,
4091 [TXCTL4] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4092 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4093 E1000_DCA_TXCTRL_DESC_RRO_EN,
4094 [TXCTL5] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4095 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4096 E1000_DCA_TXCTRL_DESC_RRO_EN,
4097 [TXCTL6] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4098 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4099 E1000_DCA_TXCTRL_DESC_RRO_EN,
4100 [TXCTL7] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4101 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4102 E1000_DCA_TXCTRL_DESC_RRO_EN,
4103 [TXCTL8] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4104 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4105 E1000_DCA_TXCTRL_DESC_RRO_EN,
4106 [TXCTL9] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4107 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4108 E1000_DCA_TXCTRL_DESC_RRO_EN,
4109 [TXCTL10] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4110 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4111 E1000_DCA_TXCTRL_DESC_RRO_EN,
4112 [TXCTL11] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4113 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4114 E1000_DCA_TXCTRL_DESC_RRO_EN,
4115 [TXCTL12] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4116 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4117 E1000_DCA_TXCTRL_DESC_RRO_EN,
4118 [TXCTL13] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4119 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4120 E1000_DCA_TXCTRL_DESC_RRO_EN,
4121 [TXCTL14] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4122 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4123 E1000_DCA_TXCTRL_DESC_RRO_EN,
4124 [TXCTL15] = E1000_DCA_TXCTRL_DATA_RRO_EN |
4125 E1000_DCA_TXCTRL_TX_WB_RO_EN |
4126 E1000_DCA_TXCTRL_DESC_RRO_EN,
4127 };
4128
4129 static void igb_reset(IGBCore *core, bool sw)
4130 {
4131 struct igb_tx *tx;
4132 int i;
4133
4134 timer_del(core->autoneg_timer);
4135
4136 igb_intrmgr_reset(core);
4137
4138 memset(core->phy, 0, sizeof core->phy);
4139 memcpy(core->phy, igb_phy_reg_init, sizeof igb_phy_reg_init);
4140
4141 for (i = 0; i < E1000E_MAC_SIZE; i++) {
4142 if (sw &&
4143 (i == RXPBS || i == TXPBS ||
4144 (i >= EITR0 && i < EITR0 + IGB_INTR_NUM))) {
4145 continue;
4146 }
4147
4148 core->mac[i] = i < ARRAY_SIZE(igb_mac_reg_init) ?
4149 igb_mac_reg_init[i] : 0;
4150 }
4151
4152 if (qemu_get_queue(core->owner_nic)->link_down) {
4153 igb_link_down(core);
4154 }
4155
4156 e1000x_reset_mac_addr(core->owner_nic, core->mac, core->permanent_mac);
4157
4158 for (int vfn = 0; vfn < IGB_MAX_VF_FUNCTIONS; vfn++) {
4159 /* Set RSTI, so VF can identify a PF reset is in progress */
4160 core->mac[V2PMAILBOX0 + vfn] |= E1000_V2PMAILBOX_RSTI;
4161 }
4162
4163 for (i = 0; i < ARRAY_SIZE(core->tx); i++) {
4164 tx = &core->tx[i];
4165 memset(tx->ctx, 0, sizeof(tx->ctx));
4166 tx->first = true;
4167 tx->skip_cp = false;
4168 }
4169 }
4170
4171 void
4172 igb_core_reset(IGBCore *core)
4173 {
4174 igb_reset(core, false);
4175 }
4176
4177 void igb_core_pre_save(IGBCore *core)
4178 {
4179 int i;
4180 NetClientState *nc = qemu_get_queue(core->owner_nic);
4181
4182 /*
4183 * If link is down and auto-negotiation is supported and ongoing,
4184 * complete auto-negotiation immediately. This allows us to look
4185 * at MII_BMSR_AN_COMP to infer link status on load.
4186 */
4187 if (nc->link_down && igb_have_autoneg(core)) {
4188 core->phy[MII_BMSR] |= MII_BMSR_AN_COMP;
4189 igb_update_flowctl_status(core);
4190 }
4191
4192 for (i = 0; i < ARRAY_SIZE(core->tx); i++) {
4193 if (net_tx_pkt_has_fragments(core->tx[i].tx_pkt)) {
4194 core->tx[i].skip_cp = true;
4195 }
4196 }
4197 }
4198
4199 int
4200 igb_core_post_load(IGBCore *core)
4201 {
4202 NetClientState *nc = qemu_get_queue(core->owner_nic);
4203
4204 /*
4205 * nc.link_down can't be migrated, so infer link_down according
4206 * to link status bit in core.mac[STATUS].
4207 */
4208 nc->link_down = (core->mac[STATUS] & E1000_STATUS_LU) == 0;
4209
4210 return 0;
4211 }
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