hw/net/mcf_fec.c

   1 /*
   2  * ColdFire Fast Ethernet Controller emulation.
   3  *
   4  * Copyright (c) 2007 CodeSourcery.
   5  *
   6  * This code is licensed under the GPL
   7  */
   8
   9 #include "qemu/osdep.h"
  10 #include "hw/hw.h"
  11 #include "hw/irq.h"
  12 #include "net/net.h"
  13 #include "qemu/module.h"
  14 #include "hw/m68k/mcf.h"
  15 #include "hw/m68k/mcf_fec.h"
  16 #include "hw/net/mii.h"
  17 #include "hw/sysbus.h"
  18 /* For crc32 */
  19 #include <zlib.h>
  20
  21 //#define DEBUG_FEC 1
  22
  23 #ifdef DEBUG_FEC
  24 #define DPRINTF(fmt, ...) \
  25 do { printf("mcf_fec: " fmt , ## __VA_ARGS__); } while (0)
  26 #else
  27 #define DPRINTF(fmt, ...) do {} while(0)
  28 #endif
  29
  30 #define FEC_MAX_DESC 1024
  31 #define FEC_MAX_FRAME_SIZE 2032
  32 #define FEC_MIB_SIZE 64
  33
  34 typedef struct {
  35     SysBusDevice parent_obj;
  36
  37     MemoryRegion iomem;
  38     qemu_irq irq[FEC_NUM_IRQ];
  39     NICState *nic;
  40     NICConf conf;
  41     uint32_t irq_state;
  42     uint32_t eir;
  43     uint32_t eimr;
  44     int rx_enabled;
  45     uint32_t rx_descriptor;
  46     uint32_t tx_descriptor;
  47     uint32_t ecr;
  48     uint32_t mmfr;
  49     uint32_t mscr;
  50     uint32_t rcr;
  51     uint32_t tcr;
  52     uint32_t tfwr;
  53     uint32_t rfsr;
  54     uint32_t erdsr;
  55     uint32_t etdsr;
  56     uint32_t emrbr;
  57     uint32_t mib[FEC_MIB_SIZE];
  58 } mcf_fec_state;
  59
  60 #define FEC_INT_HB   0x80000000
  61 #define FEC_INT_BABR 0x40000000
  62 #define FEC_INT_BABT 0x20000000
  63 #define FEC_INT_GRA  0x10000000
  64 #define FEC_INT_TXF  0x08000000
  65 #define FEC_INT_TXB  0x04000000
  66 #define FEC_INT_RXF  0x02000000
  67 #define FEC_INT_RXB  0x01000000
  68 #define FEC_INT_MII  0x00800000
  69 #define FEC_INT_EB   0x00400000
  70 #define FEC_INT_LC   0x00200000
  71 #define FEC_INT_RL   0x00100000
  72 #define FEC_INT_UN   0x00080000
  73
  74 #define FEC_EN      2
  75 #define FEC_RESET   1
  76
  77 /* Map interrupt flags onto IRQ lines.  */
  78 static const uint32_t mcf_fec_irq_map[FEC_NUM_IRQ] = {
  79     FEC_INT_TXF,
  80     FEC_INT_TXB,
  81     FEC_INT_UN,
  82     FEC_INT_RL,
  83     FEC_INT_RXF,
  84     FEC_INT_RXB,
  85     FEC_INT_MII,
  86     FEC_INT_LC,
  87     FEC_INT_HB,
  88     FEC_INT_GRA,
  89     FEC_INT_EB,
  90     FEC_INT_BABT,
  91     FEC_INT_BABR
  92 };
  93
  94 /* Buffer Descriptor.  */
  95 typedef struct {
  96     uint16_t flags;
  97     uint16_t length;
  98     uint32_t data;
  99 } mcf_fec_bd;
 100
 101 #define FEC_BD_R    0x8000
 102 #define FEC_BD_E    0x8000
 103 #define FEC_BD_O1   0x4000
 104 #define FEC_BD_W    0x2000
 105 #define FEC_BD_O2   0x1000
 106 #define FEC_BD_L    0x0800
 107 #define FEC_BD_TC   0x0400
 108 #define FEC_BD_ABC  0x0200
 109 #define FEC_BD_M    0x0100
 110 #define FEC_BD_BC   0x0080
 111 #define FEC_BD_MC   0x0040
 112 #define FEC_BD_LG   0x0020
 113 #define FEC_BD_NO   0x0010
 114 #define FEC_BD_CR   0x0004
 115 #define FEC_BD_OV   0x0002
 116 #define FEC_BD_TR   0x0001
 117
 118 #define MIB_RMON_T_DROP         0
 119 #define MIB_RMON_T_PACKETS      1
 120 #define MIB_RMON_T_BC_PKT       2
 121 #define MIB_RMON_T_MC_PKT       3
 122 #define MIB_RMON_T_CRC_ALIGN    4
 123 #define MIB_RMON_T_UNDERSIZE    5
 124 #define MIB_RMON_T_OVERSIZE     6
 125 #define MIB_RMON_T_FRAG         7
 126 #define MIB_RMON_T_JAB          8
 127 #define MIB_RMON_T_COL          9
 128 #define MIB_RMON_T_P64          10
 129 #define MIB_RMON_T_P65TO127     11
 130 #define MIB_RMON_T_P128TO255    12
 131 #define MIB_RMON_T_P256TO511    13
 132 #define MIB_RMON_T_P512TO1023   14
 133 #define MIB_RMON_T_P1024TO2047  15
 134 #define MIB_RMON_T_P_GTE2048    16
 135 #define MIB_RMON_T_OCTETS       17
 136 #define MIB_IEEE_T_DROP         18
 137 #define MIB_IEEE_T_FRAME_OK     19
 138 #define MIB_IEEE_T_1COL         20
 139 #define MIB_IEEE_T_MCOL         21
 140 #define MIB_IEEE_T_DEF          22
 141 #define MIB_IEEE_T_LCOL         23
 142 #define MIB_IEEE_T_EXCOL        24
 143 #define MIB_IEEE_T_MACERR       25
 144 #define MIB_IEEE_T_CSERR        26
 145 #define MIB_IEEE_T_SQE          27
 146 #define MIB_IEEE_T_FDXFC        28
 147 #define MIB_IEEE_T_OCTETS_OK    29
 148
 149 #define MIB_RMON_R_DROP         32
 150 #define MIB_RMON_R_PACKETS      33
 151 #define MIB_RMON_R_BC_PKT       34
 152 #define MIB_RMON_R_MC_PKT       35
 153 #define MIB_RMON_R_CRC_ALIGN    36
 154 #define MIB_RMON_R_UNDERSIZE    37
 155 #define MIB_RMON_R_OVERSIZE     38
 156 #define MIB_RMON_R_FRAG         39
 157 #define MIB_RMON_R_JAB          40
 158 #define MIB_RMON_R_RESVD_0      41
 159 #define MIB_RMON_R_P64          42
 160 #define MIB_RMON_R_P65TO127     43
 161 #define MIB_RMON_R_P128TO255    44
 162 #define MIB_RMON_R_P256TO511    45
 163 #define MIB_RMON_R_P512TO1023   46
 164 #define MIB_RMON_R_P1024TO2047  47
 165 #define MIB_RMON_R_P_GTE2048    48
 166 #define MIB_RMON_R_OCTETS       49
 167 #define MIB_IEEE_R_DROP         50
 168 #define MIB_IEEE_R_FRAME_OK     51
 169 #define MIB_IEEE_R_CRC          52
 170 #define MIB_IEEE_R_ALIGN        53
 171 #define MIB_IEEE_R_MACERR       54
 172 #define MIB_IEEE_R_FDXFC        55
 173 #define MIB_IEEE_R_OCTETS_OK    56
 174
 175 static void mcf_fec_read_bd(mcf_fec_bd *bd, uint32_t addr)
 176 {
 177     cpu_physical_memory_read(addr, bd, sizeof(*bd));
 178     be16_to_cpus(&bd->flags);
 179     be16_to_cpus(&bd->length);
 180     be32_to_cpus(&bd->data);
 181 }
 182
 183 static void mcf_fec_write_bd(mcf_fec_bd *bd, uint32_t addr)
 184 {
 185     mcf_fec_bd tmp;
 186     tmp.flags = cpu_to_be16(bd->flags);
 187     tmp.length = cpu_to_be16(bd->length);
 188     tmp.data = cpu_to_be32(bd->data);
 189     cpu_physical_memory_write(addr, &tmp, sizeof(tmp));
 190 }
 191
 192 static void mcf_fec_update(mcf_fec_state *s)
 193 {
 194     uint32_t active;
 195     uint32_t changed;
 196     uint32_t mask;
 197     int i;
 198
 199     active = s->eir & s->eimr;
 200     changed = active ^s->irq_state;
 201     for (i = 0; i < FEC_NUM_IRQ; i++) {
 202         mask = mcf_fec_irq_map[i];
 203         if (changed & mask) {
 204             DPRINTF("IRQ %d = %d\n", i, (active & mask) != 0);
 205             qemu_set_irq(s->irq[i], (active & mask) != 0);
 206         }
 207     }
 208     s->irq_state = active;
 209 }
 210
 211 static void mcf_fec_tx_stats(mcf_fec_state *s, int size)
 212 {
 213     s->mib[MIB_RMON_T_PACKETS]++;
 214     s->mib[MIB_RMON_T_OCTETS] += size;
 215     if (size < 64) {
 216         s->mib[MIB_RMON_T_FRAG]++;
 217     } else if (size == 64) {
 218         s->mib[MIB_RMON_T_P64]++;
 219     } else if (size < 128) {
 220         s->mib[MIB_RMON_T_P65TO127]++;
 221     } else if (size < 256) {
 222         s->mib[MIB_RMON_T_P128TO255]++;
 223     } else if (size < 512) {
 224         s->mib[MIB_RMON_T_P256TO511]++;
 225     } else if (size < 1024) {
 226         s->mib[MIB_RMON_T_P512TO1023]++;
 227     } else if (size < 2048) {
 228         s->mib[MIB_RMON_T_P1024TO2047]++;
 229     } else {
 230         s->mib[MIB_RMON_T_P_GTE2048]++;
 231     }
 232     s->mib[MIB_IEEE_T_FRAME_OK]++;
 233     s->mib[MIB_IEEE_T_OCTETS_OK] += size;
 234 }
 235
 236 static void mcf_fec_do_tx(mcf_fec_state *s)
 237 {
 238     uint32_t addr;
 239     mcf_fec_bd bd;
 240     int frame_size;
 241     int len, descnt = 0;
 242     uint8_t frame[FEC_MAX_FRAME_SIZE];
 243     uint8_t *ptr;
 244
 245     DPRINTF("do_tx\n");
 246     ptr = frame;
 247     frame_size = 0;
 248     addr = s->tx_descriptor;
 249     while (descnt++ < FEC_MAX_DESC) {
 250         mcf_fec_read_bd(&bd, addr);
 251         DPRINTF("tx_bd %x flags %04x len %d data %08x\n",
 252                 addr, bd.flags, bd.length, bd.data);
 253         if ((bd.flags & FEC_BD_R) == 0) {
 254             /* Run out of descriptors to transmit.  */
 255             break;
 256         }
 257         len = bd.length;
 258         if (frame_size + len > FEC_MAX_FRAME_SIZE) {
 259             len = FEC_MAX_FRAME_SIZE - frame_size;
 260             s->eir |= FEC_INT_BABT;
 261         }
 262         cpu_physical_memory_read(bd.data, ptr, len);
 263         ptr += len;
 264         frame_size += len;
 265         if (bd.flags & FEC_BD_L) {
 266             /* Last buffer in frame.  */
 267             DPRINTF("Sending packet\n");
 268             qemu_send_packet(qemu_get_queue(s->nic), frame, frame_size);
 269             mcf_fec_tx_stats(s, frame_size);
 270             ptr = frame;
 271             frame_size = 0;
 272             s->eir |= FEC_INT_TXF;
 273         }
 274         s->eir |= FEC_INT_TXB;
 275         bd.flags &= ~FEC_BD_R;
 276         /* Write back the modified descriptor.  */
 277         mcf_fec_write_bd(&bd, addr);
 278         /* Advance to the next descriptor.  */
 279         if ((bd.flags & FEC_BD_W) != 0) {
 280             addr = s->etdsr;
 281         } else {
 282             addr += 8;
 283         }
 284     }
 285     s->tx_descriptor = addr;
 286 }
 287
 288 static void mcf_fec_enable_rx(mcf_fec_state *s)
 289 {
 290     NetClientState *nc = qemu_get_queue(s->nic);
 291     mcf_fec_bd bd;
 292
 293     mcf_fec_read_bd(&bd, s->rx_descriptor);
 294     s->rx_enabled = ((bd.flags & FEC_BD_E) != 0);
 295     if (s->rx_enabled) {
 296         qemu_flush_queued_packets(nc);
 297     }
 298 }
 299
 300 static void mcf_fec_reset(DeviceState *dev)
 301 {
 302     mcf_fec_state *s = MCF_FEC_NET(dev);
 303
 304     s->eir = 0;
 305     s->eimr = 0;
 306     s->rx_enabled = 0;
 307     s->ecr = 0;
 308     s->mscr = 0;
 309     s->rcr = 0x05ee0001;
 310     s->tcr = 0;
 311     s->tfwr = 0;
 312     s->rfsr = 0x500;
 313 }
 314
 315 #define MMFR_WRITE_OP   (1 << 28)
 316 #define MMFR_READ_OP    (2 << 28)
 317 #define MMFR_PHYADDR(v) (((v) >> 23) & 0x1f)
 318 #define MMFR_REGNUM(v)  (((v) >> 18) & 0x1f)
 319
 320 static uint64_t mcf_fec_read_mdio(mcf_fec_state *s)
 321 {
 322     uint64_t v;
 323
 324     if (s->mmfr & MMFR_WRITE_OP)
 325         return s->mmfr;
 326     if (MMFR_PHYADDR(s->mmfr) != 1)
 327         return s->mmfr |= 0xffff;
 328
 329     switch (MMFR_REGNUM(s->mmfr)) {
 330     case MII_BMCR:
 331         v = MII_BMCR_SPEED | MII_BMCR_AUTOEN | MII_BMCR_FD;
 332         break;
 333     case MII_BMSR:
 334         v = MII_BMSR_100TX_FD | MII_BMSR_100TX_HD | MII_BMSR_10T_FD |
 335             MII_BMSR_10T_HD | MII_BMSR_MFPS | MII_BMSR_AN_COMP |
 336             MII_BMSR_AUTONEG | MII_BMSR_LINK_ST;
 337         break;
 338     case MII_PHYID1:
 339         v = DP83848_PHYID1;
 340         break;
 341     case MII_PHYID2:
 342         v = DP83848_PHYID2;
 343         break;
 344     case MII_ANAR:
 345         v = MII_ANAR_TXFD | MII_ANAR_TX | MII_ANAR_10FD |
 346             MII_ANAR_10 | MII_ANAR_CSMACD;
 347         break;
 348     case MII_ANLPAR:
 349         v = MII_ANLPAR_ACK | MII_ANLPAR_TXFD | MII_ANLPAR_TX |
 350             MII_ANLPAR_10FD | MII_ANLPAR_10 | MII_ANLPAR_CSMACD;
 351         break;
 352     default:
 353         v = 0xffff;
 354         break;
 355     }
 356     s->mmfr = (s->mmfr & ~0xffff) | v;
 357     return s->mmfr;
 358 }
 359
 360 static uint64_t mcf_fec_read(void *opaque, hwaddr addr,
 361                              unsigned size)
 362 {
 363     mcf_fec_state *s = (mcf_fec_state *)opaque;
 364     switch (addr & 0x3ff) {
 365     case 0x004: return s->eir;
 366     case 0x008: return s->eimr;
 367     case 0x010: return s->rx_enabled ? (1 << 24) : 0; /* RDAR */
 368     case 0x014: return 0; /* TDAR */
 369     case 0x024: return s->ecr;
 370     case 0x040: return mcf_fec_read_mdio(s);
 371     case 0x044: return s->mscr;
 372     case 0x064: return 0; /* MIBC */
 373     case 0x084: return s->rcr;
 374     case 0x0c4: return s->tcr;
 375     case 0x0e4: /* PALR */
 376         return (s->conf.macaddr.a[0] << 24) | (s->conf.macaddr.a[1] << 16)
 377               | (s->conf.macaddr.a[2] << 8) | s->conf.macaddr.a[3];
 378         break;
 379     case 0x0e8: /* PAUR */
 380         return (s->conf.macaddr.a[4] << 24) | (s->conf.macaddr.a[5] << 16) | 0x8808;
 381     case 0x0ec: return 0x10000; /* OPD */
 382     case 0x118: return 0;
 383     case 0x11c: return 0;
 384     case 0x120: return 0;
 385     case 0x124: return 0;
 386     case 0x144: return s->tfwr;
 387     case 0x14c: return 0x600;
 388     case 0x150: return s->rfsr;
 389     case 0x180: return s->erdsr;
 390     case 0x184: return s->etdsr;
 391     case 0x188: return s->emrbr;
 392     case 0x200 ... 0x2e0: return s->mib[(addr & 0x1ff) / 4];
 393     default:
 394         hw_error("mcf_fec_read: Bad address 0x%x\n", (int)addr);
 395         return 0;
 396     }
 397 }
 398
 399 static void mcf_fec_write(void *opaque, hwaddr addr,
 400                           uint64_t value, unsigned size)
 401 {
 402     mcf_fec_state *s = (mcf_fec_state *)opaque;
 403     switch (addr & 0x3ff) {
 404     case 0x004:
 405         s->eir &= ~value;
 406         break;
 407     case 0x008:
 408         s->eimr = value;
 409         break;
 410     case 0x010: /* RDAR */
 411         if ((s->ecr & FEC_EN) && !s->rx_enabled) {
 412             DPRINTF("RX enable\n");
 413             mcf_fec_enable_rx(s);
 414         }
 415         break;
 416     case 0x014: /* TDAR */
 417         if (s->ecr & FEC_EN) {
 418             mcf_fec_do_tx(s);
 419         }
 420         break;
 421     case 0x024:
 422         s->ecr = value;
 423         if (value & FEC_RESET) {
 424             DPRINTF("Reset\n");
 425             mcf_fec_reset(opaque);
 426         }
 427         if ((s->ecr & FEC_EN) == 0) {
 428             s->rx_enabled = 0;
 429         }
 430         break;
 431     case 0x040:
 432         s->mmfr = value;
 433         s->eir |= FEC_INT_MII;
 434         break;
 435     case 0x044:
 436         s->mscr = value & 0xfe;
 437         break;
 438     case 0x064:
 439         /* TODO: Implement MIB.  */
 440         break;
 441     case 0x084:
 442         s->rcr = value & 0x07ff003f;
 443         /* TODO: Implement LOOP mode.  */
 444         break;
 445     case 0x0c4: /* TCR */
 446         /* We transmit immediately, so raise GRA immediately.  */
 447         s->tcr = value;
 448         if (value & 1)
 449             s->eir |= FEC_INT_GRA;
 450         break;
 451     case 0x0e4: /* PALR */
 452         s->conf.macaddr.a[0] = value >> 24;
 453         s->conf.macaddr.a[1] = value >> 16;
 454         s->conf.macaddr.a[2] = value >> 8;
 455         s->conf.macaddr.a[3] = value;
 456         break;
 457     case 0x0e8: /* PAUR */
 458         s->conf.macaddr.a[4] = value >> 24;
 459         s->conf.macaddr.a[5] = value >> 16;
 460         break;
 461     case 0x0ec:
 462         /* OPD */
 463         break;
 464     case 0x118:
 465     case 0x11c:
 466     case 0x120:
 467     case 0x124:
 468         /* TODO: implement MAC hash filtering.  */
 469         break;
 470     case 0x144:
 471         s->tfwr = value & 3;
 472         break;
 473     case 0x14c:
 474         /* FRBR writes ignored.  */
 475         break;
 476     case 0x150:
 477         s->rfsr = (value & 0x3fc) | 0x400;
 478         break;
 479     case 0x180:
 480         s->erdsr = value & ~3;
 481         s->rx_descriptor = s->erdsr;
 482         break;
 483     case 0x184:
 484         s->etdsr = value & ~3;
 485         s->tx_descriptor = s->etdsr;
 486         break;
 487     case 0x188:
 488         s->emrbr = value > 0 ? value & 0x7F0 : 0x7F0;
 489         break;
 490     case 0x200 ... 0x2e0:
 491         s->mib[(addr & 0x1ff) / 4] = value;
 492         break;
 493     default:
 494         hw_error("mcf_fec_write Bad address 0x%x\n", (int)addr);
 495     }
 496     mcf_fec_update(s);
 497 }
 498
 499 static void mcf_fec_rx_stats(mcf_fec_state *s, int size)
 500 {
 501     s->mib[MIB_RMON_R_PACKETS]++;
 502     s->mib[MIB_RMON_R_OCTETS] += size;
 503     if (size < 64) {
 504         s->mib[MIB_RMON_R_FRAG]++;
 505     } else if (size == 64) {
 506         s->mib[MIB_RMON_R_P64]++;
 507     } else if (size < 128) {
 508         s->mib[MIB_RMON_R_P65TO127]++;
 509     } else if (size < 256) {
 510         s->mib[MIB_RMON_R_P128TO255]++;
 511     } else if (size < 512) {
 512         s->mib[MIB_RMON_R_P256TO511]++;
 513     } else if (size < 1024) {
 514         s->mib[MIB_RMON_R_P512TO1023]++;
 515     } else if (size < 2048) {
 516         s->mib[MIB_RMON_R_P1024TO2047]++;
 517     } else {
 518         s->mib[MIB_RMON_R_P_GTE2048]++;
 519     }
 520     s->mib[MIB_IEEE_R_FRAME_OK]++;
 521     s->mib[MIB_IEEE_R_OCTETS_OK] += size;
 522 }
 523
 524 static int mcf_fec_have_receive_space(mcf_fec_state *s, size_t want)
 525 {
 526     mcf_fec_bd bd;
 527     uint32_t addr;
 528
 529     /* Walk descriptor list to determine if we have enough buffer */
 530     addr = s->rx_descriptor;
 531     while (want > 0) {
 532         mcf_fec_read_bd(&bd, addr);
 533         if ((bd.flags & FEC_BD_E) == 0) {
 534             return 0;
 535         }
 536         if (want < s->emrbr) {
 537             return 1;
 538         }
 539         want -= s->emrbr;
 540         /* Advance to the next descriptor.  */
 541         if ((bd.flags & FEC_BD_W) != 0) {
 542             addr = s->erdsr;
 543         } else {
 544             addr += 8;
 545         }
 546     }
 547     return 0;
 548 }
 549
 550 static ssize_t mcf_fec_receive(NetClientState *nc, const uint8_t *buf, size_t size)
 551 {
 552     mcf_fec_state *s = qemu_get_nic_opaque(nc);
 553     mcf_fec_bd bd;
 554     uint32_t flags = 0;
 555     uint32_t addr;
 556     uint32_t crc;
 557     uint32_t buf_addr;
 558     uint8_t *crc_ptr;
 559     unsigned int buf_len;
 560     size_t retsize;
 561
 562     DPRINTF("do_rx len %d\n", size);
 563     if (!s->rx_enabled) {
 564         return -1;
 565     }
 566     /* 4 bytes for the CRC.  */
 567     size += 4;
 568     crc = cpu_to_be32(crc32(~0, buf, size));
 569     crc_ptr = (uint8_t *)&crc;
 570     /* Huge frames are truncted.  */
 571     if (size > FEC_MAX_FRAME_SIZE) {
 572         size = FEC_MAX_FRAME_SIZE;
 573         flags |= FEC_BD_TR | FEC_BD_LG;
 574     }
 575     /* Frames larger than the user limit just set error flags.  */
 576     if (size > (s->rcr >> 16)) {
 577         flags |= FEC_BD_LG;
 578     }
 579     /* Check if we have enough space in current descriptors */
 580     if (!mcf_fec_have_receive_space(s, size)) {
 581         return 0;
 582     }
 583     addr = s->rx_descriptor;
 584     retsize = size;
 585     while (size > 0) {
 586         mcf_fec_read_bd(&bd, addr);
 587         buf_len = (size <= s->emrbr) ? size: s->emrbr;
 588         bd.length = buf_len;
 589         size -= buf_len;
 590         DPRINTF("rx_bd %x length %d\n", addr, bd.length);
 591         /* The last 4 bytes are the CRC.  */
 592         if (size < 4)
 593             buf_len += size - 4;
 594         buf_addr = bd.data;
 595         cpu_physical_memory_write(buf_addr, buf, buf_len);
 596         buf += buf_len;
 597         if (size < 4) {
 598             cpu_physical_memory_write(buf_addr + buf_len, crc_ptr, 4 - size);
 599             crc_ptr += 4 - size;
 600         }
 601         bd.flags &= ~FEC_BD_E;
 602         if (size == 0) {
 603             /* Last buffer in frame.  */
 604             bd.flags |= flags | FEC_BD_L;
 605             DPRINTF("rx frame flags %04x\n", bd.flags);
 606             s->eir |= FEC_INT_RXF;
 607         } else {
 608             s->eir |= FEC_INT_RXB;
 609         }
 610         mcf_fec_write_bd(&bd, addr);
 611         /* Advance to the next descriptor.  */
 612         if ((bd.flags & FEC_BD_W) != 0) {
 613             addr = s->erdsr;
 614         } else {
 615             addr += 8;
 616         }
 617     }
 618     s->rx_descriptor = addr;
 619     mcf_fec_rx_stats(s, retsize);
 620     mcf_fec_enable_rx(s);
 621     mcf_fec_update(s);
 622     return retsize;
 623 }
 624
 625 static const MemoryRegionOps mcf_fec_ops = {
 626     .read = mcf_fec_read,
 627     .write = mcf_fec_write,
 628     .endianness = DEVICE_NATIVE_ENDIAN,
 629 };
 630
 631 static NetClientInfo net_mcf_fec_info = {
 632     .type = NET_CLIENT_DRIVER_NIC,
 633     .size = sizeof(NICState),
 634     .receive = mcf_fec_receive,
 635 };
 636
 637 static void mcf_fec_realize(DeviceState *dev, Error **errp)
 638 {
 639     mcf_fec_state *s = MCF_FEC_NET(dev);
 640
 641     s->nic = qemu_new_nic(&net_mcf_fec_info, &s->conf,
 642                           object_get_typename(OBJECT(dev)), dev->id, s);
 643     qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
 644 }
 645
 646 static void mcf_fec_instance_init(Object *obj)
 647 {
 648     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 649     mcf_fec_state *s = MCF_FEC_NET(obj);
 650     int i;
 651
 652     memory_region_init_io(&s->iomem, obj, &mcf_fec_ops, s, "fec", 0x400);
 653     sysbus_init_mmio(sbd, &s->iomem);
 654     for (i = 0; i < FEC_NUM_IRQ; i++) {
 655         sysbus_init_irq(sbd, &s->irq[i]);
 656     }
 657 }
 658
 659 static Property mcf_fec_properties[] = {
 660     DEFINE_NIC_PROPERTIES(mcf_fec_state, conf),
 661     DEFINE_PROP_END_OF_LIST(),
 662 };
 663
 664 static void mcf_fec_class_init(ObjectClass *oc, void *data)
 665 {
 666     DeviceClass *dc = DEVICE_CLASS(oc);
 667
 668     set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
 669     dc->realize = mcf_fec_realize;
 670     dc->desc = "MCF Fast Ethernet Controller network device";
 671     dc->reset = mcf_fec_reset;
 672     dc->props = mcf_fec_properties;
 673 }
 674
 675 static const TypeInfo mcf_fec_info = {
 676     .name          = TYPE_MCF_FEC_NET,
 677     .parent        = TYPE_SYS_BUS_DEVICE,
 678     .instance_size = sizeof(mcf_fec_state),
 679     .instance_init = mcf_fec_instance_init,
 680     .class_init    = mcf_fec_class_init,
 681 };
 682
 683 static void mcf_fec_register_types(void)
 684 {
 685     type_register_static(&mcf_fec_info);
 686 }
 687
 688 type_init(mcf_fec_register_types)