hw/net/milkymist-minimac2.c

   1 /*
   2  *  QEMU model of the Milkymist minimac2 block.
   3  *
   4  *  Copyright (c) 2011 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  *
  19  *
  20  * Specification available at:
  21  *   not available yet
  22  *
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qapi/error.h"
  27 #include "hw/hw.h"
  28 #include "hw/sysbus.h"
  29 #include "trace.h"
  30 #include "net/net.h"
  31 #include "qemu/error-report.h"
  32
  33 #include <zlib.h>
  34
  35 enum {
  36     R_SETUP = 0,
  37     R_MDIO,
  38     R_STATE0,
  39     R_COUNT0,
  40     R_STATE1,
  41     R_COUNT1,
  42     R_TXCOUNT,
  43     R_MAX
  44 };
  45
  46 enum {
  47     SETUP_PHY_RST = (1<<0),
  48 };
  49
  50 enum {
  51     MDIO_DO  = (1<<0),
  52     MDIO_DI  = (1<<1),
  53     MDIO_OE  = (1<<2),
  54     MDIO_CLK = (1<<3),
  55 };
  56
  57 enum {
  58     STATE_EMPTY   = 0,
  59     STATE_LOADED  = 1,
  60     STATE_PENDING = 2,
  61 };
  62
  63 enum {
  64     MDIO_OP_WRITE = 1,
  65     MDIO_OP_READ  = 2,
  66 };
  67
  68 enum mdio_state {
  69     MDIO_STATE_IDLE,
  70     MDIO_STATE_READING,
  71     MDIO_STATE_WRITING,
  72 };
  73
  74 enum {
  75     R_PHY_ID1  = 2,
  76     R_PHY_ID2  = 3,
  77     R_PHY_MAX  = 32
  78 };
  79
  80 #define MINIMAC2_MTU 1530
  81 #define MINIMAC2_BUFFER_SIZE 2048
  82
  83 struct MilkymistMinimac2MdioState {
  84     int last_clk;
  85     int count;
  86     uint32_t data;
  87     uint16_t data_out;
  88     int state;
  89
  90     uint8_t phy_addr;
  91     uint8_t reg_addr;
  92 };
  93 typedef struct MilkymistMinimac2MdioState MilkymistMinimac2MdioState;
  94
  95 #define TYPE_MILKYMIST_MINIMAC2 "milkymist-minimac2"
  96 #define MILKYMIST_MINIMAC2(obj) \
  97     OBJECT_CHECK(MilkymistMinimac2State, (obj), TYPE_MILKYMIST_MINIMAC2)
  98
  99 struct MilkymistMinimac2State {
 100     SysBusDevice parent_obj;
 101
 102     NICState *nic;
 103     NICConf conf;
 104     char *phy_model;
 105     MemoryRegion buffers;
 106     MemoryRegion regs_region;
 107
 108     qemu_irq rx_irq;
 109     qemu_irq tx_irq;
 110
 111     uint32_t regs[R_MAX];
 112
 113     MilkymistMinimac2MdioState mdio;
 114
 115     uint16_t phy_regs[R_PHY_MAX];
 116
 117     uint8_t *rx0_buf;
 118     uint8_t *rx1_buf;
 119     uint8_t *tx_buf;
 120 };
 121 typedef struct MilkymistMinimac2State MilkymistMinimac2State;
 122
 123 static const uint8_t preamble_sfd[] = {
 124         0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xd5
 125 };
 126
 127 static void minimac2_mdio_write_reg(MilkymistMinimac2State *s,
 128         uint8_t phy_addr, uint8_t reg_addr, uint16_t value)
 129 {
 130     trace_milkymist_minimac2_mdio_write(phy_addr, reg_addr, value);
 131
 132     /* nop */
 133 }
 134
 135 static uint16_t minimac2_mdio_read_reg(MilkymistMinimac2State *s,
 136         uint8_t phy_addr, uint8_t reg_addr)
 137 {
 138     uint16_t r = s->phy_regs[reg_addr];
 139
 140     trace_milkymist_minimac2_mdio_read(phy_addr, reg_addr, r);
 141
 142     return r;
 143 }
 144
 145 static void minimac2_update_mdio(MilkymistMinimac2State *s)
 146 {
 147     MilkymistMinimac2MdioState *m = &s->mdio;
 148
 149     /* detect rising clk edge */
 150     if (m->last_clk == 0 && (s->regs[R_MDIO] & MDIO_CLK)) {
 151         /* shift data in */
 152         int bit = ((s->regs[R_MDIO] & MDIO_DO)
 153                    && (s->regs[R_MDIO] & MDIO_OE)) ? 1 : 0;
 154         m->data = (m->data << 1) | bit;
 155
 156         /* check for sync */
 157         if (m->data == 0xffffffff) {
 158             m->count = 32;
 159         }
 160
 161         if (m->count == 16) {
 162             uint8_t start = (m->data >> 14) & 0x3;
 163             uint8_t op = (m->data >> 12) & 0x3;
 164             uint8_t ta = (m->data) & 0x3;
 165
 166             if (start == 1 && op == MDIO_OP_WRITE && ta == 2) {
 167                 m->state = MDIO_STATE_WRITING;
 168             } else if (start == 1 && op == MDIO_OP_READ && (ta & 1) == 0) {
 169                 m->state = MDIO_STATE_READING;
 170             } else {
 171                 m->state = MDIO_STATE_IDLE;
 172             }
 173
 174             if (m->state != MDIO_STATE_IDLE) {
 175                 m->phy_addr = (m->data >> 7) & 0x1f;
 176                 m->reg_addr = (m->data >> 2) & 0x1f;
 177             }
 178
 179             if (m->state == MDIO_STATE_READING) {
 180                 m->data_out = minimac2_mdio_read_reg(s, m->phy_addr,
 181                         m->reg_addr);
 182             }
 183         }
 184
 185         if (m->count < 16 && m->state == MDIO_STATE_READING) {
 186             int bit = (m->data_out & 0x8000) ? 1 : 0;
 187             m->data_out <<= 1;
 188
 189             if (bit) {
 190                 s->regs[R_MDIO] |= MDIO_DI;
 191             } else {
 192                 s->regs[R_MDIO] &= ~MDIO_DI;
 193             }
 194         }
 195
 196         if (m->count == 0 && m->state) {
 197             if (m->state == MDIO_STATE_WRITING) {
 198                 uint16_t data = m->data & 0xffff;
 199                 minimac2_mdio_write_reg(s, m->phy_addr, m->reg_addr, data);
 200             }
 201             m->state = MDIO_STATE_IDLE;
 202         }
 203         m->count--;
 204     }
 205
 206     m->last_clk = (s->regs[R_MDIO] & MDIO_CLK) ? 1 : 0;
 207 }
 208
 209 static size_t assemble_frame(uint8_t *buf, size_t size,
 210         const uint8_t *payload, size_t payload_size)
 211 {
 212     uint32_t crc;
 213
 214     if (size < payload_size + 12) {
 215         error_report("milkymist_minimac2: received too big ethernet frame");
 216         return 0;
 217     }
 218
 219     /* prepend preamble and sfd */
 220     memcpy(buf, preamble_sfd, 8);
 221
 222     /* now copy the payload */
 223     memcpy(buf + 8, payload, payload_size);
 224
 225     /* pad frame if needed */
 226     if (payload_size < 60) {
 227         memset(buf + payload_size + 8, 0, 60 - payload_size);
 228         payload_size = 60;
 229     }
 230
 231     /* append fcs */
 232     crc = cpu_to_le32(crc32(0, buf + 8, payload_size));
 233     memcpy(buf + payload_size + 8, &crc, 4);
 234
 235     return payload_size + 12;
 236 }
 237
 238 static void minimac2_tx(MilkymistMinimac2State *s)
 239 {
 240     uint32_t txcount = s->regs[R_TXCOUNT];
 241     uint8_t *buf = s->tx_buf;
 242
 243     if (txcount < 64) {
 244         error_report("milkymist_minimac2: ethernet frame too small (%u < %u)",
 245                 txcount, 64);
 246         goto err;
 247     }
 248
 249     if (txcount > MINIMAC2_MTU) {
 250         error_report("milkymist_minimac2: MTU exceeded (%u > %u)",
 251                 txcount, MINIMAC2_MTU);
 252         goto err;
 253     }
 254
 255     if (memcmp(buf, preamble_sfd, 8) != 0) {
 256         error_report("milkymist_minimac2: frame doesn't contain the preamble "
 257                 "and/or the SFD (%02x %02x %02x %02x %02x %02x %02x %02x)",
 258                 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7]);
 259         goto err;
 260     }
 261
 262     trace_milkymist_minimac2_tx_frame(txcount - 12);
 263
 264     /* send packet, skipping preamble and sfd */
 265     qemu_send_packet_raw(qemu_get_queue(s->nic), buf + 8, txcount - 12);
 266
 267     s->regs[R_TXCOUNT] = 0;
 268
 269 err:
 270     trace_milkymist_minimac2_pulse_irq_tx();
 271     qemu_irq_pulse(s->tx_irq);
 272 }
 273
 274 static void update_rx_interrupt(MilkymistMinimac2State *s)
 275 {
 276     if (s->regs[R_STATE0] == STATE_PENDING
 277             || s->regs[R_STATE1] == STATE_PENDING) {
 278         trace_milkymist_minimac2_raise_irq_rx();
 279         qemu_irq_raise(s->rx_irq);
 280     } else {
 281         trace_milkymist_minimac2_lower_irq_rx();
 282         qemu_irq_lower(s->rx_irq);
 283     }
 284 }
 285
 286 static ssize_t minimac2_rx(NetClientState *nc, const uint8_t *buf, size_t size)
 287 {
 288     MilkymistMinimac2State *s = qemu_get_nic_opaque(nc);
 289
 290     uint32_t r_count;
 291     uint32_t r_state;
 292     uint8_t *rx_buf;
 293
 294     size_t frame_size;
 295
 296     trace_milkymist_minimac2_rx_frame(buf, size);
 297
 298     /* choose appropriate slot */
 299     if (s->regs[R_STATE0] == STATE_LOADED) {
 300         r_count = R_COUNT0;
 301         r_state = R_STATE0;
 302         rx_buf = s->rx0_buf;
 303     } else if (s->regs[R_STATE1] == STATE_LOADED) {
 304         r_count = R_COUNT1;
 305         r_state = R_STATE1;
 306         rx_buf = s->rx1_buf;
 307     } else {
 308         return 0;
 309     }
 310
 311     /* assemble frame */
 312     frame_size = assemble_frame(rx_buf, MINIMAC2_BUFFER_SIZE, buf, size);
 313
 314     if (frame_size == 0) {
 315         return size;
 316     }
 317
 318     trace_milkymist_minimac2_rx_transfer(rx_buf, frame_size);
 319
 320     /* update slot */
 321     s->regs[r_count] = frame_size;
 322     s->regs[r_state] = STATE_PENDING;
 323
 324     update_rx_interrupt(s);
 325
 326     return size;
 327 }
 328
 329 static uint64_t
 330 minimac2_read(void *opaque, hwaddr addr, unsigned size)
 331 {
 332     MilkymistMinimac2State *s = opaque;
 333     uint32_t r = 0;
 334
 335     addr >>= 2;
 336     switch (addr) {
 337     case R_SETUP:
 338     case R_MDIO:
 339     case R_STATE0:
 340     case R_COUNT0:
 341     case R_STATE1:
 342     case R_COUNT1:
 343     case R_TXCOUNT:
 344         r = s->regs[addr];
 345         break;
 346
 347     default:
 348         error_report("milkymist_minimac2: read access to unknown register 0x"
 349                 TARGET_FMT_plx, addr << 2);
 350         break;
 351     }
 352
 353     trace_milkymist_minimac2_memory_read(addr << 2, r);
 354
 355     return r;
 356 }
 357
 358 static int minimac2_can_rx(MilkymistMinimac2State *s)
 359 {
 360     if (s->regs[R_STATE0] == STATE_LOADED) {
 361         return 1;
 362     }
 363     if (s->regs[R_STATE1] == STATE_LOADED) {
 364         return 1;
 365     }
 366
 367     return 0;
 368 }
 369
 370 static void
 371 minimac2_write(void *opaque, hwaddr addr, uint64_t value,
 372                unsigned size)
 373 {
 374     MilkymistMinimac2State *s = opaque;
 375
 376     trace_milkymist_minimac2_memory_write(addr, value);
 377
 378     addr >>= 2;
 379     switch (addr) {
 380     case R_MDIO:
 381     {
 382         /* MDIO_DI is read only */
 383         int mdio_di = (s->regs[R_MDIO] & MDIO_DI);
 384         s->regs[R_MDIO] = value;
 385         if (mdio_di) {
 386             s->regs[R_MDIO] |= mdio_di;
 387         } else {
 388             s->regs[R_MDIO] &= ~mdio_di;
 389         }
 390
 391         minimac2_update_mdio(s);
 392     } break;
 393     case R_TXCOUNT:
 394         s->regs[addr] = value;
 395         if (value > 0) {
 396             minimac2_tx(s);
 397         }
 398         break;
 399     case R_STATE0:
 400     case R_STATE1:
 401         s->regs[addr] = value;
 402         update_rx_interrupt(s);
 403         if (minimac2_can_rx(s)) {
 404             qemu_flush_queued_packets(qemu_get_queue(s->nic));
 405         }
 406         break;
 407     case R_SETUP:
 408     case R_COUNT0:
 409     case R_COUNT1:
 410         s->regs[addr] = value;
 411         break;
 412
 413     default:
 414         error_report("milkymist_minimac2: write access to unknown register 0x"
 415                 TARGET_FMT_plx, addr << 2);
 416         break;
 417     }
 418 }
 419
 420 static const MemoryRegionOps minimac2_ops = {
 421     .read = minimac2_read,
 422     .write = minimac2_write,
 423     .valid = {
 424         .min_access_size = 4,
 425         .max_access_size = 4,
 426     },
 427     .endianness = DEVICE_NATIVE_ENDIAN,
 428 };
 429
 430 static void milkymist_minimac2_reset(DeviceState *d)
 431 {
 432     MilkymistMinimac2State *s = MILKYMIST_MINIMAC2(d);
 433     int i;
 434
 435     for (i = 0; i < R_MAX; i++) {
 436         s->regs[i] = 0;
 437     }
 438     for (i = 0; i < R_PHY_MAX; i++) {
 439         s->phy_regs[i] = 0;
 440     }
 441
 442     /* defaults */
 443     s->phy_regs[R_PHY_ID1] = 0x0022; /* Micrel KSZ8001L */
 444     s->phy_regs[R_PHY_ID2] = 0x161a;
 445 }
 446
 447 static NetClientInfo net_milkymist_minimac2_info = {
 448     .type = NET_CLIENT_OPTIONS_KIND_NIC,
 449     .size = sizeof(NICState),
 450     .receive = minimac2_rx,
 451 };
 452
 453 static int milkymist_minimac2_init(SysBusDevice *sbd)
 454 {
 455     DeviceState *dev = DEVICE(sbd);
 456     MilkymistMinimac2State *s = MILKYMIST_MINIMAC2(dev);
 457     size_t buffers_size = TARGET_PAGE_ALIGN(3 * MINIMAC2_BUFFER_SIZE);
 458
 459     sysbus_init_irq(sbd, &s->rx_irq);
 460     sysbus_init_irq(sbd, &s->tx_irq);
 461
 462     memory_region_init_io(&s->regs_region, OBJECT(dev), &minimac2_ops, s,
 463                           "milkymist-minimac2", R_MAX * 4);
 464     sysbus_init_mmio(sbd, &s->regs_region);
 465
 466     /* register buffers memory */
 467     memory_region_init_ram(&s->buffers, OBJECT(dev), "milkymist-minimac2.buffers",
 468                            buffers_size, &error_fatal);
 469     vmstate_register_ram_global(&s->buffers);
 470     s->rx0_buf = memory_region_get_ram_ptr(&s->buffers);
 471     s->rx1_buf = s->rx0_buf + MINIMAC2_BUFFER_SIZE;
 472     s->tx_buf = s->rx1_buf + MINIMAC2_BUFFER_SIZE;
 473
 474     sysbus_init_mmio(sbd, &s->buffers);
 475
 476     qemu_macaddr_default_if_unset(&s->conf.macaddr);
 477     s->nic = qemu_new_nic(&net_milkymist_minimac2_info, &s->conf,
 478                           object_get_typename(OBJECT(dev)), dev->id, s);
 479     qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
 480
 481     return 0;
 482 }
 483
 484 static const VMStateDescription vmstate_milkymist_minimac2_mdio = {
 485     .name = "milkymist-minimac2-mdio",
 486     .version_id = 1,
 487     .minimum_version_id = 1,
 488     .fields = (VMStateField[]) {
 489         VMSTATE_INT32(last_clk, MilkymistMinimac2MdioState),
 490         VMSTATE_INT32(count, MilkymistMinimac2MdioState),
 491         VMSTATE_UINT32(data, MilkymistMinimac2MdioState),
 492         VMSTATE_UINT16(data_out, MilkymistMinimac2MdioState),
 493         VMSTATE_INT32(state, MilkymistMinimac2MdioState),
 494         VMSTATE_UINT8(phy_addr, MilkymistMinimac2MdioState),
 495         VMSTATE_UINT8(reg_addr, MilkymistMinimac2MdioState),
 496         VMSTATE_END_OF_LIST()
 497     }
 498 };
 499
 500 static const VMStateDescription vmstate_milkymist_minimac2 = {
 501     .name = "milkymist-minimac2",
 502     .version_id = 1,
 503     .minimum_version_id = 1,
 504     .fields = (VMStateField[]) {
 505         VMSTATE_UINT32_ARRAY(regs, MilkymistMinimac2State, R_MAX),
 506         VMSTATE_UINT16_ARRAY(phy_regs, MilkymistMinimac2State, R_PHY_MAX),
 507         VMSTATE_STRUCT(mdio, MilkymistMinimac2State, 0,
 508                 vmstate_milkymist_minimac2_mdio, MilkymistMinimac2MdioState),
 509         VMSTATE_END_OF_LIST()
 510     }
 511 };
 512
 513 static Property milkymist_minimac2_properties[] = {
 514     DEFINE_NIC_PROPERTIES(MilkymistMinimac2State, conf),
 515     DEFINE_PROP_STRING("phy_model", MilkymistMinimac2State, phy_model),
 516     DEFINE_PROP_END_OF_LIST(),
 517 };
 518
 519 static void milkymist_minimac2_class_init(ObjectClass *klass, void *data)
 520 {
 521     DeviceClass *dc = DEVICE_CLASS(klass);
 522     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 523
 524     k->init = milkymist_minimac2_init;
 525     dc->reset = milkymist_minimac2_reset;
 526     dc->vmsd = &vmstate_milkymist_minimac2;
 527     dc->props = milkymist_minimac2_properties;
 528 }
 529
 530 static const TypeInfo milkymist_minimac2_info = {
 531     .name          = TYPE_MILKYMIST_MINIMAC2,
 532     .parent        = TYPE_SYS_BUS_DEVICE,
 533     .instance_size = sizeof(MilkymistMinimac2State),
 534     .class_init    = milkymist_minimac2_class_init,
 535 };
 536
 537 static void milkymist_minimac2_register_types(void)
 538 {
 539     type_register_static(&milkymist_minimac2_info);
 540 }
 541
 542 type_init(milkymist_minimac2_register_types)