hw/net/ne2000.c

   1 /*
   2  * QEMU NE2000 emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "net/eth.h"
  27 #include "qemu/module.h"
  28 #include "ne2000.h"
  29 #include "sysemu/sysemu.h"
  30 #include "trace.h"
  31
  32 /* debug NE2000 card */
  33 //#define DEBUG_NE2000
  34
  35 #define MAX_ETH_FRAME_SIZE 1514
  36
  37 #define E8390_CMD       0x00  /* The command register (for all pages) */
  38 /* Page 0 register offsets. */
  39 #define EN0_CLDALO      0x01    /* Low byte of current local dma addr  RD */
  40 #define EN0_STARTPG     0x01    /* Starting page of ring bfr WR */
  41 #define EN0_CLDAHI      0x02    /* High byte of current local dma addr  RD */
  42 #define EN0_STOPPG      0x02    /* Ending page +1 of ring bfr WR */
  43 #define EN0_BOUNDARY    0x03    /* Boundary page of ring bfr RD WR */
  44 #define EN0_TSR         0x04    /* Transmit status reg RD */
  45 #define EN0_TPSR        0x04    /* Transmit starting page WR */
  46 #define EN0_NCR         0x05    /* Number of collision reg RD */
  47 #define EN0_TCNTLO      0x05    /* Low  byte of tx byte count WR */
  48 #define EN0_FIFO        0x06    /* FIFO RD */
  49 #define EN0_TCNTHI      0x06    /* High byte of tx byte count WR */
  50 #define EN0_ISR         0x07    /* Interrupt status reg RD WR */
  51 #define EN0_CRDALO      0x08    /* low byte of current remote dma address RD */
  52 #define EN0_RSARLO      0x08    /* Remote start address reg 0 */
  53 #define EN0_CRDAHI      0x09    /* high byte, current remote dma address RD */
  54 #define EN0_RSARHI      0x09    /* Remote start address reg 1 */
  55 #define EN0_RCNTLO      0x0a    /* Remote byte count reg WR */
  56 #define EN0_RTL8029ID0  0x0a    /* Realtek ID byte #1 RD */
  57 #define EN0_RCNTHI      0x0b    /* Remote byte count reg WR */
  58 #define EN0_RTL8029ID1  0x0b    /* Realtek ID byte #2 RD */
  59 #define EN0_RSR         0x0c    /* rx status reg RD */
  60 #define EN0_RXCR        0x0c    /* RX configuration reg WR */
  61 #define EN0_TXCR        0x0d    /* TX configuration reg WR */
  62 #define EN0_COUNTER0    0x0d    /* Rcv alignment error counter RD */
  63 #define EN0_DCFG        0x0e    /* Data configuration reg WR */
  64 #define EN0_COUNTER1    0x0e    /* Rcv CRC error counter RD */
  65 #define EN0_IMR         0x0f    /* Interrupt mask reg WR */
  66 #define EN0_COUNTER2    0x0f    /* Rcv missed frame error counter RD */
  67
  68 #define EN1_PHYS        0x11
  69 #define EN1_CURPAG      0x17
  70 #define EN1_MULT        0x18
  71
  72 #define EN2_STARTPG     0x21    /* Starting page of ring bfr RD */
  73 #define EN2_STOPPG      0x22    /* Ending page +1 of ring bfr RD */
  74
  75 #define EN3_CONFIG0     0x33
  76 #define EN3_CONFIG1     0x34
  77 #define EN3_CONFIG2     0x35
  78 #define EN3_CONFIG3     0x36
  79
  80 /*  Register accessed at EN_CMD, the 8390 base addr.  */
  81 #define E8390_STOP      0x01    /* Stop and reset the chip */
  82 #define E8390_START     0x02    /* Start the chip, clear reset */
  83 #define E8390_TRANS     0x04    /* Transmit a frame */
  84 #define E8390_RREAD     0x08    /* Remote read */
  85 #define E8390_RWRITE    0x10    /* Remote write  */
  86 #define E8390_NODMA     0x20    /* Remote DMA */
  87 #define E8390_PAGE0     0x00    /* Select page chip registers */
  88 #define E8390_PAGE1     0x40    /* using the two high-order bits */
  89 #define E8390_PAGE2     0x80    /* Page 3 is invalid. */
  90
  91 /* Bits in EN0_ISR - Interrupt status register */
  92 #define ENISR_RX        0x01    /* Receiver, no error */
  93 #define ENISR_TX        0x02    /* Transmitter, no error */
  94 #define ENISR_RX_ERR    0x04    /* Receiver, with error */
  95 #define ENISR_TX_ERR    0x08    /* Transmitter, with error */
  96 #define ENISR_OVER      0x10    /* Receiver overwrote the ring */
  97 #define ENISR_COUNTERS  0x20    /* Counters need emptying */
  98 #define ENISR_RDC       0x40    /* remote dma complete */
  99 #define ENISR_RESET     0x80    /* Reset completed */
 100 #define ENISR_ALL       0x3f    /* Interrupts we will enable */
 101
 102 /* Bits in received packet status byte and EN0_RSR*/
 103 #define ENRSR_RXOK      0x01    /* Received a good packet */
 104 #define ENRSR_CRC       0x02    /* CRC error */
 105 #define ENRSR_FAE       0x04    /* frame alignment error */
 106 #define ENRSR_FO        0x08    /* FIFO overrun */
 107 #define ENRSR_MPA       0x10    /* missed pkt */
 108 #define ENRSR_PHY       0x20    /* physical/multicast address */
 109 #define ENRSR_DIS       0x40    /* receiver disable. set in monitor mode */
 110 #define ENRSR_DEF       0x80    /* deferring */
 111
 112 /* Transmitted packet status, EN0_TSR. */
 113 #define ENTSR_PTX 0x01  /* Packet transmitted without error */
 114 #define ENTSR_ND  0x02  /* The transmit wasn't deferred. */
 115 #define ENTSR_COL 0x04  /* The transmit collided at least once. */
 116 #define ENTSR_ABT 0x08  /* The transmit collided 16 times, and was deferred. */
 117 #define ENTSR_CRS 0x10  /* The carrier sense was lost. */
 118 #define ENTSR_FU  0x20  /* A "FIFO underrun" occurred during transmit. */
 119 #define ENTSR_CDH 0x40  /* The collision detect "heartbeat" signal was lost. */
 120 #define ENTSR_OWC 0x80  /* There was an out-of-window collision. */
 121
 122 void ne2000_reset(NE2000State *s)
 123 {
 124     int i;
 125
 126     s->isr = ENISR_RESET;
 127     memcpy(s->mem, &s->c.macaddr, 6);
 128     s->mem[14] = 0x57;
 129     s->mem[15] = 0x57;
 130
 131     /* duplicate prom data */
 132     for(i = 15;i >= 0; i--) {
 133         s->mem[2 * i] = s->mem[i];
 134         s->mem[2 * i + 1] = s->mem[i];
 135     }
 136 }
 137
 138 static void ne2000_update_irq(NE2000State *s)
 139 {
 140     int isr;
 141     isr = (s->isr & s->imr) & 0x7f;
 142 #if defined(DEBUG_NE2000)
 143     printf("NE2000: Set IRQ to %d (%02x %02x)\n",
 144            isr ? 1 : 0, s->isr, s->imr);
 145 #endif
 146     qemu_set_irq(s->irq, (isr != 0));
 147 }
 148
 149 static int ne2000_buffer_full(NE2000State *s)
 150 {
 151     int avail, index, boundary;
 152
 153     if (s->stop <= s->start) {
 154         return 1;
 155     }
 156
 157     index = s->curpag << 8;
 158     boundary = s->boundary << 8;
 159     if (index < boundary)
 160         avail = boundary - index;
 161     else
 162         avail = (s->stop - s->start) - (index - boundary);
 163     if (avail < (MAX_ETH_FRAME_SIZE + 4))
 164         return 1;
 165     return 0;
 166 }
 167
 168 #define MIN_BUF_SIZE 60
 169
 170 ssize_t ne2000_receive(NetClientState *nc, const uint8_t *buf, size_t size_)
 171 {
 172     NE2000State *s = qemu_get_nic_opaque(nc);
 173     size_t size = size_;
 174     uint8_t *p;
 175     unsigned int total_len, next, avail, len, index, mcast_idx;
 176     uint8_t buf1[60];
 177     static const uint8_t broadcast_macaddr[6] =
 178         { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
 179
 180 #if defined(DEBUG_NE2000)
 181     printf("NE2000: received len=%zu\n", size);
 182 #endif
 183
 184     if (s->cmd & E8390_STOP || ne2000_buffer_full(s))
 185         return -1;
 186
 187     /* XXX: check this */
 188     if (s->rxcr & 0x10) {
 189         /* promiscuous: receive all */
 190     } else {
 191         if (!memcmp(buf,  broadcast_macaddr, 6)) {
 192             /* broadcast address */
 193             if (!(s->rxcr & 0x04))
 194                 return size;
 195         } else if (buf[0] & 0x01) {
 196             /* multicast */
 197             if (!(s->rxcr & 0x08))
 198                 return size;
 199             mcast_idx = net_crc32(buf, ETH_ALEN) >> 26;
 200             if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
 201                 return size;
 202         } else if (s->mem[0] == buf[0] &&
 203                    s->mem[2] == buf[1] &&
 204                    s->mem[4] == buf[2] &&
 205                    s->mem[6] == buf[3] &&
 206                    s->mem[8] == buf[4] &&
 207                    s->mem[10] == buf[5]) {
 208             /* match */
 209         } else {
 210             return size;
 211         }
 212     }
 213
 214
 215     /* if too small buffer, then expand it */
 216     if (size < MIN_BUF_SIZE) {
 217         memcpy(buf1, buf, size);
 218         memset(buf1 + size, 0, MIN_BUF_SIZE - size);
 219         buf = buf1;
 220         size = MIN_BUF_SIZE;
 221     }
 222
 223     index = s->curpag << 8;
 224     if (index >= NE2000_PMEM_END) {
 225         index = s->start;
 226     }
 227     /* 4 bytes for header */
 228     total_len = size + 4;
 229     /* address for next packet (4 bytes for CRC) */
 230     next = index + ((total_len + 4 + 255) & ~0xff);
 231     if (next >= s->stop)
 232         next -= (s->stop - s->start);
 233     /* prepare packet header */
 234     p = s->mem + index;
 235     s->rsr = ENRSR_RXOK; /* receive status */
 236     /* XXX: check this */
 237     if (buf[0] & 0x01)
 238         s->rsr |= ENRSR_PHY;
 239     p[0] = s->rsr;
 240     p[1] = next >> 8;
 241     p[2] = total_len;
 242     p[3] = total_len >> 8;
 243     index += 4;
 244
 245     /* write packet data */
 246     while (size > 0) {
 247         if (index <= s->stop)
 248             avail = s->stop - index;
 249         else
 250             break;
 251         len = size;
 252         if (len > avail)
 253             len = avail;
 254         memcpy(s->mem + index, buf, len);
 255         buf += len;
 256         index += len;
 257         if (index == s->stop)
 258             index = s->start;
 259         size -= len;
 260     }
 261     s->curpag = next >> 8;
 262
 263     /* now we can signal we have received something */
 264     s->isr |= ENISR_RX;
 265     ne2000_update_irq(s);
 266
 267     return size_;
 268 }
 269
 270 static void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 271 {
 272     NE2000State *s = opaque;
 273     int offset, page, index;
 274
 275     addr &= 0xf;
 276     trace_ne2000_ioport_write(addr, val);
 277     if (addr == E8390_CMD) {
 278         /* control register */
 279         s->cmd = val;
 280         if (!(val & E8390_STOP)) { /* START bit makes no sense on RTL8029... */
 281             s->isr &= ~ENISR_RESET;
 282             /* test specific case: zero length transfer */
 283             if ((val & (E8390_RREAD | E8390_RWRITE)) &&
 284                 s->rcnt == 0) {
 285                 s->isr |= ENISR_RDC;
 286                 ne2000_update_irq(s);
 287             }
 288             if (val & E8390_TRANS) {
 289                 index = (s->tpsr << 8);
 290                 /* XXX: next 2 lines are a hack to make netware 3.11 work */
 291                 if (index >= NE2000_PMEM_END)
 292                     index -= NE2000_PMEM_SIZE;
 293                 /* fail safe: check range on the transmitted length  */
 294                 if (index + s->tcnt <= NE2000_PMEM_END) {
 295                     qemu_send_packet(qemu_get_queue(s->nic), s->mem + index,
 296                                      s->tcnt);
 297                 }
 298                 /* signal end of transfer */
 299                 s->tsr = ENTSR_PTX;
 300                 s->isr |= ENISR_TX;
 301                 s->cmd &= ~E8390_TRANS;
 302                 ne2000_update_irq(s);
 303             }
 304         }
 305     } else {
 306         page = s->cmd >> 6;
 307         offset = addr | (page << 4);
 308         switch(offset) {
 309         case EN0_STARTPG:
 310             if (val << 8 <= NE2000_PMEM_END) {
 311                 s->start = val << 8;
 312             }
 313             break;
 314         case EN0_STOPPG:
 315             if (val << 8 <= NE2000_PMEM_END) {
 316                 s->stop = val << 8;
 317             }
 318             break;
 319         case EN0_BOUNDARY:
 320             if (val << 8 < NE2000_PMEM_END) {
 321                 s->boundary = val;
 322             }
 323             break;
 324         case EN0_IMR:
 325             s->imr = val;
 326             ne2000_update_irq(s);
 327             break;
 328         case EN0_TPSR:
 329             s->tpsr = val;
 330             break;
 331         case EN0_TCNTLO:
 332             s->tcnt = (s->tcnt & 0xff00) | val;
 333             break;
 334         case EN0_TCNTHI:
 335             s->tcnt = (s->tcnt & 0x00ff) | (val << 8);
 336             break;
 337         case EN0_RSARLO:
 338             s->rsar = (s->rsar & 0xff00) | val;
 339             break;
 340         case EN0_RSARHI:
 341             s->rsar = (s->rsar & 0x00ff) | (val << 8);
 342             break;
 343         case EN0_RCNTLO:
 344             s->rcnt = (s->rcnt & 0xff00) | val;
 345             break;
 346         case EN0_RCNTHI:
 347             s->rcnt = (s->rcnt & 0x00ff) | (val << 8);
 348             break;
 349         case EN0_RXCR:
 350             s->rxcr = val;
 351             break;
 352         case EN0_DCFG:
 353             s->dcfg = val;
 354             break;
 355         case EN0_ISR:
 356             s->isr &= ~(val & 0x7f);
 357             ne2000_update_irq(s);
 358             break;
 359         case EN1_PHYS ... EN1_PHYS + 5:
 360             s->phys[offset - EN1_PHYS] = val;
 361             break;
 362         case EN1_CURPAG:
 363             if (val << 8 < NE2000_PMEM_END) {
 364                 s->curpag = val;
 365             }
 366             break;
 367         case EN1_MULT ... EN1_MULT + 7:
 368             s->mult[offset - EN1_MULT] = val;
 369             break;
 370         }
 371     }
 372 }
 373
 374 static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr)
 375 {
 376     NE2000State *s = opaque;
 377     int offset, page, ret;
 378
 379     addr &= 0xf;
 380     if (addr == E8390_CMD) {
 381         ret = s->cmd;
 382     } else {
 383         page = s->cmd >> 6;
 384         offset = addr | (page << 4);
 385         switch(offset) {
 386         case EN0_TSR:
 387             ret = s->tsr;
 388             break;
 389         case EN0_BOUNDARY:
 390             ret = s->boundary;
 391             break;
 392         case EN0_ISR:
 393             ret = s->isr;
 394             break;
 395         case EN0_RSARLO:
 396             ret = s->rsar & 0x00ff;
 397             break;
 398         case EN0_RSARHI:
 399             ret = s->rsar >> 8;
 400             break;
 401         case EN1_PHYS ... EN1_PHYS + 5:
 402             ret = s->phys[offset - EN1_PHYS];
 403             break;
 404         case EN1_CURPAG:
 405             ret = s->curpag;
 406             break;
 407         case EN1_MULT ... EN1_MULT + 7:
 408             ret = s->mult[offset - EN1_MULT];
 409             break;
 410         case EN0_RSR:
 411             ret = s->rsr;
 412             break;
 413         case EN2_STARTPG:
 414             ret = s->start >> 8;
 415             break;
 416         case EN2_STOPPG:
 417             ret = s->stop >> 8;
 418             break;
 419         case EN0_RTL8029ID0:
 420             ret = 0x50;
 421             break;
 422         case EN0_RTL8029ID1:
 423             ret = 0x43;
 424             break;
 425         case EN3_CONFIG0:
 426             ret = 0;            /* 10baseT media */
 427             break;
 428         case EN3_CONFIG2:
 429             ret = 0x40;         /* 10baseT active */
 430             break;
 431         case EN3_CONFIG3:
 432             ret = 0x40;         /* Full duplex */
 433             break;
 434         default:
 435             ret = 0x00;
 436             break;
 437         }
 438     }
 439     trace_ne2000_ioport_read(addr, ret);
 440     return ret;
 441 }
 442
 443 static inline void ne2000_mem_writeb(NE2000State *s, uint32_t addr,
 444                                      uint32_t val)
 445 {
 446     if (addr < 32 ||
 447         (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
 448         s->mem[addr] = val;
 449     }
 450 }
 451
 452 static inline void ne2000_mem_writew(NE2000State *s, uint32_t addr,
 453                                      uint32_t val)
 454 {
 455     addr &= ~1; /* XXX: check exact behaviour if not even */
 456     if (addr < 32 ||
 457         (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
 458         *(uint16_t *)(s->mem + addr) = cpu_to_le16(val);
 459     }
 460 }
 461
 462 static inline void ne2000_mem_writel(NE2000State *s, uint32_t addr,
 463                                      uint32_t val)
 464 {
 465     addr &= ~1; /* XXX: check exact behaviour if not even */
 466     if (addr < 32
 467         || (addr >= NE2000_PMEM_START
 468             && addr + sizeof(uint32_t) <= NE2000_MEM_SIZE)) {
 469         stl_le_p(s->mem + addr, val);
 470     }
 471 }
 472
 473 static inline uint32_t ne2000_mem_readb(NE2000State *s, uint32_t addr)
 474 {
 475     if (addr < 32 ||
 476         (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
 477         return s->mem[addr];
 478     } else {
 479         return 0xff;
 480     }
 481 }
 482
 483 static inline uint32_t ne2000_mem_readw(NE2000State *s, uint32_t addr)
 484 {
 485     addr &= ~1; /* XXX: check exact behaviour if not even */
 486     if (addr < 32 ||
 487         (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
 488         return le16_to_cpu(*(uint16_t *)(s->mem + addr));
 489     } else {
 490         return 0xffff;
 491     }
 492 }
 493
 494 static inline uint32_t ne2000_mem_readl(NE2000State *s, uint32_t addr)
 495 {
 496     addr &= ~1; /* XXX: check exact behaviour if not even */
 497     if (addr < 32
 498         || (addr >= NE2000_PMEM_START
 499             && addr + sizeof(uint32_t) <= NE2000_MEM_SIZE)) {
 500         return ldl_le_p(s->mem + addr);
 501     } else {
 502         return 0xffffffff;
 503     }
 504 }
 505
 506 static inline void ne2000_dma_update(NE2000State *s, int len)
 507 {
 508     s->rsar += len;
 509     /* wrap */
 510     /* XXX: check what to do if rsar > stop */
 511     if (s->rsar == s->stop)
 512         s->rsar = s->start;
 513
 514     if (s->rcnt <= len) {
 515         s->rcnt = 0;
 516         /* signal end of transfer */
 517         s->isr |= ENISR_RDC;
 518         ne2000_update_irq(s);
 519     } else {
 520         s->rcnt -= len;
 521     }
 522 }
 523
 524 static void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 525 {
 526     NE2000State *s = opaque;
 527
 528 #ifdef DEBUG_NE2000
 529     printf("NE2000: asic write val=0x%04x\n", val);
 530 #endif
 531     if (s->rcnt == 0)
 532         return;
 533     if (s->dcfg & 0x01) {
 534         /* 16 bit access */
 535         ne2000_mem_writew(s, s->rsar, val);
 536         ne2000_dma_update(s, 2);
 537     } else {
 538         /* 8 bit access */
 539         ne2000_mem_writeb(s, s->rsar, val);
 540         ne2000_dma_update(s, 1);
 541     }
 542 }
 543
 544 static uint32_t ne2000_asic_ioport_read(void *opaque, uint32_t addr)
 545 {
 546     NE2000State *s = opaque;
 547     int ret;
 548
 549     if (s->dcfg & 0x01) {
 550         /* 16 bit access */
 551         ret = ne2000_mem_readw(s, s->rsar);
 552         ne2000_dma_update(s, 2);
 553     } else {
 554         /* 8 bit access */
 555         ret = ne2000_mem_readb(s, s->rsar);
 556         ne2000_dma_update(s, 1);
 557     }
 558 #ifdef DEBUG_NE2000
 559     printf("NE2000: asic read val=0x%04x\n", ret);
 560 #endif
 561     return ret;
 562 }
 563
 564 static void ne2000_asic_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
 565 {
 566     NE2000State *s = opaque;
 567
 568 #ifdef DEBUG_NE2000
 569     printf("NE2000: asic writel val=0x%04x\n", val);
 570 #endif
 571     if (s->rcnt == 0)
 572         return;
 573     /* 32 bit access */
 574     ne2000_mem_writel(s, s->rsar, val);
 575     ne2000_dma_update(s, 4);
 576 }
 577
 578 static uint32_t ne2000_asic_ioport_readl(void *opaque, uint32_t addr)
 579 {
 580     NE2000State *s = opaque;
 581     int ret;
 582
 583     /* 32 bit access */
 584     ret = ne2000_mem_readl(s, s->rsar);
 585     ne2000_dma_update(s, 4);
 586 #ifdef DEBUG_NE2000
 587     printf("NE2000: asic readl val=0x%04x\n", ret);
 588 #endif
 589     return ret;
 590 }
 591
 592 static void ne2000_reset_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 593 {
 594     /* nothing to do (end of reset pulse) */
 595 }
 596
 597 static uint32_t ne2000_reset_ioport_read(void *opaque, uint32_t addr)
 598 {
 599     NE2000State *s = opaque;
 600     ne2000_reset(s);
 601     return 0;
 602 }
 603
 604 static int ne2000_post_load(void* opaque, int version_id)
 605 {
 606     NE2000State* s = opaque;
 607
 608     if (version_id < 2) {
 609         s->rxcr = 0x0c;
 610     }
 611     return 0;
 612 }
 613
 614 const VMStateDescription vmstate_ne2000 = {
 615     .name = "ne2000",
 616     .version_id = 2,
 617     .minimum_version_id = 0,
 618     .post_load = ne2000_post_load,
 619     .fields = (VMStateField[]) {
 620         VMSTATE_UINT8_V(rxcr, NE2000State, 2),
 621         VMSTATE_UINT8(cmd, NE2000State),
 622         VMSTATE_UINT32(start, NE2000State),
 623         VMSTATE_UINT32(stop, NE2000State),
 624         VMSTATE_UINT8(boundary, NE2000State),
 625         VMSTATE_UINT8(tsr, NE2000State),
 626         VMSTATE_UINT8(tpsr, NE2000State),
 627         VMSTATE_UINT16(tcnt, NE2000State),
 628         VMSTATE_UINT16(rcnt, NE2000State),
 629         VMSTATE_UINT32(rsar, NE2000State),
 630         VMSTATE_UINT8(rsr, NE2000State),
 631         VMSTATE_UINT8(isr, NE2000State),
 632         VMSTATE_UINT8(dcfg, NE2000State),
 633         VMSTATE_UINT8(imr, NE2000State),
 634         VMSTATE_BUFFER(phys, NE2000State),
 635         VMSTATE_UINT8(curpag, NE2000State),
 636         VMSTATE_BUFFER(mult, NE2000State),
 637         VMSTATE_UNUSED(4), /* was irq */
 638         VMSTATE_BUFFER(mem, NE2000State),
 639         VMSTATE_END_OF_LIST()
 640     }
 641 };
 642
 643 static uint64_t ne2000_read(void *opaque, hwaddr addr,
 644                             unsigned size)
 645 {
 646     NE2000State *s = opaque;
 647     uint64_t val;
 648
 649     if (addr < 0x10 && size == 1) {
 650         val = ne2000_ioport_read(s, addr);
 651     } else if (addr == 0x10) {
 652         if (size <= 2) {
 653             val = ne2000_asic_ioport_read(s, addr);
 654         } else {
 655             val = ne2000_asic_ioport_readl(s, addr);
 656         }
 657     } else if (addr == 0x1f && size == 1) {
 658         val = ne2000_reset_ioport_read(s, addr);
 659     } else {
 660         val = ((uint64_t)1 << (size * 8)) - 1;
 661     }
 662     trace_ne2000_read(addr, val);
 663
 664     return val;
 665 }
 666
 667 static void ne2000_write(void *opaque, hwaddr addr,
 668                          uint64_t data, unsigned size)
 669 {
 670     NE2000State *s = opaque;
 671
 672     trace_ne2000_write(addr, data);
 673     if (addr < 0x10 && size == 1) {
 674         ne2000_ioport_write(s, addr, data);
 675     } else if (addr == 0x10) {
 676         if (size <= 2) {
 677             ne2000_asic_ioport_write(s, addr, data);
 678         } else {
 679             ne2000_asic_ioport_writel(s, addr, data);
 680         }
 681     } else if (addr == 0x1f && size == 1) {
 682         ne2000_reset_ioport_write(s, addr, data);
 683     }
 684 }
 685
 686 static const MemoryRegionOps ne2000_ops = {
 687     .read = ne2000_read,
 688     .write = ne2000_write,
 689     .endianness = DEVICE_LITTLE_ENDIAN,
 690 };
 691
 692 /***********************************************************/
 693 /* PCI NE2000 definitions */
 694
 695 void ne2000_setup_io(NE2000State *s, DeviceState *dev, unsigned size)
 696 {
 697     memory_region_init_io(&s->io, OBJECT(dev), &ne2000_ops, s, "ne2000", size);
 698 }