2 * QEMU Sun Happy Meal Ethernet emulation
4 * Copyright (c) 2017 Mark Cave-Ayland
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
27 #include "hw/pci/pci.h"
28 #include "hw/net/mii.h"
30 #include "qemu/module.h"
31 #include "net/checksum.h"
33 #include "sysemu/sysemu.h"
36 #define HME_REG_SIZE 0x8000
38 #define HME_SEB_REG_SIZE 0x2000
40 #define HME_SEBI_RESET 0x0
41 #define HME_SEB_RESET_ETX 0x1
42 #define HME_SEB_RESET_ERX 0x2
44 #define HME_SEBI_STAT 0x100
45 #define HME_SEBI_STAT_LINUXBUG 0x108
46 #define HME_SEB_STAT_RXTOHOST 0x10000
47 #define HME_SEB_STAT_MIFIRQ 0x800000
48 #define HME_SEB_STAT_HOSTTOTX 0x1000000
49 #define HME_SEB_STAT_TXALL 0x2000000
51 #define HME_SEBI_IMASK 0x104
52 #define HME_SEBI_IMASK_LINUXBUG 0x10c
54 #define HME_ETX_REG_SIZE 0x2000
56 #define HME_ETXI_PENDING 0x0
58 #define HME_ETXI_RING 0x8
59 #define HME_ETXI_RING_ADDR 0xffffff00
60 #define HME_ETXI_RING_OFFSET 0xff
62 #define HME_ETXI_RSIZE 0x2c
64 #define HME_ERX_REG_SIZE 0x2000
66 #define HME_ERXI_CFG 0x0
67 #define HME_ERX_CFG_RINGSIZE 0x600
68 #define HME_ERX_CFG_RINGSIZE_SHIFT 9
69 #define HME_ERX_CFG_BYTEOFFSET 0x38
70 #define HME_ERX_CFG_BYTEOFFSET_SHIFT 3
71 #define HME_ERX_CFG_CSUMSTART 0x7f0000
72 #define HME_ERX_CFG_CSUMSHIFT 16
74 #define HME_ERXI_RING 0x4
75 #define HME_ERXI_RING_ADDR 0xffffff00
76 #define HME_ERXI_RING_OFFSET 0xff
78 #define HME_MAC_REG_SIZE 0x1000
80 #define HME_MACI_TXCFG 0x20c
81 #define HME_MAC_TXCFG_ENABLE 0x1
83 #define HME_MACI_RXCFG 0x30c
84 #define HME_MAC_RXCFG_ENABLE 0x1
85 #define HME_MAC_RXCFG_PMISC 0x40
86 #define HME_MAC_RXCFG_HENABLE 0x800
88 #define HME_MACI_MACADDR2 0x318
89 #define HME_MACI_MACADDR1 0x31c
90 #define HME_MACI_MACADDR0 0x320
92 #define HME_MACI_HASHTAB3 0x340
93 #define HME_MACI_HASHTAB2 0x344
94 #define HME_MACI_HASHTAB1 0x348
95 #define HME_MACI_HASHTAB0 0x34c
97 #define HME_MIF_REG_SIZE 0x20
99 #define HME_MIFI_FO 0xc
100 #define HME_MIF_FO_ST 0xc0000000
101 #define HME_MIF_FO_ST_SHIFT 30
102 #define HME_MIF_FO_OPC 0x30000000
103 #define HME_MIF_FO_OPC_SHIFT 28
104 #define HME_MIF_FO_PHYAD 0x0f800000
105 #define HME_MIF_FO_PHYAD_SHIFT 23
106 #define HME_MIF_FO_REGAD 0x007c0000
107 #define HME_MIF_FO_REGAD_SHIFT 18
108 #define HME_MIF_FO_TAMSB 0x20000
109 #define HME_MIF_FO_TALSB 0x10000
110 #define HME_MIF_FO_DATA 0xffff
112 #define HME_MIFI_CFG 0x10
113 #define HME_MIF_CFG_MDI0 0x100
114 #define HME_MIF_CFG_MDI1 0x200
116 #define HME_MIFI_IMASK 0x14
118 #define HME_MIFI_STAT 0x18
121 /* Wired HME PHY addresses */
122 #define HME_PHYAD_INTERNAL 1
123 #define HME_PHYAD_EXTERNAL 0
125 #define MII_COMMAND_START 0x1
126 #define MII_COMMAND_READ 0x2
127 #define MII_COMMAND_WRITE 0x1
129 #define TYPE_SUNHME "sunhme"
130 #define SUNHME(obj) OBJECT_CHECK(SunHMEState, (obj), TYPE_SUNHME)
132 /* Maximum size of buffer */
133 #define HME_FIFO_SIZE 0x800
135 /* Size of TX/RX descriptor */
136 #define HME_DESC_SIZE 0x8
138 #define HME_XD_OWN 0x80000000
139 #define HME_XD_OFL 0x40000000
140 #define HME_XD_SOP 0x40000000
141 #define HME_XD_EOP 0x20000000
142 #define HME_XD_RXLENMSK 0x3fff0000
143 #define HME_XD_RXLENSHIFT 16
144 #define HME_XD_RXCKSUM 0xffff
145 #define HME_XD_TXLENMSK 0x00001fff
146 #define HME_XD_TXCKSUM 0x10000000
147 #define HME_XD_TXCSSTUFF 0xff00000
148 #define HME_XD_TXCSSTUFFSHIFT 20
149 #define HME_XD_TXCSSTART 0xfc000
150 #define HME_XD_TXCSSTARTSHIFT 14
152 #define HME_MII_REGS_SIZE 0x20
154 typedef struct SunHMEState
{
156 PCIDevice parent_obj
;
168 uint32_t sebregs
[HME_SEB_REG_SIZE
>> 2];
169 uint32_t etxregs
[HME_ETX_REG_SIZE
>> 2];
170 uint32_t erxregs
[HME_ERX_REG_SIZE
>> 2];
171 uint32_t macregs
[HME_MAC_REG_SIZE
>> 2];
172 uint32_t mifregs
[HME_MIF_REG_SIZE
>> 2];
174 uint16_t miiregs
[HME_MII_REGS_SIZE
];
177 static Property sunhme_properties
[] = {
178 DEFINE_NIC_PROPERTIES(SunHMEState
, conf
),
179 DEFINE_PROP_END_OF_LIST(),
182 static void sunhme_reset_tx(SunHMEState
*s
)
184 /* Indicate TX reset complete */
185 s
->sebregs
[HME_SEBI_RESET
] &= ~HME_SEB_RESET_ETX
;
188 static void sunhme_reset_rx(SunHMEState
*s
)
190 /* Indicate RX reset complete */
191 s
->sebregs
[HME_SEBI_RESET
] &= ~HME_SEB_RESET_ERX
;
194 static void sunhme_update_irq(SunHMEState
*s
)
196 PCIDevice
*d
= PCI_DEVICE(s
);
199 /* MIF interrupt mask (16-bit) */
200 uint32_t mifmask
= ~(s
->mifregs
[HME_MIFI_IMASK
>> 2]) & 0xffff;
201 uint32_t mif
= s
->mifregs
[HME_MIFI_STAT
>> 2] & mifmask
;
203 /* Main SEB interrupt mask (include MIF status from above) */
204 uint32_t sebmask
= ~(s
->sebregs
[HME_SEBI_IMASK
>> 2]) &
205 ~HME_SEB_STAT_MIFIRQ
;
206 uint32_t seb
= s
->sebregs
[HME_SEBI_STAT
>> 2] & sebmask
;
208 seb
|= HME_SEB_STAT_MIFIRQ
;
211 level
= (seb
? 1 : 0);
212 pci_set_irq(d
, level
);
215 static void sunhme_seb_write(void *opaque
, hwaddr addr
,
216 uint64_t val
, unsigned size
)
218 SunHMEState
*s
= SUNHME(opaque
);
220 trace_sunhme_seb_write(addr
, val
);
222 /* Handly buggy Linux drivers before 4.13 which have
223 the wrong offsets for HME_SEBI_STAT and HME_SEBI_IMASK */
225 case HME_SEBI_STAT_LINUXBUG
:
226 addr
= HME_SEBI_STAT
;
228 case HME_SEBI_IMASK_LINUXBUG
:
229 addr
= HME_SEBI_IMASK
;
237 if (val
& HME_SEB_RESET_ETX
) {
240 if (val
& HME_SEB_RESET_ERX
) {
243 val
= s
->sebregs
[HME_SEBI_RESET
>> 2];
247 s
->sebregs
[addr
>> 2] = val
;
250 static uint64_t sunhme_seb_read(void *opaque
, hwaddr addr
,
253 SunHMEState
*s
= SUNHME(opaque
);
256 /* Handly buggy Linux drivers before 4.13 which have
257 the wrong offsets for HME_SEBI_STAT and HME_SEBI_IMASK */
259 case HME_SEBI_STAT_LINUXBUG
:
260 addr
= HME_SEBI_STAT
;
262 case HME_SEBI_IMASK_LINUXBUG
:
263 addr
= HME_SEBI_IMASK
;
269 val
= s
->sebregs
[addr
>> 2];
273 /* Autoclear status (except MIF) */
274 s
->sebregs
[HME_SEBI_STAT
>> 2] &= HME_SEB_STAT_MIFIRQ
;
275 sunhme_update_irq(s
);
279 trace_sunhme_seb_read(addr
, val
);
284 static const MemoryRegionOps sunhme_seb_ops
= {
285 .read
= sunhme_seb_read
,
286 .write
= sunhme_seb_write
,
287 .endianness
= DEVICE_LITTLE_ENDIAN
,
289 .min_access_size
= 4,
290 .max_access_size
= 4,
294 static void sunhme_transmit(SunHMEState
*s
);
296 static void sunhme_etx_write(void *opaque
, hwaddr addr
,
297 uint64_t val
, unsigned size
)
299 SunHMEState
*s
= SUNHME(opaque
);
301 trace_sunhme_etx_write(addr
, val
);
304 case HME_ETXI_PENDING
:
311 s
->etxregs
[addr
>> 2] = val
;
314 static uint64_t sunhme_etx_read(void *opaque
, hwaddr addr
,
317 SunHMEState
*s
= SUNHME(opaque
);
320 val
= s
->etxregs
[addr
>> 2];
322 trace_sunhme_etx_read(addr
, val
);
327 static const MemoryRegionOps sunhme_etx_ops
= {
328 .read
= sunhme_etx_read
,
329 .write
= sunhme_etx_write
,
330 .endianness
= DEVICE_LITTLE_ENDIAN
,
332 .min_access_size
= 4,
333 .max_access_size
= 4,
337 static void sunhme_erx_write(void *opaque
, hwaddr addr
,
338 uint64_t val
, unsigned size
)
340 SunHMEState
*s
= SUNHME(opaque
);
342 trace_sunhme_erx_write(addr
, val
);
344 s
->erxregs
[addr
>> 2] = val
;
347 static uint64_t sunhme_erx_read(void *opaque
, hwaddr addr
,
350 SunHMEState
*s
= SUNHME(opaque
);
353 val
= s
->erxregs
[addr
>> 2];
355 trace_sunhme_erx_read(addr
, val
);
360 static const MemoryRegionOps sunhme_erx_ops
= {
361 .read
= sunhme_erx_read
,
362 .write
= sunhme_erx_write
,
363 .endianness
= DEVICE_LITTLE_ENDIAN
,
365 .min_access_size
= 4,
366 .max_access_size
= 4,
370 static void sunhme_mac_write(void *opaque
, hwaddr addr
,
371 uint64_t val
, unsigned size
)
373 SunHMEState
*s
= SUNHME(opaque
);
375 trace_sunhme_mac_write(addr
, val
);
377 s
->macregs
[addr
>> 2] = val
;
380 static uint64_t sunhme_mac_read(void *opaque
, hwaddr addr
,
383 SunHMEState
*s
= SUNHME(opaque
);
386 val
= s
->macregs
[addr
>> 2];
388 trace_sunhme_mac_read(addr
, val
);
393 static const MemoryRegionOps sunhme_mac_ops
= {
394 .read
= sunhme_mac_read
,
395 .write
= sunhme_mac_write
,
396 .endianness
= DEVICE_LITTLE_ENDIAN
,
398 .min_access_size
= 4,
399 .max_access_size
= 4,
403 static void sunhme_mii_write(SunHMEState
*s
, uint8_t reg
, uint16_t data
)
405 trace_sunhme_mii_write(reg
, data
);
409 if (data
& MII_BMCR_RESET
) {
410 /* Autoclear reset bit, enable auto negotiation */
411 data
&= ~MII_BMCR_RESET
;
412 data
|= MII_BMCR_AUTOEN
;
414 if (data
& MII_BMCR_ANRESTART
) {
415 /* Autoclear auto negotiation restart */
416 data
&= ~MII_BMCR_ANRESTART
;
418 /* Indicate negotiation complete */
419 s
->miiregs
[MII_BMSR
] |= MII_BMSR_AN_COMP
;
421 if (!qemu_get_queue(s
->nic
)->link_down
) {
422 s
->miiregs
[MII_ANLPAR
] |= MII_ANLPAR_TXFD
;
423 s
->miiregs
[MII_BMSR
] |= MII_BMSR_LINK_ST
;
429 s
->miiregs
[reg
] = data
;
432 static uint16_t sunhme_mii_read(SunHMEState
*s
, uint8_t reg
)
434 uint16_t data
= s
->miiregs
[reg
];
436 trace_sunhme_mii_read(reg
, data
);
441 static void sunhme_mif_write(void *opaque
, hwaddr addr
,
442 uint64_t val
, unsigned size
)
444 SunHMEState
*s
= SUNHME(opaque
);
448 trace_sunhme_mif_write(addr
, val
);
452 /* Mask the read-only bits */
453 val
&= ~(HME_MIF_CFG_MDI0
| HME_MIF_CFG_MDI1
);
454 val
|= s
->mifregs
[HME_MIFI_CFG
>> 2] &
455 (HME_MIF_CFG_MDI0
| HME_MIF_CFG_MDI1
);
458 /* Detect start of MII command */
459 if ((val
& HME_MIF_FO_ST
) >> HME_MIF_FO_ST_SHIFT
460 != MII_COMMAND_START
) {
461 val
|= HME_MIF_FO_TALSB
;
465 /* Internal phy only */
466 if ((val
& HME_MIF_FO_PHYAD
) >> HME_MIF_FO_PHYAD_SHIFT
467 != HME_PHYAD_INTERNAL
) {
468 val
|= HME_MIF_FO_TALSB
;
472 cmd
= (val
& HME_MIF_FO_OPC
) >> HME_MIF_FO_OPC_SHIFT
;
473 reg
= (val
& HME_MIF_FO_REGAD
) >> HME_MIF_FO_REGAD_SHIFT
;
474 data
= (val
& HME_MIF_FO_DATA
);
477 case MII_COMMAND_WRITE
:
478 sunhme_mii_write(s
, reg
, data
);
481 case MII_COMMAND_READ
:
482 val
&= ~HME_MIF_FO_DATA
;
483 val
|= sunhme_mii_read(s
, reg
);
487 val
|= HME_MIF_FO_TALSB
;
491 s
->mifregs
[addr
>> 2] = val
;
494 static uint64_t sunhme_mif_read(void *opaque
, hwaddr addr
,
497 SunHMEState
*s
= SUNHME(opaque
);
500 val
= s
->mifregs
[addr
>> 2];
504 /* Autoclear MIF interrupt status */
505 s
->mifregs
[HME_MIFI_STAT
>> 2] = 0;
506 sunhme_update_irq(s
);
510 trace_sunhme_mif_read(addr
, val
);
515 static const MemoryRegionOps sunhme_mif_ops
= {
516 .read
= sunhme_mif_read
,
517 .write
= sunhme_mif_write
,
518 .endianness
= DEVICE_LITTLE_ENDIAN
,
520 .min_access_size
= 4,
521 .max_access_size
= 4,
525 static void sunhme_transmit_frame(SunHMEState
*s
, uint8_t *buf
, int size
)
527 qemu_send_packet(qemu_get_queue(s
->nic
), buf
, size
);
530 static inline int sunhme_get_tx_ring_count(SunHMEState
*s
)
532 return (s
->etxregs
[HME_ETXI_RSIZE
>> 2] + 1) << 4;
535 static inline int sunhme_get_tx_ring_nr(SunHMEState
*s
)
537 return s
->etxregs
[HME_ETXI_RING
>> 2] & HME_ETXI_RING_OFFSET
;
540 static inline void sunhme_set_tx_ring_nr(SunHMEState
*s
, int i
)
542 uint32_t ring
= s
->etxregs
[HME_ETXI_RING
>> 2] & ~HME_ETXI_RING_OFFSET
;
543 ring
|= i
& HME_ETXI_RING_OFFSET
;
545 s
->etxregs
[HME_ETXI_RING
>> 2] = ring
;
548 static void sunhme_transmit(SunHMEState
*s
)
550 PCIDevice
*d
= PCI_DEVICE(s
);
552 uint32_t intstatus
, status
, buffer
, sum
= 0;
553 int cr
, nr
, len
, xmit_pos
, csum_offset
= 0, csum_stuff_offset
= 0;
555 uint8_t xmit_buffer
[HME_FIFO_SIZE
];
557 tb
= s
->etxregs
[HME_ETXI_RING
>> 2] & HME_ETXI_RING_ADDR
;
558 nr
= sunhme_get_tx_ring_count(s
);
559 cr
= sunhme_get_tx_ring_nr(s
);
561 pci_dma_read(d
, tb
+ cr
* HME_DESC_SIZE
, &status
, 4);
562 pci_dma_read(d
, tb
+ cr
* HME_DESC_SIZE
+ 4, &buffer
, 4);
565 while (status
& HME_XD_OWN
) {
566 trace_sunhme_tx_desc(buffer
, status
, cr
, nr
);
568 /* Copy data into transmit buffer */
570 len
= status
& HME_XD_TXLENMSK
;
572 if (xmit_pos
+ len
> HME_FIFO_SIZE
) {
573 len
= HME_FIFO_SIZE
- xmit_pos
;
576 pci_dma_read(d
, addr
, &xmit_buffer
[xmit_pos
], len
);
579 /* Detect start of packet for TX checksum */
580 if (status
& HME_XD_SOP
) {
582 csum_offset
= (status
& HME_XD_TXCSSTART
) >> HME_XD_TXCSSTARTSHIFT
;
583 csum_stuff_offset
= (status
& HME_XD_TXCSSTUFF
) >>
584 HME_XD_TXCSSTUFFSHIFT
;
587 if (status
& HME_XD_TXCKSUM
) {
588 /* Only start calculation from csum_offset */
589 if (xmit_pos
- len
<= csum_offset
&& xmit_pos
> csum_offset
) {
590 sum
+= net_checksum_add(xmit_pos
- csum_offset
,
591 xmit_buffer
+ csum_offset
);
592 trace_sunhme_tx_xsum_add(csum_offset
, xmit_pos
- csum_offset
);
594 sum
+= net_checksum_add(len
, xmit_buffer
+ xmit_pos
- len
);
595 trace_sunhme_tx_xsum_add(xmit_pos
- len
, len
);
599 /* Detect end of packet for TX checksum */
600 if (status
& HME_XD_EOP
) {
601 /* Stuff the checksum if required */
602 if (status
& HME_XD_TXCKSUM
) {
603 csum
= net_checksum_finish(sum
);
604 stw_be_p(xmit_buffer
+ csum_stuff_offset
, csum
);
605 trace_sunhme_tx_xsum_stuff(csum
, csum_stuff_offset
);
608 if (s
->macregs
[HME_MACI_TXCFG
>> 2] & HME_MAC_TXCFG_ENABLE
) {
609 sunhme_transmit_frame(s
, xmit_buffer
, xmit_pos
);
610 trace_sunhme_tx_done(xmit_pos
);
615 status
&= ~HME_XD_OWN
;
616 pci_dma_write(d
, tb
+ cr
* HME_DESC_SIZE
, &status
, 4);
618 /* Move onto next descriptor */
623 sunhme_set_tx_ring_nr(s
, cr
);
625 pci_dma_read(d
, tb
+ cr
* HME_DESC_SIZE
, &status
, 4);
626 pci_dma_read(d
, tb
+ cr
* HME_DESC_SIZE
+ 4, &buffer
, 4);
628 /* Indicate TX complete */
629 intstatus
= s
->sebregs
[HME_SEBI_STAT
>> 2];
630 intstatus
|= HME_SEB_STAT_HOSTTOTX
;
631 s
->sebregs
[HME_SEBI_STAT
>> 2] = intstatus
;
633 /* Autoclear TX pending */
634 s
->etxregs
[HME_ETXI_PENDING
>> 2] = 0;
636 sunhme_update_irq(s
);
639 /* TX FIFO now clear */
640 intstatus
= s
->sebregs
[HME_SEBI_STAT
>> 2];
641 intstatus
|= HME_SEB_STAT_TXALL
;
642 s
->sebregs
[HME_SEBI_STAT
>> 2] = intstatus
;
643 sunhme_update_irq(s
);
646 static int sunhme_can_receive(NetClientState
*nc
)
648 SunHMEState
*s
= qemu_get_nic_opaque(nc
);
650 return s
->macregs
[HME_MAC_RXCFG_ENABLE
>> 2] & HME_MAC_RXCFG_ENABLE
;
653 static void sunhme_link_status_changed(NetClientState
*nc
)
655 SunHMEState
*s
= qemu_get_nic_opaque(nc
);
658 s
->miiregs
[MII_ANLPAR
] &= ~MII_ANLPAR_TXFD
;
659 s
->miiregs
[MII_BMSR
] &= ~MII_BMSR_LINK_ST
;
661 s
->miiregs
[MII_ANLPAR
] |= MII_ANLPAR_TXFD
;
662 s
->miiregs
[MII_BMSR
] |= MII_BMSR_LINK_ST
;
665 /* Exact bits unknown */
666 s
->mifregs
[HME_MIFI_STAT
>> 2] = 0xffff;
667 sunhme_update_irq(s
);
670 static inline int sunhme_get_rx_ring_count(SunHMEState
*s
)
672 uint32_t rings
= (s
->erxregs
[HME_ERXI_CFG
>> 2] & HME_ERX_CFG_RINGSIZE
)
673 >> HME_ERX_CFG_RINGSIZE_SHIFT
;
689 static inline int sunhme_get_rx_ring_nr(SunHMEState
*s
)
691 return s
->erxregs
[HME_ERXI_RING
>> 2] & HME_ERXI_RING_OFFSET
;
694 static inline void sunhme_set_rx_ring_nr(SunHMEState
*s
, int i
)
696 uint32_t ring
= s
->erxregs
[HME_ERXI_RING
>> 2] & ~HME_ERXI_RING_OFFSET
;
697 ring
|= i
& HME_ERXI_RING_OFFSET
;
699 s
->erxregs
[HME_ERXI_RING
>> 2] = ring
;
702 #define MIN_BUF_SIZE 60
704 static ssize_t
sunhme_receive(NetClientState
*nc
, const uint8_t *buf
,
707 SunHMEState
*s
= qemu_get_nic_opaque(nc
);
708 PCIDevice
*d
= PCI_DEVICE(s
);
710 uint32_t intstatus
, status
, buffer
, buffersize
, sum
;
713 int nr
, cr
, len
, rxoffset
, csum_offset
;
715 trace_sunhme_rx_incoming(size
);
717 /* Do nothing if MAC RX disabled */
718 if (!(s
->macregs
[HME_MACI_RXCFG
>> 2] & HME_MAC_RXCFG_ENABLE
)) {
722 trace_sunhme_rx_filter_destmac(buf
[0], buf
[1], buf
[2],
723 buf
[3], buf
[4], buf
[5]);
725 /* Check destination MAC address */
726 if (!(s
->macregs
[HME_MACI_RXCFG
>> 2] & HME_MAC_RXCFG_PMISC
)) {
727 /* Try and match local MAC address */
728 if (((s
->macregs
[HME_MACI_MACADDR0
>> 2] & 0xff00) >> 8) == buf
[0] &&
729 (s
->macregs
[HME_MACI_MACADDR0
>> 2] & 0xff) == buf
[1] &&
730 ((s
->macregs
[HME_MACI_MACADDR1
>> 2] & 0xff00) >> 8) == buf
[2] &&
731 (s
->macregs
[HME_MACI_MACADDR1
>> 2] & 0xff) == buf
[3] &&
732 ((s
->macregs
[HME_MACI_MACADDR2
>> 2] & 0xff00) >> 8) == buf
[4] &&
733 (s
->macregs
[HME_MACI_MACADDR2
>> 2] & 0xff) == buf
[5]) {
734 /* Matched local MAC address */
735 trace_sunhme_rx_filter_local_match();
736 } else if (buf
[0] == 0xff && buf
[1] == 0xff && buf
[2] == 0xff &&
737 buf
[3] == 0xff && buf
[4] == 0xff && buf
[5] == 0xff) {
738 /* Matched broadcast address */
739 trace_sunhme_rx_filter_bcast_match();
740 } else if (s
->macregs
[HME_MACI_RXCFG
>> 2] & HME_MAC_RXCFG_HENABLE
) {
741 /* Didn't match local address, check hash filter */
742 int mcast_idx
= net_crc32_le(buf
, ETH_ALEN
) >> 26;
743 if (!(s
->macregs
[(HME_MACI_HASHTAB0
>> 2) - (mcast_idx
>> 4)] &
744 (1 << (mcast_idx
& 0xf)))) {
745 /* Didn't match hash filter */
746 trace_sunhme_rx_filter_hash_nomatch();
747 trace_sunhme_rx_filter_reject();
750 trace_sunhme_rx_filter_hash_match();
754 trace_sunhme_rx_filter_reject();
758 trace_sunhme_rx_filter_promisc_match();
761 trace_sunhme_rx_filter_accept();
763 /* If too small buffer, then expand it */
764 if (size
< MIN_BUF_SIZE
) {
765 memcpy(buf1
, buf
, size
);
766 memset(buf1
+ size
, 0, MIN_BUF_SIZE
- size
);
771 rb
= s
->erxregs
[HME_ERXI_RING
>> 2] & HME_ERXI_RING_ADDR
;
772 nr
= sunhme_get_rx_ring_count(s
);
773 cr
= sunhme_get_rx_ring_nr(s
);
775 pci_dma_read(d
, rb
+ cr
* HME_DESC_SIZE
, &status
, 4);
776 pci_dma_read(d
, rb
+ cr
* HME_DESC_SIZE
+ 4, &buffer
, 4);
778 rxoffset
= (s
->erxregs
[HME_ERXI_CFG
>> 2] & HME_ERX_CFG_BYTEOFFSET
) >>
779 HME_ERX_CFG_BYTEOFFSET_SHIFT
;
781 addr
= buffer
+ rxoffset
;
782 buffersize
= (status
& HME_XD_RXLENMSK
) >> HME_XD_RXLENSHIFT
;
784 /* Detect receive overflow */
786 if (size
> buffersize
) {
787 status
|= HME_XD_OFL
;
791 pci_dma_write(d
, addr
, buf
, len
);
793 trace_sunhme_rx_desc(buffer
, rxoffset
, status
, len
, cr
, nr
);
795 /* Calculate the receive checksum */
796 csum_offset
= (s
->erxregs
[HME_ERXI_CFG
>> 2] & HME_ERX_CFG_CSUMSTART
) >>
797 HME_ERX_CFG_CSUMSHIFT
<< 1;
799 sum
+= net_checksum_add(len
- csum_offset
, (uint8_t *)buf
+ csum_offset
);
800 csum
= net_checksum_finish(sum
);
802 trace_sunhme_rx_xsum_calc(csum
);
805 status
&= ~HME_XD_OWN
;
806 status
&= ~HME_XD_RXLENMSK
;
807 status
|= len
<< HME_XD_RXLENSHIFT
;
808 status
&= ~HME_XD_RXCKSUM
;
811 pci_dma_write(d
, rb
+ cr
* HME_DESC_SIZE
, &status
, 4);
818 sunhme_set_rx_ring_nr(s
, cr
);
820 /* Indicate RX complete */
821 intstatus
= s
->sebregs
[HME_SEBI_STAT
>> 2];
822 intstatus
|= HME_SEB_STAT_RXTOHOST
;
823 s
->sebregs
[HME_SEBI_STAT
>> 2] = intstatus
;
825 sunhme_update_irq(s
);
830 static NetClientInfo net_sunhme_info
= {
831 .type
= NET_CLIENT_DRIVER_NIC
,
832 .size
= sizeof(NICState
),
833 .can_receive
= sunhme_can_receive
,
834 .receive
= sunhme_receive
,
835 .link_status_changed
= sunhme_link_status_changed
,
838 static void sunhme_realize(PCIDevice
*pci_dev
, Error
**errp
)
840 SunHMEState
*s
= SUNHME(pci_dev
);
841 DeviceState
*d
= DEVICE(pci_dev
);
844 pci_conf
= pci_dev
->config
;
845 pci_conf
[PCI_INTERRUPT_PIN
] = 1; /* interrupt pin A */
847 memory_region_init(&s
->hme
, OBJECT(pci_dev
), "sunhme", HME_REG_SIZE
);
848 pci_register_bar(pci_dev
, 0, PCI_BASE_ADDRESS_SPACE_MEMORY
, &s
->hme
);
850 memory_region_init_io(&s
->sebreg
, OBJECT(pci_dev
), &sunhme_seb_ops
, s
,
851 "sunhme.seb", HME_SEB_REG_SIZE
);
852 memory_region_add_subregion(&s
->hme
, 0, &s
->sebreg
);
854 memory_region_init_io(&s
->etxreg
, OBJECT(pci_dev
), &sunhme_etx_ops
, s
,
855 "sunhme.etx", HME_ETX_REG_SIZE
);
856 memory_region_add_subregion(&s
->hme
, 0x2000, &s
->etxreg
);
858 memory_region_init_io(&s
->erxreg
, OBJECT(pci_dev
), &sunhme_erx_ops
, s
,
859 "sunhme.erx", HME_ERX_REG_SIZE
);
860 memory_region_add_subregion(&s
->hme
, 0x4000, &s
->erxreg
);
862 memory_region_init_io(&s
->macreg
, OBJECT(pci_dev
), &sunhme_mac_ops
, s
,
863 "sunhme.mac", HME_MAC_REG_SIZE
);
864 memory_region_add_subregion(&s
->hme
, 0x6000, &s
->macreg
);
866 memory_region_init_io(&s
->mifreg
, OBJECT(pci_dev
), &sunhme_mif_ops
, s
,
867 "sunhme.mif", HME_MIF_REG_SIZE
);
868 memory_region_add_subregion(&s
->hme
, 0x7000, &s
->mifreg
);
870 qemu_macaddr_default_if_unset(&s
->conf
.macaddr
);
871 s
->nic
= qemu_new_nic(&net_sunhme_info
, &s
->conf
,
872 object_get_typename(OBJECT(d
)), d
->id
, s
);
873 qemu_format_nic_info_str(qemu_get_queue(s
->nic
), s
->conf
.macaddr
.a
);
876 static void sunhme_instance_init(Object
*obj
)
878 SunHMEState
*s
= SUNHME(obj
);
880 device_add_bootindex_property(obj
, &s
->conf
.bootindex
,
881 "bootindex", "/ethernet-phy@0",
885 static void sunhme_reset(DeviceState
*ds
)
887 SunHMEState
*s
= SUNHME(ds
);
889 /* Configure internal transceiver */
890 s
->mifregs
[HME_MIFI_CFG
>> 2] |= HME_MIF_CFG_MDI0
;
892 /* Advetise auto, 100Mbps FD */
893 s
->miiregs
[MII_ANAR
] = MII_ANAR_TXFD
;
894 s
->miiregs
[MII_BMSR
] = MII_BMSR_AUTONEG
| MII_BMSR_100TX_FD
|
897 if (!qemu_get_queue(s
->nic
)->link_down
) {
898 s
->miiregs
[MII_ANLPAR
] |= MII_ANLPAR_TXFD
;
899 s
->miiregs
[MII_BMSR
] |= MII_BMSR_LINK_ST
;
902 /* Set manufacturer */
903 s
->miiregs
[MII_PHYID1
] = DP83840_PHYID1
;
904 s
->miiregs
[MII_PHYID2
] = DP83840_PHYID2
;
906 /* Configure default interrupt mask */
907 s
->mifregs
[HME_MIFI_IMASK
>> 2] = 0xffff;
908 s
->sebregs
[HME_SEBI_IMASK
>> 2] = 0xff7fffff;
911 static const VMStateDescription vmstate_hme
= {
914 .minimum_version_id
= 0,
915 .fields
= (VMStateField
[]) {
916 VMSTATE_PCI_DEVICE(parent_obj
, SunHMEState
),
917 VMSTATE_MACADDR(conf
.macaddr
, SunHMEState
),
918 VMSTATE_UINT32_ARRAY(sebregs
, SunHMEState
, (HME_SEB_REG_SIZE
>> 2)),
919 VMSTATE_UINT32_ARRAY(etxregs
, SunHMEState
, (HME_ETX_REG_SIZE
>> 2)),
920 VMSTATE_UINT32_ARRAY(erxregs
, SunHMEState
, (HME_ERX_REG_SIZE
>> 2)),
921 VMSTATE_UINT32_ARRAY(macregs
, SunHMEState
, (HME_MAC_REG_SIZE
>> 2)),
922 VMSTATE_UINT32_ARRAY(mifregs
, SunHMEState
, (HME_MIF_REG_SIZE
>> 2)),
923 VMSTATE_UINT16_ARRAY(miiregs
, SunHMEState
, HME_MII_REGS_SIZE
),
924 VMSTATE_END_OF_LIST()
928 static void sunhme_class_init(ObjectClass
*klass
, void *data
)
930 DeviceClass
*dc
= DEVICE_CLASS(klass
);
931 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
933 k
->realize
= sunhme_realize
;
934 k
->vendor_id
= PCI_VENDOR_ID_SUN
;
935 k
->device_id
= PCI_DEVICE_ID_SUN_HME
;
936 k
->class_id
= PCI_CLASS_NETWORK_ETHERNET
;
937 dc
->vmsd
= &vmstate_hme
;
938 dc
->reset
= sunhme_reset
;
939 dc
->props
= sunhme_properties
;
940 set_bit(DEVICE_CATEGORY_NETWORK
, dc
->categories
);
943 static const TypeInfo sunhme_info
= {
945 .parent
= TYPE_PCI_DEVICE
,
946 .class_init
= sunhme_class_init
,
947 .instance_size
= sizeof(SunHMEState
),
948 .instance_init
= sunhme_instance_init
,
949 .interfaces
= (InterfaceInfo
[]) {
950 { INTERFACE_CONVENTIONAL_PCI_DEVICE
},
955 static void sunhme_register_types(void)
957 type_register_static(&sunhme_info
);
960 type_init(sunhme_register_types
)