hw/net/xilinx_axienet.c

   1 /*
   2  * QEMU model of Xilinx AXI-Ethernet.
   3  *
   4  * Copyright (c) 2011 Edgar E. Iglesias.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw/sysbus.h"
  26 #include "qemu/log.h"
  27 #include "net/net.h"
  28 #include "net/checksum.h"
  29
  30 #include "hw/stream.h"
  31
  32 #define DPHY(x)
  33
  34 #define TYPE_XILINX_AXI_ENET "xlnx.axi-ethernet"
  35 #define TYPE_XILINX_AXI_ENET_DATA_STREAM "xilinx-axienet-data-stream"
  36 #define TYPE_XILINX_AXI_ENET_CONTROL_STREAM "xilinx-axienet-control-stream"
  37
  38 #define XILINX_AXI_ENET(obj) \
  39      OBJECT_CHECK(XilinxAXIEnet, (obj), TYPE_XILINX_AXI_ENET)
  40
  41 #define XILINX_AXI_ENET_DATA_STREAM(obj) \
  42      OBJECT_CHECK(XilinxAXIEnetStreamSlave, (obj),\
  43      TYPE_XILINX_AXI_ENET_DATA_STREAM)
  44
  45 #define XILINX_AXI_ENET_CONTROL_STREAM(obj) \
  46      OBJECT_CHECK(XilinxAXIEnetStreamSlave, (obj),\
  47      TYPE_XILINX_AXI_ENET_CONTROL_STREAM)
  48
  49 /* Advertisement control register. */
  50 #define ADVERTISE_10HALF        0x0020  /* Try for 10mbps half-duplex  */
  51 #define ADVERTISE_10FULL        0x0040  /* Try for 10mbps full-duplex  */
  52 #define ADVERTISE_100HALF       0x0080  /* Try for 100mbps half-duplex */
  53 #define ADVERTISE_100FULL       0x0100  /* Try for 100mbps full-duplex */
  54
  55 #define CONTROL_PAYLOAD_WORDS 5
  56 #define CONTROL_PAYLOAD_SIZE (CONTROL_PAYLOAD_WORDS * (sizeof(uint32_t)))
  57
  58 struct PHY {
  59     uint32_t regs[32];
  60
  61     int link;
  62
  63     unsigned int (*read)(struct PHY *phy, unsigned int req);
  64     void (*write)(struct PHY *phy, unsigned int req,
  65                   unsigned int data);
  66 };
  67
  68 static unsigned int tdk_read(struct PHY *phy, unsigned int req)
  69 {
  70     int regnum;
  71     unsigned r = 0;
  72
  73     regnum = req & 0x1f;
  74
  75     switch (regnum) {
  76         case 1:
  77             if (!phy->link) {
  78                 break;
  79             }
  80             /* MR1.  */
  81             /* Speeds and modes.  */
  82             r |= (1 << 13) | (1 << 14);
  83             r |= (1 << 11) | (1 << 12);
  84             r |= (1 << 5); /* Autoneg complete.  */
  85             r |= (1 << 3); /* Autoneg able.  */
  86             r |= (1 << 2); /* link.  */
  87             r |= (1 << 1); /* link.  */
  88             break;
  89         case 5:
  90             /* Link partner ability.
  91                We are kind; always agree with whatever best mode
  92                the guest advertises.  */
  93             r = 1 << 14; /* Success.  */
  94             /* Copy advertised modes.  */
  95             r |= phy->regs[4] & (15 << 5);
  96             /* Autoneg support.  */
  97             r |= 1;
  98             break;
  99         case 17:
 100             /* Marvell PHY on many xilinx boards.  */
 101             r = 0x8000; /* 1000Mb  */
 102             break;
 103         case 18:
 104             {
 105                 /* Diagnostics reg.  */
 106                 int duplex = 0;
 107                 int speed_100 = 0;
 108
 109                 if (!phy->link) {
 110                     break;
 111                 }
 112
 113                 /* Are we advertising 100 half or 100 duplex ? */
 114                 speed_100 = !!(phy->regs[4] & ADVERTISE_100HALF);
 115                 speed_100 |= !!(phy->regs[4] & ADVERTISE_100FULL);
 116
 117                 /* Are we advertising 10 duplex or 100 duplex ? */
 118                 duplex = !!(phy->regs[4] & ADVERTISE_100FULL);
 119                 duplex |= !!(phy->regs[4] & ADVERTISE_10FULL);
 120                 r = (speed_100 << 10) | (duplex << 11);
 121             }
 122             break;
 123
 124         default:
 125             r = phy->regs[regnum];
 126             break;
 127     }
 128     DPHY(qemu_log("\n%s %x = reg[%d]\n", __func__, r, regnum));
 129     return r;
 130 }
 131
 132 static void
 133 tdk_write(struct PHY *phy, unsigned int req, unsigned int data)
 134 {
 135     int regnum;
 136
 137     regnum = req & 0x1f;
 138     DPHY(qemu_log("%s reg[%d] = %x\n", __func__, regnum, data));
 139     switch (regnum) {
 140         default:
 141             phy->regs[regnum] = data;
 142             break;
 143     }
 144
 145     /* Unconditionally clear regs[BMCR][BMCR_RESET] */
 146     phy->regs[0] &= ~0x8000;
 147 }
 148
 149 static void
 150 tdk_init(struct PHY *phy)
 151 {
 152     phy->regs[0] = 0x3100;
 153     /* PHY Id.  */
 154     phy->regs[2] = 0x0300;
 155     phy->regs[3] = 0xe400;
 156     /* Autonegotiation advertisement reg.  */
 157     phy->regs[4] = 0x01E1;
 158     phy->link = 1;
 159
 160     phy->read = tdk_read;
 161     phy->write = tdk_write;
 162 }
 163
 164 struct MDIOBus {
 165     /* bus.  */
 166     int mdc;
 167     int mdio;
 168
 169     /* decoder.  */
 170     enum {
 171         PREAMBLE,
 172         SOF,
 173         OPC,
 174         ADDR,
 175         REQ,
 176         TURNAROUND,
 177         DATA
 178     } state;
 179     unsigned int drive;
 180
 181     unsigned int cnt;
 182     unsigned int addr;
 183     unsigned int opc;
 184     unsigned int req;
 185     unsigned int data;
 186
 187     struct PHY *devs[32];
 188 };
 189
 190 static void
 191 mdio_attach(struct MDIOBus *bus, struct PHY *phy, unsigned int addr)
 192 {
 193     bus->devs[addr & 0x1f] = phy;
 194 }
 195
 196 #ifdef USE_THIS_DEAD_CODE
 197 static void
 198 mdio_detach(struct MDIOBus *bus, struct PHY *phy, unsigned int addr)
 199 {
 200     bus->devs[addr & 0x1f] = NULL;
 201 }
 202 #endif
 203
 204 static uint16_t mdio_read_req(struct MDIOBus *bus, unsigned int addr,
 205                   unsigned int reg)
 206 {
 207     struct PHY *phy;
 208     uint16_t data;
 209
 210     phy = bus->devs[addr];
 211     if (phy && phy->read) {
 212         data = phy->read(phy, reg);
 213     } else {
 214         data = 0xffff;
 215     }
 216     DPHY(qemu_log("%s addr=%d reg=%d data=%x\n", __func__, addr, reg, data));
 217     return data;
 218 }
 219
 220 static void mdio_write_req(struct MDIOBus *bus, unsigned int addr,
 221                unsigned int reg, uint16_t data)
 222 {
 223     struct PHY *phy;
 224
 225     DPHY(qemu_log("%s addr=%d reg=%d data=%x\n", __func__, addr, reg, data));
 226     phy = bus->devs[addr];
 227     if (phy && phy->write) {
 228         phy->write(phy, reg, data);
 229     }
 230 }
 231
 232 #define DENET(x)
 233
 234 #define R_RAF      (0x000 / 4)
 235 enum {
 236     RAF_MCAST_REJ = (1 << 1),
 237     RAF_BCAST_REJ = (1 << 2),
 238     RAF_EMCF_EN = (1 << 12),
 239     RAF_NEWFUNC_EN = (1 << 11)
 240 };
 241
 242 #define R_IS       (0x00C / 4)
 243 enum {
 244     IS_HARD_ACCESS_COMPLETE = 1,
 245     IS_AUTONEG = (1 << 1),
 246     IS_RX_COMPLETE = (1 << 2),
 247     IS_RX_REJECT = (1 << 3),
 248     IS_TX_COMPLETE = (1 << 5),
 249     IS_RX_DCM_LOCK = (1 << 6),
 250     IS_MGM_RDY = (1 << 7),
 251     IS_PHY_RST_DONE = (1 << 8),
 252 };
 253
 254 #define R_IP       (0x010 / 4)
 255 #define R_IE       (0x014 / 4)
 256 #define R_UAWL     (0x020 / 4)
 257 #define R_UAWU     (0x024 / 4)
 258 #define R_PPST     (0x030 / 4)
 259 enum {
 260     PPST_LINKSTATUS = (1 << 0),
 261     PPST_PHY_LINKSTATUS = (1 << 7),
 262 };
 263
 264 #define R_STATS_RX_BYTESL (0x200 / 4)
 265 #define R_STATS_RX_BYTESH (0x204 / 4)
 266 #define R_STATS_TX_BYTESL (0x208 / 4)
 267 #define R_STATS_TX_BYTESH (0x20C / 4)
 268 #define R_STATS_RXL       (0x290 / 4)
 269 #define R_STATS_RXH       (0x294 / 4)
 270 #define R_STATS_RX_BCASTL (0x2a0 / 4)
 271 #define R_STATS_RX_BCASTH (0x2a4 / 4)
 272 #define R_STATS_RX_MCASTL (0x2a8 / 4)
 273 #define R_STATS_RX_MCASTH (0x2ac / 4)
 274
 275 #define R_RCW0     (0x400 / 4)
 276 #define R_RCW1     (0x404 / 4)
 277 enum {
 278     RCW1_VLAN = (1 << 27),
 279     RCW1_RX   = (1 << 28),
 280     RCW1_FCS  = (1 << 29),
 281     RCW1_JUM  = (1 << 30),
 282     RCW1_RST  = (1 << 31),
 283 };
 284
 285 #define R_TC       (0x408 / 4)
 286 enum {
 287     TC_VLAN = (1 << 27),
 288     TC_TX   = (1 << 28),
 289     TC_FCS  = (1 << 29),
 290     TC_JUM  = (1 << 30),
 291     TC_RST  = (1 << 31),
 292 };
 293
 294 #define R_EMMC     (0x410 / 4)
 295 enum {
 296     EMMC_LINKSPEED_10MB = (0 << 30),
 297     EMMC_LINKSPEED_100MB = (1 << 30),
 298     EMMC_LINKSPEED_1000MB = (2 << 30),
 299 };
 300
 301 #define R_PHYC     (0x414 / 4)
 302
 303 #define R_MC       (0x500 / 4)
 304 #define MC_EN      (1 << 6)
 305
 306 #define R_MCR      (0x504 / 4)
 307 #define R_MWD      (0x508 / 4)
 308 #define R_MRD      (0x50c / 4)
 309 #define R_MIS      (0x600 / 4)
 310 #define R_MIP      (0x620 / 4)
 311 #define R_MIE      (0x640 / 4)
 312 #define R_MIC      (0x640 / 4)
 313
 314 #define R_UAW0     (0x700 / 4)
 315 #define R_UAW1     (0x704 / 4)
 316 #define R_FMI      (0x708 / 4)
 317 #define R_AF0      (0x710 / 4)
 318 #define R_AF1      (0x714 / 4)
 319 #define R_MAX      (0x34 / 4)
 320
 321 /* Indirect registers.  */
 322 struct TEMAC  {
 323     struct MDIOBus mdio_bus;
 324     struct PHY phy;
 325
 326     void *parent;
 327 };
 328
 329 typedef struct XilinxAXIEnetStreamSlave XilinxAXIEnetStreamSlave;
 330 typedef struct XilinxAXIEnet XilinxAXIEnet;
 331
 332 struct XilinxAXIEnetStreamSlave {
 333     Object parent;
 334
 335     struct XilinxAXIEnet *enet;
 336 } ;
 337
 338 struct XilinxAXIEnet {
 339     SysBusDevice busdev;
 340     MemoryRegion iomem;
 341     qemu_irq irq;
 342     StreamSlave *tx_data_dev;
 343     StreamSlave *tx_control_dev;
 344     XilinxAXIEnetStreamSlave rx_data_dev;
 345     XilinxAXIEnetStreamSlave rx_control_dev;
 346     NICState *nic;
 347     NICConf conf;
 348
 349
 350     uint32_t c_rxmem;
 351     uint32_t c_txmem;
 352     uint32_t c_phyaddr;
 353
 354     struct TEMAC TEMAC;
 355
 356     /* MII regs.  */
 357     union {
 358         uint32_t regs[4];
 359         struct {
 360             uint32_t mc;
 361             uint32_t mcr;
 362             uint32_t mwd;
 363             uint32_t mrd;
 364         };
 365     } mii;
 366
 367     struct {
 368         uint64_t rx_bytes;
 369         uint64_t tx_bytes;
 370
 371         uint64_t rx;
 372         uint64_t rx_bcast;
 373         uint64_t rx_mcast;
 374     } stats;
 375
 376     /* Receive configuration words.  */
 377     uint32_t rcw[2];
 378     /* Transmit config.  */
 379     uint32_t tc;
 380     uint32_t emmc;
 381     uint32_t phyc;
 382
 383     /* Unicast Address Word.  */
 384     uint32_t uaw[2];
 385     /* Unicast address filter used with extended mcast.  */
 386     uint32_t ext_uaw[2];
 387     uint32_t fmi;
 388
 389     uint32_t regs[R_MAX];
 390
 391     /* Multicast filter addrs.  */
 392     uint32_t maddr[4][2];
 393     /* 32K x 1 lookup filter.  */
 394     uint32_t ext_mtable[1024];
 395
 396     uint32_t hdr[CONTROL_PAYLOAD_WORDS];
 397
 398     uint8_t *rxmem;
 399     uint32_t rxsize;
 400     uint32_t rxpos;
 401
 402     uint8_t rxapp[CONTROL_PAYLOAD_SIZE];
 403     uint32_t rxappsize;
 404 };
 405
 406 static void axienet_rx_reset(XilinxAXIEnet *s)
 407 {
 408     s->rcw[1] = RCW1_JUM | RCW1_FCS | RCW1_RX | RCW1_VLAN;
 409 }
 410
 411 static void axienet_tx_reset(XilinxAXIEnet *s)
 412 {
 413     s->tc = TC_JUM | TC_TX | TC_VLAN;
 414 }
 415
 416 static inline int axienet_rx_resetting(XilinxAXIEnet *s)
 417 {
 418     return s->rcw[1] & RCW1_RST;
 419 }
 420
 421 static inline int axienet_rx_enabled(XilinxAXIEnet *s)
 422 {
 423     return s->rcw[1] & RCW1_RX;
 424 }
 425
 426 static inline int axienet_extmcf_enabled(XilinxAXIEnet *s)
 427 {
 428     return !!(s->regs[R_RAF] & RAF_EMCF_EN);
 429 }
 430
 431 static inline int axienet_newfunc_enabled(XilinxAXIEnet *s)
 432 {
 433     return !!(s->regs[R_RAF] & RAF_NEWFUNC_EN);
 434 }
 435
 436 static void xilinx_axienet_reset(DeviceState *d)
 437 {
 438     XilinxAXIEnet *s = XILINX_AXI_ENET(d);
 439
 440     axienet_rx_reset(s);
 441     axienet_tx_reset(s);
 442
 443     s->regs[R_PPST] = PPST_LINKSTATUS | PPST_PHY_LINKSTATUS;
 444     s->regs[R_IS] = IS_AUTONEG | IS_RX_DCM_LOCK | IS_MGM_RDY | IS_PHY_RST_DONE;
 445
 446     s->emmc = EMMC_LINKSPEED_100MB;
 447 }
 448
 449 static void enet_update_irq(XilinxAXIEnet *s)
 450 {
 451     s->regs[R_IP] = s->regs[R_IS] & s->regs[R_IE];
 452     qemu_set_irq(s->irq, !!s->regs[R_IP]);
 453 }
 454
 455 static uint64_t enet_read(void *opaque, hwaddr addr, unsigned size)
 456 {
 457     XilinxAXIEnet *s = opaque;
 458     uint32_t r = 0;
 459     addr >>= 2;
 460
 461     switch (addr) {
 462         case R_RCW0:
 463         case R_RCW1:
 464             r = s->rcw[addr & 1];
 465             break;
 466
 467         case R_TC:
 468             r = s->tc;
 469             break;
 470
 471         case R_EMMC:
 472             r = s->emmc;
 473             break;
 474
 475         case R_PHYC:
 476             r = s->phyc;
 477             break;
 478
 479         case R_MCR:
 480             r = s->mii.regs[addr & 3] | (1 << 7); /* Always ready.  */
 481             break;
 482
 483         case R_STATS_RX_BYTESL:
 484         case R_STATS_RX_BYTESH:
 485             r = s->stats.rx_bytes >> (32 * (addr & 1));
 486             break;
 487
 488         case R_STATS_TX_BYTESL:
 489         case R_STATS_TX_BYTESH:
 490             r = s->stats.tx_bytes >> (32 * (addr & 1));
 491             break;
 492
 493         case R_STATS_RXL:
 494         case R_STATS_RXH:
 495             r = s->stats.rx >> (32 * (addr & 1));
 496             break;
 497         case R_STATS_RX_BCASTL:
 498         case R_STATS_RX_BCASTH:
 499             r = s->stats.rx_bcast >> (32 * (addr & 1));
 500             break;
 501         case R_STATS_RX_MCASTL:
 502         case R_STATS_RX_MCASTH:
 503             r = s->stats.rx_mcast >> (32 * (addr & 1));
 504             break;
 505
 506         case R_MC:
 507         case R_MWD:
 508         case R_MRD:
 509             r = s->mii.regs[addr & 3];
 510             break;
 511
 512         case R_UAW0:
 513         case R_UAW1:
 514             r = s->uaw[addr & 1];
 515             break;
 516
 517         case R_UAWU:
 518         case R_UAWL:
 519             r = s->ext_uaw[addr & 1];
 520             break;
 521
 522         case R_FMI:
 523             r = s->fmi;
 524             break;
 525
 526         case R_AF0:
 527         case R_AF1:
 528             r = s->maddr[s->fmi & 3][addr & 1];
 529             break;
 530
 531         case 0x8000 ... 0x83ff:
 532             r = s->ext_mtable[addr - 0x8000];
 533             break;
 534
 535         default:
 536             if (addr < ARRAY_SIZE(s->regs)) {
 537                 r = s->regs[addr];
 538             }
 539             DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n",
 540                             __func__, addr * 4, r));
 541             break;
 542     }
 543     return r;
 544 }
 545
 546 static void enet_write(void *opaque, hwaddr addr,
 547                        uint64_t value, unsigned size)
 548 {
 549     XilinxAXIEnet *s = opaque;
 550     struct TEMAC *t = &s->TEMAC;
 551
 552     addr >>= 2;
 553     switch (addr) {
 554         case R_RCW0:
 555         case R_RCW1:
 556             s->rcw[addr & 1] = value;
 557             if ((addr & 1) && value & RCW1_RST) {
 558                 axienet_rx_reset(s);
 559             } else {
 560                 qemu_flush_queued_packets(qemu_get_queue(s->nic));
 561             }
 562             break;
 563
 564         case R_TC:
 565             s->tc = value;
 566             if (value & TC_RST) {
 567                 axienet_tx_reset(s);
 568             }
 569             break;
 570
 571         case R_EMMC:
 572             s->emmc = value;
 573             break;
 574
 575         case R_PHYC:
 576             s->phyc = value;
 577             break;
 578
 579         case R_MC:
 580              value &= ((1 << 7) - 1);
 581
 582              /* Enable the MII.  */
 583              if (value & MC_EN) {
 584                  unsigned int miiclkdiv = value & ((1 << 6) - 1);
 585                  if (!miiclkdiv) {
 586                      qemu_log("AXIENET: MDIO enabled but MDIOCLK is zero!\n");
 587                  }
 588              }
 589              s->mii.mc = value;
 590              break;
 591
 592         case R_MCR: {
 593              unsigned int phyaddr = (value >> 24) & 0x1f;
 594              unsigned int regaddr = (value >> 16) & 0x1f;
 595              unsigned int op = (value >> 14) & 3;
 596              unsigned int initiate = (value >> 11) & 1;
 597
 598              if (initiate) {
 599                  if (op == 1) {
 600                      mdio_write_req(&t->mdio_bus, phyaddr, regaddr, s->mii.mwd);
 601                  } else if (op == 2) {
 602                      s->mii.mrd = mdio_read_req(&t->mdio_bus, phyaddr, regaddr);
 603                  } else {
 604                      qemu_log("AXIENET: invalid MDIOBus OP=%d\n", op);
 605                  }
 606              }
 607              s->mii.mcr = value;
 608              break;
 609         }
 610
 611         case R_MWD:
 612         case R_MRD:
 613              s->mii.regs[addr & 3] = value;
 614              break;
 615
 616
 617         case R_UAW0:
 618         case R_UAW1:
 619             s->uaw[addr & 1] = value;
 620             break;
 621
 622         case R_UAWL:
 623         case R_UAWU:
 624             s->ext_uaw[addr & 1] = value;
 625             break;
 626
 627         case R_FMI:
 628             s->fmi = value;
 629             break;
 630
 631         case R_AF0:
 632         case R_AF1:
 633             s->maddr[s->fmi & 3][addr & 1] = value;
 634             break;
 635
 636         case R_IS:
 637             s->regs[addr] &= ~value;
 638             break;
 639
 640         case 0x8000 ... 0x83ff:
 641             s->ext_mtable[addr - 0x8000] = value;
 642             break;
 643
 644         default:
 645             DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n",
 646                            __func__, addr * 4, (unsigned)value));
 647             if (addr < ARRAY_SIZE(s->regs)) {
 648                 s->regs[addr] = value;
 649             }
 650             break;
 651     }
 652     enet_update_irq(s);
 653 }
 654
 655 static const MemoryRegionOps enet_ops = {
 656     .read = enet_read,
 657     .write = enet_write,
 658     .endianness = DEVICE_LITTLE_ENDIAN,
 659 };
 660
 661 static int eth_can_rx(NetClientState *nc)
 662 {
 663     XilinxAXIEnet *s = qemu_get_nic_opaque(nc);
 664
 665     /* RX enabled?  */
 666     return !s->rxsize && !axienet_rx_resetting(s) && axienet_rx_enabled(s);
 667 }
 668
 669 static int enet_match_addr(const uint8_t *buf, uint32_t f0, uint32_t f1)
 670 {
 671     int match = 1;
 672
 673     if (memcmp(buf, &f0, 4)) {
 674         match = 0;
 675     }
 676
 677     if (buf[4] != (f1 & 0xff) || buf[5] != ((f1 >> 8) & 0xff)) {
 678         match = 0;
 679     }
 680
 681     return match;
 682 }
 683
 684 static void axienet_eth_rx_notify(void *opaque)
 685 {
 686     XilinxAXIEnet *s = XILINX_AXI_ENET(opaque);
 687
 688     while (s->rxappsize && stream_can_push(s->tx_control_dev,
 689                                            axienet_eth_rx_notify, s)) {
 690         size_t ret = stream_push(s->tx_control_dev,
 691                                  (void *)s->rxapp + CONTROL_PAYLOAD_SIZE
 692                                  - s->rxappsize, s->rxappsize);
 693         s->rxappsize -= ret;
 694     }
 695
 696     while (s->rxsize && stream_can_push(s->tx_data_dev,
 697                                         axienet_eth_rx_notify, s)) {
 698         size_t ret = stream_push(s->tx_data_dev, (void *)s->rxmem + s->rxpos,
 699                                  s->rxsize);
 700         s->rxsize -= ret;
 701         s->rxpos += ret;
 702         if (!s->rxsize) {
 703             s->regs[R_IS] |= IS_RX_COMPLETE;
 704         }
 705     }
 706     enet_update_irq(s);
 707 }
 708
 709 static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size)
 710 {
 711     XilinxAXIEnet *s = qemu_get_nic_opaque(nc);
 712     static const unsigned char sa_bcast[6] = {0xff, 0xff, 0xff,
 713                                               0xff, 0xff, 0xff};
 714     static const unsigned char sa_ipmcast[3] = {0x01, 0x00, 0x52};
 715     uint32_t app[CONTROL_PAYLOAD_WORDS] = {0};
 716     int promisc = s->fmi & (1 << 31);
 717     int unicast, broadcast, multicast, ip_multicast = 0;
 718     uint32_t csum32;
 719     uint16_t csum16;
 720     int i;
 721
 722     DENET(qemu_log("%s: %zd bytes\n", __func__, size));
 723
 724     unicast = ~buf[0] & 0x1;
 725     broadcast = memcmp(buf, sa_bcast, 6) == 0;
 726     multicast = !unicast && !broadcast;
 727     if (multicast && (memcmp(sa_ipmcast, buf, sizeof sa_ipmcast) == 0)) {
 728         ip_multicast = 1;
 729     }
 730
 731     /* Jumbo or vlan sizes ?  */
 732     if (!(s->rcw[1] & RCW1_JUM)) {
 733         if (size > 1518 && size <= 1522 && !(s->rcw[1] & RCW1_VLAN)) {
 734             return size;
 735         }
 736     }
 737
 738     /* Basic Address filters.  If you want to use the extended filters
 739        you'll generally have to place the ethernet mac into promiscuous mode
 740        to avoid the basic filtering from dropping most frames.  */
 741     if (!promisc) {
 742         if (unicast) {
 743             if (!enet_match_addr(buf, s->uaw[0], s->uaw[1])) {
 744                 return size;
 745             }
 746         } else {
 747             if (broadcast) {
 748                 /* Broadcast.  */
 749                 if (s->regs[R_RAF] & RAF_BCAST_REJ) {
 750                     return size;
 751                 }
 752             } else {
 753                 int drop = 1;
 754
 755                 /* Multicast.  */
 756                 if (s->regs[R_RAF] & RAF_MCAST_REJ) {
 757                     return size;
 758                 }
 759
 760                 for (i = 0; i < 4; i++) {
 761                     if (enet_match_addr(buf, s->maddr[i][0], s->maddr[i][1])) {
 762                         drop = 0;
 763                         break;
 764                     }
 765                 }
 766
 767                 if (drop) {
 768                     return size;
 769                 }
 770             }
 771         }
 772     }
 773
 774     /* Extended mcast filtering enabled?  */
 775     if (axienet_newfunc_enabled(s) && axienet_extmcf_enabled(s)) {
 776         if (unicast) {
 777             if (!enet_match_addr(buf, s->ext_uaw[0], s->ext_uaw[1])) {
 778                 return size;
 779             }
 780         } else {
 781             if (broadcast) {
 782                 /* Broadcast. ???  */
 783                 if (s->regs[R_RAF] & RAF_BCAST_REJ) {
 784                     return size;
 785                 }
 786             } else {
 787                 int idx, bit;
 788
 789                 /* Multicast.  */
 790                 if (!memcmp(buf, sa_ipmcast, 3)) {
 791                     return size;
 792                 }
 793
 794                 idx  = (buf[4] & 0x7f) << 8;
 795                 idx |= buf[5];
 796
 797                 bit = 1 << (idx & 0x1f);
 798                 idx >>= 5;
 799
 800                 if (!(s->ext_mtable[idx] & bit)) {
 801                     return size;
 802                 }
 803             }
 804         }
 805     }
 806
 807     if (size < 12) {
 808         s->regs[R_IS] |= IS_RX_REJECT;
 809         enet_update_irq(s);
 810         return -1;
 811     }
 812
 813     if (size > (s->c_rxmem - 4)) {
 814         size = s->c_rxmem - 4;
 815     }
 816
 817     memcpy(s->rxmem, buf, size);
 818     memset(s->rxmem + size, 0, 4); /* Clear the FCS.  */
 819
 820     if (s->rcw[1] & RCW1_FCS) {
 821         size += 4; /* fcs is inband.  */
 822     }
 823
 824     app[0] = 5 << 28;
 825     csum32 = net_checksum_add(size - 14, (uint8_t *)s->rxmem + 14);
 826     /* Fold it once.  */
 827     csum32 = (csum32 & 0xffff) + (csum32 >> 16);
 828     /* And twice to get rid of possible carries.  */
 829     csum16 = (csum32 & 0xffff) + (csum32 >> 16);
 830     app[3] = csum16;
 831     app[4] = size & 0xffff;
 832
 833     s->stats.rx_bytes += size;
 834     s->stats.rx++;
 835     if (multicast) {
 836         s->stats.rx_mcast++;
 837         app[2] |= 1 | (ip_multicast << 1);
 838     } else if (broadcast) {
 839         s->stats.rx_bcast++;
 840         app[2] |= 1 << 3;
 841     }
 842
 843     /* Good frame.  */
 844     app[2] |= 1 << 6;
 845
 846     s->rxsize = size;
 847     s->rxpos = 0;
 848     for (i = 0; i < ARRAY_SIZE(app); ++i) {
 849         app[i] = cpu_to_le32(app[i]);
 850     }
 851     s->rxappsize = CONTROL_PAYLOAD_SIZE;
 852     memcpy(s->rxapp, app, s->rxappsize);
 853     axienet_eth_rx_notify(s);
 854
 855     enet_update_irq(s);
 856     return size;
 857 }
 858
 859 static size_t
 860 xilinx_axienet_control_stream_push(StreamSlave *obj, uint8_t *buf, size_t len)
 861 {
 862     int i;
 863     XilinxAXIEnetStreamSlave *cs = XILINX_AXI_ENET_CONTROL_STREAM(obj);
 864     XilinxAXIEnet *s = cs->enet;
 865
 866     if (len != CONTROL_PAYLOAD_SIZE) {
 867         hw_error("AXI Enet requires %d byte control stream payload\n",
 868                  (int)CONTROL_PAYLOAD_SIZE);
 869     }
 870
 871     memcpy(s->hdr, buf, len);
 872
 873     for (i = 0; i < ARRAY_SIZE(s->hdr); ++i) {
 874         s->hdr[i] = le32_to_cpu(s->hdr[i]);
 875     }
 876     return len;
 877 }
 878
 879 static size_t
 880 xilinx_axienet_data_stream_push(StreamSlave *obj, uint8_t *buf, size_t size)
 881 {
 882     XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(obj);
 883     XilinxAXIEnet *s = ds->enet;
 884
 885     /* TX enable ?  */
 886     if (!(s->tc & TC_TX)) {
 887         return size;
 888     }
 889
 890     /* Jumbo or vlan sizes ?  */
 891     if (!(s->tc & TC_JUM)) {
 892         if (size > 1518 && size <= 1522 && !(s->tc & TC_VLAN)) {
 893             return size;
 894         }
 895     }
 896
 897     if (s->hdr[0] & 1) {
 898         unsigned int start_off = s->hdr[1] >> 16;
 899         unsigned int write_off = s->hdr[1] & 0xffff;
 900         uint32_t tmp_csum;
 901         uint16_t csum;
 902
 903         tmp_csum = net_checksum_add(size - start_off,
 904                                     (uint8_t *)buf + start_off);
 905         /* Accumulate the seed.  */
 906         tmp_csum += s->hdr[2] & 0xffff;
 907
 908         /* Fold the 32bit partial checksum.  */
 909         csum = net_checksum_finish(tmp_csum);
 910
 911         /* Writeback.  */
 912         buf[write_off] = csum >> 8;
 913         buf[write_off + 1] = csum & 0xff;
 914     }
 915
 916     qemu_send_packet(qemu_get_queue(s->nic), buf, size);
 917
 918     s->stats.tx_bytes += size;
 919     s->regs[R_IS] |= IS_TX_COMPLETE;
 920     enet_update_irq(s);
 921
 922     return size;
 923 }
 924
 925 static NetClientInfo net_xilinx_enet_info = {
 926     .type = NET_CLIENT_OPTIONS_KIND_NIC,
 927     .size = sizeof(NICState),
 928     .can_receive = eth_can_rx,
 929     .receive = eth_rx,
 930 };
 931
 932 static void xilinx_enet_realize(DeviceState *dev, Error **errp)
 933 {
 934     XilinxAXIEnet *s = XILINX_AXI_ENET(dev);
 935     XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(&s->rx_data_dev);
 936     XilinxAXIEnetStreamSlave *cs = XILINX_AXI_ENET_CONTROL_STREAM(
 937                                                             &s->rx_control_dev);
 938     Error *local_err = NULL;
 939
 940     object_property_add_link(OBJECT(ds), "enet", "xlnx.axi-ethernet",
 941                              (Object **) &ds->enet,
 942                              object_property_allow_set_link,
 943                              OBJ_PROP_LINK_UNREF_ON_RELEASE,
 944                              &local_err);
 945     object_property_add_link(OBJECT(cs), "enet", "xlnx.axi-ethernet",
 946                              (Object **) &cs->enet,
 947                              object_property_allow_set_link,
 948                              OBJ_PROP_LINK_UNREF_ON_RELEASE,
 949                              &local_err);
 950     if (local_err) {
 951         goto xilinx_enet_realize_fail;
 952     }
 953     object_property_set_link(OBJECT(ds), OBJECT(s), "enet", &local_err);
 954     object_property_set_link(OBJECT(cs), OBJECT(s), "enet", &local_err);
 955     if (local_err) {
 956         goto xilinx_enet_realize_fail;
 957     }
 958
 959     qemu_macaddr_default_if_unset(&s->conf.macaddr);
 960     s->nic = qemu_new_nic(&net_xilinx_enet_info, &s->conf,
 961                           object_get_typename(OBJECT(dev)), dev->id, s);
 962     qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
 963
 964     tdk_init(&s->TEMAC.phy);
 965     mdio_attach(&s->TEMAC.mdio_bus, &s->TEMAC.phy, s->c_phyaddr);
 966
 967     s->TEMAC.parent = s;
 968
 969     s->rxmem = g_malloc(s->c_rxmem);
 970     return;
 971
 972 xilinx_enet_realize_fail:
 973     if (!*errp) {
 974         *errp = local_err;
 975     }
 976 }
 977
 978 static void xilinx_enet_init(Object *obj)
 979 {
 980     XilinxAXIEnet *s = XILINX_AXI_ENET(obj);
 981     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 982
 983     object_property_add_link(obj, "axistream-connected", TYPE_STREAM_SLAVE,
 984                              (Object **) &s->tx_data_dev,
 985                              qdev_prop_allow_set_link_before_realize,
 986                              OBJ_PROP_LINK_UNREF_ON_RELEASE,
 987                              &error_abort);
 988     object_property_add_link(obj, "axistream-control-connected",
 989                              TYPE_STREAM_SLAVE,
 990                              (Object **) &s->tx_control_dev,
 991                              qdev_prop_allow_set_link_before_realize,
 992                              OBJ_PROP_LINK_UNREF_ON_RELEASE,
 993                              &error_abort);
 994
 995     object_initialize(&s->rx_data_dev, sizeof(s->rx_data_dev),
 996                       TYPE_XILINX_AXI_ENET_DATA_STREAM);
 997     object_initialize(&s->rx_control_dev, sizeof(s->rx_control_dev),
 998                       TYPE_XILINX_AXI_ENET_CONTROL_STREAM);
 999     object_property_add_child(OBJECT(s), "axistream-connected-target",
1000                               (Object *)&s->rx_data_dev, &error_abort);
1001     object_property_add_child(OBJECT(s), "axistream-control-connected-target",
1002                               (Object *)&s->rx_control_dev, &error_abort);
1003
1004     sysbus_init_irq(sbd, &s->irq);
1005
1006     memory_region_init_io(&s->iomem, OBJECT(s), &enet_ops, s, "enet", 0x40000);
1007     sysbus_init_mmio(sbd, &s->iomem);
1008 }
1009
1010 static Property xilinx_enet_properties[] = {
1011     DEFINE_PROP_UINT32("phyaddr", XilinxAXIEnet, c_phyaddr, 7),
1012     DEFINE_PROP_UINT32("rxmem", XilinxAXIEnet, c_rxmem, 0x1000),
1013     DEFINE_PROP_UINT32("txmem", XilinxAXIEnet, c_txmem, 0x1000),
1014     DEFINE_NIC_PROPERTIES(XilinxAXIEnet, conf),
1015     DEFINE_PROP_END_OF_LIST(),
1016 };
1017
1018 static void xilinx_enet_class_init(ObjectClass *klass, void *data)
1019 {
1020     DeviceClass *dc = DEVICE_CLASS(klass);
1021
1022     dc->realize = xilinx_enet_realize;
1023     dc->props = xilinx_enet_properties;
1024     dc->reset = xilinx_axienet_reset;
1025 }
1026
1027 static void xilinx_enet_stream_class_init(ObjectClass *klass, void *data)
1028 {
1029     StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass);
1030
1031     ssc->push = data;
1032 }
1033
1034 static const TypeInfo xilinx_enet_info = {
1035     .name          = TYPE_XILINX_AXI_ENET,
1036     .parent        = TYPE_SYS_BUS_DEVICE,
1037     .instance_size = sizeof(XilinxAXIEnet),
1038     .class_init    = xilinx_enet_class_init,
1039     .instance_init = xilinx_enet_init,
1040 };
1041
1042 static const TypeInfo xilinx_enet_data_stream_info = {
1043     .name          = TYPE_XILINX_AXI_ENET_DATA_STREAM,
1044     .parent        = TYPE_OBJECT,
1045     .instance_size = sizeof(struct XilinxAXIEnetStreamSlave),
1046     .class_init    = xilinx_enet_stream_class_init,
1047     .class_data    = xilinx_axienet_data_stream_push,
1048     .interfaces = (InterfaceInfo[]) {
1049             { TYPE_STREAM_SLAVE },
1050             { }
1051     }
1052 };
1053
1054 static const TypeInfo xilinx_enet_control_stream_info = {
1055     .name          = TYPE_XILINX_AXI_ENET_CONTROL_STREAM,
1056     .parent        = TYPE_OBJECT,
1057     .instance_size = sizeof(struct XilinxAXIEnetStreamSlave),
1058     .class_init    = xilinx_enet_stream_class_init,
1059     .class_data    = xilinx_axienet_control_stream_push,
1060     .interfaces = (InterfaceInfo[]) {
1061             { TYPE_STREAM_SLAVE },
1062             { }
1063     }
1064 };
1065
1066 static void xilinx_enet_register_types(void)
1067 {
1068     type_register_static(&xilinx_enet_info);
1069     type_register_static(&xilinx_enet_data_stream_info);
1070     type_register_static(&xilinx_enet_control_stream_info);
1071 }
1072
1073 type_init(xilinx_enet_register_types)