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1 /*
2 * Nokia N-series internet tablets.
3 *
4 * Copyright (C) 2007 Nokia Corporation
5 * Written by Andrzej Zaborowski <andrew@openedhand.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu-common.h"
22 #include "sysemu.h"
23 #include "omap.h"
24 #include "arm-misc.h"
25 #include "irq.h"
26 #include "console.h"
27 #include "boards.h"
28 #include "i2c.h"
29 #include "devices.h"
30 #include "flash.h"
31 #include "hw.h"
32 #include "bt.h"
33 #include "loader.h"
34 #include "blockdev.h"
35
36 /* Nokia N8x0 support */
37 struct n800_s {
38 struct omap_mpu_state_s *cpu;
39
40 struct rfbi_chip_s blizzard;
41 struct {
42 void *opaque;
43 uint32_t (*txrx)(void *opaque, uint32_t value, int len);
44 uWireSlave *chip;
45 } ts;
46 i2c_bus *i2c;
47
48 int keymap[0x80];
49 DeviceState *kbd;
50
51 TUSBState *usb;
52 void *retu;
53 void *tahvo;
54 void *nand;
55 };
56
57 /* GPIO pins */
58 #define N8X0_TUSB_ENABLE_GPIO 0
59 #define N800_MMC2_WP_GPIO 8
60 #define N800_UNKNOWN_GPIO0 9 /* out */
61 #define N810_MMC2_VIOSD_GPIO 9
62 #define N810_HEADSET_AMP_GPIO 10
63 #define N800_CAM_TURN_GPIO 12
64 #define N810_GPS_RESET_GPIO 12
65 #define N800_BLIZZARD_POWERDOWN_GPIO 15
66 #define N800_MMC1_WP_GPIO 23
67 #define N810_MMC2_VSD_GPIO 23
68 #define N8X0_ONENAND_GPIO 26
69 #define N810_BLIZZARD_RESET_GPIO 30
70 #define N800_UNKNOWN_GPIO2 53 /* out */
71 #define N8X0_TUSB_INT_GPIO 58
72 #define N8X0_BT_WKUP_GPIO 61
73 #define N8X0_STI_GPIO 62
74 #define N8X0_CBUS_SEL_GPIO 64
75 #define N8X0_CBUS_DAT_GPIO 65
76 #define N8X0_CBUS_CLK_GPIO 66
77 #define N8X0_WLAN_IRQ_GPIO 87
78 #define N8X0_BT_RESET_GPIO 92
79 #define N8X0_TEA5761_CS_GPIO 93
80 #define N800_UNKNOWN_GPIO 94
81 #define N810_TSC_RESET_GPIO 94
82 #define N800_CAM_ACT_GPIO 95
83 #define N810_GPS_WAKEUP_GPIO 95
84 #define N8X0_MMC_CS_GPIO 96
85 #define N8X0_WLAN_PWR_GPIO 97
86 #define N8X0_BT_HOST_WKUP_GPIO 98
87 #define N810_SPEAKER_AMP_GPIO 101
88 #define N810_KB_LOCK_GPIO 102
89 #define N800_TSC_TS_GPIO 103
90 #define N810_TSC_TS_GPIO 106
91 #define N8X0_HEADPHONE_GPIO 107
92 #define N8X0_RETU_GPIO 108
93 #define N800_TSC_KP_IRQ_GPIO 109
94 #define N810_KEYBOARD_GPIO 109
95 #define N800_BAT_COVER_GPIO 110
96 #define N810_SLIDE_GPIO 110
97 #define N8X0_TAHVO_GPIO 111
98 #define N800_UNKNOWN_GPIO4 112 /* out */
99 #define N810_SLEEPX_LED_GPIO 112
100 #define N800_TSC_RESET_GPIO 118 /* ? */
101 #define N810_AIC33_RESET_GPIO 118
102 #define N800_TSC_UNKNOWN_GPIO 119 /* out */
103 #define N8X0_TMP105_GPIO 125
104
105 /* Config */
106 #define BT_UART 0
107 #define XLDR_LL_UART 1
108
109 /* Addresses on the I2C bus 0 */
110 #define N810_TLV320AIC33_ADDR 0x18 /* Audio CODEC */
111 #define N8X0_TCM825x_ADDR 0x29 /* Camera */
112 #define N810_LP5521_ADDR 0x32 /* LEDs */
113 #define N810_TSL2563_ADDR 0x3d /* Light sensor */
114 #define N810_LM8323_ADDR 0x45 /* Keyboard */
115 /* Addresses on the I2C bus 1 */
116 #define N8X0_TMP105_ADDR 0x48 /* Temperature sensor */
117 #define N8X0_MENELAUS_ADDR 0x72 /* Power management */
118
119 /* Chipselects on GPMC NOR interface */
120 #define N8X0_ONENAND_CS 0
121 #define N8X0_USB_ASYNC_CS 1
122 #define N8X0_USB_SYNC_CS 4
123
124 #define N8X0_BD_ADDR 0x00, 0x1a, 0x89, 0x9e, 0x3e, 0x81
125
126 static void n800_mmc_cs_cb(void *opaque, int line, int level)
127 {
128 /* TODO: this seems to actually be connected to the menelaus, to
129 * which also both MMC slots connect. */
130 omap_mmc_enable((struct omap_mmc_s *) opaque, !level);
131
132 printf("%s: MMC slot %i active\n", __FUNCTION__, level + 1);
133 }
134
135 static void n8x0_gpio_setup(struct n800_s *s)
136 {
137 qemu_irq *mmc_cs = qemu_allocate_irqs(n800_mmc_cs_cb, s->cpu->mmc, 1);
138 qdev_connect_gpio_out(s->cpu->gpio, N8X0_MMC_CS_GPIO, mmc_cs[0]);
139
140 qemu_irq_lower(qdev_get_gpio_in(s->cpu->gpio, N800_BAT_COVER_GPIO));
141 }
142
143 #define MAEMO_CAL_HEADER(...) \
144 'C', 'o', 'n', 'F', 0x02, 0x00, 0x04, 0x00, \
145 __VA_ARGS__, \
146 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
147
148 static const uint8_t n8x0_cal_wlan_mac[] = {
149 MAEMO_CAL_HEADER('w', 'l', 'a', 'n', '-', 'm', 'a', 'c')
150 0x1c, 0x00, 0x00, 0x00, 0x47, 0xd6, 0x69, 0xb3,
151 0x30, 0x08, 0xa0, 0x83, 0x00, 0x00, 0x00, 0x00,
152 0x00, 0x00, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x00,
153 0x89, 0x00, 0x00, 0x00, 0x9e, 0x00, 0x00, 0x00,
154 0x5d, 0x00, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00,
155 };
156
157 static const uint8_t n8x0_cal_bt_id[] = {
158 MAEMO_CAL_HEADER('b', 't', '-', 'i', 'd', 0, 0, 0)
159 0x0a, 0x00, 0x00, 0x00, 0xa3, 0x4b, 0xf6, 0x96,
160 0xa8, 0xeb, 0xb2, 0x41, 0x00, 0x00, 0x00, 0x00,
161 N8X0_BD_ADDR,
162 };
163
164 static void n8x0_nand_setup(struct n800_s *s)
165 {
166 char *otp_region;
167 DriveInfo *dinfo;
168
169 dinfo = drive_get(IF_MTD, 0, 0);
170 /* Either 0x40 or 0x48 are OK for the device ID */
171 s->nand = onenand_init(dinfo ? dinfo->bdrv : 0,
172 NAND_MFR_SAMSUNG, 0x48, 0, 1,
173 qdev_get_gpio_in(s->cpu->gpio, N8X0_ONENAND_GPIO));
174 omap_gpmc_attach(s->cpu->gpmc, N8X0_ONENAND_CS, 0, onenand_base_update,
175 onenand_base_unmap, s->nand);
176 otp_region = onenand_raw_otp(s->nand);
177
178 memcpy(otp_region + 0x000, n8x0_cal_wlan_mac, sizeof(n8x0_cal_wlan_mac));
179 memcpy(otp_region + 0x800, n8x0_cal_bt_id, sizeof(n8x0_cal_bt_id));
180 /* XXX: in theory should also update the OOB for both pages */
181 }
182
183 static void n8x0_i2c_setup(struct n800_s *s)
184 {
185 DeviceState *dev;
186 qemu_irq tmp_irq = qdev_get_gpio_in(s->cpu->gpio, N8X0_TMP105_GPIO);
187
188 /* Attach the CPU on one end of our I2C bus. */
189 s->i2c = omap_i2c_bus(s->cpu->i2c[0]);
190
191 /* Attach a menelaus PM chip */
192 dev = i2c_create_slave(s->i2c, "twl92230", N8X0_MENELAUS_ADDR);
193 qdev_connect_gpio_out(dev, 3, s->cpu->irq[0][OMAP_INT_24XX_SYS_NIRQ]);
194
195 /* Attach a TMP105 PM chip (A0 wired to ground) */
196 dev = i2c_create_slave(s->i2c, "tmp105", N8X0_TMP105_ADDR);
197 qdev_connect_gpio_out(dev, 0, tmp_irq);
198 }
199
200 /* Touchscreen and keypad controller */
201 static MouseTransformInfo n800_pointercal = {
202 .x = 800,
203 .y = 480,
204 .a = { 14560, -68, -3455208, -39, -9621, 35152972, 65536 },
205 };
206
207 static MouseTransformInfo n810_pointercal = {
208 .x = 800,
209 .y = 480,
210 .a = { 15041, 148, -4731056, 171, -10238, 35933380, 65536 },
211 };
212
213 #define RETU_KEYCODE 61 /* F3 */
214
215 static void n800_key_event(void *opaque, int keycode)
216 {
217 struct n800_s *s = (struct n800_s *) opaque;
218 int code = s->keymap[keycode & 0x7f];
219
220 if (code == -1) {
221 if ((keycode & 0x7f) == RETU_KEYCODE)
222 retu_key_event(s->retu, !(keycode & 0x80));
223 return;
224 }
225
226 tsc210x_key_event(s->ts.chip, code, !(keycode & 0x80));
227 }
228
229 static const int n800_keys[16] = {
230 -1,
231 72, /* Up */
232 63, /* Home (F5) */
233 -1,
234 75, /* Left */
235 28, /* Enter */
236 77, /* Right */
237 -1,
238 1, /* Cycle (ESC) */
239 80, /* Down */
240 62, /* Menu (F4) */
241 -1,
242 66, /* Zoom- (F8) */
243 64, /* FullScreen (F6) */
244 65, /* Zoom+ (F7) */
245 -1,
246 };
247
248 static void n800_tsc_kbd_setup(struct n800_s *s)
249 {
250 int i;
251
252 /* XXX: are the three pins inverted inside the chip between the
253 * tsc and the cpu (N4111)? */
254 qemu_irq penirq = NULL; /* NC */
255 qemu_irq kbirq = qdev_get_gpio_in(s->cpu->gpio, N800_TSC_KP_IRQ_GPIO);
256 qemu_irq dav = qdev_get_gpio_in(s->cpu->gpio, N800_TSC_TS_GPIO);
257
258 s->ts.chip = tsc2301_init(penirq, kbirq, dav);
259 s->ts.opaque = s->ts.chip->opaque;
260 s->ts.txrx = tsc210x_txrx;
261
262 for (i = 0; i < 0x80; i ++)
263 s->keymap[i] = -1;
264 for (i = 0; i < 0x10; i ++)
265 if (n800_keys[i] >= 0)
266 s->keymap[n800_keys[i]] = i;
267
268 qemu_add_kbd_event_handler(n800_key_event, s);
269
270 tsc210x_set_transform(s->ts.chip, &n800_pointercal);
271 }
272
273 static void n810_tsc_setup(struct n800_s *s)
274 {
275 qemu_irq pintdav = qdev_get_gpio_in(s->cpu->gpio, N810_TSC_TS_GPIO);
276
277 s->ts.opaque = tsc2005_init(pintdav);
278 s->ts.txrx = tsc2005_txrx;
279
280 tsc2005_set_transform(s->ts.opaque, &n810_pointercal);
281 }
282
283 /* N810 Keyboard controller */
284 static void n810_key_event(void *opaque, int keycode)
285 {
286 struct n800_s *s = (struct n800_s *) opaque;
287 int code = s->keymap[keycode & 0x7f];
288
289 if (code == -1) {
290 if ((keycode & 0x7f) == RETU_KEYCODE)
291 retu_key_event(s->retu, !(keycode & 0x80));
292 return;
293 }
294
295 lm832x_key_event(s->kbd, code, !(keycode & 0x80));
296 }
297
298 #define M 0
299
300 static int n810_keys[0x80] = {
301 [0x01] = 16, /* Q */
302 [0x02] = 37, /* K */
303 [0x03] = 24, /* O */
304 [0x04] = 25, /* P */
305 [0x05] = 14, /* Backspace */
306 [0x06] = 30, /* A */
307 [0x07] = 31, /* S */
308 [0x08] = 32, /* D */
309 [0x09] = 33, /* F */
310 [0x0a] = 34, /* G */
311 [0x0b] = 35, /* H */
312 [0x0c] = 36, /* J */
313
314 [0x11] = 17, /* W */
315 [0x12] = 62, /* Menu (F4) */
316 [0x13] = 38, /* L */
317 [0x14] = 40, /* ' (Apostrophe) */
318 [0x16] = 44, /* Z */
319 [0x17] = 45, /* X */
320 [0x18] = 46, /* C */
321 [0x19] = 47, /* V */
322 [0x1a] = 48, /* B */
323 [0x1b] = 49, /* N */
324 [0x1c] = 42, /* Shift (Left shift) */
325 [0x1f] = 65, /* Zoom+ (F7) */
326
327 [0x21] = 18, /* E */
328 [0x22] = 39, /* ; (Semicolon) */
329 [0x23] = 12, /* - (Minus) */
330 [0x24] = 13, /* = (Equal) */
331 [0x2b] = 56, /* Fn (Left Alt) */
332 [0x2c] = 50, /* M */
333 [0x2f] = 66, /* Zoom- (F8) */
334
335 [0x31] = 19, /* R */
336 [0x32] = 29 | M, /* Right Ctrl */
337 [0x34] = 57, /* Space */
338 [0x35] = 51, /* , (Comma) */
339 [0x37] = 72 | M, /* Up */
340 [0x3c] = 82 | M, /* Compose (Insert) */
341 [0x3f] = 64, /* FullScreen (F6) */
342
343 [0x41] = 20, /* T */
344 [0x44] = 52, /* . (Dot) */
345 [0x46] = 77 | M, /* Right */
346 [0x4f] = 63, /* Home (F5) */
347 [0x51] = 21, /* Y */
348 [0x53] = 80 | M, /* Down */
349 [0x55] = 28, /* Enter */
350 [0x5f] = 1, /* Cycle (ESC) */
351
352 [0x61] = 22, /* U */
353 [0x64] = 75 | M, /* Left */
354
355 [0x71] = 23, /* I */
356 #if 0
357 [0x75] = 28 | M, /* KP Enter (KP Enter) */
358 #else
359 [0x75] = 15, /* KP Enter (Tab) */
360 #endif
361 };
362
363 #undef M
364
365 static void n810_kbd_setup(struct n800_s *s)
366 {
367 qemu_irq kbd_irq = qdev_get_gpio_in(s->cpu->gpio, N810_KEYBOARD_GPIO);
368 int i;
369
370 for (i = 0; i < 0x80; i ++)
371 s->keymap[i] = -1;
372 for (i = 0; i < 0x80; i ++)
373 if (n810_keys[i] > 0)
374 s->keymap[n810_keys[i]] = i;
375
376 qemu_add_kbd_event_handler(n810_key_event, s);
377
378 /* Attach the LM8322 keyboard to the I2C bus,
379 * should happen in n8x0_i2c_setup and s->kbd be initialised here. */
380 s->kbd = i2c_create_slave(s->i2c, "lm8323", N810_LM8323_ADDR);
381 qdev_connect_gpio_out(s->kbd, 0, kbd_irq);
382 }
383
384 /* LCD MIPI DBI-C controller (URAL) */
385 struct mipid_s {
386 int resp[4];
387 int param[4];
388 int p;
389 int pm;
390 int cmd;
391
392 int sleep;
393 int booster;
394 int te;
395 int selfcheck;
396 int partial;
397 int normal;
398 int vscr;
399 int invert;
400 int onoff;
401 int gamma;
402 uint32_t id;
403 };
404
405 static void mipid_reset(struct mipid_s *s)
406 {
407 if (!s->sleep)
408 fprintf(stderr, "%s: Display off\n", __FUNCTION__);
409
410 s->pm = 0;
411 s->cmd = 0;
412
413 s->sleep = 1;
414 s->booster = 0;
415 s->selfcheck =
416 (1 << 7) | /* Register loading OK. */
417 (1 << 5) | /* The chip is attached. */
418 (1 << 4); /* Display glass still in one piece. */
419 s->te = 0;
420 s->partial = 0;
421 s->normal = 1;
422 s->vscr = 0;
423 s->invert = 0;
424 s->onoff = 1;
425 s->gamma = 0;
426 }
427
428 static uint32_t mipid_txrx(void *opaque, uint32_t cmd, int len)
429 {
430 struct mipid_s *s = (struct mipid_s *) opaque;
431 uint8_t ret;
432
433 if (len > 9)
434 hw_error("%s: FIXME: bad SPI word width %i\n", __FUNCTION__, len);
435
436 if (s->p >= ARRAY_SIZE(s->resp))
437 ret = 0;
438 else
439 ret = s->resp[s->p ++];
440 if (s->pm --> 0)
441 s->param[s->pm] = cmd;
442 else
443 s->cmd = cmd;
444
445 switch (s->cmd) {
446 case 0x00: /* NOP */
447 break;
448
449 case 0x01: /* SWRESET */
450 mipid_reset(s);
451 break;
452
453 case 0x02: /* BSTROFF */
454 s->booster = 0;
455 break;
456 case 0x03: /* BSTRON */
457 s->booster = 1;
458 break;
459
460 case 0x04: /* RDDID */
461 s->p = 0;
462 s->resp[0] = (s->id >> 16) & 0xff;
463 s->resp[1] = (s->id >> 8) & 0xff;
464 s->resp[2] = (s->id >> 0) & 0xff;
465 break;
466
467 case 0x06: /* RD_RED */
468 case 0x07: /* RD_GREEN */
469 /* XXX the bootloader sometimes issues RD_BLUE meaning RDDID so
470 * for the bootloader one needs to change this. */
471 case 0x08: /* RD_BLUE */
472 s->p = 0;
473 /* TODO: return first pixel components */
474 s->resp[0] = 0x01;
475 break;
476
477 case 0x09: /* RDDST */
478 s->p = 0;
479 s->resp[0] = s->booster << 7;
480 s->resp[1] = (5 << 4) | (s->partial << 2) |
481 (s->sleep << 1) | s->normal;
482 s->resp[2] = (s->vscr << 7) | (s->invert << 5) |
483 (s->onoff << 2) | (s->te << 1) | (s->gamma >> 2);
484 s->resp[3] = s->gamma << 6;
485 break;
486
487 case 0x0a: /* RDDPM */
488 s->p = 0;
489 s->resp[0] = (s->onoff << 2) | (s->normal << 3) | (s->sleep << 4) |
490 (s->partial << 5) | (s->sleep << 6) | (s->booster << 7);
491 break;
492 case 0x0b: /* RDDMADCTR */
493 s->p = 0;
494 s->resp[0] = 0;
495 break;
496 case 0x0c: /* RDDCOLMOD */
497 s->p = 0;
498 s->resp[0] = 5; /* 65K colours */
499 break;
500 case 0x0d: /* RDDIM */
501 s->p = 0;
502 s->resp[0] = (s->invert << 5) | (s->vscr << 7) | s->gamma;
503 break;
504 case 0x0e: /* RDDSM */
505 s->p = 0;
506 s->resp[0] = s->te << 7;
507 break;
508 case 0x0f: /* RDDSDR */
509 s->p = 0;
510 s->resp[0] = s->selfcheck;
511 break;
512
513 case 0x10: /* SLPIN */
514 s->sleep = 1;
515 break;
516 case 0x11: /* SLPOUT */
517 s->sleep = 0;
518 s->selfcheck ^= 1 << 6; /* POFF self-diagnosis Ok */
519 break;
520
521 case 0x12: /* PTLON */
522 s->partial = 1;
523 s->normal = 0;
524 s->vscr = 0;
525 break;
526 case 0x13: /* NORON */
527 s->partial = 0;
528 s->normal = 1;
529 s->vscr = 0;
530 break;
531
532 case 0x20: /* INVOFF */
533 s->invert = 0;
534 break;
535 case 0x21: /* INVON */
536 s->invert = 1;
537 break;
538
539 case 0x22: /* APOFF */
540 case 0x23: /* APON */
541 goto bad_cmd;
542
543 case 0x25: /* WRCNTR */
544 if (s->pm < 0)
545 s->pm = 1;
546 goto bad_cmd;
547
548 case 0x26: /* GAMSET */
549 if (!s->pm)
550 s->gamma = ffs(s->param[0] & 0xf) - 1;
551 else if (s->pm < 0)
552 s->pm = 1;
553 break;
554
555 case 0x28: /* DISPOFF */
556 s->onoff = 0;
557 fprintf(stderr, "%s: Display off\n", __FUNCTION__);
558 break;
559 case 0x29: /* DISPON */
560 s->onoff = 1;
561 fprintf(stderr, "%s: Display on\n", __FUNCTION__);
562 break;
563
564 case 0x2a: /* CASET */
565 case 0x2b: /* RASET */
566 case 0x2c: /* RAMWR */
567 case 0x2d: /* RGBSET */
568 case 0x2e: /* RAMRD */
569 case 0x30: /* PTLAR */
570 case 0x33: /* SCRLAR */
571 goto bad_cmd;
572
573 case 0x34: /* TEOFF */
574 s->te = 0;
575 break;
576 case 0x35: /* TEON */
577 if (!s->pm)
578 s->te = 1;
579 else if (s->pm < 0)
580 s->pm = 1;
581 break;
582
583 case 0x36: /* MADCTR */
584 goto bad_cmd;
585
586 case 0x37: /* VSCSAD */
587 s->partial = 0;
588 s->normal = 0;
589 s->vscr = 1;
590 break;
591
592 case 0x38: /* IDMOFF */
593 case 0x39: /* IDMON */
594 case 0x3a: /* COLMOD */
595 goto bad_cmd;
596
597 case 0xb0: /* CLKINT / DISCTL */
598 case 0xb1: /* CLKEXT */
599 if (s->pm < 0)
600 s->pm = 2;
601 break;
602
603 case 0xb4: /* FRMSEL */
604 break;
605
606 case 0xb5: /* FRM8SEL */
607 case 0xb6: /* TMPRNG / INIESC */
608 case 0xb7: /* TMPHIS / NOP2 */
609 case 0xb8: /* TMPREAD / MADCTL */
610 case 0xba: /* DISTCTR */
611 case 0xbb: /* EPVOL */
612 goto bad_cmd;
613
614 case 0xbd: /* Unknown */
615 s->p = 0;
616 s->resp[0] = 0;
617 s->resp[1] = 1;
618 break;
619
620 case 0xc2: /* IFMOD */
621 if (s->pm < 0)
622 s->pm = 2;
623 break;
624
625 case 0xc6: /* PWRCTL */
626 case 0xc7: /* PPWRCTL */
627 case 0xd0: /* EPWROUT */
628 case 0xd1: /* EPWRIN */
629 case 0xd4: /* RDEV */
630 case 0xd5: /* RDRR */
631 goto bad_cmd;
632
633 case 0xda: /* RDID1 */
634 s->p = 0;
635 s->resp[0] = (s->id >> 16) & 0xff;
636 break;
637 case 0xdb: /* RDID2 */
638 s->p = 0;
639 s->resp[0] = (s->id >> 8) & 0xff;
640 break;
641 case 0xdc: /* RDID3 */
642 s->p = 0;
643 s->resp[0] = (s->id >> 0) & 0xff;
644 break;
645
646 default:
647 bad_cmd:
648 fprintf(stderr, "%s: unknown command %02x\n", __FUNCTION__, s->cmd);
649 break;
650 }
651
652 return ret;
653 }
654
655 static void *mipid_init(void)
656 {
657 struct mipid_s *s = (struct mipid_s *) g_malloc0(sizeof(*s));
658
659 s->id = 0x838f03;
660 mipid_reset(s);
661
662 return s;
663 }
664
665 static void n8x0_spi_setup(struct n800_s *s)
666 {
667 void *tsc = s->ts.opaque;
668 void *mipid = mipid_init();
669
670 omap_mcspi_attach(s->cpu->mcspi[0], s->ts.txrx, tsc, 0);
671 omap_mcspi_attach(s->cpu->mcspi[0], mipid_txrx, mipid, 1);
672 }
673
674 /* This task is normally performed by the bootloader. If we're loading
675 * a kernel directly, we need to enable the Blizzard ourselves. */
676 static void n800_dss_init(struct rfbi_chip_s *chip)
677 {
678 uint8_t *fb_blank;
679
680 chip->write(chip->opaque, 0, 0x2a); /* LCD Width register */
681 chip->write(chip->opaque, 1, 0x64);
682 chip->write(chip->opaque, 0, 0x2c); /* LCD HNDP register */
683 chip->write(chip->opaque, 1, 0x1e);
684 chip->write(chip->opaque, 0, 0x2e); /* LCD Height 0 register */
685 chip->write(chip->opaque, 1, 0xe0);
686 chip->write(chip->opaque, 0, 0x30); /* LCD Height 1 register */
687 chip->write(chip->opaque, 1, 0x01);
688 chip->write(chip->opaque, 0, 0x32); /* LCD VNDP register */
689 chip->write(chip->opaque, 1, 0x06);
690 chip->write(chip->opaque, 0, 0x68); /* Display Mode register */
691 chip->write(chip->opaque, 1, 1); /* Enable bit */
692
693 chip->write(chip->opaque, 0, 0x6c);
694 chip->write(chip->opaque, 1, 0x00); /* Input X Start Position */
695 chip->write(chip->opaque, 1, 0x00); /* Input X Start Position */
696 chip->write(chip->opaque, 1, 0x00); /* Input Y Start Position */
697 chip->write(chip->opaque, 1, 0x00); /* Input Y Start Position */
698 chip->write(chip->opaque, 1, 0x1f); /* Input X End Position */
699 chip->write(chip->opaque, 1, 0x03); /* Input X End Position */
700 chip->write(chip->opaque, 1, 0xdf); /* Input Y End Position */
701 chip->write(chip->opaque, 1, 0x01); /* Input Y End Position */
702 chip->write(chip->opaque, 1, 0x00); /* Output X Start Position */
703 chip->write(chip->opaque, 1, 0x00); /* Output X Start Position */
704 chip->write(chip->opaque, 1, 0x00); /* Output Y Start Position */
705 chip->write(chip->opaque, 1, 0x00); /* Output Y Start Position */
706 chip->write(chip->opaque, 1, 0x1f); /* Output X End Position */
707 chip->write(chip->opaque, 1, 0x03); /* Output X End Position */
708 chip->write(chip->opaque, 1, 0xdf); /* Output Y End Position */
709 chip->write(chip->opaque, 1, 0x01); /* Output Y End Position */
710 chip->write(chip->opaque, 1, 0x01); /* Input Data Format */
711 chip->write(chip->opaque, 1, 0x01); /* Data Source Select */
712
713 fb_blank = memset(g_malloc(800 * 480 * 2), 0xff, 800 * 480 * 2);
714 /* Display Memory Data Port */
715 chip->block(chip->opaque, 1, fb_blank, 800 * 480 * 2, 800);
716 g_free(fb_blank);
717 }
718
719 static void n8x0_dss_setup(struct n800_s *s)
720 {
721 s->blizzard.opaque = s1d13745_init(NULL);
722 s->blizzard.block = s1d13745_write_block;
723 s->blizzard.write = s1d13745_write;
724 s->blizzard.read = s1d13745_read;
725
726 omap_rfbi_attach(s->cpu->dss, 0, &s->blizzard);
727 }
728
729 static void n8x0_cbus_setup(struct n800_s *s)
730 {
731 qemu_irq dat_out = qdev_get_gpio_in(s->cpu->gpio, N8X0_CBUS_DAT_GPIO);
732 qemu_irq retu_irq = qdev_get_gpio_in(s->cpu->gpio, N8X0_RETU_GPIO);
733 qemu_irq tahvo_irq = qdev_get_gpio_in(s->cpu->gpio, N8X0_TAHVO_GPIO);
734
735 CBus *cbus = cbus_init(dat_out);
736
737 qdev_connect_gpio_out(s->cpu->gpio, N8X0_CBUS_CLK_GPIO, cbus->clk);
738 qdev_connect_gpio_out(s->cpu->gpio, N8X0_CBUS_DAT_GPIO, cbus->dat);
739 qdev_connect_gpio_out(s->cpu->gpio, N8X0_CBUS_SEL_GPIO, cbus->sel);
740
741 cbus_attach(cbus, s->retu = retu_init(retu_irq, 1));
742 cbus_attach(cbus, s->tahvo = tahvo_init(tahvo_irq, 1));
743 }
744
745 static void n8x0_uart_setup(struct n800_s *s)
746 {
747 CharDriverState *radio = uart_hci_init(
748 qdev_get_gpio_in(s->cpu->gpio, N8X0_BT_HOST_WKUP_GPIO));
749
750 qdev_connect_gpio_out(s->cpu->gpio, N8X0_BT_RESET_GPIO,
751 csrhci_pins_get(radio)[csrhci_pin_reset]);
752 qdev_connect_gpio_out(s->cpu->gpio, N8X0_BT_WKUP_GPIO,
753 csrhci_pins_get(radio)[csrhci_pin_wakeup]);
754
755 omap_uart_attach(s->cpu->uart[BT_UART], radio);
756 }
757
758 static void n8x0_usb_power_cb(void *opaque, int line, int level)
759 {
760 struct n800_s *s = opaque;
761
762 tusb6010_power(s->usb, level);
763 }
764
765 static void n8x0_usb_setup(struct n800_s *s)
766 {
767 qemu_irq tusb_irq = qdev_get_gpio_in(s->cpu->gpio, N8X0_TUSB_INT_GPIO);
768 qemu_irq tusb_pwr = qemu_allocate_irqs(n8x0_usb_power_cb, s, 1)[0];
769 TUSBState *tusb = tusb6010_init(tusb_irq);
770
771 /* Using the NOR interface */
772 omap_gpmc_attach(s->cpu->gpmc, N8X0_USB_ASYNC_CS,
773 tusb6010_async_io(tusb), NULL, NULL, tusb);
774 omap_gpmc_attach(s->cpu->gpmc, N8X0_USB_SYNC_CS,
775 tusb6010_sync_io(tusb), NULL, NULL, tusb);
776
777 s->usb = tusb;
778 qdev_connect_gpio_out(s->cpu->gpio, N8X0_TUSB_ENABLE_GPIO, tusb_pwr);
779 }
780
781 /* Setup done before the main bootloader starts by some early setup code
782 * - used when we want to run the main bootloader in emulation. This
783 * isn't documented. */
784 static uint32_t n800_pinout[104] = {
785 0x080f00d8, 0x00d40808, 0x03080808, 0x080800d0,
786 0x00dc0808, 0x0b0f0f00, 0x080800b4, 0x00c00808,
787 0x08080808, 0x180800c4, 0x00b80000, 0x08080808,
788 0x080800bc, 0x00cc0808, 0x08081818, 0x18180128,
789 0x01241800, 0x18181818, 0x000000f0, 0x01300000,
790 0x00001b0b, 0x1b0f0138, 0x00e0181b, 0x1b031b0b,
791 0x180f0078, 0x00740018, 0x0f0f0f1a, 0x00000080,
792 0x007c0000, 0x00000000, 0x00000088, 0x00840000,
793 0x00000000, 0x00000094, 0x00980300, 0x0f180003,
794 0x0000008c, 0x00900f0f, 0x0f0f1b00, 0x0f00009c,
795 0x01140000, 0x1b1b0f18, 0x0818013c, 0x01400008,
796 0x00001818, 0x000b0110, 0x010c1800, 0x0b030b0f,
797 0x181800f4, 0x00f81818, 0x00000018, 0x000000fc,
798 0x00401808, 0x00000000, 0x0f1b0030, 0x003c0008,
799 0x00000000, 0x00000038, 0x00340000, 0x00000000,
800 0x1a080070, 0x00641a1a, 0x08080808, 0x08080060,
801 0x005c0808, 0x08080808, 0x08080058, 0x00540808,
802 0x08080808, 0x0808006c, 0x00680808, 0x08080808,
803 0x000000a8, 0x00b00000, 0x08080808, 0x000000a0,
804 0x00a40000, 0x00000000, 0x08ff0050, 0x004c0808,
805 0xffffffff, 0xffff0048, 0x0044ffff, 0xffffffff,
806 0x000000ac, 0x01040800, 0x08080b0f, 0x18180100,
807 0x01081818, 0x0b0b1808, 0x1a0300e4, 0x012c0b1a,
808 0x02020018, 0x0b000134, 0x011c0800, 0x0b1b1b00,
809 0x0f0000c8, 0x00ec181b, 0x000f0f02, 0x00180118,
810 0x01200000, 0x0f0b1b1b, 0x0f0200e8, 0x0000020b,
811 };
812
813 static void n800_setup_nolo_tags(void *sram_base)
814 {
815 int i;
816 uint32_t *p = sram_base + 0x8000;
817 uint32_t *v = sram_base + 0xa000;
818
819 memset(p, 0, 0x3000);
820
821 strcpy((void *) (p + 0), "QEMU N800");
822
823 strcpy((void *) (p + 8), "F5");
824
825 stl_raw(p + 10, 0x04f70000);
826 strcpy((void *) (p + 9), "RX-34");
827
828 /* RAM size in MB? */
829 stl_raw(p + 12, 0x80);
830
831 /* Pointer to the list of tags */
832 stl_raw(p + 13, OMAP2_SRAM_BASE + 0x9000);
833
834 /* The NOLO tags start here */
835 p = sram_base + 0x9000;
836 #define ADD_TAG(tag, len) \
837 stw_raw((uint16_t *) p + 0, tag); \
838 stw_raw((uint16_t *) p + 1, len); p ++; \
839 stl_raw(p ++, OMAP2_SRAM_BASE | (((void *) v - sram_base) & 0xffff));
840
841 /* OMAP STI console? Pin out settings? */
842 ADD_TAG(0x6e01, 414);
843 for (i = 0; i < ARRAY_SIZE(n800_pinout); i ++)
844 stl_raw(v ++, n800_pinout[i]);
845
846 /* Kernel memsize? */
847 ADD_TAG(0x6e05, 1);
848 stl_raw(v ++, 2);
849
850 /* NOLO serial console */
851 ADD_TAG(0x6e02, 4);
852 stl_raw(v ++, XLDR_LL_UART); /* UART number (1 - 3) */
853
854 #if 0
855 /* CBUS settings (Retu/AVilma) */
856 ADD_TAG(0x6e03, 6);
857 stw_raw((uint16_t *) v + 0, 65); /* CBUS GPIO0 */
858 stw_raw((uint16_t *) v + 1, 66); /* CBUS GPIO1 */
859 stw_raw((uint16_t *) v + 2, 64); /* CBUS GPIO2 */
860 v += 2;
861 #endif
862
863 /* Nokia ASIC BB5 (Retu/Tahvo) */
864 ADD_TAG(0x6e0a, 4);
865 stw_raw((uint16_t *) v + 0, 111); /* "Retu" interrupt GPIO */
866 stw_raw((uint16_t *) v + 1, 108); /* "Tahvo" interrupt GPIO */
867 v ++;
868
869 /* LCD console? */
870 ADD_TAG(0x6e04, 4);
871 stw_raw((uint16_t *) v + 0, 30); /* ??? */
872 stw_raw((uint16_t *) v + 1, 24); /* ??? */
873 v ++;
874
875 #if 0
876 /* LCD settings */
877 ADD_TAG(0x6e06, 2);
878 stw_raw((uint16_t *) (v ++), 15); /* ??? */
879 #endif
880
881 /* I^2C (Menelaus) */
882 ADD_TAG(0x6e07, 4);
883 stl_raw(v ++, 0x00720000); /* ??? */
884
885 /* Unknown */
886 ADD_TAG(0x6e0b, 6);
887 stw_raw((uint16_t *) v + 0, 94); /* ??? */
888 stw_raw((uint16_t *) v + 1, 23); /* ??? */
889 stw_raw((uint16_t *) v + 2, 0); /* ??? */
890 v += 2;
891
892 /* OMAP gpio switch info */
893 ADD_TAG(0x6e0c, 80);
894 strcpy((void *) v, "bat_cover"); v += 3;
895 stw_raw((uint16_t *) v + 0, 110); /* GPIO num ??? */
896 stw_raw((uint16_t *) v + 1, 1); /* GPIO num ??? */
897 v += 2;
898 strcpy((void *) v, "cam_act"); v += 3;
899 stw_raw((uint16_t *) v + 0, 95); /* GPIO num ??? */
900 stw_raw((uint16_t *) v + 1, 32); /* GPIO num ??? */
901 v += 2;
902 strcpy((void *) v, "cam_turn"); v += 3;
903 stw_raw((uint16_t *) v + 0, 12); /* GPIO num ??? */
904 stw_raw((uint16_t *) v + 1, 33); /* GPIO num ??? */
905 v += 2;
906 strcpy((void *) v, "headphone"); v += 3;
907 stw_raw((uint16_t *) v + 0, 107); /* GPIO num ??? */
908 stw_raw((uint16_t *) v + 1, 17); /* GPIO num ??? */
909 v += 2;
910
911 /* Bluetooth */
912 ADD_TAG(0x6e0e, 12);
913 stl_raw(v ++, 0x5c623d01); /* ??? */
914 stl_raw(v ++, 0x00000201); /* ??? */
915 stl_raw(v ++, 0x00000000); /* ??? */
916
917 /* CX3110x WLAN settings */
918 ADD_TAG(0x6e0f, 8);
919 stl_raw(v ++, 0x00610025); /* ??? */
920 stl_raw(v ++, 0xffff0057); /* ??? */
921
922 /* MMC host settings */
923 ADD_TAG(0x6e10, 12);
924 stl_raw(v ++, 0xffff000f); /* ??? */
925 stl_raw(v ++, 0xffffffff); /* ??? */
926 stl_raw(v ++, 0x00000060); /* ??? */
927
928 /* OneNAND chip select */
929 ADD_TAG(0x6e11, 10);
930 stl_raw(v ++, 0x00000401); /* ??? */
931 stl_raw(v ++, 0x0002003a); /* ??? */
932 stl_raw(v ++, 0x00000002); /* ??? */
933
934 /* TEA5761 sensor settings */
935 ADD_TAG(0x6e12, 2);
936 stl_raw(v ++, 93); /* GPIO num ??? */
937
938 #if 0
939 /* Unknown tag */
940 ADD_TAG(6e09, 0);
941
942 /* Kernel UART / console */
943 ADD_TAG(6e12, 0);
944 #endif
945
946 /* End of the list */
947 stl_raw(p ++, 0x00000000);
948 stl_raw(p ++, 0x00000000);
949 }
950
951 /* This task is normally performed by the bootloader. If we're loading
952 * a kernel directly, we need to set up GPMC mappings ourselves. */
953 static void n800_gpmc_init(struct n800_s *s)
954 {
955 uint32_t config7 =
956 (0xf << 8) | /* MASKADDRESS */
957 (1 << 6) | /* CSVALID */
958 (4 << 0); /* BASEADDRESS */
959
960 cpu_physical_memory_write(0x6800a078, /* GPMC_CONFIG7_0 */
961 (void *) &config7, sizeof(config7));
962 }
963
964 /* Setup sequence done by the bootloader */
965 static void n8x0_boot_init(void *opaque)
966 {
967 struct n800_s *s = (struct n800_s *) opaque;
968 uint32_t buf;
969
970 /* PRCM setup */
971 #define omap_writel(addr, val) \
972 buf = (val); \
973 cpu_physical_memory_write(addr, (void *) &buf, sizeof(buf))
974
975 omap_writel(0x48008060, 0x41); /* PRCM_CLKSRC_CTRL */
976 omap_writel(0x48008070, 1); /* PRCM_CLKOUT_CTRL */
977 omap_writel(0x48008078, 0); /* PRCM_CLKEMUL_CTRL */
978 omap_writel(0x48008090, 0); /* PRCM_VOLTSETUP */
979 omap_writel(0x48008094, 0); /* PRCM_CLKSSETUP */
980 omap_writel(0x48008098, 0); /* PRCM_POLCTRL */
981 omap_writel(0x48008140, 2); /* CM_CLKSEL_MPU */
982 omap_writel(0x48008148, 0); /* CM_CLKSTCTRL_MPU */
983 omap_writel(0x48008158, 1); /* RM_RSTST_MPU */
984 omap_writel(0x480081c8, 0x15); /* PM_WKDEP_MPU */
985 omap_writel(0x480081d4, 0x1d4); /* PM_EVGENCTRL_MPU */
986 omap_writel(0x480081d8, 0); /* PM_EVEGENONTIM_MPU */
987 omap_writel(0x480081dc, 0); /* PM_EVEGENOFFTIM_MPU */
988 omap_writel(0x480081e0, 0xc); /* PM_PWSTCTRL_MPU */
989 omap_writel(0x48008200, 0x047e7ff7); /* CM_FCLKEN1_CORE */
990 omap_writel(0x48008204, 0x00000004); /* CM_FCLKEN2_CORE */
991 omap_writel(0x48008210, 0x047e7ff1); /* CM_ICLKEN1_CORE */
992 omap_writel(0x48008214, 0x00000004); /* CM_ICLKEN2_CORE */
993 omap_writel(0x4800821c, 0x00000000); /* CM_ICLKEN4_CORE */
994 omap_writel(0x48008230, 0); /* CM_AUTOIDLE1_CORE */
995 omap_writel(0x48008234, 0); /* CM_AUTOIDLE2_CORE */
996 omap_writel(0x48008238, 7); /* CM_AUTOIDLE3_CORE */
997 omap_writel(0x4800823c, 0); /* CM_AUTOIDLE4_CORE */
998 omap_writel(0x48008240, 0x04360626); /* CM_CLKSEL1_CORE */
999 omap_writel(0x48008244, 0x00000014); /* CM_CLKSEL2_CORE */
1000 omap_writel(0x48008248, 0); /* CM_CLKSTCTRL_CORE */
1001 omap_writel(0x48008300, 0x00000000); /* CM_FCLKEN_GFX */
1002 omap_writel(0x48008310, 0x00000000); /* CM_ICLKEN_GFX */
1003 omap_writel(0x48008340, 0x00000001); /* CM_CLKSEL_GFX */
1004 omap_writel(0x48008400, 0x00000004); /* CM_FCLKEN_WKUP */
1005 omap_writel(0x48008410, 0x00000004); /* CM_ICLKEN_WKUP */
1006 omap_writel(0x48008440, 0x00000000); /* CM_CLKSEL_WKUP */
1007 omap_writel(0x48008500, 0x000000cf); /* CM_CLKEN_PLL */
1008 omap_writel(0x48008530, 0x0000000c); /* CM_AUTOIDLE_PLL */
1009 omap_writel(0x48008540, /* CM_CLKSEL1_PLL */
1010 (0x78 << 12) | (6 << 8));
1011 omap_writel(0x48008544, 2); /* CM_CLKSEL2_PLL */
1012
1013 /* GPMC setup */
1014 n800_gpmc_init(s);
1015
1016 /* Video setup */
1017 n800_dss_init(&s->blizzard);
1018
1019 /* CPU setup */
1020 s->cpu->env->GE = 0x5;
1021
1022 /* If the machine has a slided keyboard, open it */
1023 if (s->kbd)
1024 qemu_irq_raise(qdev_get_gpio_in(s->cpu->gpio, N810_SLIDE_GPIO));
1025 }
1026
1027 #define OMAP_TAG_NOKIA_BT 0x4e01
1028 #define OMAP_TAG_WLAN_CX3110X 0x4e02
1029 #define OMAP_TAG_CBUS 0x4e03
1030 #define OMAP_TAG_EM_ASIC_BB5 0x4e04
1031
1032 static struct omap_gpiosw_info_s {
1033 const char *name;
1034 int line;
1035 int type;
1036 } n800_gpiosw_info[] = {
1037 {
1038 "bat_cover", N800_BAT_COVER_GPIO,
1039 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1040 }, {
1041 "cam_act", N800_CAM_ACT_GPIO,
1042 OMAP_GPIOSW_TYPE_ACTIVITY,
1043 }, {
1044 "cam_turn", N800_CAM_TURN_GPIO,
1045 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED,
1046 }, {
1047 "headphone", N8X0_HEADPHONE_GPIO,
1048 OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED,
1049 },
1050 { NULL }
1051 }, n810_gpiosw_info[] = {
1052 {
1053 "gps_reset", N810_GPS_RESET_GPIO,
1054 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT,
1055 }, {
1056 "gps_wakeup", N810_GPS_WAKEUP_GPIO,
1057 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT,
1058 }, {
1059 "headphone", N8X0_HEADPHONE_GPIO,
1060 OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED,
1061 }, {
1062 "kb_lock", N810_KB_LOCK_GPIO,
1063 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1064 }, {
1065 "sleepx_led", N810_SLEEPX_LED_GPIO,
1066 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED | OMAP_GPIOSW_OUTPUT,
1067 }, {
1068 "slide", N810_SLIDE_GPIO,
1069 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
1070 },
1071 { NULL }
1072 };
1073
1074 static struct omap_partition_info_s {
1075 uint32_t offset;
1076 uint32_t size;
1077 int mask;
1078 const char *name;
1079 } n800_part_info[] = {
1080 { 0x00000000, 0x00020000, 0x3, "bootloader" },
1081 { 0x00020000, 0x00060000, 0x0, "config" },
1082 { 0x00080000, 0x00200000, 0x0, "kernel" },
1083 { 0x00280000, 0x00200000, 0x3, "initfs" },
1084 { 0x00480000, 0x0fb80000, 0x3, "rootfs" },
1085
1086 { 0, 0, 0, NULL }
1087 }, n810_part_info[] = {
1088 { 0x00000000, 0x00020000, 0x3, "bootloader" },
1089 { 0x00020000, 0x00060000, 0x0, "config" },
1090 { 0x00080000, 0x00220000, 0x0, "kernel" },
1091 { 0x002a0000, 0x00400000, 0x0, "initfs" },
1092 { 0x006a0000, 0x0f960000, 0x0, "rootfs" },
1093
1094 { 0, 0, 0, NULL }
1095 };
1096
1097 static bdaddr_t n8x0_bd_addr = {{ N8X0_BD_ADDR }};
1098
1099 static int n8x0_atag_setup(void *p, int model)
1100 {
1101 uint8_t *b;
1102 uint16_t *w;
1103 uint32_t *l;
1104 struct omap_gpiosw_info_s *gpiosw;
1105 struct omap_partition_info_s *partition;
1106 const char *tag;
1107
1108 w = p;
1109
1110 stw_raw(w ++, OMAP_TAG_UART); /* u16 tag */
1111 stw_raw(w ++, 4); /* u16 len */
1112 stw_raw(w ++, (1 << 2) | (1 << 1) | (1 << 0)); /* uint enabled_uarts */
1113 w ++;
1114
1115 #if 0
1116 stw_raw(w ++, OMAP_TAG_SERIAL_CONSOLE); /* u16 tag */
1117 stw_raw(w ++, 4); /* u16 len */
1118 stw_raw(w ++, XLDR_LL_UART + 1); /* u8 console_uart */
1119 stw_raw(w ++, 115200); /* u32 console_speed */
1120 #endif
1121
1122 stw_raw(w ++, OMAP_TAG_LCD); /* u16 tag */
1123 stw_raw(w ++, 36); /* u16 len */
1124 strcpy((void *) w, "QEMU LCD panel"); /* char panel_name[16] */
1125 w += 8;
1126 strcpy((void *) w, "blizzard"); /* char ctrl_name[16] */
1127 w += 8;
1128 stw_raw(w ++, N810_BLIZZARD_RESET_GPIO); /* TODO: n800 s16 nreset_gpio */
1129 stw_raw(w ++, 24); /* u8 data_lines */
1130
1131 stw_raw(w ++, OMAP_TAG_CBUS); /* u16 tag */
1132 stw_raw(w ++, 8); /* u16 len */
1133 stw_raw(w ++, N8X0_CBUS_CLK_GPIO); /* s16 clk_gpio */
1134 stw_raw(w ++, N8X0_CBUS_DAT_GPIO); /* s16 dat_gpio */
1135 stw_raw(w ++, N8X0_CBUS_SEL_GPIO); /* s16 sel_gpio */
1136 w ++;
1137
1138 stw_raw(w ++, OMAP_TAG_EM_ASIC_BB5); /* u16 tag */
1139 stw_raw(w ++, 4); /* u16 len */
1140 stw_raw(w ++, N8X0_RETU_GPIO); /* s16 retu_irq_gpio */
1141 stw_raw(w ++, N8X0_TAHVO_GPIO); /* s16 tahvo_irq_gpio */
1142
1143 gpiosw = (model == 810) ? n810_gpiosw_info : n800_gpiosw_info;
1144 for (; gpiosw->name; gpiosw ++) {
1145 stw_raw(w ++, OMAP_TAG_GPIO_SWITCH); /* u16 tag */
1146 stw_raw(w ++, 20); /* u16 len */
1147 strcpy((void *) w, gpiosw->name); /* char name[12] */
1148 w += 6;
1149 stw_raw(w ++, gpiosw->line); /* u16 gpio */
1150 stw_raw(w ++, gpiosw->type);
1151 stw_raw(w ++, 0);
1152 stw_raw(w ++, 0);
1153 }
1154
1155 stw_raw(w ++, OMAP_TAG_NOKIA_BT); /* u16 tag */
1156 stw_raw(w ++, 12); /* u16 len */
1157 b = (void *) w;
1158 stb_raw(b ++, 0x01); /* u8 chip_type (CSR) */
1159 stb_raw(b ++, N8X0_BT_WKUP_GPIO); /* u8 bt_wakeup_gpio */
1160 stb_raw(b ++, N8X0_BT_HOST_WKUP_GPIO); /* u8 host_wakeup_gpio */
1161 stb_raw(b ++, N8X0_BT_RESET_GPIO); /* u8 reset_gpio */
1162 stb_raw(b ++, BT_UART + 1); /* u8 bt_uart */
1163 memcpy(b, &n8x0_bd_addr, 6); /* u8 bd_addr[6] */
1164 b += 6;
1165 stb_raw(b ++, 0x02); /* u8 bt_sysclk (38.4) */
1166 w = (void *) b;
1167
1168 stw_raw(w ++, OMAP_TAG_WLAN_CX3110X); /* u16 tag */
1169 stw_raw(w ++, 8); /* u16 len */
1170 stw_raw(w ++, 0x25); /* u8 chip_type */
1171 stw_raw(w ++, N8X0_WLAN_PWR_GPIO); /* s16 power_gpio */
1172 stw_raw(w ++, N8X0_WLAN_IRQ_GPIO); /* s16 irq_gpio */
1173 stw_raw(w ++, -1); /* s16 spi_cs_gpio */
1174
1175 stw_raw(w ++, OMAP_TAG_MMC); /* u16 tag */
1176 stw_raw(w ++, 16); /* u16 len */
1177 if (model == 810) {
1178 stw_raw(w ++, 0x23f); /* unsigned flags */
1179 stw_raw(w ++, -1); /* s16 power_pin */
1180 stw_raw(w ++, -1); /* s16 switch_pin */
1181 stw_raw(w ++, -1); /* s16 wp_pin */
1182 stw_raw(w ++, 0x240); /* unsigned flags */
1183 stw_raw(w ++, 0xc000); /* s16 power_pin */
1184 stw_raw(w ++, 0x0248); /* s16 switch_pin */
1185 stw_raw(w ++, 0xc000); /* s16 wp_pin */
1186 } else {
1187 stw_raw(w ++, 0xf); /* unsigned flags */
1188 stw_raw(w ++, -1); /* s16 power_pin */
1189 stw_raw(w ++, -1); /* s16 switch_pin */
1190 stw_raw(w ++, -1); /* s16 wp_pin */
1191 stw_raw(w ++, 0); /* unsigned flags */
1192 stw_raw(w ++, 0); /* s16 power_pin */
1193 stw_raw(w ++, 0); /* s16 switch_pin */
1194 stw_raw(w ++, 0); /* s16 wp_pin */
1195 }
1196
1197 stw_raw(w ++, OMAP_TAG_TEA5761); /* u16 tag */
1198 stw_raw(w ++, 4); /* u16 len */
1199 stw_raw(w ++, N8X0_TEA5761_CS_GPIO); /* u16 enable_gpio */
1200 w ++;
1201
1202 partition = (model == 810) ? n810_part_info : n800_part_info;
1203 for (; partition->name; partition ++) {
1204 stw_raw(w ++, OMAP_TAG_PARTITION); /* u16 tag */
1205 stw_raw(w ++, 28); /* u16 len */
1206 strcpy((void *) w, partition->name); /* char name[16] */
1207 l = (void *) (w + 8);
1208 stl_raw(l ++, partition->size); /* unsigned int size */
1209 stl_raw(l ++, partition->offset); /* unsigned int offset */
1210 stl_raw(l ++, partition->mask); /* unsigned int mask_flags */
1211 w = (void *) l;
1212 }
1213
1214 stw_raw(w ++, OMAP_TAG_BOOT_REASON); /* u16 tag */
1215 stw_raw(w ++, 12); /* u16 len */
1216 #if 0
1217 strcpy((void *) w, "por"); /* char reason_str[12] */
1218 strcpy((void *) w, "charger"); /* char reason_str[12] */
1219 strcpy((void *) w, "32wd_to"); /* char reason_str[12] */
1220 strcpy((void *) w, "sw_rst"); /* char reason_str[12] */
1221 strcpy((void *) w, "mbus"); /* char reason_str[12] */
1222 strcpy((void *) w, "unknown"); /* char reason_str[12] */
1223 strcpy((void *) w, "swdg_to"); /* char reason_str[12] */
1224 strcpy((void *) w, "sec_vio"); /* char reason_str[12] */
1225 strcpy((void *) w, "pwr_key"); /* char reason_str[12] */
1226 strcpy((void *) w, "rtc_alarm"); /* char reason_str[12] */
1227 #else
1228 strcpy((void *) w, "pwr_key"); /* char reason_str[12] */
1229 #endif
1230 w += 6;
1231
1232 tag = (model == 810) ? "RX-44" : "RX-34";
1233 stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
1234 stw_raw(w ++, 24); /* u16 len */
1235 strcpy((void *) w, "product"); /* char component[12] */
1236 w += 6;
1237 strcpy((void *) w, tag); /* char version[12] */
1238 w += 6;
1239
1240 stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
1241 stw_raw(w ++, 24); /* u16 len */
1242 strcpy((void *) w, "hw-build"); /* char component[12] */
1243 w += 6;
1244 strcpy((void *) w, "QEMU " QEMU_VERSION); /* char version[12] */
1245 w += 6;
1246
1247 tag = (model == 810) ? "1.1.10-qemu" : "1.1.6-qemu";
1248 stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */
1249 stw_raw(w ++, 24); /* u16 len */
1250 strcpy((void *) w, "nolo"); /* char component[12] */
1251 w += 6;
1252 strcpy((void *) w, tag); /* char version[12] */
1253 w += 6;
1254
1255 return (void *) w - p;
1256 }
1257
1258 static int n800_atag_setup(const struct arm_boot_info *info, void *p)
1259 {
1260 return n8x0_atag_setup(p, 800);
1261 }
1262
1263 static int n810_atag_setup(const struct arm_boot_info *info, void *p)
1264 {
1265 return n8x0_atag_setup(p, 810);
1266 }
1267
1268 static void n8x0_init(ram_addr_t ram_size, const char *boot_device,
1269 const char *kernel_filename,
1270 const char *kernel_cmdline, const char *initrd_filename,
1271 const char *cpu_model, struct arm_boot_info *binfo, int model)
1272 {
1273 struct n800_s *s = (struct n800_s *) g_malloc0(sizeof(*s));
1274 int sdram_size = binfo->ram_size;
1275 DisplayState *ds;
1276
1277 s->cpu = omap2420_mpu_init(sdram_size, cpu_model);
1278
1279 /* Setup peripherals
1280 *
1281 * Believed external peripherals layout in the N810:
1282 * (spi bus 1)
1283 * tsc2005
1284 * lcd_mipid
1285 * (spi bus 2)
1286 * Conexant cx3110x (WLAN)
1287 * optional: pc2400m (WiMAX)
1288 * (i2c bus 0)
1289 * TLV320AIC33 (audio codec)
1290 * TCM825x (camera by Toshiba)
1291 * lp5521 (clever LEDs)
1292 * tsl2563 (light sensor, hwmon, model 7, rev. 0)
1293 * lm8323 (keypad, manf 00, rev 04)
1294 * (i2c bus 1)
1295 * tmp105 (temperature sensor, hwmon)
1296 * menelaus (pm)
1297 * (somewhere on i2c - maybe N800-only)
1298 * tea5761 (FM tuner)
1299 * (serial 0)
1300 * GPS
1301 * (some serial port)
1302 * csr41814 (Bluetooth)
1303 */
1304 n8x0_gpio_setup(s);
1305 n8x0_nand_setup(s);
1306 n8x0_i2c_setup(s);
1307 if (model == 800)
1308 n800_tsc_kbd_setup(s);
1309 else if (model == 810) {
1310 n810_tsc_setup(s);
1311 n810_kbd_setup(s);
1312 }
1313 n8x0_spi_setup(s);
1314 n8x0_dss_setup(s);
1315 n8x0_cbus_setup(s);
1316 n8x0_uart_setup(s);
1317 if (usb_enabled)
1318 n8x0_usb_setup(s);
1319
1320 if (kernel_filename) {
1321 /* Or at the linux loader. */
1322 binfo->kernel_filename = kernel_filename;
1323 binfo->kernel_cmdline = kernel_cmdline;
1324 binfo->initrd_filename = initrd_filename;
1325 arm_load_kernel(s->cpu->env, binfo);
1326
1327 qemu_register_reset(n8x0_boot_init, s);
1328 }
1329
1330 if (option_rom[0].name && (boot_device[0] == 'n' || !kernel_filename)) {
1331 int rom_size;
1332 uint8_t nolo_tags[0x10000];
1333 /* No, wait, better start at the ROM. */
1334 s->cpu->env->regs[15] = OMAP2_Q2_BASE + 0x400000;
1335
1336 /* This is intended for loading the `secondary.bin' program from
1337 * Nokia images (the NOLO bootloader). The entry point seems
1338 * to be at OMAP2_Q2_BASE + 0x400000.
1339 *
1340 * The `2nd.bin' files contain some kind of earlier boot code and
1341 * for them the entry point needs to be set to OMAP2_SRAM_BASE.
1342 *
1343 * The code above is for loading the `zImage' file from Nokia
1344 * images. */
1345 rom_size = load_image_targphys(option_rom[0].name,
1346 OMAP2_Q2_BASE + 0x400000,
1347 sdram_size - 0x400000);
1348 printf("%i bytes of image loaded\n", rom_size);
1349
1350 n800_setup_nolo_tags(nolo_tags);
1351 cpu_physical_memory_write(OMAP2_SRAM_BASE, nolo_tags, 0x10000);
1352 }
1353 /* FIXME: We shouldn't really be doing this here. The LCD controller
1354 will set the size once configured, so this just sets an initial
1355 size until the guest activates the display. */
1356 ds = get_displaystate();
1357 ds->surface = qemu_resize_displaysurface(ds, 800, 480);
1358 dpy_resize(ds);
1359 }
1360
1361 static struct arm_boot_info n800_binfo = {
1362 .loader_start = OMAP2_Q2_BASE,
1363 /* Actually two chips of 0x4000000 bytes each */
1364 .ram_size = 0x08000000,
1365 .board_id = 0x4f7,
1366 .atag_board = n800_atag_setup,
1367 };
1368
1369 static struct arm_boot_info n810_binfo = {
1370 .loader_start = OMAP2_Q2_BASE,
1371 /* Actually two chips of 0x4000000 bytes each */
1372 .ram_size = 0x08000000,
1373 /* 0x60c and 0x6bf (WiMAX Edition) have been assigned but are not
1374 * used by some older versions of the bootloader and 5555 is used
1375 * instead (including versions that shipped with many devices). */
1376 .board_id = 0x60c,
1377 .atag_board = n810_atag_setup,
1378 };
1379
1380 static void n800_init(ram_addr_t ram_size,
1381 const char *boot_device,
1382 const char *kernel_filename, const char *kernel_cmdline,
1383 const char *initrd_filename, const char *cpu_model)
1384 {
1385 return n8x0_init(ram_size, boot_device,
1386 kernel_filename, kernel_cmdline, initrd_filename,
1387 cpu_model, &n800_binfo, 800);
1388 }
1389
1390 static void n810_init(ram_addr_t ram_size,
1391 const char *boot_device,
1392 const char *kernel_filename, const char *kernel_cmdline,
1393 const char *initrd_filename, const char *cpu_model)
1394 {
1395 return n8x0_init(ram_size, boot_device,
1396 kernel_filename, kernel_cmdline, initrd_filename,
1397 cpu_model, &n810_binfo, 810);
1398 }
1399
1400 static QEMUMachine n800_machine = {
1401 .name = "n800",
1402 .desc = "Nokia N800 tablet aka. RX-34 (OMAP2420)",
1403 .init = n800_init,
1404 };
1405
1406 static QEMUMachine n810_machine = {
1407 .name = "n810",
1408 .desc = "Nokia N810 tablet aka. RX-44 (OMAP2420)",
1409 .init = n810_init,
1410 };
1411
1412 static void nseries_machine_init(void)
1413 {
1414 qemu_register_machine(&n800_machine);
1415 qemu_register_machine(&n810_machine);
1416 }
1417
1418 machine_init(nseries_machine_init);
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