2 * QEMU Firmware configuration device emulation
4 * Copyright (c) 2008 Gleb Natapov
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 #include "qemu/osdep.h"
26 #include "sysemu/sysemu.h"
27 #include "sysemu/dma.h"
28 #include "hw/boards.h"
29 #include "hw/isa/isa.h"
30 #include "hw/nvram/fw_cfg.h"
31 #include "hw/sysbus.h"
33 #include "qemu/error-report.h"
34 #include "qemu/config-file.h"
35 #include "qemu/cutils.h"
36 #include "qapi/error.h"
38 #define FW_CFG_NAME "fw_cfg"
39 #define FW_CFG_PATH "/machine/" FW_CFG_NAME
41 #define TYPE_FW_CFG "fw_cfg"
42 #define TYPE_FW_CFG_IO "fw_cfg_io"
43 #define TYPE_FW_CFG_MEM "fw_cfg_mem"
45 #define FW_CFG(obj) OBJECT_CHECK(FWCfgState, (obj), TYPE_FW_CFG)
46 #define FW_CFG_IO(obj) OBJECT_CHECK(FWCfgIoState, (obj), TYPE_FW_CFG_IO)
47 #define FW_CFG_MEM(obj) OBJECT_CHECK(FWCfgMemState, (obj), TYPE_FW_CFG_MEM)
49 /* FW_CFG_VERSION bits */
50 #define FW_CFG_VERSION 0x01
51 #define FW_CFG_VERSION_DMA 0x02
53 /* FW_CFG_DMA_CONTROL bits */
54 #define FW_CFG_DMA_CTL_ERROR 0x01
55 #define FW_CFG_DMA_CTL_READ 0x02
56 #define FW_CFG_DMA_CTL_SKIP 0x04
57 #define FW_CFG_DMA_CTL_SELECT 0x08
58 #define FW_CFG_DMA_CTL_WRITE 0x10
60 #define FW_CFG_DMA_SIGNATURE 0x51454d5520434647ULL /* "QEMU CFG" */
62 typedef struct FWCfgEntry
{
66 void *callback_opaque
;
67 FWCfgReadCallback read_callback
;
72 SysBusDevice parent_obj
;
76 FWCfgEntry
*entries
[2];
81 Notifier machine_ready
;
83 int fw_cfg_order_override
;
88 MemoryRegion dma_iomem
;
93 FWCfgState parent_obj
;
96 MemoryRegion comb_iomem
;
97 uint32_t iobase
, dma_iobase
;
100 struct FWCfgMemState
{
102 FWCfgState parent_obj
;
105 MemoryRegion ctl_iomem
, data_iomem
;
107 MemoryRegionOps wide_data_ops
;
113 static char *read_splashfile(char *filename
, gsize
*file_sizep
,
120 unsigned int filehead
;
123 res
= g_file_get_contents(filename
, &content
, file_sizep
, &err
);
125 error_report("failed to read splash file '%s'", filename
);
130 /* check file size */
131 if (*file_sizep
< 30) {
136 filehead
= ((content
[0] & 0xff) + (content
[1] << 8)) & 0xffff;
137 if (filehead
== 0xd8ff) {
138 file_type
= JPG_FILE
;
139 } else if (filehead
== 0x4d42) {
140 file_type
= BMP_FILE
;
146 if (file_type
== BMP_FILE
) {
147 bmp_bpp
= (content
[28] + (content
[29] << 8)) & 0xffff;
154 *file_typep
= file_type
;
159 error_report("splash file '%s' format not recognized; must be JPEG "
160 "or 24 bit BMP", filename
);
165 static void fw_cfg_bootsplash(FWCfgState
*s
)
167 int boot_splash_time
= -1;
168 const char *boot_splash_filename
= NULL
;
170 char *filename
, *file_data
;
175 /* get user configuration */
176 QemuOptsList
*plist
= qemu_find_opts("boot-opts");
177 QemuOpts
*opts
= QTAILQ_FIRST(&plist
->head
);
179 temp
= qemu_opt_get(opts
, "splash");
181 boot_splash_filename
= temp
;
183 temp
= qemu_opt_get(opts
, "splash-time");
186 boot_splash_time
= strtol(p
, &p
, 10);
190 /* insert splash time if user configurated */
191 if (boot_splash_time
>= 0) {
192 /* validate the input */
193 if (boot_splash_time
> 0xffff) {
194 error_report("splash time is big than 65535, force it to 65535.");
195 boot_splash_time
= 0xffff;
197 /* use little endian format */
198 qemu_extra_params_fw
[0] = (uint8_t)(boot_splash_time
& 0xff);
199 qemu_extra_params_fw
[1] = (uint8_t)((boot_splash_time
>> 8) & 0xff);
200 fw_cfg_add_file(s
, "etc/boot-menu-wait", qemu_extra_params_fw
, 2);
203 /* insert splash file if user configurated */
204 if (boot_splash_filename
!= NULL
) {
205 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, boot_splash_filename
);
206 if (filename
== NULL
) {
207 error_report("failed to find file '%s'.", boot_splash_filename
);
211 /* loading file data */
212 file_data
= read_splashfile(filename
, &file_size
, &file_type
);
213 if (file_data
== NULL
) {
217 g_free(boot_splash_filedata
);
218 boot_splash_filedata
= (uint8_t *)file_data
;
219 boot_splash_filedata_size
= file_size
;
222 if (file_type
== JPG_FILE
) {
223 fw_cfg_add_file(s
, "bootsplash.jpg",
224 boot_splash_filedata
, boot_splash_filedata_size
);
226 fw_cfg_add_file(s
, "bootsplash.bmp",
227 boot_splash_filedata
, boot_splash_filedata_size
);
233 static void fw_cfg_reboot(FWCfgState
*s
)
235 int reboot_timeout
= -1;
239 /* get user configuration */
240 QemuOptsList
*plist
= qemu_find_opts("boot-opts");
241 QemuOpts
*opts
= QTAILQ_FIRST(&plist
->head
);
243 temp
= qemu_opt_get(opts
, "reboot-timeout");
246 reboot_timeout
= strtol(p
, &p
, 10);
249 /* validate the input */
250 if (reboot_timeout
> 0xffff) {
251 error_report("reboot timeout is larger than 65535, force it to 65535.");
252 reboot_timeout
= 0xffff;
254 fw_cfg_add_file(s
, "etc/boot-fail-wait", g_memdup(&reboot_timeout
, 4), 4);
257 static void fw_cfg_write(FWCfgState
*s
, uint8_t value
)
259 /* nothing, write support removed in QEMU v2.4+ */
262 static inline uint16_t fw_cfg_file_slots(const FWCfgState
*s
)
264 return s
->file_slots
;
267 /* Note: this function returns an exclusive limit. */
268 static inline uint32_t fw_cfg_max_entry(const FWCfgState
*s
)
270 return FW_CFG_FILE_FIRST
+ fw_cfg_file_slots(s
);
273 static int fw_cfg_select(FWCfgState
*s
, uint16_t key
)
279 if ((key
& FW_CFG_ENTRY_MASK
) >= fw_cfg_max_entry(s
)) {
280 s
->cur_entry
= FW_CFG_INVALID
;
285 /* entry successfully selected, now run callback if present */
286 arch
= !!(key
& FW_CFG_ARCH_LOCAL
);
287 e
= &s
->entries
[arch
][key
& FW_CFG_ENTRY_MASK
];
288 if (e
->read_callback
) {
289 e
->read_callback(e
->callback_opaque
);
293 trace_fw_cfg_select(s
, key
, ret
);
297 static uint64_t fw_cfg_data_read(void *opaque
, hwaddr addr
, unsigned size
)
299 FWCfgState
*s
= opaque
;
300 int arch
= !!(s
->cur_entry
& FW_CFG_ARCH_LOCAL
);
301 FWCfgEntry
*e
= (s
->cur_entry
== FW_CFG_INVALID
) ? NULL
:
302 &s
->entries
[arch
][s
->cur_entry
& FW_CFG_ENTRY_MASK
];
305 assert(size
> 0 && size
<= sizeof(value
));
306 if (s
->cur_entry
!= FW_CFG_INVALID
&& e
->data
&& s
->cur_offset
< e
->len
) {
307 /* The least significant 'size' bytes of the return value are
308 * expected to contain a string preserving portion of the item
309 * data, padded with zeros on the right in case we run out early.
310 * In technical terms, we're composing the host-endian representation
311 * of the big endian interpretation of the fw_cfg string.
314 value
= (value
<< 8) | e
->data
[s
->cur_offset
++];
315 } while (--size
&& s
->cur_offset
< e
->len
);
316 /* If size is still not zero, we *did* run out early, so continue
317 * left-shifting, to add the appropriate number of padding zeros
323 trace_fw_cfg_read(s
, value
);
327 static void fw_cfg_data_mem_write(void *opaque
, hwaddr addr
,
328 uint64_t value
, unsigned size
)
330 FWCfgState
*s
= opaque
;
334 fw_cfg_write(s
, value
>> (8 * --i
));
338 static void fw_cfg_dma_transfer(FWCfgState
*s
)
344 int read
= 0, write
= 0;
347 /* Reset the address before the next access */
348 dma_addr
= s
->dma_addr
;
351 if (dma_memory_read(s
->dma_as
, dma_addr
, &dma
, sizeof(dma
))) {
352 stl_be_dma(s
->dma_as
, dma_addr
+ offsetof(FWCfgDmaAccess
, control
),
353 FW_CFG_DMA_CTL_ERROR
);
357 dma
.address
= be64_to_cpu(dma
.address
);
358 dma
.length
= be32_to_cpu(dma
.length
);
359 dma
.control
= be32_to_cpu(dma
.control
);
361 if (dma
.control
& FW_CFG_DMA_CTL_SELECT
) {
362 fw_cfg_select(s
, dma
.control
>> 16);
365 arch
= !!(s
->cur_entry
& FW_CFG_ARCH_LOCAL
);
366 e
= (s
->cur_entry
== FW_CFG_INVALID
) ? NULL
:
367 &s
->entries
[arch
][s
->cur_entry
& FW_CFG_ENTRY_MASK
];
369 if (dma
.control
& FW_CFG_DMA_CTL_READ
) {
372 } else if (dma
.control
& FW_CFG_DMA_CTL_WRITE
) {
375 } else if (dma
.control
& FW_CFG_DMA_CTL_SKIP
) {
384 while (dma
.length
> 0 && !(dma
.control
& FW_CFG_DMA_CTL_ERROR
)) {
385 if (s
->cur_entry
== FW_CFG_INVALID
|| !e
->data
||
386 s
->cur_offset
>= e
->len
) {
389 /* If the access is not a read access, it will be a skip access,
393 if (dma_memory_set(s
->dma_as
, dma
.address
, 0, len
)) {
394 dma
.control
|= FW_CFG_DMA_CTL_ERROR
;
398 dma
.control
|= FW_CFG_DMA_CTL_ERROR
;
401 if (dma
.length
<= (e
->len
- s
->cur_offset
)) {
404 len
= (e
->len
- s
->cur_offset
);
407 /* If the access is not a read access, it will be a skip access,
411 if (dma_memory_write(s
->dma_as
, dma
.address
,
412 &e
->data
[s
->cur_offset
], len
)) {
413 dma
.control
|= FW_CFG_DMA_CTL_ERROR
;
417 if (!e
->allow_write
||
419 dma_memory_read(s
->dma_as
, dma
.address
,
420 &e
->data
[s
->cur_offset
], len
)) {
421 dma
.control
|= FW_CFG_DMA_CTL_ERROR
;
425 s
->cur_offset
+= len
;
433 stl_be_dma(s
->dma_as
, dma_addr
+ offsetof(FWCfgDmaAccess
, control
),
436 trace_fw_cfg_read(s
, 0);
439 static uint64_t fw_cfg_dma_mem_read(void *opaque
, hwaddr addr
,
442 /* Return a signature value (and handle various read sizes) */
443 return extract64(FW_CFG_DMA_SIGNATURE
, (8 - addr
- size
) * 8, size
* 8);
446 static void fw_cfg_dma_mem_write(void *opaque
, hwaddr addr
,
447 uint64_t value
, unsigned size
)
449 FWCfgState
*s
= opaque
;
453 /* FWCfgDmaAccess high address */
454 s
->dma_addr
= value
<< 32;
455 } else if (addr
== 4) {
456 /* FWCfgDmaAccess low address */
457 s
->dma_addr
|= value
;
458 fw_cfg_dma_transfer(s
);
460 } else if (size
== 8 && addr
== 0) {
462 fw_cfg_dma_transfer(s
);
466 static bool fw_cfg_dma_mem_valid(void *opaque
, hwaddr addr
,
467 unsigned size
, bool is_write
)
469 return !is_write
|| ((size
== 4 && (addr
== 0 || addr
== 4)) ||
470 (size
== 8 && addr
== 0));
473 static bool fw_cfg_data_mem_valid(void *opaque
, hwaddr addr
,
474 unsigned size
, bool is_write
)
479 static void fw_cfg_ctl_mem_write(void *opaque
, hwaddr addr
,
480 uint64_t value
, unsigned size
)
482 fw_cfg_select(opaque
, (uint16_t)value
);
485 static bool fw_cfg_ctl_mem_valid(void *opaque
, hwaddr addr
,
486 unsigned size
, bool is_write
)
488 return is_write
&& size
== 2;
491 static void fw_cfg_comb_write(void *opaque
, hwaddr addr
,
492 uint64_t value
, unsigned size
)
496 fw_cfg_write(opaque
, (uint8_t)value
);
499 fw_cfg_select(opaque
, (uint16_t)value
);
504 static bool fw_cfg_comb_valid(void *opaque
, hwaddr addr
,
505 unsigned size
, bool is_write
)
507 return (size
== 1) || (is_write
&& size
== 2);
510 static const MemoryRegionOps fw_cfg_ctl_mem_ops
= {
511 .write
= fw_cfg_ctl_mem_write
,
512 .endianness
= DEVICE_BIG_ENDIAN
,
513 .valid
.accepts
= fw_cfg_ctl_mem_valid
,
516 static const MemoryRegionOps fw_cfg_data_mem_ops
= {
517 .read
= fw_cfg_data_read
,
518 .write
= fw_cfg_data_mem_write
,
519 .endianness
= DEVICE_BIG_ENDIAN
,
521 .min_access_size
= 1,
522 .max_access_size
= 1,
523 .accepts
= fw_cfg_data_mem_valid
,
527 static const MemoryRegionOps fw_cfg_comb_mem_ops
= {
528 .read
= fw_cfg_data_read
,
529 .write
= fw_cfg_comb_write
,
530 .endianness
= DEVICE_LITTLE_ENDIAN
,
531 .valid
.accepts
= fw_cfg_comb_valid
,
534 static const MemoryRegionOps fw_cfg_dma_mem_ops
= {
535 .read
= fw_cfg_dma_mem_read
,
536 .write
= fw_cfg_dma_mem_write
,
537 .endianness
= DEVICE_BIG_ENDIAN
,
538 .valid
.accepts
= fw_cfg_dma_mem_valid
,
539 .valid
.max_access_size
= 8,
540 .impl
.max_access_size
= 8,
543 static void fw_cfg_reset(DeviceState
*d
)
545 FWCfgState
*s
= FW_CFG(d
);
547 /* we never register a read callback for FW_CFG_SIGNATURE */
548 fw_cfg_select(s
, FW_CFG_SIGNATURE
);
551 /* Save restore 32 bit int as uint16_t
552 This is a Big hack, but it is how the old state did it.
553 Or we broke compatibility in the state, or we can't use struct tm
556 static int get_uint32_as_uint16(QEMUFile
*f
, void *pv
, size_t size
)
559 *v
= qemu_get_be16(f
);
563 static void put_unused(QEMUFile
*f
, void *pv
, size_t size
)
565 fprintf(stderr
, "uint32_as_uint16 is only used for backward compatibility.\n");
566 fprintf(stderr
, "This functions shouldn't be called.\n");
569 static const VMStateInfo vmstate_hack_uint32_as_uint16
= {
570 .name
= "int32_as_uint16",
571 .get
= get_uint32_as_uint16
,
575 #define VMSTATE_UINT16_HACK(_f, _s, _t) \
576 VMSTATE_SINGLE_TEST(_f, _s, _t, 0, vmstate_hack_uint32_as_uint16, uint32_t)
579 static bool is_version_1(void *opaque
, int version_id
)
581 return version_id
== 1;
584 bool fw_cfg_dma_enabled(void *opaque
)
586 FWCfgState
*s
= opaque
;
588 return s
->dma_enabled
;
591 static const VMStateDescription vmstate_fw_cfg_dma
= {
592 .name
= "fw_cfg/dma",
593 .needed
= fw_cfg_dma_enabled
,
594 .fields
= (VMStateField
[]) {
595 VMSTATE_UINT64(dma_addr
, FWCfgState
),
596 VMSTATE_END_OF_LIST()
600 static const VMStateDescription vmstate_fw_cfg
= {
603 .minimum_version_id
= 1,
604 .fields
= (VMStateField
[]) {
605 VMSTATE_UINT16(cur_entry
, FWCfgState
),
606 VMSTATE_UINT16_HACK(cur_offset
, FWCfgState
, is_version_1
),
607 VMSTATE_UINT32_V(cur_offset
, FWCfgState
, 2),
608 VMSTATE_END_OF_LIST()
610 .subsections
= (const VMStateDescription
*[]) {
616 static void fw_cfg_add_bytes_read_callback(FWCfgState
*s
, uint16_t key
,
617 FWCfgReadCallback callback
,
618 void *callback_opaque
,
619 void *data
, size_t len
,
622 int arch
= !!(key
& FW_CFG_ARCH_LOCAL
);
624 key
&= FW_CFG_ENTRY_MASK
;
626 assert(key
< fw_cfg_max_entry(s
) && len
< UINT32_MAX
);
627 assert(s
->entries
[arch
][key
].data
== NULL
); /* avoid key conflict */
629 s
->entries
[arch
][key
].data
= data
;
630 s
->entries
[arch
][key
].len
= (uint32_t)len
;
631 s
->entries
[arch
][key
].read_callback
= callback
;
632 s
->entries
[arch
][key
].callback_opaque
= callback_opaque
;
633 s
->entries
[arch
][key
].allow_write
= !read_only
;
636 static void *fw_cfg_modify_bytes_read(FWCfgState
*s
, uint16_t key
,
637 void *data
, size_t len
)
640 int arch
= !!(key
& FW_CFG_ARCH_LOCAL
);
642 key
&= FW_CFG_ENTRY_MASK
;
644 assert(key
< fw_cfg_max_entry(s
) && len
< UINT32_MAX
);
646 /* return the old data to the function caller, avoid memory leak */
647 ptr
= s
->entries
[arch
][key
].data
;
648 s
->entries
[arch
][key
].data
= data
;
649 s
->entries
[arch
][key
].len
= len
;
650 s
->entries
[arch
][key
].callback_opaque
= NULL
;
651 s
->entries
[arch
][key
].allow_write
= false;
656 void fw_cfg_add_bytes(FWCfgState
*s
, uint16_t key
, void *data
, size_t len
)
658 fw_cfg_add_bytes_read_callback(s
, key
, NULL
, NULL
, data
, len
, true);
661 void fw_cfg_add_string(FWCfgState
*s
, uint16_t key
, const char *value
)
663 size_t sz
= strlen(value
) + 1;
665 fw_cfg_add_bytes(s
, key
, g_memdup(value
, sz
), sz
);
668 void fw_cfg_add_i16(FWCfgState
*s
, uint16_t key
, uint16_t value
)
672 copy
= g_malloc(sizeof(value
));
673 *copy
= cpu_to_le16(value
);
674 fw_cfg_add_bytes(s
, key
, copy
, sizeof(value
));
677 void fw_cfg_modify_i16(FWCfgState
*s
, uint16_t key
, uint16_t value
)
679 uint16_t *copy
, *old
;
681 copy
= g_malloc(sizeof(value
));
682 *copy
= cpu_to_le16(value
);
683 old
= fw_cfg_modify_bytes_read(s
, key
, copy
, sizeof(value
));
687 void fw_cfg_add_i32(FWCfgState
*s
, uint16_t key
, uint32_t value
)
691 copy
= g_malloc(sizeof(value
));
692 *copy
= cpu_to_le32(value
);
693 fw_cfg_add_bytes(s
, key
, copy
, sizeof(value
));
696 void fw_cfg_add_i64(FWCfgState
*s
, uint16_t key
, uint64_t value
)
700 copy
= g_malloc(sizeof(value
));
701 *copy
= cpu_to_le64(value
);
702 fw_cfg_add_bytes(s
, key
, copy
, sizeof(value
));
705 void fw_cfg_set_order_override(FWCfgState
*s
, int order
)
707 assert(s
->fw_cfg_order_override
== 0);
708 s
->fw_cfg_order_override
= order
;
711 void fw_cfg_reset_order_override(FWCfgState
*s
)
713 assert(s
->fw_cfg_order_override
!= 0);
714 s
->fw_cfg_order_override
= 0;
718 * This is the legacy order list. For legacy systems, files are in
719 * the fw_cfg in the order defined below, by the "order" value. Note
720 * that some entries (VGA ROMs, NIC option ROMS, etc.) go into a
721 * specific area, but there may be more than one and they occur in the
722 * order that the user specifies them on the command line. Those are
723 * handled in a special manner, using the order override above.
725 * For non-legacy, the files are sorted by filename to avoid this kind
726 * of complexity in the future.
728 * This is only for x86, other arches don't implement versioning so
729 * they won't set legacy mode.
735 { "etc/boot-menu-wait", 10 },
736 { "bootsplash.jpg", 11 },
737 { "bootsplash.bmp", 12 },
738 { "etc/boot-fail-wait", 15 },
739 { "etc/smbios/smbios-tables", 20 },
740 { "etc/smbios/smbios-anchor", 30 },
742 { "etc/reserved-memory-end", 50 },
743 { "genroms/kvmvapic.bin", 55 },
744 { "genroms/linuxboot.bin", 60 },
745 { }, /* VGA ROMs from pc_vga_init come here, 70. */
746 { }, /* NIC option ROMs from pc_nic_init come here, 80. */
747 { "etc/system-states", 90 },
748 { }, /* User ROMs come here, 100. */
749 { }, /* Device FW comes here, 110. */
750 { "etc/extra-pci-roots", 120 },
751 { "etc/acpi/tables", 130 },
752 { "etc/table-loader", 140 },
753 { "etc/tpm/log", 150 },
754 { "etc/acpi/rsdp", 160 },
755 { "bootorder", 170 },
757 #define FW_CFG_ORDER_OVERRIDE_LAST 200
760 static int get_fw_cfg_order(FWCfgState
*s
, const char *name
)
764 if (s
->fw_cfg_order_override
> 0) {
765 return s
->fw_cfg_order_override
;
768 for (i
= 0; i
< ARRAY_SIZE(fw_cfg_order
); i
++) {
769 if (fw_cfg_order
[i
].name
== NULL
) {
773 if (strcmp(name
, fw_cfg_order
[i
].name
) == 0) {
774 return fw_cfg_order
[i
].order
;
778 /* Stick unknown stuff at the end. */
779 error_report("warning: Unknown firmware file in legacy mode: %s", name
);
780 return FW_CFG_ORDER_OVERRIDE_LAST
;
783 void fw_cfg_add_file_callback(FWCfgState
*s
, const char *filename
,
784 FWCfgReadCallback callback
, void *callback_opaque
,
785 void *data
, size_t len
, bool read_only
)
789 MachineClass
*mc
= MACHINE_GET_CLASS(qdev_get_machine());
793 dsize
= sizeof(uint32_t) + sizeof(FWCfgFile
) * fw_cfg_file_slots(s
);
794 s
->files
= g_malloc0(dsize
);
795 fw_cfg_add_bytes(s
, FW_CFG_FILE_DIR
, s
->files
, dsize
);
798 count
= be32_to_cpu(s
->files
->count
);
799 assert(count
< fw_cfg_file_slots(s
));
801 /* Find the insertion point. */
802 if (mc
->legacy_fw_cfg_order
) {
804 * Sort by order. For files with the same order, we keep them
805 * in the sequence in which they were added.
807 order
= get_fw_cfg_order(s
, filename
);
809 index
> 0 && order
< s
->entry_order
[index
- 1];
812 /* Sort by file name. */
814 index
> 0 && strcmp(filename
, s
->files
->f
[index
- 1].name
) < 0;
819 * Move all the entries from the index point and after down one
820 * to create a slot for the new entry. Because calculations are
821 * being done with the index, make it so that "i" is the current
822 * index and "i - 1" is the one being copied from, thus the
823 * unusual start and end in the for statement.
825 for (i
= count
+ 1; i
> index
; i
--) {
826 s
->files
->f
[i
] = s
->files
->f
[i
- 1];
827 s
->files
->f
[i
].select
= cpu_to_be16(FW_CFG_FILE_FIRST
+ i
);
828 s
->entries
[0][FW_CFG_FILE_FIRST
+ i
] =
829 s
->entries
[0][FW_CFG_FILE_FIRST
+ i
- 1];
830 s
->entry_order
[i
] = s
->entry_order
[i
- 1];
833 memset(&s
->files
->f
[index
], 0, sizeof(FWCfgFile
));
834 memset(&s
->entries
[0][FW_CFG_FILE_FIRST
+ index
], 0, sizeof(FWCfgEntry
));
836 pstrcpy(s
->files
->f
[index
].name
, sizeof(s
->files
->f
[index
].name
), filename
);
837 for (i
= 0; i
<= count
; i
++) {
839 strcmp(s
->files
->f
[index
].name
, s
->files
->f
[i
].name
) == 0) {
840 error_report("duplicate fw_cfg file name: %s",
841 s
->files
->f
[index
].name
);
846 fw_cfg_add_bytes_read_callback(s
, FW_CFG_FILE_FIRST
+ index
,
847 callback
, callback_opaque
, data
, len
,
850 s
->files
->f
[index
].size
= cpu_to_be32(len
);
851 s
->files
->f
[index
].select
= cpu_to_be16(FW_CFG_FILE_FIRST
+ index
);
852 s
->entry_order
[index
] = order
;
853 trace_fw_cfg_add_file(s
, index
, s
->files
->f
[index
].name
, len
);
855 s
->files
->count
= cpu_to_be32(count
+1);
858 void fw_cfg_add_file(FWCfgState
*s
, const char *filename
,
859 void *data
, size_t len
)
861 fw_cfg_add_file_callback(s
, filename
, NULL
, NULL
, data
, len
, true);
864 void *fw_cfg_modify_file(FWCfgState
*s
, const char *filename
,
865 void *data
, size_t len
)
872 index
= be32_to_cpu(s
->files
->count
);
873 assert(index
< fw_cfg_file_slots(s
));
875 for (i
= 0; i
< index
; i
++) {
876 if (strcmp(filename
, s
->files
->f
[i
].name
) == 0) {
877 ptr
= fw_cfg_modify_bytes_read(s
, FW_CFG_FILE_FIRST
+ i
,
879 s
->files
->f
[i
].size
= cpu_to_be32(len
);
884 fw_cfg_add_file_callback(s
, filename
, NULL
, NULL
, data
, len
, true);
888 static void fw_cfg_machine_reset(void *opaque
)
892 FWCfgState
*s
= opaque
;
893 char *bootindex
= get_boot_devices_list(&len
, false);
895 ptr
= fw_cfg_modify_file(s
, "bootorder", (uint8_t *)bootindex
, len
);
899 static void fw_cfg_machine_ready(struct Notifier
*n
, void *data
)
901 FWCfgState
*s
= container_of(n
, FWCfgState
, machine_ready
);
902 qemu_register_reset(fw_cfg_machine_reset
, s
);
907 static void fw_cfg_init1(DeviceState
*dev
)
909 FWCfgState
*s
= FW_CFG(dev
);
910 MachineState
*machine
= MACHINE(qdev_get_machine());
912 assert(!object_resolve_path(FW_CFG_PATH
, NULL
));
914 object_property_add_child(OBJECT(machine
), FW_CFG_NAME
, OBJECT(s
), NULL
);
916 qdev_init_nofail(dev
);
918 fw_cfg_add_bytes(s
, FW_CFG_SIGNATURE
, (char *)"QEMU", 4);
919 fw_cfg_add_bytes(s
, FW_CFG_UUID
, &qemu_uuid
, 16);
920 fw_cfg_add_i16(s
, FW_CFG_NOGRAPHIC
, (uint16_t)!machine
->enable_graphics
);
921 fw_cfg_add_i16(s
, FW_CFG_BOOT_MENU
, (uint16_t)boot_menu
);
922 fw_cfg_bootsplash(s
);
925 s
->machine_ready
.notify
= fw_cfg_machine_ready
;
926 qemu_add_machine_init_done_notifier(&s
->machine_ready
);
929 FWCfgState
*fw_cfg_init_io_dma(uint32_t iobase
, uint32_t dma_iobase
,
930 AddressSpace
*dma_as
)
934 uint32_t version
= FW_CFG_VERSION
;
935 bool dma_requested
= dma_iobase
&& dma_as
;
937 dev
= qdev_create(NULL
, TYPE_FW_CFG_IO
);
938 qdev_prop_set_uint32(dev
, "iobase", iobase
);
939 qdev_prop_set_uint32(dev
, "dma_iobase", dma_iobase
);
940 if (!dma_requested
) {
941 qdev_prop_set_bit(dev
, "dma_enabled", false);
947 if (s
->dma_enabled
) {
948 /* 64 bits for the address field */
952 version
|= FW_CFG_VERSION_DMA
;
955 fw_cfg_add_i32(s
, FW_CFG_ID
, version
);
960 FWCfgState
*fw_cfg_init_io(uint32_t iobase
)
962 return fw_cfg_init_io_dma(iobase
, 0, NULL
);
965 FWCfgState
*fw_cfg_init_mem_wide(hwaddr ctl_addr
,
966 hwaddr data_addr
, uint32_t data_width
,
967 hwaddr dma_addr
, AddressSpace
*dma_as
)
972 uint32_t version
= FW_CFG_VERSION
;
973 bool dma_requested
= dma_addr
&& dma_as
;
975 dev
= qdev_create(NULL
, TYPE_FW_CFG_MEM
);
976 qdev_prop_set_uint32(dev
, "data_width", data_width
);
977 if (!dma_requested
) {
978 qdev_prop_set_bit(dev
, "dma_enabled", false);
983 sbd
= SYS_BUS_DEVICE(dev
);
984 sysbus_mmio_map(sbd
, 0, ctl_addr
);
985 sysbus_mmio_map(sbd
, 1, data_addr
);
989 if (s
->dma_enabled
) {
992 sysbus_mmio_map(sbd
, 2, dma_addr
);
993 version
|= FW_CFG_VERSION_DMA
;
996 fw_cfg_add_i32(s
, FW_CFG_ID
, version
);
1001 FWCfgState
*fw_cfg_init_mem(hwaddr ctl_addr
, hwaddr data_addr
)
1003 return fw_cfg_init_mem_wide(ctl_addr
, data_addr
,
1004 fw_cfg_data_mem_ops
.valid
.max_access_size
,
1009 FWCfgState
*fw_cfg_find(void)
1011 return FW_CFG(object_resolve_path(FW_CFG_PATH
, NULL
));
1014 static void fw_cfg_class_init(ObjectClass
*klass
, void *data
)
1016 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1018 dc
->reset
= fw_cfg_reset
;
1019 dc
->vmsd
= &vmstate_fw_cfg
;
1022 static const TypeInfo fw_cfg_info
= {
1023 .name
= TYPE_FW_CFG
,
1024 .parent
= TYPE_SYS_BUS_DEVICE
,
1026 .instance_size
= sizeof(FWCfgState
),
1027 .class_init
= fw_cfg_class_init
,
1030 static void fw_cfg_file_slots_allocate(FWCfgState
*s
, Error
**errp
)
1032 uint16_t file_slots_max
;
1034 if (fw_cfg_file_slots(s
) < FW_CFG_FILE_SLOTS_MIN
) {
1035 error_setg(errp
, "\"file_slots\" must be at least 0x%x",
1036 FW_CFG_FILE_SLOTS_MIN
);
1040 /* (UINT16_MAX & FW_CFG_ENTRY_MASK) is the highest inclusive selector value
1041 * that we permit. The actual (exclusive) value coming from the
1042 * configuration is (FW_CFG_FILE_FIRST + fw_cfg_file_slots(s)). */
1043 file_slots_max
= (UINT16_MAX
& FW_CFG_ENTRY_MASK
) - FW_CFG_FILE_FIRST
+ 1;
1044 if (fw_cfg_file_slots(s
) > file_slots_max
) {
1045 error_setg(errp
, "\"file_slots\" must not exceed 0x%" PRIx16
,
1050 s
->entries
[0] = g_new0(FWCfgEntry
, fw_cfg_max_entry(s
));
1051 s
->entries
[1] = g_new0(FWCfgEntry
, fw_cfg_max_entry(s
));
1052 s
->entry_order
= g_new0(int, fw_cfg_max_entry(s
));
1055 static Property fw_cfg_io_properties
[] = {
1056 DEFINE_PROP_UINT32("iobase", FWCfgIoState
, iobase
, -1),
1057 DEFINE_PROP_UINT32("dma_iobase", FWCfgIoState
, dma_iobase
, -1),
1058 DEFINE_PROP_BOOL("dma_enabled", FWCfgIoState
, parent_obj
.dma_enabled
,
1060 DEFINE_PROP_UINT16("x-file-slots", FWCfgIoState
, parent_obj
.file_slots
,
1061 FW_CFG_FILE_SLOTS_MIN
),
1062 DEFINE_PROP_END_OF_LIST(),
1065 static void fw_cfg_io_realize(DeviceState
*dev
, Error
**errp
)
1067 FWCfgIoState
*s
= FW_CFG_IO(dev
);
1068 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
1069 Error
*local_err
= NULL
;
1071 fw_cfg_file_slots_allocate(FW_CFG(s
), &local_err
);
1073 error_propagate(errp
, local_err
);
1077 /* when using port i/o, the 8-bit data register ALWAYS overlaps
1078 * with half of the 16-bit control register. Hence, the total size
1079 * of the i/o region used is FW_CFG_CTL_SIZE */
1080 memory_region_init_io(&s
->comb_iomem
, OBJECT(s
), &fw_cfg_comb_mem_ops
,
1081 FW_CFG(s
), "fwcfg", FW_CFG_CTL_SIZE
);
1082 sysbus_add_io(sbd
, s
->iobase
, &s
->comb_iomem
);
1084 if (FW_CFG(s
)->dma_enabled
) {
1085 memory_region_init_io(&FW_CFG(s
)->dma_iomem
, OBJECT(s
),
1086 &fw_cfg_dma_mem_ops
, FW_CFG(s
), "fwcfg.dma",
1087 sizeof(dma_addr_t
));
1088 sysbus_add_io(sbd
, s
->dma_iobase
, &FW_CFG(s
)->dma_iomem
);
1092 static void fw_cfg_io_class_init(ObjectClass
*klass
, void *data
)
1094 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1096 dc
->realize
= fw_cfg_io_realize
;
1097 dc
->props
= fw_cfg_io_properties
;
1100 static const TypeInfo fw_cfg_io_info
= {
1101 .name
= TYPE_FW_CFG_IO
,
1102 .parent
= TYPE_FW_CFG
,
1103 .instance_size
= sizeof(FWCfgIoState
),
1104 .class_init
= fw_cfg_io_class_init
,
1108 static Property fw_cfg_mem_properties
[] = {
1109 DEFINE_PROP_UINT32("data_width", FWCfgMemState
, data_width
, -1),
1110 DEFINE_PROP_BOOL("dma_enabled", FWCfgMemState
, parent_obj
.dma_enabled
,
1112 DEFINE_PROP_UINT16("x-file-slots", FWCfgMemState
, parent_obj
.file_slots
,
1113 FW_CFG_FILE_SLOTS_MIN
),
1114 DEFINE_PROP_END_OF_LIST(),
1117 static void fw_cfg_mem_realize(DeviceState
*dev
, Error
**errp
)
1119 FWCfgMemState
*s
= FW_CFG_MEM(dev
);
1120 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
1121 const MemoryRegionOps
*data_ops
= &fw_cfg_data_mem_ops
;
1122 Error
*local_err
= NULL
;
1124 fw_cfg_file_slots_allocate(FW_CFG(s
), &local_err
);
1126 error_propagate(errp
, local_err
);
1130 memory_region_init_io(&s
->ctl_iomem
, OBJECT(s
), &fw_cfg_ctl_mem_ops
,
1131 FW_CFG(s
), "fwcfg.ctl", FW_CFG_CTL_SIZE
);
1132 sysbus_init_mmio(sbd
, &s
->ctl_iomem
);
1134 if (s
->data_width
> data_ops
->valid
.max_access_size
) {
1135 /* memberwise copy because the "old_mmio" member is const */
1136 s
->wide_data_ops
.read
= data_ops
->read
;
1137 s
->wide_data_ops
.write
= data_ops
->write
;
1138 s
->wide_data_ops
.endianness
= data_ops
->endianness
;
1139 s
->wide_data_ops
.valid
= data_ops
->valid
;
1140 s
->wide_data_ops
.impl
= data_ops
->impl
;
1142 s
->wide_data_ops
.valid
.max_access_size
= s
->data_width
;
1143 s
->wide_data_ops
.impl
.max_access_size
= s
->data_width
;
1144 data_ops
= &s
->wide_data_ops
;
1146 memory_region_init_io(&s
->data_iomem
, OBJECT(s
), data_ops
, FW_CFG(s
),
1147 "fwcfg.data", data_ops
->valid
.max_access_size
);
1148 sysbus_init_mmio(sbd
, &s
->data_iomem
);
1150 if (FW_CFG(s
)->dma_enabled
) {
1151 memory_region_init_io(&FW_CFG(s
)->dma_iomem
, OBJECT(s
),
1152 &fw_cfg_dma_mem_ops
, FW_CFG(s
), "fwcfg.dma",
1153 sizeof(dma_addr_t
));
1154 sysbus_init_mmio(sbd
, &FW_CFG(s
)->dma_iomem
);
1158 static void fw_cfg_mem_class_init(ObjectClass
*klass
, void *data
)
1160 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1162 dc
->realize
= fw_cfg_mem_realize
;
1163 dc
->props
= fw_cfg_mem_properties
;
1166 static const TypeInfo fw_cfg_mem_info
= {
1167 .name
= TYPE_FW_CFG_MEM
,
1168 .parent
= TYPE_FW_CFG
,
1169 .instance_size
= sizeof(FWCfgMemState
),
1170 .class_init
= fw_cfg_mem_class_init
,
1174 static void fw_cfg_register_types(void)
1176 type_register_static(&fw_cfg_info
);
1177 type_register_static(&fw_cfg_io_info
);
1178 type_register_static(&fw_cfg_mem_info
);
1181 type_init(fw_cfg_register_types
)