2 * Nordic Semiconductor nRF51 non-volatile memory
4 * It provides an interface to erase regions in flash memory.
5 * Furthermore it provides the user and factory information registers.
7 * Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf
9 * See nRF51 reference manual and product sheet sections:
10 * + Non-Volatile Memory Controller (NVMC)
11 * + Factory Information Configuration Registers (FICR)
12 * + User Information Configuration Registers (UICR)
14 * Copyright 2018 Steffen Görtz <contrib@steffen-goertz.de>
16 * This code is licensed under the GPL version 2 or later. See
17 * the COPYING file in the top-level directory.
20 #include "qemu/osdep.h"
21 #include "qapi/error.h"
23 #include "qemu/module.h"
24 #include "exec/address-spaces.h"
25 #include "hw/arm/nrf51.h"
26 #include "hw/nvram/nrf51_nvm.h"
27 #include "migration/vmstate.h"
30 * FICR Registers Assignments
37 * SIZERAMBLOCK[0] 0x038
38 * SIZERAMBLOCK[1] 0x03C
39 * SIZERAMBLOCK[2] 0x040
40 * SIZERAMBLOCK[3] 0x044
52 * DEVICEADDRTYPE 0x0A0
67 static const uint32_t ficr_content
[64] = {
68 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000400,
69 0x00000100, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000002, 0x00002000,
70 0x00002000, 0x00002000, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
71 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
72 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000003,
73 0x12345678, 0x9ABCDEF1, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
74 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
75 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
76 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
77 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
78 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
79 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
80 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF
83 static uint64_t ficr_read(void *opaque
, hwaddr offset
, unsigned int size
)
85 assert(offset
< sizeof(ficr_content
));
86 return ficr_content
[offset
/ 4];
89 static void ficr_write(void *opaque
, hwaddr offset
, uint64_t value
,
92 /* Intentionally do nothing */
95 static const MemoryRegionOps ficr_ops
= {
98 .impl
.min_access_size
= 4,
99 .impl
.max_access_size
= 4,
100 .endianness
= DEVICE_LITTLE_ENDIAN
104 * UICR Registers Assignments
109 * BOOTLOADERADDR 0x014
171 static uint64_t uicr_read(void *opaque
, hwaddr offset
, unsigned int size
)
173 NRF51NVMState
*s
= NRF51_NVM(opaque
);
175 assert(offset
< sizeof(s
->uicr_content
));
176 return s
->uicr_content
[offset
/ 4];
179 static void uicr_write(void *opaque
, hwaddr offset
, uint64_t value
,
182 NRF51NVMState
*s
= NRF51_NVM(opaque
);
184 assert(offset
< sizeof(s
->uicr_content
));
185 s
->uicr_content
[offset
/ 4] = value
;
188 static const MemoryRegionOps uicr_ops
= {
191 .impl
.min_access_size
= 4,
192 .impl
.max_access_size
= 4,
193 .endianness
= DEVICE_LITTLE_ENDIAN
197 static uint64_t io_read(void *opaque
, hwaddr offset
, unsigned int size
)
199 NRF51NVMState
*s
= NRF51_NVM(opaque
);
203 case NRF51_NVMC_READY
:
204 r
= NRF51_NVMC_READY_READY
;
206 case NRF51_NVMC_CONFIG
:
210 qemu_log_mask(LOG_GUEST_ERROR
,
211 "%s: bad read offset 0x%" HWADDR_PRIx
"\n", __func__
, offset
);
218 static void io_write(void *opaque
, hwaddr offset
, uint64_t value
,
221 NRF51NVMState
*s
= NRF51_NVM(opaque
);
224 case NRF51_NVMC_CONFIG
:
225 s
->config
= value
& NRF51_NVMC_CONFIG_MASK
;
227 case NRF51_NVMC_ERASEPCR0
:
228 case NRF51_NVMC_ERASEPCR1
:
229 if (s
->config
& NRF51_NVMC_CONFIG_EEN
) {
230 /* Mask in-page sub address */
231 value
&= ~(NRF51_PAGE_SIZE
- 1);
232 if (value
<= (s
->flash_size
- NRF51_PAGE_SIZE
)) {
233 memset(s
->storage
+ value
, 0xFF, NRF51_PAGE_SIZE
);
234 memory_region_flush_rom_device(&s
->flash
, value
,
238 qemu_log_mask(LOG_GUEST_ERROR
,
239 "%s: Flash erase at 0x%" HWADDR_PRIx
" while flash not erasable.\n",
243 case NRF51_NVMC_ERASEALL
:
244 if (value
== NRF51_NVMC_ERASE
) {
245 if (s
->config
& NRF51_NVMC_CONFIG_EEN
) {
246 memset(s
->storage
, 0xFF, s
->flash_size
);
247 memory_region_flush_rom_device(&s
->flash
, 0, s
->flash_size
);
248 memset(s
->uicr_content
, 0xFF, sizeof(s
->uicr_content
));
250 qemu_log_mask(LOG_GUEST_ERROR
, "%s: Flash not erasable.\n",
255 case NRF51_NVMC_ERASEUICR
:
256 if (value
== NRF51_NVMC_ERASE
) {
257 memset(s
->uicr_content
, 0xFF, sizeof(s
->uicr_content
));
262 qemu_log_mask(LOG_GUEST_ERROR
,
263 "%s: bad write offset 0x%" HWADDR_PRIx
"\n", __func__
, offset
);
267 static const MemoryRegionOps io_ops
= {
270 .impl
.min_access_size
= 4,
271 .impl
.max_access_size
= 4,
272 .endianness
= DEVICE_LITTLE_ENDIAN
,
276 static void flash_write(void *opaque
, hwaddr offset
, uint64_t value
,
279 NRF51NVMState
*s
= NRF51_NVM(opaque
);
281 if (s
->config
& NRF51_NVMC_CONFIG_WEN
) {
284 assert(offset
+ size
<= s
->flash_size
);
286 /* NOR Flash only allows bits to be flipped from 1's to 0's on write */
287 oldval
= ldl_le_p(s
->storage
+ offset
);
289 stl_le_p(s
->storage
+ offset
, oldval
);
291 memory_region_flush_rom_device(&s
->flash
, offset
, size
);
293 qemu_log_mask(LOG_GUEST_ERROR
,
294 "%s: Flash write 0x%" HWADDR_PRIx
" while flash not writable.\n",
301 static const MemoryRegionOps flash_ops
= {
302 .write
= flash_write
,
303 .valid
.min_access_size
= 4,
304 .valid
.max_access_size
= 4,
305 .endianness
= DEVICE_LITTLE_ENDIAN
,
308 static void nrf51_nvm_init(Object
*obj
)
310 NRF51NVMState
*s
= NRF51_NVM(obj
);
311 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
313 memory_region_init_io(&s
->mmio
, obj
, &io_ops
, s
, "nrf51_soc.nvmc",
315 sysbus_init_mmio(sbd
, &s
->mmio
);
317 memory_region_init_io(&s
->ficr
, obj
, &ficr_ops
, s
, "nrf51_soc.ficr",
318 sizeof(ficr_content
));
319 sysbus_init_mmio(sbd
, &s
->ficr
);
321 memory_region_init_io(&s
->uicr
, obj
, &uicr_ops
, s
, "nrf51_soc.uicr",
322 sizeof(s
->uicr_content
));
323 sysbus_init_mmio(sbd
, &s
->uicr
);
326 static void nrf51_nvm_realize(DeviceState
*dev
, Error
**errp
)
328 NRF51NVMState
*s
= NRF51_NVM(dev
);
331 memory_region_init_rom_device(&s
->flash
, OBJECT(dev
), &flash_ops
, s
,
332 "nrf51_soc.flash", s
->flash_size
, &err
);
334 error_propagate(errp
, err
);
338 s
->storage
= memory_region_get_ram_ptr(&s
->flash
);
339 sysbus_init_mmio(SYS_BUS_DEVICE(dev
), &s
->flash
);
342 static void nrf51_nvm_reset(DeviceState
*dev
)
344 NRF51NVMState
*s
= NRF51_NVM(dev
);
347 memset(s
->uicr_content
, 0xFF, sizeof(s
->uicr_content
));
350 static Property nrf51_nvm_properties
[] = {
351 DEFINE_PROP_UINT32("flash-size", NRF51NVMState
, flash_size
, 0x40000),
352 DEFINE_PROP_END_OF_LIST(),
355 static const VMStateDescription vmstate_nvm
= {
356 .name
= "nrf51_soc.nvm",
358 .minimum_version_id
= 1,
359 .fields
= (VMStateField
[]) {
360 VMSTATE_UINT32_ARRAY(uicr_content
, NRF51NVMState
,
361 NRF51_UICR_FIXTURE_SIZE
),
362 VMSTATE_UINT32(config
, NRF51NVMState
),
363 VMSTATE_END_OF_LIST()
367 static void nrf51_nvm_class_init(ObjectClass
*klass
, void *data
)
369 DeviceClass
*dc
= DEVICE_CLASS(klass
);
371 dc
->props
= nrf51_nvm_properties
;
372 dc
->vmsd
= &vmstate_nvm
;
373 dc
->realize
= nrf51_nvm_realize
;
374 dc
->reset
= nrf51_nvm_reset
;
377 static const TypeInfo nrf51_nvm_info
= {
378 .name
= TYPE_NRF51_NVM
,
379 .parent
= TYPE_SYS_BUS_DEVICE
,
380 .instance_size
= sizeof(NRF51NVMState
),
381 .instance_init
= nrf51_nvm_init
,
382 .class_init
= nrf51_nvm_class_init
385 static void nrf51_nvm_register_types(void)
387 type_register_static(&nrf51_nvm_info
);
390 type_init(nrf51_nvm_register_types
)