2 * TI OMAP processors emulation.
4 * Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* Should signal the TCMI */
25 uint32_t omap_badwidth_read8(void *opaque
, target_phys_addr_t addr
)
31 void omap_badwidth_write8(void *opaque
, target_phys_addr_t addr
,
37 uint32_t omap_badwidth_read16(void *opaque
, target_phys_addr_t addr
)
43 void omap_badwidth_write16(void *opaque
, target_phys_addr_t addr
,
49 uint32_t omap_badwidth_read32(void *opaque
, target_phys_addr_t addr
)
55 void omap_badwidth_write32(void *opaque
, target_phys_addr_t addr
,
61 /* Interrupt Handlers */
62 struct omap_intr_handler_s
{
65 target_phys_addr_t base
;
80 static void omap_inth_update(struct omap_intr_handler_s
*s
)
82 uint32_t irq
= s
->irqs
& ~s
->mask
& ~s
->fiq
;
83 uint32_t fiq
= s
->irqs
& ~s
->mask
& s
->fiq
;
85 if (s
->new_irq_agr
|| !irq
) {
86 qemu_set_irq(s
->parent_pic
[ARM_PIC_CPU_IRQ
], irq
);
91 if (s
->new_fiq_agr
|| !irq
) {
92 qemu_set_irq(s
->parent_pic
[ARM_PIC_CPU_FIQ
], fiq
);
98 static void omap_inth_sir_update(struct omap_intr_handler_s
*s
)
100 int i
, intr_irq
, intr_fiq
, p_irq
, p_fiq
, p
, f
;
101 uint32_t level
= s
->irqs
& ~s
->mask
;
107 /* Find the interrupt line with the highest dynamic priority */
108 for (f
= ffs(level
), i
= f
- 1, level
>>= f
- 1; f
; i
+= f
, level
>>= f
) {
110 if (s
->fiq
& (1 << i
)) {
125 s
->sir_irq
= intr_irq
;
126 s
->sir_fiq
= intr_fiq
;
129 #define INT_FALLING_EDGE 0
130 #define INT_LOW_LEVEL 1
132 static void omap_set_intr(void *opaque
, int irq
, int req
)
134 struct omap_intr_handler_s
*ih
= (struct omap_intr_handler_s
*) opaque
;
138 rise
= ~ih
->irqs
& (1 << irq
);
140 ih
->stats
[irq
] += !!rise
;
142 rise
= ih
->sens_edge
& ih
->irqs
& (1 << irq
);
146 if (rise
& ~ih
->mask
) {
147 omap_inth_sir_update(ih
);
149 omap_inth_update(ih
);
153 static uint32_t omap_inth_read(void *opaque
, target_phys_addr_t addr
)
155 struct omap_intr_handler_s
*s
= (struct omap_intr_handler_s
*) opaque
;
156 int i
, offset
= addr
- s
->base
;
165 case 0x10: /* SIR_IRQ_CODE */
167 if (((s
->sens_edge
>> i
) & 1) == INT_FALLING_EDGE
&& i
) {
168 s
->irqs
&= ~(1 << i
);
169 omap_inth_sir_update(s
);
174 case 0x14: /* SIR_FIQ_CODE */
176 if (((s
->sens_edge
>> i
) & 1) == INT_FALLING_EDGE
&& i
) {
177 s
->irqs
&= ~(1 << i
);
178 omap_inth_sir_update(s
);
183 case 0x18: /* CONTROL_REG */
186 case 0x1c: /* ILR0 */
187 case 0x20: /* ILR1 */
188 case 0x24: /* ILR2 */
189 case 0x28: /* ILR3 */
190 case 0x2c: /* ILR4 */
191 case 0x30: /* ILR5 */
192 case 0x34: /* ILR6 */
193 case 0x38: /* ILR7 */
194 case 0x3c: /* ILR8 */
195 case 0x40: /* ILR9 */
196 case 0x44: /* ILR10 */
197 case 0x48: /* ILR11 */
198 case 0x4c: /* ILR12 */
199 case 0x50: /* ILR13 */
200 case 0x54: /* ILR14 */
201 case 0x58: /* ILR15 */
202 case 0x5c: /* ILR16 */
203 case 0x60: /* ILR17 */
204 case 0x64: /* ILR18 */
205 case 0x68: /* ILR19 */
206 case 0x6c: /* ILR20 */
207 case 0x70: /* ILR21 */
208 case 0x74: /* ILR22 */
209 case 0x78: /* ILR23 */
210 case 0x7c: /* ILR24 */
211 case 0x80: /* ILR25 */
212 case 0x84: /* ILR26 */
213 case 0x88: /* ILR27 */
214 case 0x8c: /* ILR28 */
215 case 0x90: /* ILR29 */
216 case 0x94: /* ILR30 */
217 case 0x98: /* ILR31 */
218 i
= (offset
- 0x1c) >> 2;
219 return (s
->priority
[i
] << 2) |
220 (((s
->sens_edge
>> i
) & 1) << 1) |
233 static void omap_inth_write(void *opaque
, target_phys_addr_t addr
,
236 struct omap_intr_handler_s
*s
= (struct omap_intr_handler_s
*) opaque
;
237 int i
, offset
= addr
- s
->base
;
242 omap_inth_sir_update(s
);
248 omap_inth_sir_update(s
);
252 case 0x10: /* SIR_IRQ_CODE */
253 case 0x14: /* SIR_FIQ_CODE */
257 case 0x18: /* CONTROL_REG */
265 case 0x1c: /* ILR0 */
266 case 0x20: /* ILR1 */
267 case 0x24: /* ILR2 */
268 case 0x28: /* ILR3 */
269 case 0x2c: /* ILR4 */
270 case 0x30: /* ILR5 */
271 case 0x34: /* ILR6 */
272 case 0x38: /* ILR7 */
273 case 0x3c: /* ILR8 */
274 case 0x40: /* ILR9 */
275 case 0x44: /* ILR10 */
276 case 0x48: /* ILR11 */
277 case 0x4c: /* ILR12 */
278 case 0x50: /* ILR13 */
279 case 0x54: /* ILR14 */
280 case 0x58: /* ILR15 */
281 case 0x5c: /* ILR16 */
282 case 0x60: /* ILR17 */
283 case 0x64: /* ILR18 */
284 case 0x68: /* ILR19 */
285 case 0x6c: /* ILR20 */
286 case 0x70: /* ILR21 */
287 case 0x74: /* ILR22 */
288 case 0x78: /* ILR23 */
289 case 0x7c: /* ILR24 */
290 case 0x80: /* ILR25 */
291 case 0x84: /* ILR26 */
292 case 0x88: /* ILR27 */
293 case 0x8c: /* ILR28 */
294 case 0x90: /* ILR29 */
295 case 0x94: /* ILR30 */
296 case 0x98: /* ILR31 */
297 i
= (offset
- 0x1c) >> 2;
298 s
->priority
[i
] = (value
>> 2) & 0x1f;
299 s
->sens_edge
&= ~(1 << i
);
300 s
->sens_edge
|= ((value
>> 1) & 1) << i
;
302 s
->fiq
|= (value
& 1) << i
;
306 for (i
= 0; i
< 32; i
++)
307 if (value
& (1 << i
)) {
308 omap_set_intr(s
, i
, 1);
318 static CPUReadMemoryFunc
*omap_inth_readfn
[] = {
319 omap_badwidth_read32
,
320 omap_badwidth_read32
,
324 static CPUWriteMemoryFunc
*omap_inth_writefn
[] = {
330 static void omap_inth_reset(struct omap_intr_handler_s
*s
)
332 s
->irqs
= 0x00000000;
333 s
->mask
= 0xffffffff;
334 s
->sens_edge
= 0x00000000;
336 memset(s
->priority
, 0, sizeof(s
->priority
));
345 struct omap_intr_handler_s
*omap_inth_init(target_phys_addr_t base
,
346 unsigned long size
, qemu_irq parent
[2], omap_clk clk
)
349 struct omap_intr_handler_s
*s
= (struct omap_intr_handler_s
*)
350 qemu_mallocz(sizeof(struct omap_intr_handler_s
));
352 s
->parent_pic
= parent
;
354 s
->pins
= qemu_allocate_irqs(omap_set_intr
, s
, 32);
357 iomemtype
= cpu_register_io_memory(0, omap_inth_readfn
,
358 omap_inth_writefn
, s
);
359 cpu_register_physical_memory(s
->base
, size
, iomemtype
);
364 /* OMAP1 DMA module */
370 } omap_dma_addressing_t
;
372 struct omap_dma_channel_s
{
375 enum omap_dma_port port
[2];
376 target_phys_addr_t addr
[2];
377 omap_dma_addressing_t mode
[2];
393 uint16_t frame_index
;
394 uint16_t element_index
;
397 struct omap_dma_reg_set_s
{
398 target_phys_addr_t src
, dest
;
411 struct omap_mpu_state_s
*mpu
;
412 target_phys_addr_t base
;
421 struct omap_dma_channel_s ch
[16];
422 struct omap_dma_lcd_channel_s lcd_ch
;
425 static void omap_dma_interrupts_update(struct omap_dma_s
*s
)
427 /* First three interrupts are shared between two channels each. */
428 qemu_set_irq(s
->ih
[OMAP_INT_DMA_CH0_6
],
429 (s
->ch
[0].status
| s
->ch
[6].status
) & 0x3f);
430 qemu_set_irq(s
->ih
[OMAP_INT_DMA_CH1_7
],
431 (s
->ch
[1].status
| s
->ch
[7].status
) & 0x3f);
432 qemu_set_irq(s
->ih
[OMAP_INT_DMA_CH2_8
],
433 (s
->ch
[2].status
| s
->ch
[8].status
) & 0x3f);
434 qemu_set_irq(s
->ih
[OMAP_INT_DMA_CH3
],
435 (s
->ch
[3].status
) & 0x3f);
436 qemu_set_irq(s
->ih
[OMAP_INT_DMA_CH4
],
437 (s
->ch
[4].status
) & 0x3f);
438 qemu_set_irq(s
->ih
[OMAP_INT_DMA_CH5
],
439 (s
->ch
[5].status
) & 0x3f);
442 static void omap_dma_channel_load(struct omap_dma_s
*s
, int ch
)
444 struct omap_dma_reg_set_s
*a
= &s
->ch
[ch
].active_set
;
448 * TODO: verify address ranges and alignment
449 * TODO: port endianness
452 a
->src
= s
->ch
[ch
].addr
[0];
453 a
->dest
= s
->ch
[ch
].addr
[1];
454 a
->frames
= s
->ch
[ch
].frames
;
455 a
->elements
= s
->ch
[ch
].elements
;
459 if (unlikely(!s
->ch
[ch
].elements
|| !s
->ch
[ch
].frames
)) {
460 printf("%s: bad DMA request\n", __FUNCTION__
);
464 for (i
= 0; i
< 2; i
++)
465 switch (s
->ch
[ch
].mode
[i
]) {
467 a
->elem_delta
[i
] = 0;
468 a
->frame_delta
[i
] = 0;
470 case post_incremented
:
471 a
->elem_delta
[i
] = s
->ch
[ch
].data_type
;
472 a
->frame_delta
[i
] = 0;
475 a
->elem_delta
[i
] = s
->ch
[ch
].data_type
+
476 s
->ch
[ch
].element_index
- 1;
477 if (s
->ch
[ch
].element_index
> 0x7fff)
478 a
->elem_delta
[i
] -= 0x10000;
479 a
->frame_delta
[i
] = 0;
482 a
->elem_delta
[i
] = s
->ch
[ch
].data_type
+
483 s
->ch
[ch
].element_index
- 1;
484 if (s
->ch
[ch
].element_index
> 0x7fff)
485 a
->elem_delta
[i
] -= 0x10000;
486 a
->frame_delta
[i
] = s
->ch
[ch
].frame_index
-
487 s
->ch
[ch
].element_index
;
488 if (s
->ch
[ch
].frame_index
> 0x7fff)
489 a
->frame_delta
[i
] -= 0x10000;
496 static inline void omap_dma_request_run(struct omap_dma_s
*s
,
497 int channel
, int request
)
501 for (; channel
< 9; channel
++)
502 if (s
->ch
[channel
].sync
== request
&& s
->ch
[channel
].running
)
507 if (s
->ch
[channel
].transfer
) {
509 s
->ch
[channel
++].post_sync
= request
;
512 s
->ch
[channel
].status
|= 0x02; /* Synchronisation drop */
513 omap_dma_interrupts_update(s
);
517 if (!s
->ch
[channel
].signalled
)
519 s
->ch
[channel
].signalled
= 1;
522 s
->ch
[channel
].status
|= 0x40; /* External request */
524 if (s
->delay
&& !qemu_timer_pending(s
->tm
))
525 qemu_mod_timer(s
->tm
, qemu_get_clock(vm_clock
) + s
->delay
);
533 static inline void omap_dma_request_stop(struct omap_dma_s
*s
, int channel
)
535 if (s
->ch
[channel
].signalled
)
537 s
->ch
[channel
].signalled
= 0;
540 qemu_del_timer(s
->tm
);
543 static void omap_dma_channel_run(struct omap_dma_s
*s
)
548 struct omap_dma_port_if_s
*src_p
, *dest_p
;
549 struct omap_dma_reg_set_s
*a
;
551 for (ch
= 0; ch
< 9; ch
++) {
552 a
= &s
->ch
[ch
].active_set
;
554 src_p
= &s
->mpu
->port
[s
->ch
[ch
].port
[0]];
555 dest_p
= &s
->mpu
->port
[s
->ch
[ch
].port
[1]];
556 if (s
->ch
[ch
].signalled
&& (!src_p
->addr_valid(s
->mpu
, a
->src
) ||
557 !dest_p
->addr_valid(s
->mpu
, a
->dest
))) {
560 if (s
->ch
[ch
].interrupts
& 0x01)
561 s
->ch
[ch
].status
|= 0x01;
562 omap_dma_request_stop(s
, ch
);
565 printf("%s: Bus time-out in DMA%i operation\n", __FUNCTION__
, ch
);
568 status
= s
->ch
[ch
].status
;
569 while (status
== s
->ch
[ch
].status
&& s
->ch
[ch
].signalled
) {
570 /* Transfer a single element */
571 s
->ch
[ch
].transfer
= 1;
572 cpu_physical_memory_read(a
->src
, value
, s
->ch
[ch
].data_type
);
573 cpu_physical_memory_write(a
->dest
, value
, s
->ch
[ch
].data_type
);
574 s
->ch
[ch
].transfer
= 0;
576 a
->src
+= a
->elem_delta
[0];
577 a
->dest
+= a
->elem_delta
[1];
580 /* Check interrupt conditions */
581 if (a
->element
== a
->elements
) {
583 a
->src
+= a
->frame_delta
[0];
584 a
->dest
+= a
->frame_delta
[1];
587 if (a
->frame
== a
->frames
) {
588 if (!s
->ch
[ch
].repeat
|| !s
->ch
[ch
].auto_init
)
589 s
->ch
[ch
].running
= 0;
591 if (s
->ch
[ch
].auto_init
&&
594 omap_dma_channel_load(s
, ch
);
596 if (s
->ch
[ch
].interrupts
& 0x20)
597 s
->ch
[ch
].status
|= 0x20;
600 omap_dma_request_stop(s
, ch
);
603 if (s
->ch
[ch
].interrupts
& 0x08)
604 s
->ch
[ch
].status
|= 0x08;
606 if (s
->ch
[ch
].sync
&& s
->ch
[ch
].fs
&&
607 !(s
->drq
& (1 << s
->ch
[ch
].sync
))) {
608 s
->ch
[ch
].status
&= ~0x40;
609 omap_dma_request_stop(s
, ch
);
613 if (a
->element
== 1 && a
->frame
== a
->frames
- 1)
614 if (s
->ch
[ch
].interrupts
& 0x10)
615 s
->ch
[ch
].status
|= 0x10;
617 if (a
->element
== (a
->elements
>> 1))
618 if (s
->ch
[ch
].interrupts
& 0x04)
619 s
->ch
[ch
].status
|= 0x04;
621 if (s
->ch
[ch
].sync
&& !s
->ch
[ch
].fs
&&
622 !(s
->drq
& (1 << s
->ch
[ch
].sync
))) {
623 s
->ch
[ch
].status
&= ~0x40;
624 omap_dma_request_stop(s
, ch
);
628 * Process requests made while the element was
631 if (s
->ch
[ch
].post_sync
) {
632 omap_dma_request_run(s
, 0, s
->ch
[ch
].post_sync
);
633 s
->ch
[ch
].post_sync
= 0;
641 s
->ch
[ch
].cpc
= a
->dest
& 0x0000ffff;
644 omap_dma_interrupts_update(s
);
645 if (s
->run_count
&& s
->delay
)
646 qemu_mod_timer(s
->tm
, qemu_get_clock(vm_clock
) + s
->delay
);
649 static int omap_dma_ch_reg_read(struct omap_dma_s
*s
,
650 int ch
, int reg
, uint16_t *value
) {
652 case 0x00: /* SYS_DMA_CSDP_CH0 */
653 *value
= (s
->ch
[ch
].burst
[1] << 14) |
654 (s
->ch
[ch
].pack
[1] << 13) |
655 (s
->ch
[ch
].port
[1] << 9) |
656 (s
->ch
[ch
].burst
[0] << 7) |
657 (s
->ch
[ch
].pack
[0] << 6) |
658 (s
->ch
[ch
].port
[0] << 2) |
659 (s
->ch
[ch
].data_type
>> 1);
662 case 0x02: /* SYS_DMA_CCR_CH0 */
663 *value
= (s
->ch
[ch
].mode
[1] << 14) |
664 (s
->ch
[ch
].mode
[0] << 12) |
665 (s
->ch
[ch
].end_prog
<< 11) |
666 (s
->ch
[ch
].repeat
<< 9) |
667 (s
->ch
[ch
].auto_init
<< 8) |
668 (s
->ch
[ch
].running
<< 7) |
669 (s
->ch
[ch
].priority
<< 6) |
670 (s
->ch
[ch
].fs
<< 5) | s
->ch
[ch
].sync
;
673 case 0x04: /* SYS_DMA_CICR_CH0 */
674 *value
= s
->ch
[ch
].interrupts
;
677 case 0x06: /* SYS_DMA_CSR_CH0 */
678 /* FIXME: shared CSR for channels sharing the interrupts */
679 *value
= s
->ch
[ch
].status
;
680 s
->ch
[ch
].status
&= 0x40;
681 omap_dma_interrupts_update(s
);
684 case 0x08: /* SYS_DMA_CSSA_L_CH0 */
685 *value
= s
->ch
[ch
].addr
[0] & 0x0000ffff;
688 case 0x0a: /* SYS_DMA_CSSA_U_CH0 */
689 *value
= s
->ch
[ch
].addr
[0] >> 16;
692 case 0x0c: /* SYS_DMA_CDSA_L_CH0 */
693 *value
= s
->ch
[ch
].addr
[1] & 0x0000ffff;
696 case 0x0e: /* SYS_DMA_CDSA_U_CH0 */
697 *value
= s
->ch
[ch
].addr
[1] >> 16;
700 case 0x10: /* SYS_DMA_CEN_CH0 */
701 *value
= s
->ch
[ch
].elements
;
704 case 0x12: /* SYS_DMA_CFN_CH0 */
705 *value
= s
->ch
[ch
].frames
;
708 case 0x14: /* SYS_DMA_CFI_CH0 */
709 *value
= s
->ch
[ch
].frame_index
;
712 case 0x16: /* SYS_DMA_CEI_CH0 */
713 *value
= s
->ch
[ch
].element_index
;
716 case 0x18: /* SYS_DMA_CPC_CH0 */
717 *value
= s
->ch
[ch
].cpc
;
726 static int omap_dma_ch_reg_write(struct omap_dma_s
*s
,
727 int ch
, int reg
, uint16_t value
) {
729 case 0x00: /* SYS_DMA_CSDP_CH0 */
730 s
->ch
[ch
].burst
[1] = (value
& 0xc000) >> 14;
731 s
->ch
[ch
].pack
[1] = (value
& 0x2000) >> 13;
732 s
->ch
[ch
].port
[1] = (enum omap_dma_port
) ((value
& 0x1e00) >> 9);
733 s
->ch
[ch
].burst
[0] = (value
& 0x0180) >> 7;
734 s
->ch
[ch
].pack
[0] = (value
& 0x0040) >> 6;
735 s
->ch
[ch
].port
[0] = (enum omap_dma_port
) ((value
& 0x003c) >> 2);
736 s
->ch
[ch
].data_type
= (1 << (value
& 3));
737 if (s
->ch
[ch
].port
[0] >= omap_dma_port_last
)
738 printf("%s: invalid DMA port %i\n", __FUNCTION__
,
740 if (s
->ch
[ch
].port
[1] >= omap_dma_port_last
)
741 printf("%s: invalid DMA port %i\n", __FUNCTION__
,
743 if ((value
& 3) == 3)
744 printf("%s: bad data_type for DMA channel %i\n", __FUNCTION__
, ch
);
747 case 0x02: /* SYS_DMA_CCR_CH0 */
748 s
->ch
[ch
].mode
[1] = (omap_dma_addressing_t
) ((value
& 0xc000) >> 14);
749 s
->ch
[ch
].mode
[0] = (omap_dma_addressing_t
) ((value
& 0x3000) >> 12);
750 s
->ch
[ch
].end_prog
= (value
& 0x0800) >> 11;
751 s
->ch
[ch
].repeat
= (value
& 0x0200) >> 9;
752 s
->ch
[ch
].auto_init
= (value
& 0x0100) >> 8;
753 s
->ch
[ch
].priority
= (value
& 0x0040) >> 6;
754 s
->ch
[ch
].fs
= (value
& 0x0020) >> 5;
755 s
->ch
[ch
].sync
= value
& 0x001f;
756 if (value
& 0x0080) {
757 if (s
->ch
[ch
].running
) {
758 if (!s
->ch
[ch
].signalled
&&
759 s
->ch
[ch
].auto_init
&& s
->ch
[ch
].end_prog
)
760 omap_dma_channel_load(s
, ch
);
762 s
->ch
[ch
].running
= 1;
763 omap_dma_channel_load(s
, ch
);
765 if (!s
->ch
[ch
].sync
|| (s
->drq
& (1 << s
->ch
[ch
].sync
)))
766 omap_dma_request_run(s
, ch
, 0);
768 s
->ch
[ch
].running
= 0;
769 omap_dma_request_stop(s
, ch
);
773 case 0x04: /* SYS_DMA_CICR_CH0 */
774 s
->ch
[ch
].interrupts
= value
& 0x003f;
777 case 0x06: /* SYS_DMA_CSR_CH0 */
780 case 0x08: /* SYS_DMA_CSSA_L_CH0 */
781 s
->ch
[ch
].addr
[0] &= 0xffff0000;
782 s
->ch
[ch
].addr
[0] |= value
;
785 case 0x0a: /* SYS_DMA_CSSA_U_CH0 */
786 s
->ch
[ch
].addr
[0] &= 0x0000ffff;
787 s
->ch
[ch
].addr
[0] |= value
<< 16;
790 case 0x0c: /* SYS_DMA_CDSA_L_CH0 */
791 s
->ch
[ch
].addr
[1] &= 0xffff0000;
792 s
->ch
[ch
].addr
[1] |= value
;
795 case 0x0e: /* SYS_DMA_CDSA_U_CH0 */
796 s
->ch
[ch
].addr
[1] &= 0x0000ffff;
797 s
->ch
[ch
].addr
[1] |= value
<< 16;
800 case 0x10: /* SYS_DMA_CEN_CH0 */
801 s
->ch
[ch
].elements
= value
& 0xffff;
804 case 0x12: /* SYS_DMA_CFN_CH0 */
805 s
->ch
[ch
].frames
= value
& 0xffff;
808 case 0x14: /* SYS_DMA_CFI_CH0 */
809 s
->ch
[ch
].frame_index
= value
& 0xffff;
812 case 0x16: /* SYS_DMA_CEI_CH0 */
813 s
->ch
[ch
].element_index
= value
& 0xffff;
816 case 0x18: /* SYS_DMA_CPC_CH0 */
820 OMAP_BAD_REG((unsigned long) reg
);
825 static uint32_t omap_dma_read(void *opaque
, target_phys_addr_t addr
)
827 struct omap_dma_s
*s
= (struct omap_dma_s
*) opaque
;
828 int i
, reg
, ch
, offset
= addr
- s
->base
;
832 case 0x000 ... 0x2fe:
834 ch
= (offset
>> 6) & 0x0f;
835 if (omap_dma_ch_reg_read(s
, ch
, reg
, &ret
))
839 case 0x300: /* SYS_DMA_LCD_CTRL */
840 i
= s
->lcd_ch
.condition
;
841 s
->lcd_ch
.condition
= 0;
842 qemu_irq_lower(s
->lcd_ch
.irq
);
843 return ((s
->lcd_ch
.src
== imif
) << 6) | (i
<< 3) |
844 (s
->lcd_ch
.interrupts
<< 1) | s
->lcd_ch
.dual
;
846 case 0x302: /* SYS_DMA_LCD_TOP_F1_L */
847 return s
->lcd_ch
.src_f1_top
& 0xffff;
849 case 0x304: /* SYS_DMA_LCD_TOP_F1_U */
850 return s
->lcd_ch
.src_f1_top
>> 16;
852 case 0x306: /* SYS_DMA_LCD_BOT_F1_L */
853 return s
->lcd_ch
.src_f1_bottom
& 0xffff;
855 case 0x308: /* SYS_DMA_LCD_BOT_F1_U */
856 return s
->lcd_ch
.src_f1_bottom
>> 16;
858 case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */
859 return s
->lcd_ch
.src_f2_top
& 0xffff;
861 case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */
862 return s
->lcd_ch
.src_f2_top
>> 16;
864 case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */
865 return s
->lcd_ch
.src_f2_bottom
& 0xffff;
867 case 0x310: /* SYS_DMA_LCD_BOT_F2_U */
868 return s
->lcd_ch
.src_f2_bottom
>> 16;
870 case 0x400: /* SYS_DMA_GCR */
878 static void omap_dma_write(void *opaque
, target_phys_addr_t addr
,
881 struct omap_dma_s
*s
= (struct omap_dma_s
*) opaque
;
882 int reg
, ch
, offset
= addr
- s
->base
;
885 case 0x000 ... 0x2fe:
887 ch
= (offset
>> 6) & 0x0f;
888 if (omap_dma_ch_reg_write(s
, ch
, reg
, value
))
892 case 0x300: /* SYS_DMA_LCD_CTRL */
893 s
->lcd_ch
.src
= (value
& 0x40) ? imif
: emiff
;
894 s
->lcd_ch
.condition
= 0;
895 /* Assume no bus errors and thus no BUS_ERROR irq bits. */
896 s
->lcd_ch
.interrupts
= (value
>> 1) & 1;
897 s
->lcd_ch
.dual
= value
& 1;
900 case 0x302: /* SYS_DMA_LCD_TOP_F1_L */
901 s
->lcd_ch
.src_f1_top
&= 0xffff0000;
902 s
->lcd_ch
.src_f1_top
|= 0x0000ffff & value
;
905 case 0x304: /* SYS_DMA_LCD_TOP_F1_U */
906 s
->lcd_ch
.src_f1_top
&= 0x0000ffff;
907 s
->lcd_ch
.src_f1_top
|= value
<< 16;
910 case 0x306: /* SYS_DMA_LCD_BOT_F1_L */
911 s
->lcd_ch
.src_f1_bottom
&= 0xffff0000;
912 s
->lcd_ch
.src_f1_bottom
|= 0x0000ffff & value
;
915 case 0x308: /* SYS_DMA_LCD_BOT_F1_U */
916 s
->lcd_ch
.src_f1_bottom
&= 0x0000ffff;
917 s
->lcd_ch
.src_f1_bottom
|= value
<< 16;
920 case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */
921 s
->lcd_ch
.src_f2_top
&= 0xffff0000;
922 s
->lcd_ch
.src_f2_top
|= 0x0000ffff & value
;
925 case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */
926 s
->lcd_ch
.src_f2_top
&= 0x0000ffff;
927 s
->lcd_ch
.src_f2_top
|= value
<< 16;
930 case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */
931 s
->lcd_ch
.src_f2_bottom
&= 0xffff0000;
932 s
->lcd_ch
.src_f2_bottom
|= 0x0000ffff & value
;
935 case 0x310: /* SYS_DMA_LCD_BOT_F2_U */
936 s
->lcd_ch
.src_f2_bottom
&= 0x0000ffff;
937 s
->lcd_ch
.src_f2_bottom
|= value
<< 16;
940 case 0x400: /* SYS_DMA_GCR */
941 s
->gcr
= value
& 0x000c;
949 static CPUReadMemoryFunc
*omap_dma_readfn
[] = {
950 omap_badwidth_read16
,
952 omap_badwidth_read16
,
955 static CPUWriteMemoryFunc
*omap_dma_writefn
[] = {
956 omap_badwidth_write16
,
958 omap_badwidth_write16
,
961 static void omap_dma_request(void *opaque
, int drq
, int req
)
963 struct omap_dma_s
*s
= (struct omap_dma_s
*) opaque
;
964 /* The request pins are level triggered. */
966 if (~s
->drq
& (1 << drq
)) {
968 omap_dma_request_run(s
, 0, drq
);
971 s
->drq
&= ~(1 << drq
);
974 static void omap_dma_clk_update(void *opaque
, int line
, int on
)
976 struct omap_dma_s
*s
= (struct omap_dma_s
*) opaque
;
979 s
->delay
= ticks_per_sec
>> 5;
981 qemu_mod_timer(s
->tm
, qemu_get_clock(vm_clock
) + s
->delay
);
984 qemu_del_timer(s
->tm
);
988 static void omap_dma_reset(struct omap_dma_s
*s
)
992 qemu_del_timer(s
->tm
);
996 s
->lcd_ch
.src
= emiff
;
997 s
->lcd_ch
.condition
= 0;
998 s
->lcd_ch
.interrupts
= 0;
1000 memset(s
->ch
, 0, sizeof(s
->ch
));
1001 for (i
= 0; i
< s
->chans
; i
++)
1002 s
->ch
[i
].interrupts
= 0x0003;
1005 struct omap_dma_s
*omap_dma_init(target_phys_addr_t base
,
1006 qemu_irq pic
[], struct omap_mpu_state_s
*mpu
, omap_clk clk
)
1009 struct omap_dma_s
*s
= (struct omap_dma_s
*)
1010 qemu_mallocz(sizeof(struct omap_dma_s
));
1017 s
->lcd_ch
.irq
= pic
[OMAP_INT_DMA_LCD
];
1018 s
->lcd_ch
.mpu
= mpu
;
1019 s
->tm
= qemu_new_timer(vm_clock
, (QEMUTimerCB
*) omap_dma_channel_run
, s
);
1020 omap_clk_adduser(s
->clk
, qemu_allocate_irqs(omap_dma_clk_update
, s
, 1)[0]);
1021 mpu
->drq
= qemu_allocate_irqs(omap_dma_request
, s
, 32);
1023 omap_dma_clk_update(s
, 0, 1);
1025 iomemtype
= cpu_register_io_memory(0, omap_dma_readfn
,
1026 omap_dma_writefn
, s
);
1027 cpu_register_physical_memory(s
->base
, 0x800, iomemtype
);
1033 int omap_validate_emiff_addr(struct omap_mpu_state_s
*s
,
1034 target_phys_addr_t addr
)
1036 return addr
>= OMAP_EMIFF_BASE
&& addr
< OMAP_EMIFF_BASE
+ s
->sdram_size
;
1039 int omap_validate_emifs_addr(struct omap_mpu_state_s
*s
,
1040 target_phys_addr_t addr
)
1042 return addr
>= OMAP_EMIFS_BASE
&& addr
< OMAP_EMIFF_BASE
;
1045 int omap_validate_imif_addr(struct omap_mpu_state_s
*s
,
1046 target_phys_addr_t addr
)
1048 return addr
>= OMAP_IMIF_BASE
&& addr
< OMAP_IMIF_BASE
+ s
->sram_size
;
1051 int omap_validate_tipb_addr(struct omap_mpu_state_s
*s
,
1052 target_phys_addr_t addr
)
1054 return addr
>= 0xfffb0000 && addr
< 0xffff0000;
1057 int omap_validate_local_addr(struct omap_mpu_state_s
*s
,
1058 target_phys_addr_t addr
)
1060 return addr
>= OMAP_LOCALBUS_BASE
&& addr
< OMAP_LOCALBUS_BASE
+ 0x1000000;
1063 int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s
*s
,
1064 target_phys_addr_t addr
)
1066 return addr
>= 0xe1010000 && addr
< 0xe1020004;
1070 struct omap_mpu_timer_s
{
1073 target_phys_addr_t base
;
1087 static inline uint32_t omap_timer_read(struct omap_mpu_timer_s
*timer
)
1089 uint64_t distance
= qemu_get_clock(vm_clock
) - timer
->time
;
1091 if (timer
->st
&& timer
->enable
&& timer
->rate
)
1092 return timer
->val
- muldiv64(distance
>> (timer
->ptv
+ 1),
1093 timer
->rate
, ticks_per_sec
);
1098 static inline void omap_timer_sync(struct omap_mpu_timer_s
*timer
)
1100 timer
->val
= omap_timer_read(timer
);
1101 timer
->time
= qemu_get_clock(vm_clock
);
1104 static inline void omap_timer_update(struct omap_mpu_timer_s
*timer
)
1108 if (timer
->enable
&& timer
->st
&& timer
->rate
) {
1109 timer
->val
= timer
->reset_val
; /* Should skip this on clk enable */
1110 expires
= timer
->time
+ muldiv64(timer
->val
<< (timer
->ptv
+ 1),
1111 ticks_per_sec
, timer
->rate
);
1112 qemu_mod_timer(timer
->timer
, expires
);
1114 qemu_del_timer(timer
->timer
);
1117 static void omap_timer_tick(void *opaque
)
1119 struct omap_mpu_timer_s
*timer
= (struct omap_mpu_timer_s
*) opaque
;
1120 omap_timer_sync(timer
);
1128 qemu_irq_raise(timer
->irq
);
1129 omap_timer_update(timer
);
1132 static void omap_timer_clk_update(void *opaque
, int line
, int on
)
1134 struct omap_mpu_timer_s
*timer
= (struct omap_mpu_timer_s
*) opaque
;
1136 omap_timer_sync(timer
);
1137 timer
->rate
= on
? omap_clk_getrate(timer
->clk
) : 0;
1138 omap_timer_update(timer
);
1141 static void omap_timer_clk_setup(struct omap_mpu_timer_s
*timer
)
1143 omap_clk_adduser(timer
->clk
,
1144 qemu_allocate_irqs(omap_timer_clk_update
, timer
, 1)[0]);
1145 timer
->rate
= omap_clk_getrate(timer
->clk
);
1148 static uint32_t omap_mpu_timer_read(void *opaque
, target_phys_addr_t addr
)
1150 struct omap_mpu_timer_s
*s
= (struct omap_mpu_timer_s
*) opaque
;
1151 int offset
= addr
- s
->base
;
1154 case 0x00: /* CNTL_TIMER */
1155 return (s
->enable
<< 5) | (s
->ptv
<< 2) | (s
->ar
<< 1) | s
->st
;
1157 case 0x04: /* LOAD_TIM */
1160 case 0x08: /* READ_TIM */
1161 return omap_timer_read(s
);
1168 static void omap_mpu_timer_write(void *opaque
, target_phys_addr_t addr
,
1171 struct omap_mpu_timer_s
*s
= (struct omap_mpu_timer_s
*) opaque
;
1172 int offset
= addr
- s
->base
;
1175 case 0x00: /* CNTL_TIMER */
1177 s
->enable
= (value
>> 5) & 1;
1178 s
->ptv
= (value
>> 2) & 7;
1179 s
->ar
= (value
>> 1) & 1;
1181 omap_timer_update(s
);
1184 case 0x04: /* LOAD_TIM */
1185 s
->reset_val
= value
;
1188 case 0x08: /* READ_TIM */
1197 static CPUReadMemoryFunc
*omap_mpu_timer_readfn
[] = {
1198 omap_badwidth_read32
,
1199 omap_badwidth_read32
,
1200 omap_mpu_timer_read
,
1203 static CPUWriteMemoryFunc
*omap_mpu_timer_writefn
[] = {
1204 omap_badwidth_write32
,
1205 omap_badwidth_write32
,
1206 omap_mpu_timer_write
,
1209 static void omap_mpu_timer_reset(struct omap_mpu_timer_s
*s
)
1211 qemu_del_timer(s
->timer
);
1213 s
->reset_val
= 31337;
1221 struct omap_mpu_timer_s
*omap_mpu_timer_init(target_phys_addr_t base
,
1222 qemu_irq irq
, omap_clk clk
)
1225 struct omap_mpu_timer_s
*s
= (struct omap_mpu_timer_s
*)
1226 qemu_mallocz(sizeof(struct omap_mpu_timer_s
));
1231 s
->timer
= qemu_new_timer(vm_clock
, omap_timer_tick
, s
);
1232 omap_mpu_timer_reset(s
);
1233 omap_timer_clk_setup(s
);
1235 iomemtype
= cpu_register_io_memory(0, omap_mpu_timer_readfn
,
1236 omap_mpu_timer_writefn
, s
);
1237 cpu_register_physical_memory(s
->base
, 0x100, iomemtype
);
1242 /* Watchdog timer */
1243 struct omap_watchdog_timer_s
{
1244 struct omap_mpu_timer_s timer
;
1251 static uint32_t omap_wd_timer_read(void *opaque
, target_phys_addr_t addr
)
1253 struct omap_watchdog_timer_s
*s
= (struct omap_watchdog_timer_s
*) opaque
;
1254 int offset
= addr
- s
->timer
.base
;
1257 case 0x00: /* CNTL_TIMER */
1258 return (s
->timer
.ptv
<< 9) | (s
->timer
.ar
<< 8) |
1259 (s
->timer
.st
<< 7) | (s
->free
<< 1);
1261 case 0x04: /* READ_TIMER */
1262 return omap_timer_read(&s
->timer
);
1264 case 0x08: /* TIMER_MODE */
1265 return s
->mode
<< 15;
1272 static void omap_wd_timer_write(void *opaque
, target_phys_addr_t addr
,
1275 struct omap_watchdog_timer_s
*s
= (struct omap_watchdog_timer_s
*) opaque
;
1276 int offset
= addr
- s
->timer
.base
;
1279 case 0x00: /* CNTL_TIMER */
1280 omap_timer_sync(&s
->timer
);
1281 s
->timer
.ptv
= (value
>> 9) & 7;
1282 s
->timer
.ar
= (value
>> 8) & 1;
1283 s
->timer
.st
= (value
>> 7) & 1;
1284 s
->free
= (value
>> 1) & 1;
1285 omap_timer_update(&s
->timer
);
1288 case 0x04: /* LOAD_TIMER */
1289 s
->timer
.reset_val
= value
& 0xffff;
1292 case 0x08: /* TIMER_MODE */
1293 if (!s
->mode
&& ((value
>> 15) & 1))
1294 omap_clk_get(s
->timer
.clk
);
1295 s
->mode
|= (value
>> 15) & 1;
1296 if (s
->last_wr
== 0xf5) {
1297 if ((value
& 0xff) == 0xa0) {
1299 omap_clk_put(s
->timer
.clk
);
1301 /* XXX: on T|E hardware somehow this has no effect,
1302 * on Zire 71 it works as specified. */
1304 qemu_system_reset_request();
1307 s
->last_wr
= value
& 0xff;
1315 static CPUReadMemoryFunc
*omap_wd_timer_readfn
[] = {
1316 omap_badwidth_read16
,
1318 omap_badwidth_read16
,
1321 static CPUWriteMemoryFunc
*omap_wd_timer_writefn
[] = {
1322 omap_badwidth_write16
,
1323 omap_wd_timer_write
,
1324 omap_badwidth_write16
,
1327 static void omap_wd_timer_reset(struct omap_watchdog_timer_s
*s
)
1329 qemu_del_timer(s
->timer
.timer
);
1331 omap_clk_get(s
->timer
.clk
);
1335 s
->timer
.enable
= 1;
1336 s
->timer
.it_ena
= 1;
1337 s
->timer
.reset_val
= 0xffff;
1342 omap_timer_update(&s
->timer
);
1345 struct omap_watchdog_timer_s
*omap_wd_timer_init(target_phys_addr_t base
,
1346 qemu_irq irq
, omap_clk clk
)
1349 struct omap_watchdog_timer_s
*s
= (struct omap_watchdog_timer_s
*)
1350 qemu_mallocz(sizeof(struct omap_watchdog_timer_s
));
1354 s
->timer
.base
= base
;
1355 s
->timer
.timer
= qemu_new_timer(vm_clock
, omap_timer_tick
, &s
->timer
);
1356 omap_wd_timer_reset(s
);
1357 omap_timer_clk_setup(&s
->timer
);
1359 iomemtype
= cpu_register_io_memory(0, omap_wd_timer_readfn
,
1360 omap_wd_timer_writefn
, s
);
1361 cpu_register_physical_memory(s
->timer
.base
, 0x100, iomemtype
);
1367 struct omap_32khz_timer_s
{
1368 struct omap_mpu_timer_s timer
;
1371 static uint32_t omap_os_timer_read(void *opaque
, target_phys_addr_t addr
)
1373 struct omap_32khz_timer_s
*s
= (struct omap_32khz_timer_s
*) opaque
;
1374 int offset
= addr
- s
->timer
.base
;
1377 case 0x00: /* TVR */
1378 return s
->timer
.reset_val
;
1380 case 0x04: /* TCR */
1381 return omap_timer_read(&s
->timer
);
1384 return (s
->timer
.ar
<< 3) | (s
->timer
.it_ena
<< 2) | s
->timer
.st
;
1393 static void omap_os_timer_write(void *opaque
, target_phys_addr_t addr
,
1396 struct omap_32khz_timer_s
*s
= (struct omap_32khz_timer_s
*) opaque
;
1397 int offset
= addr
- s
->timer
.base
;
1400 case 0x00: /* TVR */
1401 s
->timer
.reset_val
= value
& 0x00ffffff;
1404 case 0x04: /* TCR */
1409 s
->timer
.ar
= (value
>> 3) & 1;
1410 s
->timer
.it_ena
= (value
>> 2) & 1;
1411 if (s
->timer
.st
!= (value
& 1) || (value
& 2)) {
1412 omap_timer_sync(&s
->timer
);
1413 s
->timer
.enable
= value
& 1;
1414 s
->timer
.st
= value
& 1;
1415 omap_timer_update(&s
->timer
);
1424 static CPUReadMemoryFunc
*omap_os_timer_readfn
[] = {
1425 omap_badwidth_read32
,
1426 omap_badwidth_read32
,
1430 static CPUWriteMemoryFunc
*omap_os_timer_writefn
[] = {
1431 omap_badwidth_write32
,
1432 omap_badwidth_write32
,
1433 omap_os_timer_write
,
1436 static void omap_os_timer_reset(struct omap_32khz_timer_s
*s
)
1438 qemu_del_timer(s
->timer
.timer
);
1439 s
->timer
.enable
= 0;
1440 s
->timer
.it_ena
= 0;
1441 s
->timer
.reset_val
= 0x00ffffff;
1448 struct omap_32khz_timer_s
*omap_os_timer_init(target_phys_addr_t base
,
1449 qemu_irq irq
, omap_clk clk
)
1452 struct omap_32khz_timer_s
*s
= (struct omap_32khz_timer_s
*)
1453 qemu_mallocz(sizeof(struct omap_32khz_timer_s
));
1457 s
->timer
.base
= base
;
1458 s
->timer
.timer
= qemu_new_timer(vm_clock
, omap_timer_tick
, &s
->timer
);
1459 omap_os_timer_reset(s
);
1460 omap_timer_clk_setup(&s
->timer
);
1462 iomemtype
= cpu_register_io_memory(0, omap_os_timer_readfn
,
1463 omap_os_timer_writefn
, s
);
1464 cpu_register_physical_memory(s
->timer
.base
, 0x800, iomemtype
);
1469 /* Ultra Low-Power Device Module */
1470 static uint32_t omap_ulpd_pm_read(void *opaque
, target_phys_addr_t addr
)
1472 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
1473 int offset
= addr
- s
->ulpd_pm_base
;
1477 case 0x14: /* IT_STATUS */
1478 ret
= s
->ulpd_pm_regs
[offset
>> 2];
1479 s
->ulpd_pm_regs
[offset
>> 2] = 0;
1480 qemu_irq_lower(s
->irq
[1][OMAP_INT_GAUGE_32K
]);
1483 case 0x18: /* Reserved */
1484 case 0x1c: /* Reserved */
1485 case 0x20: /* Reserved */
1486 case 0x28: /* Reserved */
1487 case 0x2c: /* Reserved */
1489 case 0x00: /* COUNTER_32_LSB */
1490 case 0x04: /* COUNTER_32_MSB */
1491 case 0x08: /* COUNTER_HIGH_FREQ_LSB */
1492 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */
1493 case 0x10: /* GAUGING_CTRL */
1494 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */
1495 case 0x30: /* CLOCK_CTRL */
1496 case 0x34: /* SOFT_REQ */
1497 case 0x38: /* COUNTER_32_FIQ */
1498 case 0x3c: /* DPLL_CTRL */
1499 case 0x40: /* STATUS_REQ */
1500 /* XXX: check clk::usecount state for every clock */
1501 case 0x48: /* LOCL_TIME */
1502 case 0x4c: /* APLL_CTRL */
1503 case 0x50: /* POWER_CTRL */
1504 return s
->ulpd_pm_regs
[offset
>> 2];
1511 static inline void omap_ulpd_clk_update(struct omap_mpu_state_s
*s
,
1512 uint16_t diff
, uint16_t value
)
1514 if (diff
& (1 << 4)) /* USB_MCLK_EN */
1515 omap_clk_onoff(omap_findclk(s
, "usb_clk0"), (value
>> 4) & 1);
1516 if (diff
& (1 << 5)) /* DIS_USB_PVCI_CLK */
1517 omap_clk_onoff(omap_findclk(s
, "usb_w2fc_ck"), (~value
>> 5) & 1);
1520 static inline void omap_ulpd_req_update(struct omap_mpu_state_s
*s
,
1521 uint16_t diff
, uint16_t value
)
1523 if (diff
& (1 << 0)) /* SOFT_DPLL_REQ */
1524 omap_clk_canidle(omap_findclk(s
, "dpll4"), (~value
>> 0) & 1);
1525 if (diff
& (1 << 1)) /* SOFT_COM_REQ */
1526 omap_clk_canidle(omap_findclk(s
, "com_mclk_out"), (~value
>> 1) & 1);
1527 if (diff
& (1 << 2)) /* SOFT_SDW_REQ */
1528 omap_clk_canidle(omap_findclk(s
, "bt_mclk_out"), (~value
>> 2) & 1);
1529 if (diff
& (1 << 3)) /* SOFT_USB_REQ */
1530 omap_clk_canidle(omap_findclk(s
, "usb_clk0"), (~value
>> 3) & 1);
1533 static void omap_ulpd_pm_write(void *opaque
, target_phys_addr_t addr
,
1536 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
1537 int offset
= addr
- s
->ulpd_pm_base
;
1540 static const int bypass_div
[4] = { 1, 2, 4, 4 };
1544 case 0x00: /* COUNTER_32_LSB */
1545 case 0x04: /* COUNTER_32_MSB */
1546 case 0x08: /* COUNTER_HIGH_FREQ_LSB */
1547 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */
1548 case 0x14: /* IT_STATUS */
1549 case 0x40: /* STATUS_REQ */
1553 case 0x10: /* GAUGING_CTRL */
1554 /* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */
1555 if ((s
->ulpd_pm_regs
[offset
>> 2] ^ value
) & 1) {
1556 now
= qemu_get_clock(vm_clock
);
1559 s
->ulpd_gauge_start
= now
;
1561 now
-= s
->ulpd_gauge_start
;
1564 ticks
= muldiv64(now
, 32768, ticks_per_sec
);
1565 s
->ulpd_pm_regs
[0x00 >> 2] = (ticks
>> 0) & 0xffff;
1566 s
->ulpd_pm_regs
[0x04 >> 2] = (ticks
>> 16) & 0xffff;
1567 if (ticks
>> 32) /* OVERFLOW_32K */
1568 s
->ulpd_pm_regs
[0x14 >> 2] |= 1 << 2;
1570 /* High frequency ticks */
1571 ticks
= muldiv64(now
, 12000000, ticks_per_sec
);
1572 s
->ulpd_pm_regs
[0x08 >> 2] = (ticks
>> 0) & 0xffff;
1573 s
->ulpd_pm_regs
[0x0c >> 2] = (ticks
>> 16) & 0xffff;
1574 if (ticks
>> 32) /* OVERFLOW_HI_FREQ */
1575 s
->ulpd_pm_regs
[0x14 >> 2] |= 1 << 1;
1577 s
->ulpd_pm_regs
[0x14 >> 2] |= 1 << 0; /* IT_GAUGING */
1578 qemu_irq_raise(s
->irq
[1][OMAP_INT_GAUGE_32K
]);
1581 s
->ulpd_pm_regs
[offset
>> 2] = value
;
1584 case 0x18: /* Reserved */
1585 case 0x1c: /* Reserved */
1586 case 0x20: /* Reserved */
1587 case 0x28: /* Reserved */
1588 case 0x2c: /* Reserved */
1590 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */
1591 case 0x38: /* COUNTER_32_FIQ */
1592 case 0x48: /* LOCL_TIME */
1593 case 0x50: /* POWER_CTRL */
1594 s
->ulpd_pm_regs
[offset
>> 2] = value
;
1597 case 0x30: /* CLOCK_CTRL */
1598 diff
= s
->ulpd_pm_regs
[offset
>> 2] ^ value
;
1599 s
->ulpd_pm_regs
[offset
>> 2] = value
& 0x3f;
1600 omap_ulpd_clk_update(s
, diff
, value
);
1603 case 0x34: /* SOFT_REQ */
1604 diff
= s
->ulpd_pm_regs
[offset
>> 2] ^ value
;
1605 s
->ulpd_pm_regs
[offset
>> 2] = value
& 0x1f;
1606 omap_ulpd_req_update(s
, diff
, value
);
1609 case 0x3c: /* DPLL_CTRL */
1610 /* XXX: OMAP310 TRM claims bit 3 is PLL_ENABLE, and bit 4 is
1611 * omitted altogether, probably a typo. */
1612 /* This register has identical semantics with DPLL(1:3) control
1613 * registers, see omap_dpll_write() */
1614 diff
= s
->ulpd_pm_regs
[offset
>> 2] & value
;
1615 s
->ulpd_pm_regs
[offset
>> 2] = value
& 0x2fff;
1616 if (diff
& (0x3ff << 2)) {
1617 if (value
& (1 << 4)) { /* PLL_ENABLE */
1618 div
= ((value
>> 5) & 3) + 1; /* PLL_DIV */
1619 mult
= MIN((value
>> 7) & 0x1f, 1); /* PLL_MULT */
1621 div
= bypass_div
[((value
>> 2) & 3)]; /* BYPASS_DIV */
1624 omap_clk_setrate(omap_findclk(s
, "dpll4"), div
, mult
);
1627 /* Enter the desired mode. */
1628 s
->ulpd_pm_regs
[offset
>> 2] =
1629 (s
->ulpd_pm_regs
[offset
>> 2] & 0xfffe) |
1630 ((s
->ulpd_pm_regs
[offset
>> 2] >> 4) & 1);
1632 /* Act as if the lock is restored. */
1633 s
->ulpd_pm_regs
[offset
>> 2] |= 2;
1636 case 0x4c: /* APLL_CTRL */
1637 diff
= s
->ulpd_pm_regs
[offset
>> 2] & value
;
1638 s
->ulpd_pm_regs
[offset
>> 2] = value
& 0xf;
1639 if (diff
& (1 << 0)) /* APLL_NDPLL_SWITCH */
1640 omap_clk_reparent(omap_findclk(s
, "ck_48m"), omap_findclk(s
,
1641 (value
& (1 << 0)) ? "apll" : "dpll4"));
1649 static CPUReadMemoryFunc
*omap_ulpd_pm_readfn
[] = {
1650 omap_badwidth_read16
,
1652 omap_badwidth_read16
,
1655 static CPUWriteMemoryFunc
*omap_ulpd_pm_writefn
[] = {
1656 omap_badwidth_write16
,
1658 omap_badwidth_write16
,
1661 static void omap_ulpd_pm_reset(struct omap_mpu_state_s
*mpu
)
1663 mpu
->ulpd_pm_regs
[0x00 >> 2] = 0x0001;
1664 mpu
->ulpd_pm_regs
[0x04 >> 2] = 0x0000;
1665 mpu
->ulpd_pm_regs
[0x08 >> 2] = 0x0001;
1666 mpu
->ulpd_pm_regs
[0x0c >> 2] = 0x0000;
1667 mpu
->ulpd_pm_regs
[0x10 >> 2] = 0x0000;
1668 mpu
->ulpd_pm_regs
[0x18 >> 2] = 0x01;
1669 mpu
->ulpd_pm_regs
[0x1c >> 2] = 0x01;
1670 mpu
->ulpd_pm_regs
[0x20 >> 2] = 0x01;
1671 mpu
->ulpd_pm_regs
[0x24 >> 2] = 0x03ff;
1672 mpu
->ulpd_pm_regs
[0x28 >> 2] = 0x01;
1673 mpu
->ulpd_pm_regs
[0x2c >> 2] = 0x01;
1674 omap_ulpd_clk_update(mpu
, mpu
->ulpd_pm_regs
[0x30 >> 2], 0x0000);
1675 mpu
->ulpd_pm_regs
[0x30 >> 2] = 0x0000;
1676 omap_ulpd_req_update(mpu
, mpu
->ulpd_pm_regs
[0x34 >> 2], 0x0000);
1677 mpu
->ulpd_pm_regs
[0x34 >> 2] = 0x0000;
1678 mpu
->ulpd_pm_regs
[0x38 >> 2] = 0x0001;
1679 mpu
->ulpd_pm_regs
[0x3c >> 2] = 0x2211;
1680 mpu
->ulpd_pm_regs
[0x40 >> 2] = 0x0000; /* FIXME: dump a real STATUS_REQ */
1681 mpu
->ulpd_pm_regs
[0x48 >> 2] = 0x960;
1682 mpu
->ulpd_pm_regs
[0x4c >> 2] = 0x08;
1683 mpu
->ulpd_pm_regs
[0x50 >> 2] = 0x08;
1684 omap_clk_setrate(omap_findclk(mpu
, "dpll4"), 1, 4);
1685 omap_clk_reparent(omap_findclk(mpu
, "ck_48m"), omap_findclk(mpu
, "dpll4"));
1688 static void omap_ulpd_pm_init(target_phys_addr_t base
,
1689 struct omap_mpu_state_s
*mpu
)
1691 int iomemtype
= cpu_register_io_memory(0, omap_ulpd_pm_readfn
,
1692 omap_ulpd_pm_writefn
, mpu
);
1694 mpu
->ulpd_pm_base
= base
;
1695 cpu_register_physical_memory(mpu
->ulpd_pm_base
, 0x800, iomemtype
);
1696 omap_ulpd_pm_reset(mpu
);
1699 /* OMAP Pin Configuration */
1700 static uint32_t omap_pin_cfg_read(void *opaque
, target_phys_addr_t addr
)
1702 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
1703 int offset
= addr
- s
->pin_cfg_base
;
1706 case 0x00: /* FUNC_MUX_CTRL_0 */
1707 case 0x04: /* FUNC_MUX_CTRL_1 */
1708 case 0x08: /* FUNC_MUX_CTRL_2 */
1709 return s
->func_mux_ctrl
[offset
>> 2];
1711 case 0x0c: /* COMP_MODE_CTRL_0 */
1712 return s
->comp_mode_ctrl
[0];
1714 case 0x10: /* FUNC_MUX_CTRL_3 */
1715 case 0x14: /* FUNC_MUX_CTRL_4 */
1716 case 0x18: /* FUNC_MUX_CTRL_5 */
1717 case 0x1c: /* FUNC_MUX_CTRL_6 */
1718 case 0x20: /* FUNC_MUX_CTRL_7 */
1719 case 0x24: /* FUNC_MUX_CTRL_8 */
1720 case 0x28: /* FUNC_MUX_CTRL_9 */
1721 case 0x2c: /* FUNC_MUX_CTRL_A */
1722 case 0x30: /* FUNC_MUX_CTRL_B */
1723 case 0x34: /* FUNC_MUX_CTRL_C */
1724 case 0x38: /* FUNC_MUX_CTRL_D */
1725 return s
->func_mux_ctrl
[(offset
>> 2) - 1];
1727 case 0x40: /* PULL_DWN_CTRL_0 */
1728 case 0x44: /* PULL_DWN_CTRL_1 */
1729 case 0x48: /* PULL_DWN_CTRL_2 */
1730 case 0x4c: /* PULL_DWN_CTRL_3 */
1731 return s
->pull_dwn_ctrl
[(offset
& 0xf) >> 2];
1733 case 0x50: /* GATE_INH_CTRL_0 */
1734 return s
->gate_inh_ctrl
[0];
1736 case 0x60: /* VOLTAGE_CTRL_0 */
1737 return s
->voltage_ctrl
[0];
1739 case 0x70: /* TEST_DBG_CTRL_0 */
1740 return s
->test_dbg_ctrl
[0];
1742 case 0x80: /* MOD_CONF_CTRL_0 */
1743 return s
->mod_conf_ctrl
[0];
1750 static inline void omap_pin_funcmux0_update(struct omap_mpu_state_s
*s
,
1751 uint32_t diff
, uint32_t value
)
1753 if (s
->compat1509
) {
1754 if (diff
& (1 << 9)) /* BLUETOOTH */
1755 omap_clk_onoff(omap_findclk(s
, "bt_mclk_out"),
1757 if (diff
& (1 << 7)) /* USB.CLKO */
1758 omap_clk_onoff(omap_findclk(s
, "usb.clko"),
1763 static inline void omap_pin_funcmux1_update(struct omap_mpu_state_s
*s
,
1764 uint32_t diff
, uint32_t value
)
1766 if (s
->compat1509
) {
1767 if (diff
& (1 << 31)) /* MCBSP3_CLK_HIZ_DI */
1768 omap_clk_onoff(omap_findclk(s
, "mcbsp3.clkx"),
1770 if (diff
& (1 << 1)) /* CLK32K */
1771 omap_clk_onoff(omap_findclk(s
, "clk32k_out"),
1776 static inline void omap_pin_modconf1_update(struct omap_mpu_state_s
*s
,
1777 uint32_t diff
, uint32_t value
)
1779 if (diff
& (1 << 31)) /* CONF_MOD_UART3_CLK_MODE_R */
1780 omap_clk_reparent(omap_findclk(s
, "uart3_ck"),
1781 omap_findclk(s
, ((value
>> 31) & 1) ?
1782 "ck_48m" : "armper_ck"));
1783 if (diff
& (1 << 30)) /* CONF_MOD_UART2_CLK_MODE_R */
1784 omap_clk_reparent(omap_findclk(s
, "uart2_ck"),
1785 omap_findclk(s
, ((value
>> 30) & 1) ?
1786 "ck_48m" : "armper_ck"));
1787 if (diff
& (1 << 29)) /* CONF_MOD_UART1_CLK_MODE_R */
1788 omap_clk_reparent(omap_findclk(s
, "uart1_ck"),
1789 omap_findclk(s
, ((value
>> 29) & 1) ?
1790 "ck_48m" : "armper_ck"));
1791 if (diff
& (1 << 23)) /* CONF_MOD_MMC_SD_CLK_REQ_R */
1792 omap_clk_reparent(omap_findclk(s
, "mmc_ck"),
1793 omap_findclk(s
, ((value
>> 23) & 1) ?
1794 "ck_48m" : "armper_ck"));
1795 if (diff
& (1 << 12)) /* CONF_MOD_COM_MCLK_12_48_S */
1796 omap_clk_reparent(omap_findclk(s
, "com_mclk_out"),
1797 omap_findclk(s
, ((value
>> 12) & 1) ?
1798 "ck_48m" : "armper_ck"));
1799 if (diff
& (1 << 9)) /* CONF_MOD_USB_HOST_HHC_UHO */
1800 omap_clk_onoff(omap_findclk(s
, "usb_hhc_ck"), (value
>> 9) & 1);
1803 static void omap_pin_cfg_write(void *opaque
, target_phys_addr_t addr
,
1806 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
1807 int offset
= addr
- s
->pin_cfg_base
;
1811 case 0x00: /* FUNC_MUX_CTRL_0 */
1812 diff
= s
->func_mux_ctrl
[offset
>> 2] ^ value
;
1813 s
->func_mux_ctrl
[offset
>> 2] = value
;
1814 omap_pin_funcmux0_update(s
, diff
, value
);
1817 case 0x04: /* FUNC_MUX_CTRL_1 */
1818 diff
= s
->func_mux_ctrl
[offset
>> 2] ^ value
;
1819 s
->func_mux_ctrl
[offset
>> 2] = value
;
1820 omap_pin_funcmux1_update(s
, diff
, value
);
1823 case 0x08: /* FUNC_MUX_CTRL_2 */
1824 s
->func_mux_ctrl
[offset
>> 2] = value
;
1827 case 0x0c: /* COMP_MODE_CTRL_0 */
1828 s
->comp_mode_ctrl
[0] = value
;
1829 s
->compat1509
= (value
!= 0x0000eaef);
1830 omap_pin_funcmux0_update(s
, ~0, s
->func_mux_ctrl
[0]);
1831 omap_pin_funcmux1_update(s
, ~0, s
->func_mux_ctrl
[1]);
1834 case 0x10: /* FUNC_MUX_CTRL_3 */
1835 case 0x14: /* FUNC_MUX_CTRL_4 */
1836 case 0x18: /* FUNC_MUX_CTRL_5 */
1837 case 0x1c: /* FUNC_MUX_CTRL_6 */
1838 case 0x20: /* FUNC_MUX_CTRL_7 */
1839 case 0x24: /* FUNC_MUX_CTRL_8 */
1840 case 0x28: /* FUNC_MUX_CTRL_9 */
1841 case 0x2c: /* FUNC_MUX_CTRL_A */
1842 case 0x30: /* FUNC_MUX_CTRL_B */
1843 case 0x34: /* FUNC_MUX_CTRL_C */
1844 case 0x38: /* FUNC_MUX_CTRL_D */
1845 s
->func_mux_ctrl
[(offset
>> 2) - 1] = value
;
1848 case 0x40: /* PULL_DWN_CTRL_0 */
1849 case 0x44: /* PULL_DWN_CTRL_1 */
1850 case 0x48: /* PULL_DWN_CTRL_2 */
1851 case 0x4c: /* PULL_DWN_CTRL_3 */
1852 s
->pull_dwn_ctrl
[(offset
& 0xf) >> 2] = value
;
1855 case 0x50: /* GATE_INH_CTRL_0 */
1856 s
->gate_inh_ctrl
[0] = value
;
1859 case 0x60: /* VOLTAGE_CTRL_0 */
1860 s
->voltage_ctrl
[0] = value
;
1863 case 0x70: /* TEST_DBG_CTRL_0 */
1864 s
->test_dbg_ctrl
[0] = value
;
1867 case 0x80: /* MOD_CONF_CTRL_0 */
1868 diff
= s
->mod_conf_ctrl
[0] ^ value
;
1869 s
->mod_conf_ctrl
[0] = value
;
1870 omap_pin_modconf1_update(s
, diff
, value
);
1878 static CPUReadMemoryFunc
*omap_pin_cfg_readfn
[] = {
1879 omap_badwidth_read32
,
1880 omap_badwidth_read32
,
1884 static CPUWriteMemoryFunc
*omap_pin_cfg_writefn
[] = {
1885 omap_badwidth_write32
,
1886 omap_badwidth_write32
,
1890 static void omap_pin_cfg_reset(struct omap_mpu_state_s
*mpu
)
1892 /* Start in Compatibility Mode. */
1893 mpu
->compat1509
= 1;
1894 omap_pin_funcmux0_update(mpu
, mpu
->func_mux_ctrl
[0], 0);
1895 omap_pin_funcmux1_update(mpu
, mpu
->func_mux_ctrl
[1], 0);
1896 omap_pin_modconf1_update(mpu
, mpu
->mod_conf_ctrl
[0], 0);
1897 memset(mpu
->func_mux_ctrl
, 0, sizeof(mpu
->func_mux_ctrl
));
1898 memset(mpu
->comp_mode_ctrl
, 0, sizeof(mpu
->comp_mode_ctrl
));
1899 memset(mpu
->pull_dwn_ctrl
, 0, sizeof(mpu
->pull_dwn_ctrl
));
1900 memset(mpu
->gate_inh_ctrl
, 0, sizeof(mpu
->gate_inh_ctrl
));
1901 memset(mpu
->voltage_ctrl
, 0, sizeof(mpu
->voltage_ctrl
));
1902 memset(mpu
->test_dbg_ctrl
, 0, sizeof(mpu
->test_dbg_ctrl
));
1903 memset(mpu
->mod_conf_ctrl
, 0, sizeof(mpu
->mod_conf_ctrl
));
1906 static void omap_pin_cfg_init(target_phys_addr_t base
,
1907 struct omap_mpu_state_s
*mpu
)
1909 int iomemtype
= cpu_register_io_memory(0, omap_pin_cfg_readfn
,
1910 omap_pin_cfg_writefn
, mpu
);
1912 mpu
->pin_cfg_base
= base
;
1913 cpu_register_physical_memory(mpu
->pin_cfg_base
, 0x800, iomemtype
);
1914 omap_pin_cfg_reset(mpu
);
1917 /* Device Identification, Die Identification */
1918 static uint32_t omap_id_read(void *opaque
, target_phys_addr_t addr
)
1920 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
1923 case 0xfffe1800: /* DIE_ID_LSB */
1925 case 0xfffe1804: /* DIE_ID_MSB */
1928 case 0xfffe2000: /* PRODUCT_ID_LSB */
1930 case 0xfffe2004: /* PRODUCT_ID_MSB */
1933 case 0xfffed400: /* JTAG_ID_LSB */
1934 switch (s
->mpu_model
) {
1942 case 0xfffed404: /* JTAG_ID_MSB */
1943 switch (s
->mpu_model
) {
1956 static void omap_id_write(void *opaque
, target_phys_addr_t addr
,
1962 static CPUReadMemoryFunc
*omap_id_readfn
[] = {
1963 omap_badwidth_read32
,
1964 omap_badwidth_read32
,
1968 static CPUWriteMemoryFunc
*omap_id_writefn
[] = {
1969 omap_badwidth_write32
,
1970 omap_badwidth_write32
,
1974 static void omap_id_init(struct omap_mpu_state_s
*mpu
)
1976 int iomemtype
= cpu_register_io_memory(0, omap_id_readfn
,
1977 omap_id_writefn
, mpu
);
1978 cpu_register_physical_memory(0xfffe1800, 0x800, iomemtype
);
1979 cpu_register_physical_memory(0xfffed400, 0x100, iomemtype
);
1980 if (!cpu_is_omap15xx(mpu
))
1981 cpu_register_physical_memory(0xfffe2000, 0x800, iomemtype
);
1984 /* MPUI Control (Dummy) */
1985 static uint32_t omap_mpui_read(void *opaque
, target_phys_addr_t addr
)
1987 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
1988 int offset
= addr
- s
->mpui_base
;
1991 case 0x00: /* CTRL */
1992 return s
->mpui_ctrl
;
1993 case 0x04: /* DEBUG_ADDR */
1995 case 0x08: /* DEBUG_DATA */
1997 case 0x0c: /* DEBUG_FLAG */
1999 case 0x10: /* STATUS */
2002 /* Not in OMAP310 */
2003 case 0x14: /* DSP_STATUS */
2004 case 0x18: /* DSP_BOOT_CONFIG */
2006 case 0x1c: /* DSP_MPUI_CONFIG */
2014 static void omap_mpui_write(void *opaque
, target_phys_addr_t addr
,
2017 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
2018 int offset
= addr
- s
->mpui_base
;
2021 case 0x00: /* CTRL */
2022 s
->mpui_ctrl
= value
& 0x007fffff;
2025 case 0x04: /* DEBUG_ADDR */
2026 case 0x08: /* DEBUG_DATA */
2027 case 0x0c: /* DEBUG_FLAG */
2028 case 0x10: /* STATUS */
2029 /* Not in OMAP310 */
2030 case 0x14: /* DSP_STATUS */
2032 case 0x18: /* DSP_BOOT_CONFIG */
2033 case 0x1c: /* DSP_MPUI_CONFIG */
2041 static CPUReadMemoryFunc
*omap_mpui_readfn
[] = {
2042 omap_badwidth_read32
,
2043 omap_badwidth_read32
,
2047 static CPUWriteMemoryFunc
*omap_mpui_writefn
[] = {
2048 omap_badwidth_write32
,
2049 omap_badwidth_write32
,
2053 static void omap_mpui_reset(struct omap_mpu_state_s
*s
)
2055 s
->mpui_ctrl
= 0x0003ff1b;
2058 static void omap_mpui_init(target_phys_addr_t base
,
2059 struct omap_mpu_state_s
*mpu
)
2061 int iomemtype
= cpu_register_io_memory(0, omap_mpui_readfn
,
2062 omap_mpui_writefn
, mpu
);
2064 mpu
->mpui_base
= base
;
2065 cpu_register_physical_memory(mpu
->mpui_base
, 0x100, iomemtype
);
2067 omap_mpui_reset(mpu
);
2071 struct omap_tipb_bridge_s
{
2072 target_phys_addr_t base
;
2079 uint16_t enh_control
;
2082 static uint32_t omap_tipb_bridge_read(void *opaque
, target_phys_addr_t addr
)
2084 struct omap_tipb_bridge_s
*s
= (struct omap_tipb_bridge_s
*) opaque
;
2085 int offset
= addr
- s
->base
;
2088 case 0x00: /* TIPB_CNTL */
2090 case 0x04: /* TIPB_BUS_ALLOC */
2092 case 0x08: /* MPU_TIPB_CNTL */
2094 case 0x0c: /* ENHANCED_TIPB_CNTL */
2095 return s
->enh_control
;
2096 case 0x10: /* ADDRESS_DBG */
2097 case 0x14: /* DATA_DEBUG_LOW */
2098 case 0x18: /* DATA_DEBUG_HIGH */
2100 case 0x1c: /* DEBUG_CNTR_SIG */
2108 static void omap_tipb_bridge_write(void *opaque
, target_phys_addr_t addr
,
2111 struct omap_tipb_bridge_s
*s
= (struct omap_tipb_bridge_s
*) opaque
;
2112 int offset
= addr
- s
->base
;
2115 case 0x00: /* TIPB_CNTL */
2116 s
->control
= value
& 0xffff;
2119 case 0x04: /* TIPB_BUS_ALLOC */
2120 s
->alloc
= value
& 0x003f;
2123 case 0x08: /* MPU_TIPB_CNTL */
2124 s
->buffer
= value
& 0x0003;
2127 case 0x0c: /* ENHANCED_TIPB_CNTL */
2128 s
->width_intr
= !(value
& 2);
2129 s
->enh_control
= value
& 0x000f;
2132 case 0x10: /* ADDRESS_DBG */
2133 case 0x14: /* DATA_DEBUG_LOW */
2134 case 0x18: /* DATA_DEBUG_HIGH */
2135 case 0x1c: /* DEBUG_CNTR_SIG */
2144 static CPUReadMemoryFunc
*omap_tipb_bridge_readfn
[] = {
2145 omap_badwidth_read16
,
2146 omap_tipb_bridge_read
,
2147 omap_tipb_bridge_read
,
2150 static CPUWriteMemoryFunc
*omap_tipb_bridge_writefn
[] = {
2151 omap_badwidth_write16
,
2152 omap_tipb_bridge_write
,
2153 omap_tipb_bridge_write
,
2156 static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s
*s
)
2158 s
->control
= 0xffff;
2161 s
->enh_control
= 0x000f;
2164 struct omap_tipb_bridge_s
*omap_tipb_bridge_init(target_phys_addr_t base
,
2165 qemu_irq abort_irq
, omap_clk clk
)
2168 struct omap_tipb_bridge_s
*s
= (struct omap_tipb_bridge_s
*)
2169 qemu_mallocz(sizeof(struct omap_tipb_bridge_s
));
2171 s
->abort
= abort_irq
;
2173 omap_tipb_bridge_reset(s
);
2175 iomemtype
= cpu_register_io_memory(0, omap_tipb_bridge_readfn
,
2176 omap_tipb_bridge_writefn
, s
);
2177 cpu_register_physical_memory(s
->base
, 0x100, iomemtype
);
2182 /* Dummy Traffic Controller's Memory Interface */
2183 static uint32_t omap_tcmi_read(void *opaque
, target_phys_addr_t addr
)
2185 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
2186 int offset
= addr
- s
->tcmi_base
;
2190 case 0xfffecc00: /* IMIF_PRIO */
2191 case 0xfffecc04: /* EMIFS_PRIO */
2192 case 0xfffecc08: /* EMIFF_PRIO */
2193 case 0xfffecc0c: /* EMIFS_CONFIG */
2194 case 0xfffecc10: /* EMIFS_CS0_CONFIG */
2195 case 0xfffecc14: /* EMIFS_CS1_CONFIG */
2196 case 0xfffecc18: /* EMIFS_CS2_CONFIG */
2197 case 0xfffecc1c: /* EMIFS_CS3_CONFIG */
2198 case 0xfffecc24: /* EMIFF_MRS */
2199 case 0xfffecc28: /* TIMEOUT1 */
2200 case 0xfffecc2c: /* TIMEOUT2 */
2201 case 0xfffecc30: /* TIMEOUT3 */
2202 case 0xfffecc3c: /* EMIFF_SDRAM_CONFIG_2 */
2203 case 0xfffecc40: /* EMIFS_CFG_DYN_WAIT */
2204 return s
->tcmi_regs
[offset
>> 2];
2206 case 0xfffecc20: /* EMIFF_SDRAM_CONFIG */
2207 ret
= s
->tcmi_regs
[offset
>> 2];
2208 s
->tcmi_regs
[offset
>> 2] &= ~1; /* XXX: Clear SLRF on SDRAM access */
2209 /* XXX: We can try using the VGA_DIRTY flag for this */
2217 static void omap_tcmi_write(void *opaque
, target_phys_addr_t addr
,
2220 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
2221 int offset
= addr
- s
->tcmi_base
;
2224 case 0xfffecc00: /* IMIF_PRIO */
2225 case 0xfffecc04: /* EMIFS_PRIO */
2226 case 0xfffecc08: /* EMIFF_PRIO */
2227 case 0xfffecc10: /* EMIFS_CS0_CONFIG */
2228 case 0xfffecc14: /* EMIFS_CS1_CONFIG */
2229 case 0xfffecc18: /* EMIFS_CS2_CONFIG */
2230 case 0xfffecc1c: /* EMIFS_CS3_CONFIG */
2231 case 0xfffecc20: /* EMIFF_SDRAM_CONFIG */
2232 case 0xfffecc24: /* EMIFF_MRS */
2233 case 0xfffecc28: /* TIMEOUT1 */
2234 case 0xfffecc2c: /* TIMEOUT2 */
2235 case 0xfffecc30: /* TIMEOUT3 */
2236 case 0xfffecc3c: /* EMIFF_SDRAM_CONFIG_2 */
2237 case 0xfffecc40: /* EMIFS_CFG_DYN_WAIT */
2238 s
->tcmi_regs
[offset
>> 2] = value
;
2240 case 0xfffecc0c: /* EMIFS_CONFIG */
2241 s
->tcmi_regs
[offset
>> 2] = (value
& 0xf) | (1 << 4);
2249 static CPUReadMemoryFunc
*omap_tcmi_readfn
[] = {
2250 omap_badwidth_read32
,
2251 omap_badwidth_read32
,
2255 static CPUWriteMemoryFunc
*omap_tcmi_writefn
[] = {
2256 omap_badwidth_write32
,
2257 omap_badwidth_write32
,
2261 static void omap_tcmi_reset(struct omap_mpu_state_s
*mpu
)
2263 mpu
->tcmi_regs
[0x00 >> 2] = 0x00000000;
2264 mpu
->tcmi_regs
[0x04 >> 2] = 0x00000000;
2265 mpu
->tcmi_regs
[0x08 >> 2] = 0x00000000;
2266 mpu
->tcmi_regs
[0x0c >> 2] = 0x00000010;
2267 mpu
->tcmi_regs
[0x10 >> 2] = 0x0010fffb;
2268 mpu
->tcmi_regs
[0x14 >> 2] = 0x0010fffb;
2269 mpu
->tcmi_regs
[0x18 >> 2] = 0x0010fffb;
2270 mpu
->tcmi_regs
[0x1c >> 2] = 0x0010fffb;
2271 mpu
->tcmi_regs
[0x20 >> 2] = 0x00618800;
2272 mpu
->tcmi_regs
[0x24 >> 2] = 0x00000037;
2273 mpu
->tcmi_regs
[0x28 >> 2] = 0x00000000;
2274 mpu
->tcmi_regs
[0x2c >> 2] = 0x00000000;
2275 mpu
->tcmi_regs
[0x30 >> 2] = 0x00000000;
2276 mpu
->tcmi_regs
[0x3c >> 2] = 0x00000003;
2277 mpu
->tcmi_regs
[0x40 >> 2] = 0x00000000;
2280 static void omap_tcmi_init(target_phys_addr_t base
,
2281 struct omap_mpu_state_s
*mpu
)
2283 int iomemtype
= cpu_register_io_memory(0, omap_tcmi_readfn
,
2284 omap_tcmi_writefn
, mpu
);
2286 mpu
->tcmi_base
= base
;
2287 cpu_register_physical_memory(mpu
->tcmi_base
, 0x100, iomemtype
);
2288 omap_tcmi_reset(mpu
);
2291 /* Digital phase-locked loops control */
2292 static uint32_t omap_dpll_read(void *opaque
, target_phys_addr_t addr
)
2294 struct dpll_ctl_s
*s
= (struct dpll_ctl_s
*) opaque
;
2295 int offset
= addr
- s
->base
;
2297 if (offset
== 0x00) /* CTL_REG */
2304 static void omap_dpll_write(void *opaque
, target_phys_addr_t addr
,
2307 struct dpll_ctl_s
*s
= (struct dpll_ctl_s
*) opaque
;
2309 int offset
= addr
- s
->base
;
2310 static const int bypass_div
[4] = { 1, 2, 4, 4 };
2313 if (offset
== 0x00) { /* CTL_REG */
2314 /* See omap_ulpd_pm_write() too */
2315 diff
= s
->mode
& value
;
2316 s
->mode
= value
& 0x2fff;
2317 if (diff
& (0x3ff << 2)) {
2318 if (value
& (1 << 4)) { /* PLL_ENABLE */
2319 div
= ((value
>> 5) & 3) + 1; /* PLL_DIV */
2320 mult
= MIN((value
>> 7) & 0x1f, 1); /* PLL_MULT */
2322 div
= bypass_div
[((value
>> 2) & 3)]; /* BYPASS_DIV */
2325 omap_clk_setrate(s
->dpll
, div
, mult
);
2328 /* Enter the desired mode. */
2329 s
->mode
= (s
->mode
& 0xfffe) | ((s
->mode
>> 4) & 1);
2331 /* Act as if the lock is restored. */
2338 static CPUReadMemoryFunc
*omap_dpll_readfn
[] = {
2339 omap_badwidth_read16
,
2341 omap_badwidth_read16
,
2344 static CPUWriteMemoryFunc
*omap_dpll_writefn
[] = {
2345 omap_badwidth_write16
,
2347 omap_badwidth_write16
,
2350 static void omap_dpll_reset(struct dpll_ctl_s
*s
)
2353 omap_clk_setrate(s
->dpll
, 1, 1);
2356 static void omap_dpll_init(struct dpll_ctl_s
*s
, target_phys_addr_t base
,
2359 int iomemtype
= cpu_register_io_memory(0, omap_dpll_readfn
,
2360 omap_dpll_writefn
, s
);
2366 cpu_register_physical_memory(s
->base
, 0x100, iomemtype
);
2370 struct omap_uart_s
{
2371 SerialState
*serial
; /* TODO */
2374 static void omap_uart_reset(struct omap_uart_s
*s
)
2378 struct omap_uart_s
*omap_uart_init(target_phys_addr_t base
,
2379 qemu_irq irq
, omap_clk clk
, CharDriverState
*chr
)
2381 struct omap_uart_s
*s
= (struct omap_uart_s
*)
2382 qemu_mallocz(sizeof(struct omap_uart_s
));
2384 s
->serial
= serial_mm_init(base
, 2, irq
, chr
, 1);
2388 /* MPU Clock/Reset/Power Mode Control */
2389 static uint32_t omap_clkm_read(void *opaque
, target_phys_addr_t addr
)
2391 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
2392 int offset
= addr
- s
->clkm
.mpu_base
;
2395 case 0x00: /* ARM_CKCTL */
2396 return s
->clkm
.arm_ckctl
;
2398 case 0x04: /* ARM_IDLECT1 */
2399 return s
->clkm
.arm_idlect1
;
2401 case 0x08: /* ARM_IDLECT2 */
2402 return s
->clkm
.arm_idlect2
;
2404 case 0x0c: /* ARM_EWUPCT */
2405 return s
->clkm
.arm_ewupct
;
2407 case 0x10: /* ARM_RSTCT1 */
2408 return s
->clkm
.arm_rstct1
;
2410 case 0x14: /* ARM_RSTCT2 */
2411 return s
->clkm
.arm_rstct2
;
2413 case 0x18: /* ARM_SYSST */
2414 return (s
->clkm
.clocking_scheme
< 11) | s
->clkm
.cold_start
;
2416 case 0x1c: /* ARM_CKOUT1 */
2417 return s
->clkm
.arm_ckout1
;
2419 case 0x20: /* ARM_CKOUT2 */
2427 static inline void omap_clkm_ckctl_update(struct omap_mpu_state_s
*s
,
2428 uint16_t diff
, uint16_t value
)
2432 if (diff
& (1 << 14)) { /* ARM_INTHCK_SEL */
2433 if (value
& (1 << 14))
2436 clk
= omap_findclk(s
, "arminth_ck");
2437 omap_clk_reparent(clk
, omap_findclk(s
, "tc_ck"));
2440 if (diff
& (1 << 12)) { /* ARM_TIMXO */
2441 clk
= omap_findclk(s
, "armtim_ck");
2442 if (value
& (1 << 12))
2443 omap_clk_reparent(clk
, omap_findclk(s
, "clkin"));
2445 omap_clk_reparent(clk
, omap_findclk(s
, "ck_gen1"));
2448 if (diff
& (3 << 10)) { /* DSPMMUDIV */
2449 clk
= omap_findclk(s
, "dspmmu_ck");
2450 omap_clk_setrate(clk
, 1 << ((value
>> 10) & 3), 1);
2452 if (diff
& (3 << 8)) { /* TCDIV */
2453 clk
= omap_findclk(s
, "tc_ck");
2454 omap_clk_setrate(clk
, 1 << ((value
>> 8) & 3), 1);
2456 if (diff
& (3 << 6)) { /* DSPDIV */
2457 clk
= omap_findclk(s
, "dsp_ck");
2458 omap_clk_setrate(clk
, 1 << ((value
>> 6) & 3), 1);
2460 if (diff
& (3 << 4)) { /* ARMDIV */
2461 clk
= omap_findclk(s
, "arm_ck");
2462 omap_clk_setrate(clk
, 1 << ((value
>> 4) & 3), 1);
2464 if (diff
& (3 << 2)) { /* LCDDIV */
2465 clk
= omap_findclk(s
, "lcd_ck");
2466 omap_clk_setrate(clk
, 1 << ((value
>> 2) & 3), 1);
2468 if (diff
& (3 << 0)) { /* PERDIV */
2469 clk
= omap_findclk(s
, "armper_ck");
2470 omap_clk_setrate(clk
, 1 << ((value
>> 0) & 3), 1);
2474 static inline void omap_clkm_idlect1_update(struct omap_mpu_state_s
*s
,
2475 uint16_t diff
, uint16_t value
)
2479 if (value
& (1 << 11)) /* SETARM_IDLE */
2480 cpu_interrupt(s
->env
, CPU_INTERRUPT_HALT
);
2481 if (!(value
& (1 << 10))) /* WKUP_MODE */
2482 qemu_system_shutdown_request(); /* XXX: disable wakeup from IRQ */
2484 #define SET_CANIDLE(clock, bit) \
2485 if (diff & (1 << bit)) { \
2486 clk = omap_findclk(s, clock); \
2487 omap_clk_canidle(clk, (value >> bit) & 1); \
2489 SET_CANIDLE("mpuwd_ck", 0) /* IDLWDT_ARM */
2490 SET_CANIDLE("armxor_ck", 1) /* IDLXORP_ARM */
2491 SET_CANIDLE("mpuper_ck", 2) /* IDLPER_ARM */
2492 SET_CANIDLE("lcd_ck", 3) /* IDLLCD_ARM */
2493 SET_CANIDLE("lb_ck", 4) /* IDLLB_ARM */
2494 SET_CANIDLE("hsab_ck", 5) /* IDLHSAB_ARM */
2495 SET_CANIDLE("tipb_ck", 6) /* IDLIF_ARM */
2496 SET_CANIDLE("dma_ck", 6) /* IDLIF_ARM */
2497 SET_CANIDLE("tc_ck", 6) /* IDLIF_ARM */
2498 SET_CANIDLE("dpll1", 7) /* IDLDPLL_ARM */
2499 SET_CANIDLE("dpll2", 7) /* IDLDPLL_ARM */
2500 SET_CANIDLE("dpll3", 7) /* IDLDPLL_ARM */
2501 SET_CANIDLE("mpui_ck", 8) /* IDLAPI_ARM */
2502 SET_CANIDLE("armtim_ck", 9) /* IDLTIM_ARM */
2505 static inline void omap_clkm_idlect2_update(struct omap_mpu_state_s
*s
,
2506 uint16_t diff
, uint16_t value
)
2510 #define SET_ONOFF(clock, bit) \
2511 if (diff & (1 << bit)) { \
2512 clk = omap_findclk(s, clock); \
2513 omap_clk_onoff(clk, (value >> bit) & 1); \
2515 SET_ONOFF("mpuwd_ck", 0) /* EN_WDTCK */
2516 SET_ONOFF("armxor_ck", 1) /* EN_XORPCK */
2517 SET_ONOFF("mpuper_ck", 2) /* EN_PERCK */
2518 SET_ONOFF("lcd_ck", 3) /* EN_LCDCK */
2519 SET_ONOFF("lb_ck", 4) /* EN_LBCK */
2520 SET_ONOFF("hsab_ck", 5) /* EN_HSABCK */
2521 SET_ONOFF("mpui_ck", 6) /* EN_APICK */
2522 SET_ONOFF("armtim_ck", 7) /* EN_TIMCK */
2523 SET_CANIDLE("dma_ck", 8) /* DMACK_REQ */
2524 SET_ONOFF("arm_gpio_ck", 9) /* EN_GPIOCK */
2525 SET_ONOFF("lbfree_ck", 10) /* EN_LBFREECK */
2528 static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s
*s
,
2529 uint16_t diff
, uint16_t value
)
2533 if (diff
& (3 << 4)) { /* TCLKOUT */
2534 clk
= omap_findclk(s
, "tclk_out");
2535 switch ((value
>> 4) & 3) {
2537 omap_clk_reparent(clk
, omap_findclk(s
, "ck_gen3"));
2538 omap_clk_onoff(clk
, 1);
2541 omap_clk_reparent(clk
, omap_findclk(s
, "tc_ck"));
2542 omap_clk_onoff(clk
, 1);
2545 omap_clk_onoff(clk
, 0);
2548 if (diff
& (3 << 2)) { /* DCLKOUT */
2549 clk
= omap_findclk(s
, "dclk_out");
2550 switch ((value
>> 2) & 3) {
2552 omap_clk_reparent(clk
, omap_findclk(s
, "dspmmu_ck"));
2555 omap_clk_reparent(clk
, omap_findclk(s
, "ck_gen2"));
2558 omap_clk_reparent(clk
, omap_findclk(s
, "dsp_ck"));
2561 omap_clk_reparent(clk
, omap_findclk(s
, "ck_ref14"));
2565 if (diff
& (3 << 0)) { /* ACLKOUT */
2566 clk
= omap_findclk(s
, "aclk_out");
2567 switch ((value
>> 0) & 3) {
2569 omap_clk_reparent(clk
, omap_findclk(s
, "ck_gen1"));
2570 omap_clk_onoff(clk
, 1);
2573 omap_clk_reparent(clk
, omap_findclk(s
, "arm_ck"));
2574 omap_clk_onoff(clk
, 1);
2577 omap_clk_reparent(clk
, omap_findclk(s
, "ck_ref14"));
2578 omap_clk_onoff(clk
, 1);
2581 omap_clk_onoff(clk
, 0);
2586 static void omap_clkm_write(void *opaque
, target_phys_addr_t addr
,
2589 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
2590 int offset
= addr
- s
->clkm
.mpu_base
;
2593 static const char *clkschemename
[8] = {
2594 "fully synchronous", "fully asynchronous", "synchronous scalable",
2595 "mix mode 1", "mix mode 2", "bypass mode", "mix mode 3", "mix mode 4",
2599 case 0x00: /* ARM_CKCTL */
2600 diff
= s
->clkm
.arm_ckctl
^ value
;
2601 s
->clkm
.arm_ckctl
= value
& 0x7fff;
2602 omap_clkm_ckctl_update(s
, diff
, value
);
2605 case 0x04: /* ARM_IDLECT1 */
2606 diff
= s
->clkm
.arm_idlect1
^ value
;
2607 s
->clkm
.arm_idlect1
= value
& 0x0fff;
2608 omap_clkm_idlect1_update(s
, diff
, value
);
2611 case 0x08: /* ARM_IDLECT2 */
2612 diff
= s
->clkm
.arm_idlect2
^ value
;
2613 s
->clkm
.arm_idlect2
= value
& 0x07ff;
2614 omap_clkm_idlect2_update(s
, diff
, value
);
2617 case 0x0c: /* ARM_EWUPCT */
2618 diff
= s
->clkm
.arm_ewupct
^ value
;
2619 s
->clkm
.arm_ewupct
= value
& 0x003f;
2622 case 0x10: /* ARM_RSTCT1 */
2623 diff
= s
->clkm
.arm_rstct1
^ value
;
2624 s
->clkm
.arm_rstct1
= value
& 0x0007;
2626 qemu_system_reset_request();
2627 s
->clkm
.cold_start
= 0xa;
2629 if (diff
& ~value
& 4) { /* DSP_RST */
2631 omap_tipb_bridge_reset(s
->private_tipb
);
2632 omap_tipb_bridge_reset(s
->public_tipb
);
2634 if (diff
& 2) { /* DSP_EN */
2635 clk
= omap_findclk(s
, "dsp_ck");
2636 omap_clk_canidle(clk
, (~value
>> 1) & 1);
2640 case 0x14: /* ARM_RSTCT2 */
2641 s
->clkm
.arm_rstct2
= value
& 0x0001;
2644 case 0x18: /* ARM_SYSST */
2645 if ((s
->clkm
.clocking_scheme
^ (value
>> 11)) & 7) {
2646 s
->clkm
.clocking_scheme
= (value
>> 11) & 7;
2647 printf("%s: clocking scheme set to %s\n", __FUNCTION__
,
2648 clkschemename
[s
->clkm
.clocking_scheme
]);
2650 s
->clkm
.cold_start
&= value
& 0x3f;
2653 case 0x1c: /* ARM_CKOUT1 */
2654 diff
= s
->clkm
.arm_ckout1
^ value
;
2655 s
->clkm
.arm_ckout1
= value
& 0x003f;
2656 omap_clkm_ckout1_update(s
, diff
, value
);
2659 case 0x20: /* ARM_CKOUT2 */
2665 static CPUReadMemoryFunc
*omap_clkm_readfn
[] = {
2666 omap_badwidth_read16
,
2668 omap_badwidth_read16
,
2671 static CPUWriteMemoryFunc
*omap_clkm_writefn
[] = {
2672 omap_badwidth_write16
,
2674 omap_badwidth_write16
,
2677 static uint32_t omap_clkdsp_read(void *opaque
, target_phys_addr_t addr
)
2679 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
2680 int offset
= addr
- s
->clkm
.dsp_base
;
2683 case 0x04: /* DSP_IDLECT1 */
2684 return s
->clkm
.dsp_idlect1
;
2686 case 0x08: /* DSP_IDLECT2 */
2687 return s
->clkm
.dsp_idlect2
;
2689 case 0x14: /* DSP_RSTCT2 */
2690 return s
->clkm
.dsp_rstct2
;
2692 case 0x18: /* DSP_SYSST */
2693 return (s
->clkm
.clocking_scheme
< 11) | s
->clkm
.cold_start
|
2694 (s
->env
->halted
<< 6); /* Quite useless... */
2701 static inline void omap_clkdsp_idlect1_update(struct omap_mpu_state_s
*s
,
2702 uint16_t diff
, uint16_t value
)
2706 SET_CANIDLE("dspxor_ck", 1); /* IDLXORP_DSP */
2709 static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s
*s
,
2710 uint16_t diff
, uint16_t value
)
2714 SET_ONOFF("dspxor_ck", 1); /* EN_XORPCK */
2717 static void omap_clkdsp_write(void *opaque
, target_phys_addr_t addr
,
2720 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
2721 int offset
= addr
- s
->clkm
.dsp_base
;
2725 case 0x04: /* DSP_IDLECT1 */
2726 diff
= s
->clkm
.dsp_idlect1
^ value
;
2727 s
->clkm
.dsp_idlect1
= value
& 0x01f7;
2728 omap_clkdsp_idlect1_update(s
, diff
, value
);
2731 case 0x08: /* DSP_IDLECT2 */
2732 s
->clkm
.dsp_idlect2
= value
& 0x0037;
2733 diff
= s
->clkm
.dsp_idlect1
^ value
;
2734 omap_clkdsp_idlect2_update(s
, diff
, value
);
2737 case 0x14: /* DSP_RSTCT2 */
2738 s
->clkm
.dsp_rstct2
= value
& 0x0001;
2741 case 0x18: /* DSP_SYSST */
2742 s
->clkm
.cold_start
&= value
& 0x3f;
2750 static CPUReadMemoryFunc
*omap_clkdsp_readfn
[] = {
2751 omap_badwidth_read16
,
2753 omap_badwidth_read16
,
2756 static CPUWriteMemoryFunc
*omap_clkdsp_writefn
[] = {
2757 omap_badwidth_write16
,
2759 omap_badwidth_write16
,
2762 static void omap_clkm_reset(struct omap_mpu_state_s
*s
)
2764 if (s
->wdt
&& s
->wdt
->reset
)
2765 s
->clkm
.cold_start
= 0x6;
2766 s
->clkm
.clocking_scheme
= 0;
2767 omap_clkm_ckctl_update(s
, ~0, 0x3000);
2768 s
->clkm
.arm_ckctl
= 0x3000;
2769 omap_clkm_idlect1_update(s
, s
->clkm
.arm_idlect1
& 0x0400, 0x0400);
2770 s
->clkm
.arm_idlect1
= 0x0400;
2771 omap_clkm_idlect2_update(s
, s
->clkm
.arm_idlect2
& 0x0100, 0x0100);
2772 s
->clkm
.arm_idlect2
= 0x0100;
2773 s
->clkm
.arm_ewupct
= 0x003f;
2774 s
->clkm
.arm_rstct1
= 0x0000;
2775 s
->clkm
.arm_rstct2
= 0x0000;
2776 s
->clkm
.arm_ckout1
= 0x0015;
2777 s
->clkm
.dpll1_mode
= 0x2002;
2778 omap_clkdsp_idlect1_update(s
, s
->clkm
.dsp_idlect1
^ 0x0040, 0x0040);
2779 s
->clkm
.dsp_idlect1
= 0x0040;
2780 omap_clkdsp_idlect2_update(s
, ~0, 0x0000);
2781 s
->clkm
.dsp_idlect2
= 0x0000;
2782 s
->clkm
.dsp_rstct2
= 0x0000;
2785 static void omap_clkm_init(target_phys_addr_t mpu_base
,
2786 target_phys_addr_t dsp_base
, struct omap_mpu_state_s
*s
)
2788 int iomemtype
[2] = {
2789 cpu_register_io_memory(0, omap_clkm_readfn
, omap_clkm_writefn
, s
),
2790 cpu_register_io_memory(0, omap_clkdsp_readfn
, omap_clkdsp_writefn
, s
),
2793 s
->clkm
.mpu_base
= mpu_base
;
2794 s
->clkm
.dsp_base
= dsp_base
;
2795 s
->clkm
.cold_start
= 0x3a;
2798 cpu_register_physical_memory(s
->clkm
.mpu_base
, 0x100, iomemtype
[0]);
2799 cpu_register_physical_memory(s
->clkm
.dsp_base
, 0x1000, iomemtype
[1]);
2803 struct omap_mpuio_s
{
2804 target_phys_addr_t base
;
2808 qemu_irq handler
[16];
2829 static void omap_mpuio_set(void *opaque
, int line
, int level
)
2831 struct omap_mpuio_s
*s
= (struct omap_mpuio_s
*) opaque
;
2832 uint16_t prev
= s
->inputs
;
2835 s
->inputs
|= 1 << line
;
2837 s
->inputs
&= ~(1 << line
);
2839 if (((1 << line
) & s
->dir
& ~s
->mask
) && s
->clk
) {
2840 if ((s
->edge
& s
->inputs
& ~prev
) | (~s
->edge
& ~s
->inputs
& prev
)) {
2841 s
->ints
|= 1 << line
;
2842 qemu_irq_raise(s
->irq
);
2845 if ((s
->event
& (1 << 0)) && /* SET_GPIO_EVENT_MODE */
2846 (s
->event
>> 1) == line
) /* PIN_SELECT */
2847 s
->latch
= s
->inputs
;
2851 static void omap_mpuio_kbd_update(struct omap_mpuio_s
*s
)
2854 uint8_t *row
, rows
= 0, cols
= ~s
->cols
;
2856 for (row
= s
->buttons
+ 4, i
= 1 << 4; i
; row
--, i
>>= 1)
2860 qemu_set_irq(s
->kbd_irq
, rows
&& ~s
->kbd_mask
&& s
->clk
);
2861 s
->row_latch
= rows
^ 0x1f;
2864 static uint32_t omap_mpuio_read(void *opaque
, target_phys_addr_t addr
)
2866 struct omap_mpuio_s
*s
= (struct omap_mpuio_s
*) opaque
;
2867 int offset
= addr
- s
->base
;
2871 case 0x00: /* INPUT_LATCH */
2874 case 0x04: /* OUTPUT_REG */
2877 case 0x08: /* IO_CNTL */
2880 case 0x10: /* KBR_LATCH */
2881 return s
->row_latch
;
2883 case 0x14: /* KBC_REG */
2886 case 0x18: /* GPIO_EVENT_MODE_REG */
2889 case 0x1c: /* GPIO_INT_EDGE_REG */
2892 case 0x20: /* KBD_INT */
2893 return (s
->row_latch
!= 0x1f) && !s
->kbd_mask
;
2895 case 0x24: /* GPIO_INT */
2899 qemu_irq_lower(s
->irq
);
2902 case 0x28: /* KBD_MASKIT */
2905 case 0x2c: /* GPIO_MASKIT */
2908 case 0x30: /* GPIO_DEBOUNCING_REG */
2911 case 0x34: /* GPIO_LATCH_REG */
2919 static void omap_mpuio_write(void *opaque
, target_phys_addr_t addr
,
2922 struct omap_mpuio_s
*s
= (struct omap_mpuio_s
*) opaque
;
2923 int offset
= addr
- s
->base
;
2928 case 0x04: /* OUTPUT_REG */
2929 diff
= s
->outputs
^ (value
& ~s
->dir
);
2932 while ((ln
= ffs(diff
))) {
2935 qemu_set_irq(s
->handler
[ln
], (value
>> ln
) & 1);
2940 case 0x08: /* IO_CNTL */
2941 diff
= s
->outputs
& (s
->dir
^ value
);
2944 value
= s
->outputs
& ~s
->dir
;
2945 while ((ln
= ffs(diff
))) {
2948 qemu_set_irq(s
->handler
[ln
], (value
>> ln
) & 1);
2953 case 0x14: /* KBC_REG */
2955 omap_mpuio_kbd_update(s
);
2958 case 0x18: /* GPIO_EVENT_MODE_REG */
2959 s
->event
= value
& 0x1f;
2962 case 0x1c: /* GPIO_INT_EDGE_REG */
2966 case 0x28: /* KBD_MASKIT */
2967 s
->kbd_mask
= value
& 1;
2968 omap_mpuio_kbd_update(s
);
2971 case 0x2c: /* GPIO_MASKIT */
2975 case 0x30: /* GPIO_DEBOUNCING_REG */
2976 s
->debounce
= value
& 0x1ff;
2979 case 0x00: /* INPUT_LATCH */
2980 case 0x10: /* KBR_LATCH */
2981 case 0x20: /* KBD_INT */
2982 case 0x24: /* GPIO_INT */
2983 case 0x34: /* GPIO_LATCH_REG */
2993 static CPUReadMemoryFunc
*omap_mpuio_readfn
[] = {
2994 omap_badwidth_read16
,
2996 omap_badwidth_read16
,
2999 static CPUWriteMemoryFunc
*omap_mpuio_writefn
[] = {
3000 omap_badwidth_write16
,
3002 omap_badwidth_write16
,
3005 void omap_mpuio_reset(struct omap_mpuio_s
*s
)
3017 s
->row_latch
= 0x1f;
3021 static void omap_mpuio_onoff(void *opaque
, int line
, int on
)
3023 struct omap_mpuio_s
*s
= (struct omap_mpuio_s
*) opaque
;
3027 omap_mpuio_kbd_update(s
);
3030 struct omap_mpuio_s
*omap_mpuio_init(target_phys_addr_t base
,
3031 qemu_irq kbd_int
, qemu_irq gpio_int
, qemu_irq wakeup
,
3035 struct omap_mpuio_s
*s
= (struct omap_mpuio_s
*)
3036 qemu_mallocz(sizeof(struct omap_mpuio_s
));
3040 s
->kbd_irq
= kbd_int
;
3042 s
->in
= qemu_allocate_irqs(omap_mpuio_set
, s
, 16);
3043 omap_mpuio_reset(s
);
3045 iomemtype
= cpu_register_io_memory(0, omap_mpuio_readfn
,
3046 omap_mpuio_writefn
, s
);
3047 cpu_register_physical_memory(s
->base
, 0x800, iomemtype
);
3049 omap_clk_adduser(clk
, qemu_allocate_irqs(omap_mpuio_onoff
, s
, 1)[0]);
3054 qemu_irq
*omap_mpuio_in_get(struct omap_mpuio_s
*s
)
3059 void omap_mpuio_out_set(struct omap_mpuio_s
*s
, int line
, qemu_irq handler
)
3061 if (line
>= 16 || line
< 0)
3062 cpu_abort(cpu_single_env
, "%s: No GPIO line %i\n", __FUNCTION__
, line
);
3063 s
->handler
[line
] = handler
;
3066 void omap_mpuio_key(struct omap_mpuio_s
*s
, int row
, int col
, int down
)
3068 if (row
>= 5 || row
< 0)
3069 cpu_abort(cpu_single_env
, "%s: No key %i-%i\n",
3070 __FUNCTION__
, col
, row
);
3073 s
->buttons
[row
] |= 1 << col
;
3075 s
->buttons
[row
] &= ~(1 << col
);
3077 omap_mpuio_kbd_update(s
);
3080 /* General-Purpose I/O */
3081 struct omap_gpio_s
{
3082 target_phys_addr_t base
;
3085 qemu_irq handler
[16];
3095 static void omap_gpio_set(void *opaque
, int line
, int level
)
3097 struct omap_gpio_s
*s
= (struct omap_gpio_s
*) opaque
;
3098 uint16_t prev
= s
->inputs
;
3101 s
->inputs
|= 1 << line
;
3103 s
->inputs
&= ~(1 << line
);
3105 if (((s
->edge
& s
->inputs
& ~prev
) | (~s
->edge
& ~s
->inputs
& prev
)) &
3106 (1 << line
) & s
->dir
& ~s
->mask
) {
3107 s
->ints
|= 1 << line
;
3108 qemu_irq_raise(s
->irq
);
3112 static uint32_t omap_gpio_read(void *opaque
, target_phys_addr_t addr
)
3114 struct omap_gpio_s
*s
= (struct omap_gpio_s
*) opaque
;
3115 int offset
= addr
- s
->base
;
3118 case 0x00: /* DATA_INPUT */
3121 case 0x04: /* DATA_OUTPUT */
3124 case 0x08: /* DIRECTION_CONTROL */
3127 case 0x0c: /* INTERRUPT_CONTROL */
3130 case 0x10: /* INTERRUPT_MASK */
3133 case 0x14: /* INTERRUPT_STATUS */
3141 static void omap_gpio_write(void *opaque
, target_phys_addr_t addr
,
3144 struct omap_gpio_s
*s
= (struct omap_gpio_s
*) opaque
;
3145 int offset
= addr
- s
->base
;
3150 case 0x00: /* DATA_INPUT */
3154 case 0x04: /* DATA_OUTPUT */
3155 diff
= (s
->outputs
^ value
) & ~s
->dir
;
3157 while ((ln
= ffs(diff
))) {
3160 qemu_set_irq(s
->handler
[ln
], (value
>> ln
) & 1);
3165 case 0x08: /* DIRECTION_CONTROL */
3166 diff
= s
->outputs
& (s
->dir
^ value
);
3169 value
= s
->outputs
& ~s
->dir
;
3170 while ((ln
= ffs(diff
))) {
3173 qemu_set_irq(s
->handler
[ln
], (value
>> ln
) & 1);
3178 case 0x0c: /* INTERRUPT_CONTROL */
3182 case 0x10: /* INTERRUPT_MASK */
3186 case 0x14: /* INTERRUPT_STATUS */
3189 qemu_irq_lower(s
->irq
);
3198 /* *Some* sources say the memory region is 32-bit. */
3199 static CPUReadMemoryFunc
*omap_gpio_readfn
[] = {
3200 omap_badwidth_read16
,
3202 omap_badwidth_read16
,
3205 static CPUWriteMemoryFunc
*omap_gpio_writefn
[] = {
3206 omap_badwidth_write16
,
3208 omap_badwidth_write16
,
3211 void omap_gpio_reset(struct omap_gpio_s
*s
)
3221 struct omap_gpio_s
*omap_gpio_init(target_phys_addr_t base
,
3222 qemu_irq irq
, omap_clk clk
)
3225 struct omap_gpio_s
*s
= (struct omap_gpio_s
*)
3226 qemu_mallocz(sizeof(struct omap_gpio_s
));
3230 s
->in
= qemu_allocate_irqs(omap_gpio_set
, s
, 16);
3233 iomemtype
= cpu_register_io_memory(0, omap_gpio_readfn
,
3234 omap_gpio_writefn
, s
);
3235 cpu_register_physical_memory(s
->base
, 0x1000, iomemtype
);
3240 qemu_irq
*omap_gpio_in_get(struct omap_gpio_s
*s
)
3245 void omap_gpio_out_set(struct omap_gpio_s
*s
, int line
, qemu_irq handler
)
3247 if (line
>= 16 || line
< 0)
3248 cpu_abort(cpu_single_env
, "%s: No GPIO line %i\n", __FUNCTION__
, line
);
3249 s
->handler
[line
] = handler
;
3252 /* MicroWire Interface */
3253 struct omap_uwire_s
{
3254 target_phys_addr_t base
;
3264 struct uwire_slave_s
*chip
[4];
3267 static void omap_uwire_transfer_start(struct omap_uwire_s
*s
)
3269 int chipselect
= (s
->control
>> 10) & 3; /* INDEX */
3270 struct uwire_slave_s
*slave
= s
->chip
[chipselect
];
3272 if ((s
->control
>> 5) & 0x1f) { /* NB_BITS_WR */
3273 if (s
->control
& (1 << 12)) /* CS_CMD */
3274 if (slave
&& slave
->send
)
3275 slave
->send(slave
->opaque
,
3276 s
->txbuf
>> (16 - ((s
->control
>> 5) & 0x1f)));
3277 s
->control
&= ~(1 << 14); /* CSRB */
3278 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
3279 * a DRQ. When is the level IRQ supposed to be reset? */
3282 if ((s
->control
>> 0) & 0x1f) { /* NB_BITS_RD */
3283 if (s
->control
& (1 << 12)) /* CS_CMD */
3284 if (slave
&& slave
->receive
)
3285 s
->rxbuf
= slave
->receive(slave
->opaque
);
3286 s
->control
|= 1 << 15; /* RDRB */
3287 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
3288 * a DRQ. When is the level IRQ supposed to be reset? */
3292 static uint32_t omap_uwire_read(void *opaque
, target_phys_addr_t addr
)
3294 struct omap_uwire_s
*s
= (struct omap_uwire_s
*) opaque
;
3295 int offset
= addr
- s
->base
;
3298 case 0x00: /* RDR */
3299 s
->control
&= ~(1 << 15); /* RDRB */
3302 case 0x04: /* CSR */
3305 case 0x08: /* SR1 */
3307 case 0x0c: /* SR2 */
3309 case 0x10: /* SR3 */
3311 case 0x14: /* SR4 */
3313 case 0x18: /* SR5 */
3321 static void omap_uwire_write(void *opaque
, target_phys_addr_t addr
,
3324 struct omap_uwire_s
*s
= (struct omap_uwire_s
*) opaque
;
3325 int offset
= addr
- s
->base
;
3328 case 0x00: /* TDR */
3329 s
->txbuf
= value
; /* TD */
3330 s
->control
|= 1 << 14; /* CSRB */
3331 if ((s
->setup
[4] & (1 << 2)) && /* AUTO_TX_EN */
3332 ((s
->setup
[4] & (1 << 3)) || /* CS_TOGGLE_TX_EN */
3333 (s
->control
& (1 << 12)))) /* CS_CMD */
3334 omap_uwire_transfer_start(s
);
3337 case 0x04: /* CSR */
3338 s
->control
= value
& 0x1fff;
3339 if (value
& (1 << 13)) /* START */
3340 omap_uwire_transfer_start(s
);
3343 case 0x08: /* SR1 */
3344 s
->setup
[0] = value
& 0x003f;
3347 case 0x0c: /* SR2 */
3348 s
->setup
[1] = value
& 0x0fc0;
3351 case 0x10: /* SR3 */
3352 s
->setup
[2] = value
& 0x0003;
3355 case 0x14: /* SR4 */
3356 s
->setup
[3] = value
& 0x0001;
3359 case 0x18: /* SR5 */
3360 s
->setup
[4] = value
& 0x000f;
3369 static CPUReadMemoryFunc
*omap_uwire_readfn
[] = {
3370 omap_badwidth_read16
,
3372 omap_badwidth_read16
,
3375 static CPUWriteMemoryFunc
*omap_uwire_writefn
[] = {
3376 omap_badwidth_write16
,
3378 omap_badwidth_write16
,
3381 void omap_uwire_reset(struct omap_uwire_s
*s
)
3391 struct omap_uwire_s
*omap_uwire_init(target_phys_addr_t base
,
3392 qemu_irq
*irq
, qemu_irq dma
, omap_clk clk
)
3395 struct omap_uwire_s
*s
= (struct omap_uwire_s
*)
3396 qemu_mallocz(sizeof(struct omap_uwire_s
));
3402 omap_uwire_reset(s
);
3404 iomemtype
= cpu_register_io_memory(0, omap_uwire_readfn
,
3405 omap_uwire_writefn
, s
);
3406 cpu_register_physical_memory(s
->base
, 0x800, iomemtype
);
3411 void omap_uwire_attach(struct omap_uwire_s
*s
,
3412 struct uwire_slave_s
*slave
, int chipselect
)
3414 if (chipselect
< 0 || chipselect
> 3)
3415 cpu_abort(cpu_single_env
, "%s: Bad chipselect %i\n", __FUNCTION__
,
3418 s
->chip
[chipselect
] = slave
;
3421 /* Pseudonoise Pulse-Width Light Modulator */
3422 void omap_pwl_update(struct omap_mpu_state_s
*s
)
3424 int output
= (s
->pwl
.clk
&& s
->pwl
.enable
) ? s
->pwl
.level
: 0;
3426 if (output
!= s
->pwl
.output
) {
3427 s
->pwl
.output
= output
;
3428 printf("%s: Backlight now at %i/256\n", __FUNCTION__
, output
);
3432 static uint32_t omap_pwl_read(void *opaque
, target_phys_addr_t addr
)
3434 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
3435 int offset
= addr
- s
->pwl
.base
;
3438 case 0x00: /* PWL_LEVEL */
3439 return s
->pwl
.level
;
3440 case 0x04: /* PWL_CTRL */
3441 return s
->pwl
.enable
;
3447 static void omap_pwl_write(void *opaque
, target_phys_addr_t addr
,
3450 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
3451 int offset
= addr
- s
->pwl
.base
;
3454 case 0x00: /* PWL_LEVEL */
3455 s
->pwl
.level
= value
;
3458 case 0x04: /* PWL_CTRL */
3459 s
->pwl
.enable
= value
& 1;
3468 static CPUReadMemoryFunc
*omap_pwl_readfn
[] = {
3469 omap_badwidth_read8
,
3470 omap_badwidth_read8
,
3474 static CPUWriteMemoryFunc
*omap_pwl_writefn
[] = {
3475 omap_badwidth_write8
,
3476 omap_badwidth_write8
,
3480 void omap_pwl_reset(struct omap_mpu_state_s
*s
)
3489 static void omap_pwl_clk_update(void *opaque
, int line
, int on
)
3491 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
3497 static void omap_pwl_init(target_phys_addr_t base
, struct omap_mpu_state_s
*s
,
3505 iomemtype
= cpu_register_io_memory(0, omap_pwl_readfn
,
3506 omap_pwl_writefn
, s
);
3507 cpu_register_physical_memory(s
->pwl
.base
, 0x800, iomemtype
);
3509 omap_clk_adduser(clk
, qemu_allocate_irqs(omap_pwl_clk_update
, s
, 1)[0]);
3512 /* Pulse-Width Tone module */
3513 static uint32_t omap_pwt_read(void *opaque
, target_phys_addr_t addr
)
3515 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
3516 int offset
= addr
- s
->pwt
.base
;
3519 case 0x00: /* FRC */
3521 case 0x04: /* VCR */
3523 case 0x08: /* GCR */
3530 static void omap_pwt_write(void *opaque
, target_phys_addr_t addr
,
3533 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
3534 int offset
= addr
- s
->pwt
.base
;
3537 case 0x00: /* FRC */
3538 s
->pwt
.frc
= value
& 0x3f;
3540 case 0x04: /* VRC */
3541 if ((value
^ s
->pwt
.vrc
) & 1) {
3543 printf("%s: %iHz buzz on\n", __FUNCTION__
, (int)
3544 /* 1.5 MHz from a 12-MHz or 13-MHz PWT_CLK */
3545 ((omap_clk_getrate(s
->pwt
.clk
) >> 3) /
3546 /* Pre-multiplexer divider */
3547 ((s
->pwt
.gcr
& 2) ? 1 : 154) /
3548 /* Octave multiplexer */
3549 (2 << (value
& 3)) *
3550 /* 101/107 divider */
3551 ((value
& (1 << 2)) ? 101 : 107) *
3553 ((value
& (1 << 3)) ? 49 : 55) *
3555 ((value
& (1 << 4)) ? 50 : 63) *
3556 /* 80/127 divider */
3557 ((value
& (1 << 5)) ? 80 : 127) /
3558 (107 * 55 * 63 * 127)));
3560 printf("%s: silence!\n", __FUNCTION__
);
3562 s
->pwt
.vrc
= value
& 0x7f;
3564 case 0x08: /* GCR */
3565 s
->pwt
.gcr
= value
& 3;
3573 static CPUReadMemoryFunc
*omap_pwt_readfn
[] = {
3574 omap_badwidth_read8
,
3575 omap_badwidth_read8
,
3579 static CPUWriteMemoryFunc
*omap_pwt_writefn
[] = {
3580 omap_badwidth_write8
,
3581 omap_badwidth_write8
,
3585 void omap_pwt_reset(struct omap_mpu_state_s
*s
)
3592 static void omap_pwt_init(target_phys_addr_t base
, struct omap_mpu_state_s
*s
,
3601 iomemtype
= cpu_register_io_memory(0, omap_pwt_readfn
,
3602 omap_pwt_writefn
, s
);
3603 cpu_register_physical_memory(s
->pwt
.base
, 0x800, iomemtype
);
3606 /* Inter-Integrated Circuit Controller (only the "New I2C") */
3608 target_phys_addr_t base
;
3629 static void omap_i2c_interrupts_update(struct omap_i2c_s
*s
)
3631 qemu_set_irq(s
->irq
, s
->stat
& s
->mask
);
3632 if ((s
->dma
>> 15) & 1) /* RDMA_EN */
3633 qemu_set_irq(s
->drq
[0], (s
->stat
>> 3) & 1); /* RRDY */
3634 if ((s
->dma
>> 7) & 1) /* XDMA_EN */
3635 qemu_set_irq(s
->drq
[1], (s
->stat
>> 4) & 1); /* XRDY */
3638 /* These are only stubs now. */
3639 static void omap_i2c_event(i2c_slave
*i2c
, enum i2c_event event
)
3641 struct omap_i2c_s
*s
= (struct omap_i2c_s
*) i2c
;
3643 if ((~s
->control
>> 15) & 1) /* I2C_EN */
3647 case I2C_START_SEND
:
3648 case I2C_START_RECV
:
3649 s
->stat
|= 1 << 9; /* AAS */
3652 s
->stat
|= 1 << 2; /* ARDY */
3655 s
->stat
|= 1 << 1; /* NACK */
3659 omap_i2c_interrupts_update(s
);
3662 static int omap_i2c_rx(i2c_slave
*i2c
)
3664 struct omap_i2c_s
*s
= (struct omap_i2c_s
*) i2c
;
3667 if ((~s
->control
>> 15) & 1) /* I2C_EN */
3671 ret
= s
->fifo
>> ((-- s
->txlen
) << 3) & 0xff;
3673 s
->stat
|= 1 << 10; /* XUDF */
3674 s
->stat
|= 1 << 4; /* XRDY */
3676 omap_i2c_interrupts_update(s
);
3680 static int omap_i2c_tx(i2c_slave
*i2c
, uint8_t data
)
3682 struct omap_i2c_s
*s
= (struct omap_i2c_s
*) i2c
;
3684 if ((~s
->control
>> 15) & 1) /* I2C_EN */
3688 s
->fifo
|= data
<< ((s
->rxlen
++) << 3);
3690 s
->stat
|= 1 << 11; /* ROVR */
3691 s
->stat
|= 1 << 3; /* RRDY */
3693 omap_i2c_interrupts_update(s
);
3697 static void omap_i2c_fifo_run(struct omap_i2c_s
*s
)
3701 if (!i2c_bus_busy(s
->bus
))
3704 if ((s
->control
>> 2) & 1) { /* RM */
3705 if ((s
->control
>> 1) & 1) { /* STP */
3706 i2c_end_transfer(s
->bus
);
3707 s
->control
&= ~(1 << 1); /* STP */
3708 s
->count_cur
= s
->count
;
3709 } else if ((s
->control
>> 9) & 1) { /* TRX */
3710 while (ack
&& s
->txlen
)
3711 ack
= (i2c_send(s
->bus
,
3712 (s
->fifo
>> ((-- s
->txlen
) << 3)) &
3714 s
->stat
|= 1 << 4; /* XRDY */
3716 while (s
->rxlen
< 4)
3717 s
->fifo
|= i2c_recv(s
->bus
) << ((s
->rxlen
++) << 3);
3718 s
->stat
|= 1 << 3; /* RRDY */
3721 if ((s
->control
>> 9) & 1) { /* TRX */
3722 while (ack
&& s
->count_cur
&& s
->txlen
) {
3723 ack
= (i2c_send(s
->bus
,
3724 (s
->fifo
>> ((-- s
->txlen
) << 3)) &
3728 if (ack
&& s
->count_cur
)
3729 s
->stat
|= 1 << 4; /* XRDY */
3730 if (!s
->count_cur
) {
3731 s
->stat
|= 1 << 2; /* ARDY */
3732 s
->control
&= ~(1 << 10); /* MST */
3735 while (s
->count_cur
&& s
->rxlen
< 4) {
3736 s
->fifo
|= i2c_recv(s
->bus
) << ((s
->rxlen
++) << 3);
3740 s
->stat
|= 1 << 3; /* RRDY */
3742 if (!s
->count_cur
) {
3743 if ((s
->control
>> 1) & 1) { /* STP */
3744 i2c_end_transfer(s
->bus
);
3745 s
->control
&= ~(1 << 1); /* STP */
3746 s
->count_cur
= s
->count
;
3748 s
->stat
|= 1 << 2; /* ARDY */
3749 s
->control
&= ~(1 << 10); /* MST */
3754 s
->stat
|= (!ack
) << 1; /* NACK */
3756 s
->control
&= ~(1 << 1); /* STP */
3759 static void omap_i2c_reset(struct omap_i2c_s
*s
)
3778 static uint32_t omap_i2c_read(void *opaque
, target_phys_addr_t addr
)
3780 struct omap_i2c_s
*s
= (struct omap_i2c_s
*) opaque
;
3781 int offset
= addr
- s
->base
;
3785 case 0x00: /* I2C_REV */
3786 /* TODO: set a value greater or equal to real hardware */
3787 return 0x11; /* REV */
3789 case 0x04: /* I2C_IE */
3792 case 0x08: /* I2C_STAT */
3793 return s
->stat
| (i2c_bus_busy(s
->bus
) << 12);
3795 case 0x0c: /* I2C_IV */
3796 ret
= ffs(s
->stat
& s
->mask
);
3798 s
->stat
^= 1 << (ret
- 1);
3799 omap_i2c_interrupts_update(s
);
3802 case 0x14: /* I2C_BUF */
3805 case 0x18: /* I2C_CNT */
3806 return s
->count_cur
; /* DCOUNT */
3808 case 0x1c: /* I2C_DATA */
3810 if (s
->control
& (1 << 14)) { /* BE */
3811 ret
|= ((s
->fifo
>> 0) & 0xff) << 8;
3812 ret
|= ((s
->fifo
>> 8) & 0xff) << 0;
3814 ret
|= ((s
->fifo
>> 8) & 0xff) << 8;
3815 ret
|= ((s
->fifo
>> 0) & 0xff) << 0;
3817 if (s
->rxlen
== 1) {
3818 s
->stat
|= 1 << 15; /* SBD */
3820 } else if (s
->rxlen
> 1) {
3825 /* XXX: remote access (qualifier) error - what's that? */;
3827 s
->stat
|= ~(1 << 3); /* RRDY */
3828 if (((s
->control
>> 10) & 1) && /* MST */
3829 ((~s
->control
>> 9) & 1)) { /* TRX */
3830 s
->stat
|= 1 << 2; /* ARDY */
3831 s
->control
&= ~(1 << 10); /* MST */
3834 s
->stat
&= ~(1 << 11); /* ROVR */
3835 omap_i2c_fifo_run(s
);
3836 omap_i2c_interrupts_update(s
);
3839 case 0x24: /* I2C_CON */
3842 case 0x28: /* I2C_OA */
3845 case 0x2c: /* I2C_SA */
3848 case 0x30: /* I2C_PSC */
3851 case 0x34: /* I2C_SCLL */
3854 case 0x38: /* I2C_SCLH */
3857 case 0x3c: /* I2C_SYSTEST */
3858 if (s
->test
& (1 << 15)) { /* ST_EN */
3862 return s
->test
& ~0x300f;
3869 static void omap_i2c_write(void *opaque
, target_phys_addr_t addr
,
3872 struct omap_i2c_s
*s
= (struct omap_i2c_s
*) opaque
;
3873 int offset
= addr
- s
->base
;
3877 case 0x00: /* I2C_REV */
3878 case 0x08: /* I2C_STAT */
3879 case 0x0c: /* I2C_IV */
3883 case 0x04: /* I2C_IE */
3884 s
->mask
= value
& 0x1f;
3887 case 0x14: /* I2C_BUF */
3888 s
->dma
= value
& 0x8080;
3889 if (value
& (1 << 15)) /* RDMA_EN */
3890 s
->mask
&= ~(1 << 3); /* RRDY_IE */
3891 if (value
& (1 << 7)) /* XDMA_EN */
3892 s
->mask
&= ~(1 << 4); /* XRDY_IE */
3895 case 0x18: /* I2C_CNT */
3896 s
->count
= value
; /* DCOUNT */
3899 case 0x1c: /* I2C_DATA */
3901 /* XXX: remote access (qualifier) error - what's that? */
3906 if (s
->control
& (1 << 14)) { /* BE */
3907 s
->fifo
|= ((value
>> 8) & 0xff) << 8;
3908 s
->fifo
|= ((value
>> 0) & 0xff) << 0;
3910 s
->fifo
|= ((value
>> 0) & 0xff) << 8;
3911 s
->fifo
|= ((value
>> 8) & 0xff) << 0;
3913 s
->stat
&= ~(1 << 10); /* XUDF */
3915 s
->stat
&= ~(1 << 4); /* XRDY */
3916 omap_i2c_fifo_run(s
);
3917 omap_i2c_interrupts_update(s
);
3920 case 0x24: /* I2C_CON */
3921 s
->control
= value
& 0xcf07;
3922 if (~value
& (1 << 15)) { /* I2C_EN */
3926 if (~value
& (1 << 10)) { /* MST */
3927 printf("%s: I^2C slave mode not supported\n", __FUNCTION__
);
3930 if (value
& (1 << 9)) { /* XA */
3931 printf("%s: 10-bit addressing mode not supported\n", __FUNCTION__
);
3934 if (value
& (1 << 0)) { /* STT */
3935 nack
= !!i2c_start_transfer(s
->bus
, s
->addr
[1], /* SA */
3936 (~value
>> 9) & 1); /* TRX */
3937 s
->stat
|= nack
<< 1; /* NACK */
3938 s
->control
&= ~(1 << 0); /* STT */
3940 s
->control
&= ~(1 << 1); /* STP */
3942 omap_i2c_fifo_run(s
);
3943 omap_i2c_interrupts_update(s
);
3947 case 0x28: /* I2C_OA */
3948 s
->addr
[0] = value
& 0x3ff;
3949 i2c_set_slave_address(&s
->slave
, value
& 0x7f);
3952 case 0x2c: /* I2C_SA */
3953 s
->addr
[1] = value
& 0x3ff;
3956 case 0x30: /* I2C_PSC */
3960 case 0x34: /* I2C_SCLL */
3961 s
->times
[0] = value
;
3964 case 0x38: /* I2C_SCLH */
3965 s
->times
[1] = value
;
3968 case 0x3c: /* I2C_SYSTEST */
3969 s
->test
= value
& 0xf00f;
3970 if (value
& (1 << 15)) /* ST_EN */
3971 printf("%s: System Test not supported\n", __FUNCTION__
);
3980 static CPUReadMemoryFunc
*omap_i2c_readfn
[] = {
3981 omap_badwidth_read16
,
3983 omap_badwidth_read16
,
3986 static CPUWriteMemoryFunc
*omap_i2c_writefn
[] = {
3987 omap_badwidth_write16
,
3989 omap_i2c_write
, /* TODO: Only the last fifo write can be 8 bit. */
3992 struct omap_i2c_s
*omap_i2c_init(target_phys_addr_t base
,
3993 qemu_irq irq
, qemu_irq
*dma
, omap_clk clk
)
3996 struct omap_i2c_s
*s
= (struct omap_i2c_s
*)
3997 qemu_mallocz(sizeof(struct omap_i2c_s
));
4003 s
->slave
.event
= omap_i2c_event
;
4004 s
->slave
.recv
= omap_i2c_rx
;
4005 s
->slave
.send
= omap_i2c_tx
;
4006 s
->bus
= i2c_init_bus();
4009 iomemtype
= cpu_register_io_memory(0, omap_i2c_readfn
,
4010 omap_i2c_writefn
, s
);
4011 cpu_register_physical_memory(s
->base
, 0x800, iomemtype
);
4016 i2c_bus
*omap_i2c_bus(struct omap_i2c_s
*s
)
4021 /* General chip reset */
4022 static void omap_mpu_reset(void *opaque
)
4024 struct omap_mpu_state_s
*mpu
= (struct omap_mpu_state_s
*) opaque
;
4026 omap_clkm_reset(mpu
);
4027 omap_inth_reset(mpu
->ih
[0]);
4028 omap_inth_reset(mpu
->ih
[1]);
4029 omap_dma_reset(mpu
->dma
);
4030 omap_mpu_timer_reset(mpu
->timer
[0]);
4031 omap_mpu_timer_reset(mpu
->timer
[1]);
4032 omap_mpu_timer_reset(mpu
->timer
[2]);
4033 omap_wd_timer_reset(mpu
->wdt
);
4034 omap_os_timer_reset(mpu
->os_timer
);
4035 omap_lcdc_reset(mpu
->lcd
);
4036 omap_ulpd_pm_reset(mpu
);
4037 omap_pin_cfg_reset(mpu
);
4038 omap_mpui_reset(mpu
);
4039 omap_tipb_bridge_reset(mpu
->private_tipb
);
4040 omap_tipb_bridge_reset(mpu
->public_tipb
);
4041 omap_dpll_reset(&mpu
->dpll
[0]);
4042 omap_dpll_reset(&mpu
->dpll
[1]);
4043 omap_dpll_reset(&mpu
->dpll
[2]);
4044 omap_uart_reset(mpu
->uart
[0]);
4045 omap_uart_reset(mpu
->uart
[1]);
4046 omap_uart_reset(mpu
->uart
[2]);
4047 omap_mmc_reset(mpu
->mmc
);
4048 omap_mpuio_reset(mpu
->mpuio
);
4049 omap_gpio_reset(mpu
->gpio
);
4050 omap_uwire_reset(mpu
->microwire
);
4051 omap_pwl_reset(mpu
);
4052 omap_pwt_reset(mpu
);
4053 omap_i2c_reset(mpu
->i2c
);
4054 cpu_reset(mpu
->env
);
4057 static void omap_mpu_wakeup(void *opaque
, int irq
, int req
)
4059 struct omap_mpu_state_s
*mpu
= (struct omap_mpu_state_s
*) opaque
;
4061 if (mpu
->env
->halted
)
4062 cpu_interrupt(mpu
->env
, CPU_INTERRUPT_EXITTB
);
4065 struct omap_mpu_state_s
*omap310_mpu_init(unsigned long sdram_size
,
4066 DisplayState
*ds
, const char *core
)
4068 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*)
4069 qemu_mallocz(sizeof(struct omap_mpu_state_s
));
4070 ram_addr_t imif_base
, emiff_base
;
4073 s
->mpu_model
= omap310
;
4074 s
->env
= cpu_init();
4075 s
->sdram_size
= sdram_size
;
4076 s
->sram_size
= OMAP15XX_SRAM_SIZE
;
4078 cpu_arm_set_model(s
->env
, core
?: "ti925t");
4080 s
->wakeup
= qemu_allocate_irqs(omap_mpu_wakeup
, s
, 1)[0];
4085 /* Memory-mapped stuff */
4086 cpu_register_physical_memory(OMAP_EMIFF_BASE
, s
->sdram_size
,
4087 (emiff_base
= qemu_ram_alloc(s
->sdram_size
)) | IO_MEM_RAM
);
4088 cpu_register_physical_memory(OMAP_IMIF_BASE
, s
->sram_size
,
4089 (imif_base
= qemu_ram_alloc(s
->sram_size
)) | IO_MEM_RAM
);
4091 omap_clkm_init(0xfffece00, 0xe1008000, s
);
4093 s
->ih
[0] = omap_inth_init(0xfffecb00, 0x100,
4094 arm_pic_init_cpu(s
->env
),
4095 omap_findclk(s
, "arminth_ck"));
4096 s
->ih
[1] = omap_inth_init(0xfffe0000, 0x800,
4097 &s
->ih
[0]->pins
[OMAP_INT_15XX_IH2_IRQ
],
4098 omap_findclk(s
, "arminth_ck"));
4099 s
->irq
[0] = s
->ih
[0]->pins
;
4100 s
->irq
[1] = s
->ih
[1]->pins
;
4102 s
->dma
= omap_dma_init(0xfffed800, s
->irq
[0], s
,
4103 omap_findclk(s
, "dma_ck"));
4104 s
->port
[emiff
].addr_valid
= omap_validate_emiff_addr
;
4105 s
->port
[emifs
].addr_valid
= omap_validate_emifs_addr
;
4106 s
->port
[imif
].addr_valid
= omap_validate_imif_addr
;
4107 s
->port
[tipb
].addr_valid
= omap_validate_tipb_addr
;
4108 s
->port
[local
].addr_valid
= omap_validate_local_addr
;
4109 s
->port
[tipb_mpui
].addr_valid
= omap_validate_tipb_mpui_addr
;
4111 s
->timer
[0] = omap_mpu_timer_init(0xfffec500,
4112 s
->irq
[0][OMAP_INT_TIMER1
],
4113 omap_findclk(s
, "mputim_ck"));
4114 s
->timer
[1] = omap_mpu_timer_init(0xfffec600,
4115 s
->irq
[0][OMAP_INT_TIMER2
],
4116 omap_findclk(s
, "mputim_ck"));
4117 s
->timer
[2] = omap_mpu_timer_init(0xfffec700,
4118 s
->irq
[0][OMAP_INT_TIMER3
],
4119 omap_findclk(s
, "mputim_ck"));
4121 s
->wdt
= omap_wd_timer_init(0xfffec800,
4122 s
->irq
[0][OMAP_INT_WD_TIMER
],
4123 omap_findclk(s
, "armwdt_ck"));
4125 s
->os_timer
= omap_os_timer_init(0xfffb9000,
4126 s
->irq
[1][OMAP_INT_OS_TIMER
],
4127 omap_findclk(s
, "clk32-kHz"));
4129 s
->lcd
= omap_lcdc_init(0xfffec000, s
->irq
[0][OMAP_INT_LCD_CTRL
],
4130 &s
->dma
->lcd_ch
, ds
, imif_base
, emiff_base
,
4131 omap_findclk(s
, "lcd_ck"));
4133 omap_ulpd_pm_init(0xfffe0800, s
);
4134 omap_pin_cfg_init(0xfffe1000, s
);
4137 omap_mpui_init(0xfffec900, s
);
4139 s
->private_tipb
= omap_tipb_bridge_init(0xfffeca00,
4140 s
->irq
[0][OMAP_INT_BRIDGE_PRIV
],
4141 omap_findclk(s
, "tipb_ck"));
4142 s
->public_tipb
= omap_tipb_bridge_init(0xfffed300,
4143 s
->irq
[0][OMAP_INT_BRIDGE_PUB
],
4144 omap_findclk(s
, "tipb_ck"));
4146 omap_tcmi_init(0xfffecc00, s
);
4148 s
->uart
[0] = omap_uart_init(0xfffb0000, s
->irq
[1][OMAP_INT_UART1
],
4149 omap_findclk(s
, "uart1_ck"),
4151 s
->uart
[1] = omap_uart_init(0xfffb0800, s
->irq
[1][OMAP_INT_UART2
],
4152 omap_findclk(s
, "uart2_ck"),
4153 serial_hds
[0] ? serial_hds
[1] : 0);
4154 s
->uart
[2] = omap_uart_init(0xe1019800, s
->irq
[0][OMAP_INT_UART3
],
4155 omap_findclk(s
, "uart3_ck"),
4156 serial_hds
[0] && serial_hds
[1] ? serial_hds
[2] : 0);
4158 omap_dpll_init(&s
->dpll
[0], 0xfffecf00, omap_findclk(s
, "dpll1"));
4159 omap_dpll_init(&s
->dpll
[1], 0xfffed000, omap_findclk(s
, "dpll2"));
4160 omap_dpll_init(&s
->dpll
[2], 0xfffed100, omap_findclk(s
, "dpll3"));
4162 s
->mmc
= omap_mmc_init(0xfffb7800, s
->irq
[1][OMAP_INT_OQN
],
4163 &s
->drq
[OMAP_DMA_MMC_TX
], omap_findclk(s
, "mmc_ck"));
4165 s
->mpuio
= omap_mpuio_init(0xfffb5000,
4166 s
->irq
[1][OMAP_INT_KEYBOARD
], s
->irq
[1][OMAP_INT_MPUIO
],
4167 s
->wakeup
, omap_findclk(s
, "clk32-kHz"));
4169 s
->gpio
= omap_gpio_init(0xfffce000, s
->irq
[0][OMAP_INT_GPIO_BANK1
],
4170 omap_findclk(s
, "arm_gpio_ck"));
4172 s
->microwire
= omap_uwire_init(0xfffb3000, &s
->irq
[1][OMAP_INT_uWireTX
],
4173 s
->drq
[OMAP_DMA_UWIRE_TX
], omap_findclk(s
, "mpuper_ck"));
4175 omap_pwl_init(0xfffb5800, s
, omap_findclk(s
, "clk32-kHz"));
4176 omap_pwt_init(0xfffb6000, s
, omap_findclk(s
, "xtal_osc_12m"));
4178 s
->i2c
= omap_i2c_init(0xfffb3800, s
->irq
[1][OMAP_INT_I2C
],
4179 &s
->drq
[OMAP_DMA_I2C_RX
], omap_findclk(s
, "mpuper_ck"));
4181 qemu_register_reset(omap_mpu_reset
, s
);