2 * Texas Instruments OMAP processors.
4 * Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 # define hw_omap_h "omap.h"
24 # define OMAP_EMIFS_BASE 0x00000000
25 # define OMAP_CS0_BASE 0x00000000
26 # define OMAP_CS1_BASE 0x04000000
27 # define OMAP_CS2_BASE 0x08000000
28 # define OMAP_CS3_BASE 0x0c000000
29 # define OMAP_EMIFF_BASE 0x10000000
30 # define OMAP_IMIF_BASE 0x20000000
31 # define OMAP_LOCALBUS_BASE 0x30000000
32 # define OMAP_MPUI_BASE 0xe1000000
34 # define OMAP730_SRAM_SIZE 0x00032000
35 # define OMAP15XX_SRAM_SIZE 0x00030000
36 # define OMAP16XX_SRAM_SIZE 0x00004000
37 # define OMAP1611_SRAM_SIZE 0x0003e800
38 # define OMAP_CS0_SIZE 0x04000000
39 # define OMAP_CS1_SIZE 0x04000000
40 # define OMAP_CS2_SIZE 0x04000000
41 # define OMAP_CS3_SIZE 0x04000000
44 struct omap_mpu_state_s
;
45 typedef struct clk
*omap_clk
;
46 omap_clk
omap_findclk(struct omap_mpu_state_s
*mpu
, const char *name
);
47 void omap_clk_init(struct omap_mpu_state_s
*mpu
);
48 void omap_clk_adduser(struct clk
*clk
, qemu_irq user
);
49 void omap_clk_get(omap_clk clk
);
50 void omap_clk_put(omap_clk clk
);
51 void omap_clk_onoff(omap_clk clk
, int on
);
52 void omap_clk_canidle(omap_clk clk
, int can
);
53 void omap_clk_setrate(omap_clk clk
, int divide
, int multiply
);
54 int64_t omap_clk_getrate(omap_clk clk
);
55 void omap_clk_reparent(omap_clk clk
, omap_clk parent
);
58 struct omap_intr_handler_s
;
59 struct omap_intr_handler_s
*omap_inth_init(target_phys_addr_t base
,
60 unsigned long size
, qemu_irq parent
[2], omap_clk clk
);
63 * Common IRQ numbers for level 1 interrupt handler
64 * See /usr/include/asm-arm/arch-omap/irqs.h in Linux.
66 # define OMAP_INT_CAMERA 1
67 # define OMAP_INT_FIQ 3
68 # define OMAP_INT_RTDX 6
69 # define OMAP_INT_DSP_MMU_ABORT 7
70 # define OMAP_INT_HOST 8
71 # define OMAP_INT_ABORT 9
72 # define OMAP_INT_BRIDGE_PRIV 13
73 # define OMAP_INT_GPIO_BANK1 14
74 # define OMAP_INT_UART3 15
75 # define OMAP_INT_TIMER3 16
76 # define OMAP_INT_DMA_CH0_6 19
77 # define OMAP_INT_DMA_CH1_7 20
78 # define OMAP_INT_DMA_CH2_8 21
79 # define OMAP_INT_DMA_CH3 22
80 # define OMAP_INT_DMA_CH4 23
81 # define OMAP_INT_DMA_CH5 24
82 # define OMAP_INT_DMA_LCD 25
83 # define OMAP_INT_TIMER1 26
84 # define OMAP_INT_WD_TIMER 27
85 # define OMAP_INT_BRIDGE_PUB 28
86 # define OMAP_INT_TIMER2 30
87 # define OMAP_INT_LCD_CTRL 31
90 * Common OMAP-15xx IRQ numbers for level 1 interrupt handler
92 # define OMAP_INT_15XX_IH2_IRQ 0
93 # define OMAP_INT_15XX_LB_MMU 17
94 # define OMAP_INT_15XX_LOCAL_BUS 29
97 * OMAP-1510 specific IRQ numbers for level 1 interrupt handler
99 # define OMAP_INT_1510_SPI_TX 4
100 # define OMAP_INT_1510_SPI_RX 5
101 # define OMAP_INT_1510_DSP_MAILBOX1 10
102 # define OMAP_INT_1510_DSP_MAILBOX2 11
105 * OMAP-310 specific IRQ numbers for level 1 interrupt handler
107 # define OMAP_INT_310_McBSP2_TX 4
108 # define OMAP_INT_310_McBSP2_RX 5
109 # define OMAP_INT_310_HSB_MAILBOX1 12
110 # define OMAP_INT_310_HSAB_MMU 18
113 * OMAP-1610 specific IRQ numbers for level 1 interrupt handler
115 # define OMAP_INT_1610_IH2_IRQ 0
116 # define OMAP_INT_1610_IH2_FIQ 2
117 # define OMAP_INT_1610_McBSP2_TX 4
118 # define OMAP_INT_1610_McBSP2_RX 5
119 # define OMAP_INT_1610_DSP_MAILBOX1 10
120 # define OMAP_INT_1610_DSP_MAILBOX2 11
121 # define OMAP_INT_1610_LCD_LINE 12
122 # define OMAP_INT_1610_GPTIMER1 17
123 # define OMAP_INT_1610_GPTIMER2 18
124 # define OMAP_INT_1610_SSR_FIFO_0 29
127 * OMAP-730 specific IRQ numbers for level 1 interrupt handler
129 # define OMAP_INT_730_IH2_FIQ 0
130 # define OMAP_INT_730_IH2_IRQ 1
131 # define OMAP_INT_730_USB_NON_ISO 2
132 # define OMAP_INT_730_USB_ISO 3
133 # define OMAP_INT_730_ICR 4
134 # define OMAP_INT_730_EAC 5
135 # define OMAP_INT_730_GPIO_BANK1 6
136 # define OMAP_INT_730_GPIO_BANK2 7
137 # define OMAP_INT_730_GPIO_BANK3 8
138 # define OMAP_INT_730_McBSP2TX 10
139 # define OMAP_INT_730_McBSP2RX 11
140 # define OMAP_INT_730_McBSP2RX_OVF 12
141 # define OMAP_INT_730_LCD_LINE 14
142 # define OMAP_INT_730_GSM_PROTECT 15
143 # define OMAP_INT_730_TIMER3 16
144 # define OMAP_INT_730_GPIO_BANK5 17
145 # define OMAP_INT_730_GPIO_BANK6 18
146 # define OMAP_INT_730_SPGIO_WR 29
149 * Common IRQ numbers for level 2 interrupt handler
151 # define OMAP_INT_KEYBOARD 1
152 # define OMAP_INT_uWireTX 2
153 # define OMAP_INT_uWireRX 3
154 # define OMAP_INT_I2C 4
155 # define OMAP_INT_MPUIO 5
156 # define OMAP_INT_USB_HHC_1 6
157 # define OMAP_INT_McBSP3TX 10
158 # define OMAP_INT_McBSP3RX 11
159 # define OMAP_INT_McBSP1TX 12
160 # define OMAP_INT_McBSP1RX 13
161 # define OMAP_INT_UART1 14
162 # define OMAP_INT_UART2 15
163 # define OMAP_INT_USB_W2FC 20
164 # define OMAP_INT_1WIRE 21
165 # define OMAP_INT_OS_TIMER 22
166 # define OMAP_INT_OQN 23
167 # define OMAP_INT_GAUGE_32K 24
168 # define OMAP_INT_RTC_TIMER 25
169 # define OMAP_INT_RTC_ALARM 26
170 # define OMAP_INT_DSP_MMU 28
173 * OMAP-1510 specific IRQ numbers for level 2 interrupt handler
175 # define OMAP_INT_1510_BT_MCSI1TX 16
176 # define OMAP_INT_1510_BT_MCSI1RX 17
177 # define OMAP_INT_1510_SoSSI_MATCH 19
178 # define OMAP_INT_1510_MEM_STICK 27
179 # define OMAP_INT_1510_COM_SPI_RO 31
182 * OMAP-310 specific IRQ numbers for level 2 interrupt handler
184 # define OMAP_INT_310_FAC 0
185 # define OMAP_INT_310_USB_HHC_2 7
186 # define OMAP_INT_310_MCSI1_FE 16
187 # define OMAP_INT_310_MCSI2_FE 17
188 # define OMAP_INT_310_USB_W2FC_ISO 29
189 # define OMAP_INT_310_USB_W2FC_NON_ISO 30
190 # define OMAP_INT_310_McBSP2RX_OF 31
193 * OMAP-1610 specific IRQ numbers for level 2 interrupt handler
195 # define OMAP_INT_1610_FAC 0
196 # define OMAP_INT_1610_USB_HHC_2 7
197 # define OMAP_INT_1610_USB_OTG 8
198 # define OMAP_INT_1610_SoSSI 9
199 # define OMAP_INT_1610_BT_MCSI1TX 16
200 # define OMAP_INT_1610_BT_MCSI1RX 17
201 # define OMAP_INT_1610_SoSSI_MATCH 19
202 # define OMAP_INT_1610_MEM_STICK 27
203 # define OMAP_INT_1610_McBSP2RX_OF 31
204 # define OMAP_INT_1610_STI 32
205 # define OMAP_INT_1610_STI_WAKEUP 33
206 # define OMAP_INT_1610_GPTIMER3 34
207 # define OMAP_INT_1610_GPTIMER4 35
208 # define OMAP_INT_1610_GPTIMER5 36
209 # define OMAP_INT_1610_GPTIMER6 37
210 # define OMAP_INT_1610_GPTIMER7 38
211 # define OMAP_INT_1610_GPTIMER8 39
212 # define OMAP_INT_1610_GPIO_BANK2 40
213 # define OMAP_INT_1610_GPIO_BANK3 41
214 # define OMAP_INT_1610_MMC2 42
215 # define OMAP_INT_1610_CF 43
216 # define OMAP_INT_1610_WAKE_UP_REQ 46
217 # define OMAP_INT_1610_GPIO_BANK4 48
218 # define OMAP_INT_1610_SPI 49
219 # define OMAP_INT_1610_DMA_CH6 53
220 # define OMAP_INT_1610_DMA_CH7 54
221 # define OMAP_INT_1610_DMA_CH8 55
222 # define OMAP_INT_1610_DMA_CH9 56
223 # define OMAP_INT_1610_DMA_CH10 57
224 # define OMAP_INT_1610_DMA_CH11 58
225 # define OMAP_INT_1610_DMA_CH12 59
226 # define OMAP_INT_1610_DMA_CH13 60
227 # define OMAP_INT_1610_DMA_CH14 61
228 # define OMAP_INT_1610_DMA_CH15 62
229 # define OMAP_INT_1610_NAND 63
232 * OMAP-730 specific IRQ numbers for level 2 interrupt handler
234 # define OMAP_INT_730_HW_ERRORS 0
235 # define OMAP_INT_730_NFIQ_PWR_FAIL 1
236 # define OMAP_INT_730_CFCD 2
237 # define OMAP_INT_730_CFIREQ 3
238 # define OMAP_INT_730_I2C 4
239 # define OMAP_INT_730_PCC 5
240 # define OMAP_INT_730_MPU_EXT_NIRQ 6
241 # define OMAP_INT_730_SPI_100K_1 7
242 # define OMAP_INT_730_SYREN_SPI 8
243 # define OMAP_INT_730_VLYNQ 9
244 # define OMAP_INT_730_GPIO_BANK4 10
245 # define OMAP_INT_730_McBSP1TX 11
246 # define OMAP_INT_730_McBSP1RX 12
247 # define OMAP_INT_730_McBSP1RX_OF 13
248 # define OMAP_INT_730_UART_MODEM_IRDA_2 14
249 # define OMAP_INT_730_UART_MODEM_1 15
250 # define OMAP_INT_730_MCSI 16
251 # define OMAP_INT_730_uWireTX 17
252 # define OMAP_INT_730_uWireRX 18
253 # define OMAP_INT_730_SMC_CD 19
254 # define OMAP_INT_730_SMC_IREQ 20
255 # define OMAP_INT_730_HDQ_1WIRE 21
256 # define OMAP_INT_730_TIMER32K 22
257 # define OMAP_INT_730_MMC_SDIO 23
258 # define OMAP_INT_730_UPLD 24
259 # define OMAP_INT_730_USB_HHC_1 27
260 # define OMAP_INT_730_USB_HHC_2 28
261 # define OMAP_INT_730_USB_GENI 29
262 # define OMAP_INT_730_USB_OTG 30
263 # define OMAP_INT_730_CAMERA_IF 31
264 # define OMAP_INT_730_RNG 32
265 # define OMAP_INT_730_DUAL_MODE_TIMER 33
266 # define OMAP_INT_730_DBB_RF_EN 34
267 # define OMAP_INT_730_MPUIO_KEYPAD 35
268 # define OMAP_INT_730_SHA1_MD5 36
269 # define OMAP_INT_730_SPI_100K_2 37
270 # define OMAP_INT_730_RNG_IDLE 38
271 # define OMAP_INT_730_MPUIO 39
272 # define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40
273 # define OMAP_INT_730_LLPC_OE_FALLING 41
274 # define OMAP_INT_730_LLPC_OE_RISING 42
275 # define OMAP_INT_730_LLPC_VSYNC 43
276 # define OMAP_INT_730_WAKE_UP_REQ 46
277 # define OMAP_INT_730_DMA_CH6 53
278 # define OMAP_INT_730_DMA_CH7 54
279 # define OMAP_INT_730_DMA_CH8 55
280 # define OMAP_INT_730_DMA_CH9 56
281 # define OMAP_INT_730_DMA_CH10 57
282 # define OMAP_INT_730_DMA_CH11 58
283 # define OMAP_INT_730_DMA_CH12 59
284 # define OMAP_INT_730_DMA_CH13 60
285 # define OMAP_INT_730_DMA_CH14 61
286 # define OMAP_INT_730_DMA_CH15 62
287 # define OMAP_INT_730_NAND 63
290 * OMAP-24xx common IRQ numbers
292 # define OMAP_INT_24XX_SYS_NIRQ 7
293 # define OMAP_INT_24XX_SDMA_IRQ0 12
294 # define OMAP_INT_24XX_SDMA_IRQ1 13
295 # define OMAP_INT_24XX_SDMA_IRQ2 14
296 # define OMAP_INT_24XX_SDMA_IRQ3 15
297 # define OMAP_INT_24XX_CAM_IRQ 24
298 # define OMAP_INT_24XX_DSS_IRQ 25
299 # define OMAP_INT_24XX_MAIL_U0_MPU 26
300 # define OMAP_INT_24XX_DSP_UMA 27
301 # define OMAP_INT_24XX_DSP_MMU 28
302 # define OMAP_INT_24XX_GPIO_BANK1 29
303 # define OMAP_INT_24XX_GPIO_BANK2 30
304 # define OMAP_INT_24XX_GPIO_BANK3 31
305 # define OMAP_INT_24XX_GPIO_BANK4 32
306 # define OMAP_INT_24XX_GPIO_BANK5 33
307 # define OMAP_INT_24XX_MAIL_U3_MPU 34
308 # define OMAP_INT_24XX_GPTIMER1 37
309 # define OMAP_INT_24XX_GPTIMER2 38
310 # define OMAP_INT_24XX_GPTIMER3 39
311 # define OMAP_INT_24XX_GPTIMER4 40
312 # define OMAP_INT_24XX_GPTIMER5 41
313 # define OMAP_INT_24XX_GPTIMER6 42
314 # define OMAP_INT_24XX_GPTIMER7 43
315 # define OMAP_INT_24XX_GPTIMER8 44
316 # define OMAP_INT_24XX_GPTIMER9 45
317 # define OMAP_INT_24XX_GPTIMER10 46
318 # define OMAP_INT_24XX_GPTIMER11 47
319 # define OMAP_INT_24XX_GPTIMER12 48
320 # define OMAP_INT_24XX_MCBSP1_IRQ_TX 59
321 # define OMAP_INT_24XX_MCBSP1_IRQ_RX 60
322 # define OMAP_INT_24XX_MCBSP2_IRQ_TX 62
323 # define OMAP_INT_24XX_MCBSP2_IRQ_RX 63
324 # define OMAP_INT_24XX_UART1_IRQ 72
325 # define OMAP_INT_24XX_UART2_IRQ 73
326 # define OMAP_INT_24XX_UART3_IRQ 74
327 # define OMAP_INT_24XX_USB_IRQ_GEN 75
328 # define OMAP_INT_24XX_USB_IRQ_NISO 76
329 # define OMAP_INT_24XX_USB_IRQ_ISO 77
330 # define OMAP_INT_24XX_USB_IRQ_HGEN 78
331 # define OMAP_INT_24XX_USB_IRQ_HSOF 79
332 # define OMAP_INT_24XX_USB_IRQ_OTG 80
333 # define OMAP_INT_24XX_MMC_IRQ 83
334 # define OMAP_INT_243X_HS_USB_MC 92
335 # define OMAP_INT_243X_HS_USB_DMA 93
336 # define OMAP_INT_243X_CARKIT 94
339 struct omap_dma_s
*omap_dma_init(target_phys_addr_t base
,
340 qemu_irq pic
[], struct omap_mpu_state_s
*mpu
, omap_clk clk
);
352 struct omap_dma_lcd_channel_s
{
353 enum omap_dma_port src
;
354 target_phys_addr_t src_f1_top
;
355 target_phys_addr_t src_f1_bottom
;
356 target_phys_addr_t src_f2_top
;
357 target_phys_addr_t src_f2_bottom
;
358 /* Destination port is fixed. */
364 ram_addr_t phys_framebuffer
[2];
366 struct omap_mpu_state_s
*mpu
;
370 * DMA request numbers for OMAP1
371 * See /usr/include/asm-arm/arch-omap/dma.h in Linux.
373 # define OMAP_DMA_NO_DEVICE 0
374 # define OMAP_DMA_MCSI1_TX 1
375 # define OMAP_DMA_MCSI1_RX 2
376 # define OMAP_DMA_I2C_RX 3
377 # define OMAP_DMA_I2C_TX 4
378 # define OMAP_DMA_EXT_NDMA_REQ0 5
379 # define OMAP_DMA_EXT_NDMA_REQ1 6
380 # define OMAP_DMA_UWIRE_TX 7
381 # define OMAP_DMA_MCBSP1_TX 8
382 # define OMAP_DMA_MCBSP1_RX 9
383 # define OMAP_DMA_MCBSP3_TX 10
384 # define OMAP_DMA_MCBSP3_RX 11
385 # define OMAP_DMA_UART1_TX 12
386 # define OMAP_DMA_UART1_RX 13
387 # define OMAP_DMA_UART2_TX 14
388 # define OMAP_DMA_UART2_RX 15
389 # define OMAP_DMA_MCBSP2_TX 16
390 # define OMAP_DMA_MCBSP2_RX 17
391 # define OMAP_DMA_UART3_TX 18
392 # define OMAP_DMA_UART3_RX 19
393 # define OMAP_DMA_CAMERA_IF_RX 20
394 # define OMAP_DMA_MMC_TX 21
395 # define OMAP_DMA_MMC_RX 22
396 # define OMAP_DMA_NAND 23 /* Not in OMAP310 */
397 # define OMAP_DMA_IRQ_LCD_LINE 24 /* Not in OMAP310 */
398 # define OMAP_DMA_MEMORY_STICK 25 /* Not in OMAP310 */
399 # define OMAP_DMA_USB_W2FC_RX0 26
400 # define OMAP_DMA_USB_W2FC_RX1 27
401 # define OMAP_DMA_USB_W2FC_RX2 28
402 # define OMAP_DMA_USB_W2FC_TX0 29
403 # define OMAP_DMA_USB_W2FC_TX1 30
404 # define OMAP_DMA_USB_W2FC_TX2 31
406 /* These are only for 1610 */
407 # define OMAP_DMA_CRYPTO_DES_IN 32
408 # define OMAP_DMA_SPI_TX 33
409 # define OMAP_DMA_SPI_RX 34
410 # define OMAP_DMA_CRYPTO_HASH 35
411 # define OMAP_DMA_CCP_ATTN 36
412 # define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37
413 # define OMAP_DMA_CMT_APE_TX_CHAN_0 38
414 # define OMAP_DMA_CMT_APE_RV_CHAN_0 39
415 # define OMAP_DMA_CMT_APE_TX_CHAN_1 40
416 # define OMAP_DMA_CMT_APE_RV_CHAN_1 41
417 # define OMAP_DMA_CMT_APE_TX_CHAN_2 42
418 # define OMAP_DMA_CMT_APE_RV_CHAN_2 43
419 # define OMAP_DMA_CMT_APE_TX_CHAN_3 44
420 # define OMAP_DMA_CMT_APE_RV_CHAN_3 45
421 # define OMAP_DMA_CMT_APE_TX_CHAN_4 46
422 # define OMAP_DMA_CMT_APE_RV_CHAN_4 47
423 # define OMAP_DMA_CMT_APE_TX_CHAN_5 48
424 # define OMAP_DMA_CMT_APE_RV_CHAN_5 49
425 # define OMAP_DMA_CMT_APE_TX_CHAN_6 50
426 # define OMAP_DMA_CMT_APE_RV_CHAN_6 51
427 # define OMAP_DMA_CMT_APE_TX_CHAN_7 52
428 # define OMAP_DMA_CMT_APE_RV_CHAN_7 53
429 # define OMAP_DMA_MMC2_TX 54
430 # define OMAP_DMA_MMC2_RX 55
431 # define OMAP_DMA_CRYPTO_DES_OUT 56
433 struct omap_mpu_timer_s
;
434 struct omap_mpu_timer_s
*omap_mpu_timer_init(target_phys_addr_t base
,
435 qemu_irq irq
, omap_clk clk
);
437 struct omap_watchdog_timer_s
;
438 struct omap_watchdog_timer_s
*omap_wd_timer_init(target_phys_addr_t base
,
439 qemu_irq irq
, omap_clk clk
);
441 struct omap_32khz_timer_s
;
442 struct omap_32khz_timer_s
*omap_os_timer_init(target_phys_addr_t base
,
443 qemu_irq irq
, omap_clk clk
);
445 struct omap_tipb_bridge_s
;
446 struct omap_tipb_bridge_s
*omap_tipb_bridge_init(target_phys_addr_t base
,
447 qemu_irq abort_irq
, omap_clk clk
);
450 struct omap_uart_s
*omap_uart_init(target_phys_addr_t base
,
451 qemu_irq irq
, omap_clk clk
, CharDriverState
*chr
);
454 struct omap_mpuio_s
*omap_mpuio_init(target_phys_addr_t base
,
455 qemu_irq kbd_int
, qemu_irq gpio_int
, qemu_irq wakeup
,
457 qemu_irq
*omap_mpuio_in_get(struct omap_mpuio_s
*s
);
458 void omap_mpuio_out_set(struct omap_mpuio_s
*s
, int line
, qemu_irq handler
);
459 void omap_mpuio_key(struct omap_mpuio_s
*s
, int row
, int col
, int down
);
462 struct omap_gpio_s
*omap_gpio_init(target_phys_addr_t base
,
463 qemu_irq irq
, omap_clk clk
);
464 qemu_irq
*omap_gpio_in_get(struct omap_gpio_s
*s
);
465 void omap_gpio_out_set(struct omap_gpio_s
*s
, int line
, qemu_irq handler
);
467 struct uwire_slave_s
{
468 uint16_t (*receive
)(void *opaque
);
469 void (*send
)(void *opaque
, uint16_t data
);
473 struct omap_uwire_s
*omap_uwire_init(target_phys_addr_t base
,
474 qemu_irq
*irq
, qemu_irq dma
, omap_clk clk
);
475 void omap_uwire_attach(struct omap_uwire_s
*s
,
476 struct uwire_slave_s
*slave
, int chipselect
);
479 struct omap_rtc_s
*omap_rtc_init(target_phys_addr_t base
,
480 qemu_irq
*irq
, omap_clk clk
);
485 /* The CPU can call this if it is generating the clock signal on the
486 * i2s port. The CODEC can ignore it if it is set up as a clock
487 * master and generates its own clock. */
488 void (*set_rate
)(void *opaque
, int in
, int out
);
490 void (*tx_swallow
)(void *opaque
);
507 struct omap_mcbsp_s
*omap_mcbsp_init(target_phys_addr_t base
,
508 qemu_irq
*irq
, qemu_irq
*dma
, omap_clk clk
);
509 void omap_mcbsp_i2s_attach(struct omap_mcbsp_s
*s
, struct i2s_codec_s
*slave
);
512 struct omap_lcd_panel_s
;
513 void omap_lcdc_reset(struct omap_lcd_panel_s
*s
);
514 struct omap_lcd_panel_s
*omap_lcdc_init(target_phys_addr_t base
, qemu_irq irq
,
515 struct omap_dma_lcd_channel_s
*dma
, DisplayState
*ds
,
516 ram_addr_t imif_base
, ram_addr_t emiff_base
, omap_clk clk
);
520 struct omap_mmc_s
*omap_mmc_init(target_phys_addr_t base
,
521 BlockDriverState
*bd
,
522 qemu_irq irq
, qemu_irq dma
[], omap_clk clk
);
523 void omap_mmc_reset(struct omap_mmc_s
*s
);
524 void omap_mmc_handlers(struct omap_mmc_s
*s
, qemu_irq ro
, qemu_irq cover
);
528 struct omap_i2c_s
*omap_i2c_init(target_phys_addr_t base
,
529 qemu_irq irq
, qemu_irq
*dma
, omap_clk clk
);
530 void omap_i2c_reset(struct omap_i2c_s
*s
);
531 i2c_bus
*omap_i2c_bus(struct omap_i2c_s
*s
);
533 # define cpu_is_omap310(cpu) (cpu->mpu_model == omap310)
534 # define cpu_is_omap1510(cpu) (cpu->mpu_model == omap1510)
535 # define cpu_is_omap15xx(cpu) \
536 (cpu_is_omap310(cpu) || cpu_is_omap1510(cpu))
537 # define cpu_class_omap1(cpu) 1
539 struct omap_mpu_state_s
{
540 enum omap1_mpu_model
{
552 struct omap_dma_port_if_s
{
553 uint32_t (*read
[3])(struct omap_mpu_state_s
*s
,
554 target_phys_addr_t offset
);
555 void (*write
[3])(struct omap_mpu_state_s
*s
,
556 target_phys_addr_t offset
, uint32_t value
);
557 int (*addr_valid
)(struct omap_mpu_state_s
*s
,
558 target_phys_addr_t addr
);
559 } port
[omap_dma_port_last
];
561 unsigned long sdram_size
;
562 unsigned long sram_size
;
564 /* MPUI-TIPB peripherals */
565 struct omap_uart_s
*uart
[3];
567 struct omap_gpio_s
*gpio
;
569 struct omap_mcbsp_s
*mcbsp1
;
570 struct omap_mcbsp_s
*mcbsp3
;
572 /* MPU public TIPB peripherals */
573 struct omap_32khz_timer_s
*os_timer
;
575 struct omap_mmc_s
*mmc
;
577 struct omap_mpuio_s
*mpuio
;
579 struct omap_uwire_s
*microwire
;
595 struct omap_i2c_s
*i2c
;
597 struct omap_rtc_s
*rtc
;
599 struct omap_mcbsp_s
*mcbsp2
;
601 /* MPU private TIPB peripherals */
602 struct omap_intr_handler_s
*ih
[2];
604 struct omap_dma_s
*dma
;
606 struct omap_mpu_timer_s
*timer
[3];
607 struct omap_watchdog_timer_s
*wdt
;
609 struct omap_lcd_panel_s
*lcd
;
611 target_phys_addr_t ulpd_pm_base
;
612 uint32_t ulpd_pm_regs
[21];
613 int64_t ulpd_gauge_start
;
615 target_phys_addr_t pin_cfg_base
;
616 uint32_t func_mux_ctrl
[14];
617 uint32_t comp_mode_ctrl
[1];
618 uint32_t pull_dwn_ctrl
[4];
619 uint32_t gate_inh_ctrl
[1];
620 uint32_t voltage_ctrl
[1];
621 uint32_t test_dbg_ctrl
[1];
622 uint32_t mod_conf_ctrl
[1];
626 target_phys_addr_t mpui_base
;
628 struct omap_tipb_bridge_s
*private_tipb
;
629 struct omap_tipb_bridge_s
*public_tipb
;
631 target_phys_addr_t tcmi_base
;
632 uint32_t tcmi_regs
[17];
635 target_phys_addr_t base
;
642 target_phys_addr_t mpu_base
;
643 target_phys_addr_t dsp_base
;
648 uint16_t arm_idlect1
;
649 uint16_t arm_idlect2
;
655 uint16_t dsp_idlect1
;
656 uint16_t dsp_idlect2
;
659 } *omap310_mpu_init(unsigned long sdram_size
,
660 DisplayState
*ds
, const char *core
);
662 # if TARGET_PHYS_ADDR_BITS == 32
663 # define OMAP_FMT_plx "%#08x"
664 # elif TARGET_PHYS_ADDR_BITS == 64
665 # define OMAP_FMT_plx "%#08" PRIx64
667 # error TARGET_PHYS_ADDR_BITS undefined
670 uint32_t omap_badwidth_read8(void *opaque
, target_phys_addr_t addr
);
671 void omap_badwidth_write8(void *opaque
, target_phys_addr_t addr
,
673 uint32_t omap_badwidth_read16(void *opaque
, target_phys_addr_t addr
);
674 void omap_badwidth_write16(void *opaque
, target_phys_addr_t addr
,
676 uint32_t omap_badwidth_read32(void *opaque
, target_phys_addr_t addr
);
677 void omap_badwidth_write32(void *opaque
, target_phys_addr_t addr
,
680 # define OMAP_BAD_REG(paddr) \
681 printf("%s: Bad register " OMAP_FMT_plx "\n", __FUNCTION__, paddr)
682 # define OMAP_RO_REG(paddr) \
683 printf("%s: Read-only register " OMAP_FMT_plx "\n", \
686 # define TCMI_VERBOSE 1
687 //# define MEM_VERBOSE 1
690 # define OMAP_8B_REG(paddr) \
691 printf("%s: 8-bit register " OMAP_FMT_plx "\n", \
693 # define OMAP_16B_REG(paddr) \
694 printf("%s: 16-bit register " OMAP_FMT_plx "\n", \
696 # define OMAP_32B_REG(paddr) \
697 printf("%s: 32-bit register " OMAP_FMT_plx "\n", \
700 # define OMAP_8B_REG(paddr)
701 # define OMAP_16B_REG(paddr)
702 # define OMAP_32B_REG(paddr)
705 # define OMAP_MPUI_REG_MASK 0x000007ff
709 CPUReadMemoryFunc
**mem_read
;
710 CPUWriteMemoryFunc
**mem_write
;
715 static uint32_t io_readb(void *opaque
, target_phys_addr_t addr
)
717 struct io_fn
*s
= opaque
;
721 ret
= s
->mem_read
[0](s
->opaque
, addr
);
724 fprintf(stderr
, "%08x ---> %02x\n", (uint32_t) addr
, ret
);
727 static uint32_t io_readh(void *opaque
, target_phys_addr_t addr
)
729 struct io_fn
*s
= opaque
;
733 ret
= s
->mem_read
[1](s
->opaque
, addr
);
736 fprintf(stderr
, "%08x ---> %04x\n", (uint32_t) addr
, ret
);
739 static uint32_t io_readw(void *opaque
, target_phys_addr_t addr
)
741 struct io_fn
*s
= opaque
;
745 ret
= s
->mem_read
[2](s
->opaque
, addr
);
748 fprintf(stderr
, "%08x ---> %08x\n", (uint32_t) addr
, ret
);
751 static void io_writeb(void *opaque
, target_phys_addr_t addr
, uint32_t value
)
753 struct io_fn
*s
= opaque
;
756 fprintf(stderr
, "%08x <--- %02x\n", (uint32_t) addr
, value
);
758 s
->mem_write
[0](s
->opaque
, addr
, value
);
761 static void io_writeh(void *opaque
, target_phys_addr_t addr
, uint32_t value
)
763 struct io_fn
*s
= opaque
;
766 fprintf(stderr
, "%08x <--- %04x\n", (uint32_t) addr
, value
);
768 s
->mem_write
[1](s
->opaque
, addr
, value
);
771 static void io_writew(void *opaque
, target_phys_addr_t addr
, uint32_t value
)
773 struct io_fn
*s
= opaque
;
776 fprintf(stderr
, "%08x <--- %08x\n", (uint32_t) addr
, value
);
778 s
->mem_write
[2](s
->opaque
, addr
, value
);
782 static CPUReadMemoryFunc
*io_readfn
[] = { io_readb
, io_readh
, io_readw
, };
783 static CPUWriteMemoryFunc
*io_writefn
[] = { io_writeb
, io_writeh
, io_writew
, };
785 inline static int debug_register_io_memory(int io_index
,
786 CPUReadMemoryFunc
**mem_read
, CPUWriteMemoryFunc
**mem_write
,
789 struct io_fn
*s
= qemu_malloc(sizeof(struct io_fn
));
791 s
->mem_read
= mem_read
;
792 s
->mem_write
= mem_write
;
795 return cpu_register_io_memory(io_index
, io_readfn
, io_writefn
, s
);
797 # define cpu_register_io_memory debug_register_io_memory
800 /* Not really omap specific, but is the only thing that uses the
803 struct uwire_slave_s
*tsc2102_init(qemu_irq pint
, AudioState
*audio
);
804 struct i2s_codec_s
*tsc210x_codec(struct uwire_slave_s
*chip
);
806 #endif /* hw_omap_h */