2 * TI OMAP processors emulation.
4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 or
9 * (at your option) version 3 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include "qemu-timer.h"
26 #include "qemu-char.h"
28 /* We use pc-style serial ports. */
31 /* Should signal the TCMI/GPMC */
32 uint32_t omap_badwidth_read8(void *opaque
, target_phys_addr_t addr
)
37 cpu_physical_memory_read(addr
, (void *) &ret
, 1);
41 void omap_badwidth_write8(void *opaque
, target_phys_addr_t addr
,
47 cpu_physical_memory_write(addr
, (void *) &val8
, 1);
50 uint32_t omap_badwidth_read16(void *opaque
, target_phys_addr_t addr
)
55 cpu_physical_memory_read(addr
, (void *) &ret
, 2);
59 void omap_badwidth_write16(void *opaque
, target_phys_addr_t addr
,
62 uint16_t val16
= value
;
65 cpu_physical_memory_write(addr
, (void *) &val16
, 2);
68 uint32_t omap_badwidth_read32(void *opaque
, target_phys_addr_t addr
)
73 cpu_physical_memory_read(addr
, (void *) &ret
, 4);
77 void omap_badwidth_write32(void *opaque
, target_phys_addr_t addr
,
81 cpu_physical_memory_write(addr
, (void *) &value
, 4);
84 /* Interrupt Handlers */
85 struct omap_intr_handler_bank_s
{
92 unsigned char priority
[32];
95 struct omap_intr_handler_s
{
97 qemu_irq parent_intr
[2];
106 struct omap_intr_handler_bank_s bank
[];
109 static void omap_inth_sir_update(struct omap_intr_handler_s
*s
, int is_fiq
)
111 int i
, j
, sir_intr
, p_intr
, p
, f
;
116 /* Find the interrupt line with the highest dynamic priority.
117 * Note: 0 denotes the hightest priority.
118 * If all interrupts have the same priority, the default order is IRQ_N,
119 * IRQ_N-1,...,IRQ_0. */
120 for (j
= 0; j
< s
->nbanks
; ++j
) {
121 level
= s
->bank
[j
].irqs
& ~s
->bank
[j
].mask
&
122 (is_fiq
? s
->bank
[j
].fiq
: ~s
->bank
[j
].fiq
);
123 for (f
= ffs(level
), i
= f
- 1, level
>>= f
- 1; f
; i
+= f
,
125 p
= s
->bank
[j
].priority
[i
];
128 sir_intr
= 32 * j
+ i
;
133 s
->sir_intr
[is_fiq
] = sir_intr
;
136 static inline void omap_inth_update(struct omap_intr_handler_s
*s
, int is_fiq
)
139 uint32_t has_intr
= 0;
141 for (i
= 0; i
< s
->nbanks
; ++i
)
142 has_intr
|= s
->bank
[i
].irqs
& ~s
->bank
[i
].mask
&
143 (is_fiq
? s
->bank
[i
].fiq
: ~s
->bank
[i
].fiq
);
145 if (s
->new_agr
[is_fiq
] & has_intr
& s
->mask
) {
146 s
->new_agr
[is_fiq
] = 0;
147 omap_inth_sir_update(s
, is_fiq
);
148 qemu_set_irq(s
->parent_intr
[is_fiq
], 1);
152 #define INT_FALLING_EDGE 0
153 #define INT_LOW_LEVEL 1
155 static void omap_set_intr(void *opaque
, int irq
, int req
)
157 struct omap_intr_handler_s
*ih
= (struct omap_intr_handler_s
*) opaque
;
160 struct omap_intr_handler_bank_s
*bank
= &ih
->bank
[irq
>> 5];
164 rise
= ~bank
->irqs
& (1 << n
);
165 if (~bank
->sens_edge
& (1 << n
))
166 rise
&= ~bank
->inputs
;
168 bank
->inputs
|= (1 << n
);
171 omap_inth_update(ih
, 0);
172 omap_inth_update(ih
, 1);
175 rise
= bank
->sens_edge
& bank
->irqs
& (1 << n
);
177 bank
->inputs
&= ~(1 << n
);
181 /* Simplified version with no edge detection */
182 static void omap_set_intr_noedge(void *opaque
, int irq
, int req
)
184 struct omap_intr_handler_s
*ih
= (struct omap_intr_handler_s
*) opaque
;
187 struct omap_intr_handler_bank_s
*bank
= &ih
->bank
[irq
>> 5];
191 rise
= ~bank
->inputs
& (1 << n
);
193 bank
->irqs
|= bank
->inputs
|= rise
;
194 omap_inth_update(ih
, 0);
195 omap_inth_update(ih
, 1);
198 bank
->irqs
= (bank
->inputs
&= ~(1 << n
)) | bank
->swi
;
201 static uint32_t omap_inth_read(void *opaque
, target_phys_addr_t addr
)
203 struct omap_intr_handler_s
*s
= (struct omap_intr_handler_s
*) opaque
;
204 int i
, offset
= addr
;
205 int bank_no
= offset
>> 8;
207 struct omap_intr_handler_bank_s
*bank
= &s
->bank
[bank_no
];
217 case 0x10: /* SIR_IRQ_CODE */
218 case 0x14: /* SIR_FIQ_CODE */
221 line_no
= s
->sir_intr
[(offset
- 0x10) >> 2];
222 bank
= &s
->bank
[line_no
>> 5];
224 if (((bank
->sens_edge
>> i
) & 1) == INT_FALLING_EDGE
)
225 bank
->irqs
&= ~(1 << i
);
228 case 0x18: /* CONTROL_REG */
233 case 0x1c: /* ILR0 */
234 case 0x20: /* ILR1 */
235 case 0x24: /* ILR2 */
236 case 0x28: /* ILR3 */
237 case 0x2c: /* ILR4 */
238 case 0x30: /* ILR5 */
239 case 0x34: /* ILR6 */
240 case 0x38: /* ILR7 */
241 case 0x3c: /* ILR8 */
242 case 0x40: /* ILR9 */
243 case 0x44: /* ILR10 */
244 case 0x48: /* ILR11 */
245 case 0x4c: /* ILR12 */
246 case 0x50: /* ILR13 */
247 case 0x54: /* ILR14 */
248 case 0x58: /* ILR15 */
249 case 0x5c: /* ILR16 */
250 case 0x60: /* ILR17 */
251 case 0x64: /* ILR18 */
252 case 0x68: /* ILR19 */
253 case 0x6c: /* ILR20 */
254 case 0x70: /* ILR21 */
255 case 0x74: /* ILR22 */
256 case 0x78: /* ILR23 */
257 case 0x7c: /* ILR24 */
258 case 0x80: /* ILR25 */
259 case 0x84: /* ILR26 */
260 case 0x88: /* ILR27 */
261 case 0x8c: /* ILR28 */
262 case 0x90: /* ILR29 */
263 case 0x94: /* ILR30 */
264 case 0x98: /* ILR31 */
265 i
= (offset
- 0x1c) >> 2;
266 return (bank
->priority
[i
] << 2) |
267 (((bank
->sens_edge
>> i
) & 1) << 1) |
268 ((bank
->fiq
>> i
) & 1);
278 static void omap_inth_write(void *opaque
, target_phys_addr_t addr
,
281 struct omap_intr_handler_s
*s
= (struct omap_intr_handler_s
*) opaque
;
282 int i
, offset
= addr
;
283 int bank_no
= offset
>> 8;
284 struct omap_intr_handler_bank_s
*bank
= &s
->bank
[bank_no
];
289 /* Important: ignore the clearing if the IRQ is level-triggered and
290 the input bit is 1 */
291 bank
->irqs
&= value
| (bank
->inputs
& bank
->sens_edge
);
296 omap_inth_update(s
, 0);
297 omap_inth_update(s
, 1);
300 case 0x10: /* SIR_IRQ_CODE */
301 case 0x14: /* SIR_FIQ_CODE */
305 case 0x18: /* CONTROL_REG */
309 qemu_set_irq(s
->parent_intr
[1], 0);
311 omap_inth_update(s
, 1);
314 qemu_set_irq(s
->parent_intr
[0], 0);
316 omap_inth_update(s
, 0);
320 case 0x1c: /* ILR0 */
321 case 0x20: /* ILR1 */
322 case 0x24: /* ILR2 */
323 case 0x28: /* ILR3 */
324 case 0x2c: /* ILR4 */
325 case 0x30: /* ILR5 */
326 case 0x34: /* ILR6 */
327 case 0x38: /* ILR7 */
328 case 0x3c: /* ILR8 */
329 case 0x40: /* ILR9 */
330 case 0x44: /* ILR10 */
331 case 0x48: /* ILR11 */
332 case 0x4c: /* ILR12 */
333 case 0x50: /* ILR13 */
334 case 0x54: /* ILR14 */
335 case 0x58: /* ILR15 */
336 case 0x5c: /* ILR16 */
337 case 0x60: /* ILR17 */
338 case 0x64: /* ILR18 */
339 case 0x68: /* ILR19 */
340 case 0x6c: /* ILR20 */
341 case 0x70: /* ILR21 */
342 case 0x74: /* ILR22 */
343 case 0x78: /* ILR23 */
344 case 0x7c: /* ILR24 */
345 case 0x80: /* ILR25 */
346 case 0x84: /* ILR26 */
347 case 0x88: /* ILR27 */
348 case 0x8c: /* ILR28 */
349 case 0x90: /* ILR29 */
350 case 0x94: /* ILR30 */
351 case 0x98: /* ILR31 */
352 i
= (offset
- 0x1c) >> 2;
353 bank
->priority
[i
] = (value
>> 2) & 0x1f;
354 bank
->sens_edge
&= ~(1 << i
);
355 bank
->sens_edge
|= ((value
>> 1) & 1) << i
;
356 bank
->fiq
&= ~(1 << i
);
357 bank
->fiq
|= (value
& 1) << i
;
361 for (i
= 0; i
< 32; i
++)
362 if (value
& (1 << i
)) {
363 omap_set_intr(s
, 32 * bank_no
+ i
, 1);
371 static CPUReadMemoryFunc
*omap_inth_readfn
[] = {
372 omap_badwidth_read32
,
373 omap_badwidth_read32
,
377 static CPUWriteMemoryFunc
*omap_inth_writefn
[] = {
383 void omap_inth_reset(struct omap_intr_handler_s
*s
)
387 for (i
= 0; i
< s
->nbanks
; ++i
){
388 s
->bank
[i
].irqs
= 0x00000000;
389 s
->bank
[i
].mask
= 0xffffffff;
390 s
->bank
[i
].sens_edge
= 0x00000000;
391 s
->bank
[i
].fiq
= 0x00000000;
392 s
->bank
[i
].inputs
= 0x00000000;
393 s
->bank
[i
].swi
= 0x00000000;
394 memset(s
->bank
[i
].priority
, 0, sizeof(s
->bank
[i
].priority
));
397 s
->bank
[i
].sens_edge
= 0xffffffff;
407 qemu_set_irq(s
->parent_intr
[0], 0);
408 qemu_set_irq(s
->parent_intr
[1], 0);
411 struct omap_intr_handler_s
*omap_inth_init(target_phys_addr_t base
,
412 unsigned long size
, unsigned char nbanks
, qemu_irq
**pins
,
413 qemu_irq parent_irq
, qemu_irq parent_fiq
, omap_clk clk
)
416 struct omap_intr_handler_s
*s
= (struct omap_intr_handler_s
*)
417 qemu_mallocz(sizeof(struct omap_intr_handler_s
) +
418 sizeof(struct omap_intr_handler_bank_s
) * nbanks
);
420 s
->parent_intr
[0] = parent_irq
;
421 s
->parent_intr
[1] = parent_fiq
;
423 s
->pins
= qemu_allocate_irqs(omap_set_intr
, s
, nbanks
* 32);
429 iomemtype
= cpu_register_io_memory(0, omap_inth_readfn
,
430 omap_inth_writefn
, s
);
431 cpu_register_physical_memory(base
, size
, iomemtype
);
436 static uint32_t omap2_inth_read(void *opaque
, target_phys_addr_t addr
)
438 struct omap_intr_handler_s
*s
= (struct omap_intr_handler_s
*) opaque
;
440 int bank_no
, line_no
;
441 struct omap_intr_handler_bank_s
*bank
= 0;
443 if ((offset
& 0xf80) == 0x80) {
444 bank_no
= (offset
& 0x60) >> 5;
445 if (bank_no
< s
->nbanks
) {
447 bank
= &s
->bank
[bank_no
];
452 case 0x00: /* INTC_REVISION */
455 case 0x10: /* INTC_SYSCONFIG */
456 return (s
->autoidle
>> 2) & 1;
458 case 0x14: /* INTC_SYSSTATUS */
459 return 1; /* RESETDONE */
461 case 0x40: /* INTC_SIR_IRQ */
462 return s
->sir_intr
[0];
464 case 0x44: /* INTC_SIR_FIQ */
465 return s
->sir_intr
[1];
467 case 0x48: /* INTC_CONTROL */
468 return (!s
->mask
) << 2; /* GLOBALMASK */
470 case 0x4c: /* INTC_PROTECTION */
473 case 0x50: /* INTC_IDLE */
474 return s
->autoidle
& 3;
476 /* Per-bank registers */
477 case 0x80: /* INTC_ITR */
480 case 0x84: /* INTC_MIR */
483 case 0x88: /* INTC_MIR_CLEAR */
484 case 0x8c: /* INTC_MIR_SET */
487 case 0x90: /* INTC_ISR_SET */
490 case 0x94: /* INTC_ISR_CLEAR */
493 case 0x98: /* INTC_PENDING_IRQ */
494 return bank
->irqs
& ~bank
->mask
& ~bank
->fiq
;
496 case 0x9c: /* INTC_PENDING_FIQ */
497 return bank
->irqs
& ~bank
->mask
& bank
->fiq
;
499 /* Per-line registers */
500 case 0x100 ... 0x300: /* INTC_ILR */
501 bank_no
= (offset
- 0x100) >> 7;
502 if (bank_no
> s
->nbanks
)
504 bank
= &s
->bank
[bank_no
];
505 line_no
= (offset
& 0x7f) >> 2;
506 return (bank
->priority
[line_no
] << 2) |
507 ((bank
->fiq
>> line_no
) & 1);
513 static void omap2_inth_write(void *opaque
, target_phys_addr_t addr
,
516 struct omap_intr_handler_s
*s
= (struct omap_intr_handler_s
*) opaque
;
518 int bank_no
, line_no
;
519 struct omap_intr_handler_bank_s
*bank
= 0;
521 if ((offset
& 0xf80) == 0x80) {
522 bank_no
= (offset
& 0x60) >> 5;
523 if (bank_no
< s
->nbanks
) {
525 bank
= &s
->bank
[bank_no
];
530 case 0x10: /* INTC_SYSCONFIG */
532 s
->autoidle
|= (value
& 1) << 2;
533 if (value
& 2) /* SOFTRESET */
537 case 0x48: /* INTC_CONTROL */
538 s
->mask
= (value
& 4) ? 0 : ~0; /* GLOBALMASK */
539 if (value
& 2) { /* NEWFIQAGR */
540 qemu_set_irq(s
->parent_intr
[1], 0);
542 omap_inth_update(s
, 1);
544 if (value
& 1) { /* NEWIRQAGR */
545 qemu_set_irq(s
->parent_intr
[0], 0);
547 omap_inth_update(s
, 0);
551 case 0x4c: /* INTC_PROTECTION */
552 /* TODO: Make a bitmap (or sizeof(char)map) of access privileges
553 * for every register, see Chapter 3 and 4 for privileged mode. */
555 fprintf(stderr
, "%s: protection mode enable attempt\n",
559 case 0x50: /* INTC_IDLE */
561 s
->autoidle
|= value
& 3;
564 /* Per-bank registers */
565 case 0x84: /* INTC_MIR */
567 omap_inth_update(s
, 0);
568 omap_inth_update(s
, 1);
571 case 0x88: /* INTC_MIR_CLEAR */
572 bank
->mask
&= ~value
;
573 omap_inth_update(s
, 0);
574 omap_inth_update(s
, 1);
577 case 0x8c: /* INTC_MIR_SET */
581 case 0x90: /* INTC_ISR_SET */
582 bank
->irqs
|= bank
->swi
|= value
;
583 omap_inth_update(s
, 0);
584 omap_inth_update(s
, 1);
587 case 0x94: /* INTC_ISR_CLEAR */
589 bank
->irqs
= bank
->swi
& bank
->inputs
;
592 /* Per-line registers */
593 case 0x100 ... 0x300: /* INTC_ILR */
594 bank_no
= (offset
- 0x100) >> 7;
595 if (bank_no
> s
->nbanks
)
597 bank
= &s
->bank
[bank_no
];
598 line_no
= (offset
& 0x7f) >> 2;
599 bank
->priority
[line_no
] = (value
>> 2) & 0x3f;
600 bank
->fiq
&= ~(1 << line_no
);
601 bank
->fiq
|= (value
& 1) << line_no
;
604 case 0x00: /* INTC_REVISION */
605 case 0x14: /* INTC_SYSSTATUS */
606 case 0x40: /* INTC_SIR_IRQ */
607 case 0x44: /* INTC_SIR_FIQ */
608 case 0x80: /* INTC_ITR */
609 case 0x98: /* INTC_PENDING_IRQ */
610 case 0x9c: /* INTC_PENDING_FIQ */
617 static CPUReadMemoryFunc
*omap2_inth_readfn
[] = {
618 omap_badwidth_read32
,
619 omap_badwidth_read32
,
623 static CPUWriteMemoryFunc
*omap2_inth_writefn
[] = {
629 struct omap_intr_handler_s
*omap2_inth_init(target_phys_addr_t base
,
630 int size
, int nbanks
, qemu_irq
**pins
,
631 qemu_irq parent_irq
, qemu_irq parent_fiq
,
632 omap_clk fclk
, omap_clk iclk
)
635 struct omap_intr_handler_s
*s
= (struct omap_intr_handler_s
*)
636 qemu_mallocz(sizeof(struct omap_intr_handler_s
) +
637 sizeof(struct omap_intr_handler_bank_s
) * nbanks
);
639 s
->parent_intr
[0] = parent_irq
;
640 s
->parent_intr
[1] = parent_fiq
;
643 s
->pins
= qemu_allocate_irqs(omap_set_intr_noedge
, s
, nbanks
* 32);
649 iomemtype
= cpu_register_io_memory(0, omap2_inth_readfn
,
650 omap2_inth_writefn
, s
);
651 cpu_register_physical_memory(base
, size
, iomemtype
);
657 struct omap_mpu_timer_s
{
674 static inline uint32_t omap_timer_read(struct omap_mpu_timer_s
*timer
)
676 uint64_t distance
= qemu_get_clock(vm_clock
) - timer
->time
;
678 if (timer
->st
&& timer
->enable
&& timer
->rate
)
679 return timer
->val
- muldiv64(distance
>> (timer
->ptv
+ 1),
680 timer
->rate
, ticks_per_sec
);
685 static inline void omap_timer_sync(struct omap_mpu_timer_s
*timer
)
687 timer
->val
= omap_timer_read(timer
);
688 timer
->time
= qemu_get_clock(vm_clock
);
691 static inline void omap_timer_update(struct omap_mpu_timer_s
*timer
)
695 if (timer
->enable
&& timer
->st
&& timer
->rate
) {
696 timer
->val
= timer
->reset_val
; /* Should skip this on clk enable */
697 expires
= muldiv64((uint64_t) timer
->val
<< (timer
->ptv
+ 1),
698 ticks_per_sec
, timer
->rate
);
700 /* If timer expiry would be sooner than in about 1 ms and
701 * auto-reload isn't set, then fire immediately. This is a hack
702 * to make systems like PalmOS run in acceptable time. PalmOS
703 * sets the interval to a very low value and polls the status bit
704 * in a busy loop when it wants to sleep just a couple of CPU
706 if (expires
> (ticks_per_sec
>> 10) || timer
->ar
)
707 qemu_mod_timer(timer
->timer
, timer
->time
+ expires
);
709 qemu_bh_schedule(timer
->tick
);
711 qemu_del_timer(timer
->timer
);
714 static void omap_timer_fire(void *opaque
)
716 struct omap_mpu_timer_s
*timer
= opaque
;
724 /* Edge-triggered irq */
725 qemu_irq_pulse(timer
->irq
);
728 static void omap_timer_tick(void *opaque
)
730 struct omap_mpu_timer_s
*timer
= (struct omap_mpu_timer_s
*) opaque
;
732 omap_timer_sync(timer
);
733 omap_timer_fire(timer
);
734 omap_timer_update(timer
);
737 static void omap_timer_clk_update(void *opaque
, int line
, int on
)
739 struct omap_mpu_timer_s
*timer
= (struct omap_mpu_timer_s
*) opaque
;
741 omap_timer_sync(timer
);
742 timer
->rate
= on
? omap_clk_getrate(timer
->clk
) : 0;
743 omap_timer_update(timer
);
746 static void omap_timer_clk_setup(struct omap_mpu_timer_s
*timer
)
748 omap_clk_adduser(timer
->clk
,
749 qemu_allocate_irqs(omap_timer_clk_update
, timer
, 1)[0]);
750 timer
->rate
= omap_clk_getrate(timer
->clk
);
753 static uint32_t omap_mpu_timer_read(void *opaque
, target_phys_addr_t addr
)
755 struct omap_mpu_timer_s
*s
= (struct omap_mpu_timer_s
*) opaque
;
758 case 0x00: /* CNTL_TIMER */
759 return (s
->enable
<< 5) | (s
->ptv
<< 2) | (s
->ar
<< 1) | s
->st
;
761 case 0x04: /* LOAD_TIM */
764 case 0x08: /* READ_TIM */
765 return omap_timer_read(s
);
772 static void omap_mpu_timer_write(void *opaque
, target_phys_addr_t addr
,
775 struct omap_mpu_timer_s
*s
= (struct omap_mpu_timer_s
*) opaque
;
778 case 0x00: /* CNTL_TIMER */
780 s
->enable
= (value
>> 5) & 1;
781 s
->ptv
= (value
>> 2) & 7;
782 s
->ar
= (value
>> 1) & 1;
784 omap_timer_update(s
);
787 case 0x04: /* LOAD_TIM */
788 s
->reset_val
= value
;
791 case 0x08: /* READ_TIM */
800 static CPUReadMemoryFunc
*omap_mpu_timer_readfn
[] = {
801 omap_badwidth_read32
,
802 omap_badwidth_read32
,
806 static CPUWriteMemoryFunc
*omap_mpu_timer_writefn
[] = {
807 omap_badwidth_write32
,
808 omap_badwidth_write32
,
809 omap_mpu_timer_write
,
812 static void omap_mpu_timer_reset(struct omap_mpu_timer_s
*s
)
814 qemu_del_timer(s
->timer
);
816 s
->reset_val
= 31337;
824 struct omap_mpu_timer_s
*omap_mpu_timer_init(target_phys_addr_t base
,
825 qemu_irq irq
, omap_clk clk
)
828 struct omap_mpu_timer_s
*s
= (struct omap_mpu_timer_s
*)
829 qemu_mallocz(sizeof(struct omap_mpu_timer_s
));
833 s
->timer
= qemu_new_timer(vm_clock
, omap_timer_tick
, s
);
834 s
->tick
= qemu_bh_new(omap_timer_fire
, s
);
835 omap_mpu_timer_reset(s
);
836 omap_timer_clk_setup(s
);
838 iomemtype
= cpu_register_io_memory(0, omap_mpu_timer_readfn
,
839 omap_mpu_timer_writefn
, s
);
840 cpu_register_physical_memory(base
, 0x100, iomemtype
);
846 struct omap_watchdog_timer_s
{
847 struct omap_mpu_timer_s timer
;
854 static uint32_t omap_wd_timer_read(void *opaque
, target_phys_addr_t addr
)
856 struct omap_watchdog_timer_s
*s
= (struct omap_watchdog_timer_s
*) opaque
;
859 case 0x00: /* CNTL_TIMER */
860 return (s
->timer
.ptv
<< 9) | (s
->timer
.ar
<< 8) |
861 (s
->timer
.st
<< 7) | (s
->free
<< 1);
863 case 0x04: /* READ_TIMER */
864 return omap_timer_read(&s
->timer
);
866 case 0x08: /* TIMER_MODE */
867 return s
->mode
<< 15;
874 static void omap_wd_timer_write(void *opaque
, target_phys_addr_t addr
,
877 struct omap_watchdog_timer_s
*s
= (struct omap_watchdog_timer_s
*) opaque
;
880 case 0x00: /* CNTL_TIMER */
881 omap_timer_sync(&s
->timer
);
882 s
->timer
.ptv
= (value
>> 9) & 7;
883 s
->timer
.ar
= (value
>> 8) & 1;
884 s
->timer
.st
= (value
>> 7) & 1;
885 s
->free
= (value
>> 1) & 1;
886 omap_timer_update(&s
->timer
);
889 case 0x04: /* LOAD_TIMER */
890 s
->timer
.reset_val
= value
& 0xffff;
893 case 0x08: /* TIMER_MODE */
894 if (!s
->mode
&& ((value
>> 15) & 1))
895 omap_clk_get(s
->timer
.clk
);
896 s
->mode
|= (value
>> 15) & 1;
897 if (s
->last_wr
== 0xf5) {
898 if ((value
& 0xff) == 0xa0) {
901 omap_clk_put(s
->timer
.clk
);
904 /* XXX: on T|E hardware somehow this has no effect,
905 * on Zire 71 it works as specified. */
907 qemu_system_reset_request();
910 s
->last_wr
= value
& 0xff;
918 static CPUReadMemoryFunc
*omap_wd_timer_readfn
[] = {
919 omap_badwidth_read16
,
921 omap_badwidth_read16
,
924 static CPUWriteMemoryFunc
*omap_wd_timer_writefn
[] = {
925 omap_badwidth_write16
,
927 omap_badwidth_write16
,
930 static void omap_wd_timer_reset(struct omap_watchdog_timer_s
*s
)
932 qemu_del_timer(s
->timer
.timer
);
934 omap_clk_get(s
->timer
.clk
);
940 s
->timer
.reset_val
= 0xffff;
945 omap_timer_update(&s
->timer
);
948 struct omap_watchdog_timer_s
*omap_wd_timer_init(target_phys_addr_t base
,
949 qemu_irq irq
, omap_clk clk
)
952 struct omap_watchdog_timer_s
*s
= (struct omap_watchdog_timer_s
*)
953 qemu_mallocz(sizeof(struct omap_watchdog_timer_s
));
957 s
->timer
.timer
= qemu_new_timer(vm_clock
, omap_timer_tick
, &s
->timer
);
958 omap_wd_timer_reset(s
);
959 omap_timer_clk_setup(&s
->timer
);
961 iomemtype
= cpu_register_io_memory(0, omap_wd_timer_readfn
,
962 omap_wd_timer_writefn
, s
);
963 cpu_register_physical_memory(base
, 0x100, iomemtype
);
969 struct omap_32khz_timer_s
{
970 struct omap_mpu_timer_s timer
;
973 static uint32_t omap_os_timer_read(void *opaque
, target_phys_addr_t addr
)
975 struct omap_32khz_timer_s
*s
= (struct omap_32khz_timer_s
*) opaque
;
976 int offset
= addr
& OMAP_MPUI_REG_MASK
;
980 return s
->timer
.reset_val
;
983 return omap_timer_read(&s
->timer
);
986 return (s
->timer
.ar
<< 3) | (s
->timer
.it_ena
<< 2) | s
->timer
.st
;
995 static void omap_os_timer_write(void *opaque
, target_phys_addr_t addr
,
998 struct omap_32khz_timer_s
*s
= (struct omap_32khz_timer_s
*) opaque
;
999 int offset
= addr
& OMAP_MPUI_REG_MASK
;
1002 case 0x00: /* TVR */
1003 s
->timer
.reset_val
= value
& 0x00ffffff;
1006 case 0x04: /* TCR */
1011 s
->timer
.ar
= (value
>> 3) & 1;
1012 s
->timer
.it_ena
= (value
>> 2) & 1;
1013 if (s
->timer
.st
!= (value
& 1) || (value
& 2)) {
1014 omap_timer_sync(&s
->timer
);
1015 s
->timer
.enable
= value
& 1;
1016 s
->timer
.st
= value
& 1;
1017 omap_timer_update(&s
->timer
);
1026 static CPUReadMemoryFunc
*omap_os_timer_readfn
[] = {
1027 omap_badwidth_read32
,
1028 omap_badwidth_read32
,
1032 static CPUWriteMemoryFunc
*omap_os_timer_writefn
[] = {
1033 omap_badwidth_write32
,
1034 omap_badwidth_write32
,
1035 omap_os_timer_write
,
1038 static void omap_os_timer_reset(struct omap_32khz_timer_s
*s
)
1040 qemu_del_timer(s
->timer
.timer
);
1041 s
->timer
.enable
= 0;
1042 s
->timer
.it_ena
= 0;
1043 s
->timer
.reset_val
= 0x00ffffff;
1050 struct omap_32khz_timer_s
*omap_os_timer_init(target_phys_addr_t base
,
1051 qemu_irq irq
, omap_clk clk
)
1054 struct omap_32khz_timer_s
*s
= (struct omap_32khz_timer_s
*)
1055 qemu_mallocz(sizeof(struct omap_32khz_timer_s
));
1059 s
->timer
.timer
= qemu_new_timer(vm_clock
, omap_timer_tick
, &s
->timer
);
1060 omap_os_timer_reset(s
);
1061 omap_timer_clk_setup(&s
->timer
);
1063 iomemtype
= cpu_register_io_memory(0, omap_os_timer_readfn
,
1064 omap_os_timer_writefn
, s
);
1065 cpu_register_physical_memory(base
, 0x800, iomemtype
);
1070 /* Ultra Low-Power Device Module */
1071 static uint32_t omap_ulpd_pm_read(void *opaque
, target_phys_addr_t addr
)
1073 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
1077 case 0x14: /* IT_STATUS */
1078 ret
= s
->ulpd_pm_regs
[addr
>> 2];
1079 s
->ulpd_pm_regs
[addr
>> 2] = 0;
1080 qemu_irq_lower(s
->irq
[1][OMAP_INT_GAUGE_32K
]);
1083 case 0x18: /* Reserved */
1084 case 0x1c: /* Reserved */
1085 case 0x20: /* Reserved */
1086 case 0x28: /* Reserved */
1087 case 0x2c: /* Reserved */
1089 case 0x00: /* COUNTER_32_LSB */
1090 case 0x04: /* COUNTER_32_MSB */
1091 case 0x08: /* COUNTER_HIGH_FREQ_LSB */
1092 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */
1093 case 0x10: /* GAUGING_CTRL */
1094 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */
1095 case 0x30: /* CLOCK_CTRL */
1096 case 0x34: /* SOFT_REQ */
1097 case 0x38: /* COUNTER_32_FIQ */
1098 case 0x3c: /* DPLL_CTRL */
1099 case 0x40: /* STATUS_REQ */
1100 /* XXX: check clk::usecount state for every clock */
1101 case 0x48: /* LOCL_TIME */
1102 case 0x4c: /* APLL_CTRL */
1103 case 0x50: /* POWER_CTRL */
1104 return s
->ulpd_pm_regs
[addr
>> 2];
1111 static inline void omap_ulpd_clk_update(struct omap_mpu_state_s
*s
,
1112 uint16_t diff
, uint16_t value
)
1114 if (diff
& (1 << 4)) /* USB_MCLK_EN */
1115 omap_clk_onoff(omap_findclk(s
, "usb_clk0"), (value
>> 4) & 1);
1116 if (diff
& (1 << 5)) /* DIS_USB_PVCI_CLK */
1117 omap_clk_onoff(omap_findclk(s
, "usb_w2fc_ck"), (~value
>> 5) & 1);
1120 static inline void omap_ulpd_req_update(struct omap_mpu_state_s
*s
,
1121 uint16_t diff
, uint16_t value
)
1123 if (diff
& (1 << 0)) /* SOFT_DPLL_REQ */
1124 omap_clk_canidle(omap_findclk(s
, "dpll4"), (~value
>> 0) & 1);
1125 if (diff
& (1 << 1)) /* SOFT_COM_REQ */
1126 omap_clk_canidle(omap_findclk(s
, "com_mclk_out"), (~value
>> 1) & 1);
1127 if (diff
& (1 << 2)) /* SOFT_SDW_REQ */
1128 omap_clk_canidle(omap_findclk(s
, "bt_mclk_out"), (~value
>> 2) & 1);
1129 if (diff
& (1 << 3)) /* SOFT_USB_REQ */
1130 omap_clk_canidle(omap_findclk(s
, "usb_clk0"), (~value
>> 3) & 1);
1133 static void omap_ulpd_pm_write(void *opaque
, target_phys_addr_t addr
,
1136 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
1139 static const int bypass_div
[4] = { 1, 2, 4, 4 };
1143 case 0x00: /* COUNTER_32_LSB */
1144 case 0x04: /* COUNTER_32_MSB */
1145 case 0x08: /* COUNTER_HIGH_FREQ_LSB */
1146 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */
1147 case 0x14: /* IT_STATUS */
1148 case 0x40: /* STATUS_REQ */
1152 case 0x10: /* GAUGING_CTRL */
1153 /* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */
1154 if ((s
->ulpd_pm_regs
[addr
>> 2] ^ value
) & 1) {
1155 now
= qemu_get_clock(vm_clock
);
1158 s
->ulpd_gauge_start
= now
;
1160 now
-= s
->ulpd_gauge_start
;
1163 ticks
= muldiv64(now
, 32768, ticks_per_sec
);
1164 s
->ulpd_pm_regs
[0x00 >> 2] = (ticks
>> 0) & 0xffff;
1165 s
->ulpd_pm_regs
[0x04 >> 2] = (ticks
>> 16) & 0xffff;
1166 if (ticks
>> 32) /* OVERFLOW_32K */
1167 s
->ulpd_pm_regs
[0x14 >> 2] |= 1 << 2;
1169 /* High frequency ticks */
1170 ticks
= muldiv64(now
, 12000000, ticks_per_sec
);
1171 s
->ulpd_pm_regs
[0x08 >> 2] = (ticks
>> 0) & 0xffff;
1172 s
->ulpd_pm_regs
[0x0c >> 2] = (ticks
>> 16) & 0xffff;
1173 if (ticks
>> 32) /* OVERFLOW_HI_FREQ */
1174 s
->ulpd_pm_regs
[0x14 >> 2] |= 1 << 1;
1176 s
->ulpd_pm_regs
[0x14 >> 2] |= 1 << 0; /* IT_GAUGING */
1177 qemu_irq_raise(s
->irq
[1][OMAP_INT_GAUGE_32K
]);
1180 s
->ulpd_pm_regs
[addr
>> 2] = value
;
1183 case 0x18: /* Reserved */
1184 case 0x1c: /* Reserved */
1185 case 0x20: /* Reserved */
1186 case 0x28: /* Reserved */
1187 case 0x2c: /* Reserved */
1189 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */
1190 case 0x38: /* COUNTER_32_FIQ */
1191 case 0x48: /* LOCL_TIME */
1192 case 0x50: /* POWER_CTRL */
1193 s
->ulpd_pm_regs
[addr
>> 2] = value
;
1196 case 0x30: /* CLOCK_CTRL */
1197 diff
= s
->ulpd_pm_regs
[addr
>> 2] ^ value
;
1198 s
->ulpd_pm_regs
[addr
>> 2] = value
& 0x3f;
1199 omap_ulpd_clk_update(s
, diff
, value
);
1202 case 0x34: /* SOFT_REQ */
1203 diff
= s
->ulpd_pm_regs
[addr
>> 2] ^ value
;
1204 s
->ulpd_pm_regs
[addr
>> 2] = value
& 0x1f;
1205 omap_ulpd_req_update(s
, diff
, value
);
1208 case 0x3c: /* DPLL_CTRL */
1209 /* XXX: OMAP310 TRM claims bit 3 is PLL_ENABLE, and bit 4 is
1210 * omitted altogether, probably a typo. */
1211 /* This register has identical semantics with DPLL(1:3) control
1212 * registers, see omap_dpll_write() */
1213 diff
= s
->ulpd_pm_regs
[addr
>> 2] & value
;
1214 s
->ulpd_pm_regs
[addr
>> 2] = value
& 0x2fff;
1215 if (diff
& (0x3ff << 2)) {
1216 if (value
& (1 << 4)) { /* PLL_ENABLE */
1217 div
= ((value
>> 5) & 3) + 1; /* PLL_DIV */
1218 mult
= MIN((value
>> 7) & 0x1f, 1); /* PLL_MULT */
1220 div
= bypass_div
[((value
>> 2) & 3)]; /* BYPASS_DIV */
1223 omap_clk_setrate(omap_findclk(s
, "dpll4"), div
, mult
);
1226 /* Enter the desired mode. */
1227 s
->ulpd_pm_regs
[addr
>> 2] =
1228 (s
->ulpd_pm_regs
[addr
>> 2] & 0xfffe) |
1229 ((s
->ulpd_pm_regs
[addr
>> 2] >> 4) & 1);
1231 /* Act as if the lock is restored. */
1232 s
->ulpd_pm_regs
[addr
>> 2] |= 2;
1235 case 0x4c: /* APLL_CTRL */
1236 diff
= s
->ulpd_pm_regs
[addr
>> 2] & value
;
1237 s
->ulpd_pm_regs
[addr
>> 2] = value
& 0xf;
1238 if (diff
& (1 << 0)) /* APLL_NDPLL_SWITCH */
1239 omap_clk_reparent(omap_findclk(s
, "ck_48m"), omap_findclk(s
,
1240 (value
& (1 << 0)) ? "apll" : "dpll4"));
1248 static CPUReadMemoryFunc
*omap_ulpd_pm_readfn
[] = {
1249 omap_badwidth_read16
,
1251 omap_badwidth_read16
,
1254 static CPUWriteMemoryFunc
*omap_ulpd_pm_writefn
[] = {
1255 omap_badwidth_write16
,
1257 omap_badwidth_write16
,
1260 static void omap_ulpd_pm_reset(struct omap_mpu_state_s
*mpu
)
1262 mpu
->ulpd_pm_regs
[0x00 >> 2] = 0x0001;
1263 mpu
->ulpd_pm_regs
[0x04 >> 2] = 0x0000;
1264 mpu
->ulpd_pm_regs
[0x08 >> 2] = 0x0001;
1265 mpu
->ulpd_pm_regs
[0x0c >> 2] = 0x0000;
1266 mpu
->ulpd_pm_regs
[0x10 >> 2] = 0x0000;
1267 mpu
->ulpd_pm_regs
[0x18 >> 2] = 0x01;
1268 mpu
->ulpd_pm_regs
[0x1c >> 2] = 0x01;
1269 mpu
->ulpd_pm_regs
[0x20 >> 2] = 0x01;
1270 mpu
->ulpd_pm_regs
[0x24 >> 2] = 0x03ff;
1271 mpu
->ulpd_pm_regs
[0x28 >> 2] = 0x01;
1272 mpu
->ulpd_pm_regs
[0x2c >> 2] = 0x01;
1273 omap_ulpd_clk_update(mpu
, mpu
->ulpd_pm_regs
[0x30 >> 2], 0x0000);
1274 mpu
->ulpd_pm_regs
[0x30 >> 2] = 0x0000;
1275 omap_ulpd_req_update(mpu
, mpu
->ulpd_pm_regs
[0x34 >> 2], 0x0000);
1276 mpu
->ulpd_pm_regs
[0x34 >> 2] = 0x0000;
1277 mpu
->ulpd_pm_regs
[0x38 >> 2] = 0x0001;
1278 mpu
->ulpd_pm_regs
[0x3c >> 2] = 0x2211;
1279 mpu
->ulpd_pm_regs
[0x40 >> 2] = 0x0000; /* FIXME: dump a real STATUS_REQ */
1280 mpu
->ulpd_pm_regs
[0x48 >> 2] = 0x960;
1281 mpu
->ulpd_pm_regs
[0x4c >> 2] = 0x08;
1282 mpu
->ulpd_pm_regs
[0x50 >> 2] = 0x08;
1283 omap_clk_setrate(omap_findclk(mpu
, "dpll4"), 1, 4);
1284 omap_clk_reparent(omap_findclk(mpu
, "ck_48m"), omap_findclk(mpu
, "dpll4"));
1287 static void omap_ulpd_pm_init(target_phys_addr_t base
,
1288 struct omap_mpu_state_s
*mpu
)
1290 int iomemtype
= cpu_register_io_memory(0, omap_ulpd_pm_readfn
,
1291 omap_ulpd_pm_writefn
, mpu
);
1293 cpu_register_physical_memory(base
, 0x800, iomemtype
);
1294 omap_ulpd_pm_reset(mpu
);
1297 /* OMAP Pin Configuration */
1298 static uint32_t omap_pin_cfg_read(void *opaque
, target_phys_addr_t addr
)
1300 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
1303 case 0x00: /* FUNC_MUX_CTRL_0 */
1304 case 0x04: /* FUNC_MUX_CTRL_1 */
1305 case 0x08: /* FUNC_MUX_CTRL_2 */
1306 return s
->func_mux_ctrl
[addr
>> 2];
1308 case 0x0c: /* COMP_MODE_CTRL_0 */
1309 return s
->comp_mode_ctrl
[0];
1311 case 0x10: /* FUNC_MUX_CTRL_3 */
1312 case 0x14: /* FUNC_MUX_CTRL_4 */
1313 case 0x18: /* FUNC_MUX_CTRL_5 */
1314 case 0x1c: /* FUNC_MUX_CTRL_6 */
1315 case 0x20: /* FUNC_MUX_CTRL_7 */
1316 case 0x24: /* FUNC_MUX_CTRL_8 */
1317 case 0x28: /* FUNC_MUX_CTRL_9 */
1318 case 0x2c: /* FUNC_MUX_CTRL_A */
1319 case 0x30: /* FUNC_MUX_CTRL_B */
1320 case 0x34: /* FUNC_MUX_CTRL_C */
1321 case 0x38: /* FUNC_MUX_CTRL_D */
1322 return s
->func_mux_ctrl
[(addr
>> 2) - 1];
1324 case 0x40: /* PULL_DWN_CTRL_0 */
1325 case 0x44: /* PULL_DWN_CTRL_1 */
1326 case 0x48: /* PULL_DWN_CTRL_2 */
1327 case 0x4c: /* PULL_DWN_CTRL_3 */
1328 return s
->pull_dwn_ctrl
[(addr
& 0xf) >> 2];
1330 case 0x50: /* GATE_INH_CTRL_0 */
1331 return s
->gate_inh_ctrl
[0];
1333 case 0x60: /* VOLTAGE_CTRL_0 */
1334 return s
->voltage_ctrl
[0];
1336 case 0x70: /* TEST_DBG_CTRL_0 */
1337 return s
->test_dbg_ctrl
[0];
1339 case 0x80: /* MOD_CONF_CTRL_0 */
1340 return s
->mod_conf_ctrl
[0];
1347 static inline void omap_pin_funcmux0_update(struct omap_mpu_state_s
*s
,
1348 uint32_t diff
, uint32_t value
)
1350 if (s
->compat1509
) {
1351 if (diff
& (1 << 9)) /* BLUETOOTH */
1352 omap_clk_onoff(omap_findclk(s
, "bt_mclk_out"),
1354 if (diff
& (1 << 7)) /* USB.CLKO */
1355 omap_clk_onoff(omap_findclk(s
, "usb.clko"),
1360 static inline void omap_pin_funcmux1_update(struct omap_mpu_state_s
*s
,
1361 uint32_t diff
, uint32_t value
)
1363 if (s
->compat1509
) {
1364 if (diff
& (1 << 31)) /* MCBSP3_CLK_HIZ_DI */
1365 omap_clk_onoff(omap_findclk(s
, "mcbsp3.clkx"),
1367 if (diff
& (1 << 1)) /* CLK32K */
1368 omap_clk_onoff(omap_findclk(s
, "clk32k_out"),
1373 static inline void omap_pin_modconf1_update(struct omap_mpu_state_s
*s
,
1374 uint32_t diff
, uint32_t value
)
1376 if (diff
& (1 << 31)) /* CONF_MOD_UART3_CLK_MODE_R */
1377 omap_clk_reparent(omap_findclk(s
, "uart3_ck"),
1378 omap_findclk(s
, ((value
>> 31) & 1) ?
1379 "ck_48m" : "armper_ck"));
1380 if (diff
& (1 << 30)) /* CONF_MOD_UART2_CLK_MODE_R */
1381 omap_clk_reparent(omap_findclk(s
, "uart2_ck"),
1382 omap_findclk(s
, ((value
>> 30) & 1) ?
1383 "ck_48m" : "armper_ck"));
1384 if (diff
& (1 << 29)) /* CONF_MOD_UART1_CLK_MODE_R */
1385 omap_clk_reparent(omap_findclk(s
, "uart1_ck"),
1386 omap_findclk(s
, ((value
>> 29) & 1) ?
1387 "ck_48m" : "armper_ck"));
1388 if (diff
& (1 << 23)) /* CONF_MOD_MMC_SD_CLK_REQ_R */
1389 omap_clk_reparent(omap_findclk(s
, "mmc_ck"),
1390 omap_findclk(s
, ((value
>> 23) & 1) ?
1391 "ck_48m" : "armper_ck"));
1392 if (diff
& (1 << 12)) /* CONF_MOD_COM_MCLK_12_48_S */
1393 omap_clk_reparent(omap_findclk(s
, "com_mclk_out"),
1394 omap_findclk(s
, ((value
>> 12) & 1) ?
1395 "ck_48m" : "armper_ck"));
1396 if (diff
& (1 << 9)) /* CONF_MOD_USB_HOST_HHC_UHO */
1397 omap_clk_onoff(omap_findclk(s
, "usb_hhc_ck"), (value
>> 9) & 1);
1400 static void omap_pin_cfg_write(void *opaque
, target_phys_addr_t addr
,
1403 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
1407 case 0x00: /* FUNC_MUX_CTRL_0 */
1408 diff
= s
->func_mux_ctrl
[addr
>> 2] ^ value
;
1409 s
->func_mux_ctrl
[addr
>> 2] = value
;
1410 omap_pin_funcmux0_update(s
, diff
, value
);
1413 case 0x04: /* FUNC_MUX_CTRL_1 */
1414 diff
= s
->func_mux_ctrl
[addr
>> 2] ^ value
;
1415 s
->func_mux_ctrl
[addr
>> 2] = value
;
1416 omap_pin_funcmux1_update(s
, diff
, value
);
1419 case 0x08: /* FUNC_MUX_CTRL_2 */
1420 s
->func_mux_ctrl
[addr
>> 2] = value
;
1423 case 0x0c: /* COMP_MODE_CTRL_0 */
1424 s
->comp_mode_ctrl
[0] = value
;
1425 s
->compat1509
= (value
!= 0x0000eaef);
1426 omap_pin_funcmux0_update(s
, ~0, s
->func_mux_ctrl
[0]);
1427 omap_pin_funcmux1_update(s
, ~0, s
->func_mux_ctrl
[1]);
1430 case 0x10: /* FUNC_MUX_CTRL_3 */
1431 case 0x14: /* FUNC_MUX_CTRL_4 */
1432 case 0x18: /* FUNC_MUX_CTRL_5 */
1433 case 0x1c: /* FUNC_MUX_CTRL_6 */
1434 case 0x20: /* FUNC_MUX_CTRL_7 */
1435 case 0x24: /* FUNC_MUX_CTRL_8 */
1436 case 0x28: /* FUNC_MUX_CTRL_9 */
1437 case 0x2c: /* FUNC_MUX_CTRL_A */
1438 case 0x30: /* FUNC_MUX_CTRL_B */
1439 case 0x34: /* FUNC_MUX_CTRL_C */
1440 case 0x38: /* FUNC_MUX_CTRL_D */
1441 s
->func_mux_ctrl
[(addr
>> 2) - 1] = value
;
1444 case 0x40: /* PULL_DWN_CTRL_0 */
1445 case 0x44: /* PULL_DWN_CTRL_1 */
1446 case 0x48: /* PULL_DWN_CTRL_2 */
1447 case 0x4c: /* PULL_DWN_CTRL_3 */
1448 s
->pull_dwn_ctrl
[(addr
& 0xf) >> 2] = value
;
1451 case 0x50: /* GATE_INH_CTRL_0 */
1452 s
->gate_inh_ctrl
[0] = value
;
1455 case 0x60: /* VOLTAGE_CTRL_0 */
1456 s
->voltage_ctrl
[0] = value
;
1459 case 0x70: /* TEST_DBG_CTRL_0 */
1460 s
->test_dbg_ctrl
[0] = value
;
1463 case 0x80: /* MOD_CONF_CTRL_0 */
1464 diff
= s
->mod_conf_ctrl
[0] ^ value
;
1465 s
->mod_conf_ctrl
[0] = value
;
1466 omap_pin_modconf1_update(s
, diff
, value
);
1474 static CPUReadMemoryFunc
*omap_pin_cfg_readfn
[] = {
1475 omap_badwidth_read32
,
1476 omap_badwidth_read32
,
1480 static CPUWriteMemoryFunc
*omap_pin_cfg_writefn
[] = {
1481 omap_badwidth_write32
,
1482 omap_badwidth_write32
,
1486 static void omap_pin_cfg_reset(struct omap_mpu_state_s
*mpu
)
1488 /* Start in Compatibility Mode. */
1489 mpu
->compat1509
= 1;
1490 omap_pin_funcmux0_update(mpu
, mpu
->func_mux_ctrl
[0], 0);
1491 omap_pin_funcmux1_update(mpu
, mpu
->func_mux_ctrl
[1], 0);
1492 omap_pin_modconf1_update(mpu
, mpu
->mod_conf_ctrl
[0], 0);
1493 memset(mpu
->func_mux_ctrl
, 0, sizeof(mpu
->func_mux_ctrl
));
1494 memset(mpu
->comp_mode_ctrl
, 0, sizeof(mpu
->comp_mode_ctrl
));
1495 memset(mpu
->pull_dwn_ctrl
, 0, sizeof(mpu
->pull_dwn_ctrl
));
1496 memset(mpu
->gate_inh_ctrl
, 0, sizeof(mpu
->gate_inh_ctrl
));
1497 memset(mpu
->voltage_ctrl
, 0, sizeof(mpu
->voltage_ctrl
));
1498 memset(mpu
->test_dbg_ctrl
, 0, sizeof(mpu
->test_dbg_ctrl
));
1499 memset(mpu
->mod_conf_ctrl
, 0, sizeof(mpu
->mod_conf_ctrl
));
1502 static void omap_pin_cfg_init(target_phys_addr_t base
,
1503 struct omap_mpu_state_s
*mpu
)
1505 int iomemtype
= cpu_register_io_memory(0, omap_pin_cfg_readfn
,
1506 omap_pin_cfg_writefn
, mpu
);
1508 cpu_register_physical_memory(base
, 0x800, iomemtype
);
1509 omap_pin_cfg_reset(mpu
);
1512 /* Device Identification, Die Identification */
1513 static uint32_t omap_id_read(void *opaque
, target_phys_addr_t addr
)
1515 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
1518 case 0xfffe1800: /* DIE_ID_LSB */
1520 case 0xfffe1804: /* DIE_ID_MSB */
1523 case 0xfffe2000: /* PRODUCT_ID_LSB */
1525 case 0xfffe2004: /* PRODUCT_ID_MSB */
1528 case 0xfffed400: /* JTAG_ID_LSB */
1529 switch (s
->mpu_model
) {
1535 cpu_abort(cpu_single_env
, "%s: bad mpu model\n", __FUNCTION__
);
1539 case 0xfffed404: /* JTAG_ID_MSB */
1540 switch (s
->mpu_model
) {
1546 cpu_abort(cpu_single_env
, "%s: bad mpu model\n", __FUNCTION__
);
1555 static void omap_id_write(void *opaque
, target_phys_addr_t addr
,
1561 static CPUReadMemoryFunc
*omap_id_readfn
[] = {
1562 omap_badwidth_read32
,
1563 omap_badwidth_read32
,
1567 static CPUWriteMemoryFunc
*omap_id_writefn
[] = {
1568 omap_badwidth_write32
,
1569 omap_badwidth_write32
,
1573 static void omap_id_init(struct omap_mpu_state_s
*mpu
)
1575 int iomemtype
= cpu_register_io_memory(0, omap_id_readfn
,
1576 omap_id_writefn
, mpu
);
1577 cpu_register_physical_memory_offset(0xfffe1800, 0x800, iomemtype
, 0xfffe1800);
1578 cpu_register_physical_memory_offset(0xfffed400, 0x100, iomemtype
, 0xfffed400);
1579 if (!cpu_is_omap15xx(mpu
))
1580 cpu_register_physical_memory_offset(0xfffe2000, 0x800, iomemtype
, 0xfffe2000);
1583 /* MPUI Control (Dummy) */
1584 static uint32_t omap_mpui_read(void *opaque
, target_phys_addr_t addr
)
1586 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
1589 case 0x00: /* CTRL */
1590 return s
->mpui_ctrl
;
1591 case 0x04: /* DEBUG_ADDR */
1593 case 0x08: /* DEBUG_DATA */
1595 case 0x0c: /* DEBUG_FLAG */
1597 case 0x10: /* STATUS */
1600 /* Not in OMAP310 */
1601 case 0x14: /* DSP_STATUS */
1602 case 0x18: /* DSP_BOOT_CONFIG */
1604 case 0x1c: /* DSP_MPUI_CONFIG */
1612 static void omap_mpui_write(void *opaque
, target_phys_addr_t addr
,
1615 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
1618 case 0x00: /* CTRL */
1619 s
->mpui_ctrl
= value
& 0x007fffff;
1622 case 0x04: /* DEBUG_ADDR */
1623 case 0x08: /* DEBUG_DATA */
1624 case 0x0c: /* DEBUG_FLAG */
1625 case 0x10: /* STATUS */
1626 /* Not in OMAP310 */
1627 case 0x14: /* DSP_STATUS */
1629 case 0x18: /* DSP_BOOT_CONFIG */
1630 case 0x1c: /* DSP_MPUI_CONFIG */
1638 static CPUReadMemoryFunc
*omap_mpui_readfn
[] = {
1639 omap_badwidth_read32
,
1640 omap_badwidth_read32
,
1644 static CPUWriteMemoryFunc
*omap_mpui_writefn
[] = {
1645 omap_badwidth_write32
,
1646 omap_badwidth_write32
,
1650 static void omap_mpui_reset(struct omap_mpu_state_s
*s
)
1652 s
->mpui_ctrl
= 0x0003ff1b;
1655 static void omap_mpui_init(target_phys_addr_t base
,
1656 struct omap_mpu_state_s
*mpu
)
1658 int iomemtype
= cpu_register_io_memory(0, omap_mpui_readfn
,
1659 omap_mpui_writefn
, mpu
);
1661 cpu_register_physical_memory(base
, 0x100, iomemtype
);
1663 omap_mpui_reset(mpu
);
1667 struct omap_tipb_bridge_s
{
1674 uint16_t enh_control
;
1677 static uint32_t omap_tipb_bridge_read(void *opaque
, target_phys_addr_t addr
)
1679 struct omap_tipb_bridge_s
*s
= (struct omap_tipb_bridge_s
*) opaque
;
1682 case 0x00: /* TIPB_CNTL */
1684 case 0x04: /* TIPB_BUS_ALLOC */
1686 case 0x08: /* MPU_TIPB_CNTL */
1688 case 0x0c: /* ENHANCED_TIPB_CNTL */
1689 return s
->enh_control
;
1690 case 0x10: /* ADDRESS_DBG */
1691 case 0x14: /* DATA_DEBUG_LOW */
1692 case 0x18: /* DATA_DEBUG_HIGH */
1694 case 0x1c: /* DEBUG_CNTR_SIG */
1702 static void omap_tipb_bridge_write(void *opaque
, target_phys_addr_t addr
,
1705 struct omap_tipb_bridge_s
*s
= (struct omap_tipb_bridge_s
*) opaque
;
1708 case 0x00: /* TIPB_CNTL */
1709 s
->control
= value
& 0xffff;
1712 case 0x04: /* TIPB_BUS_ALLOC */
1713 s
->alloc
= value
& 0x003f;
1716 case 0x08: /* MPU_TIPB_CNTL */
1717 s
->buffer
= value
& 0x0003;
1720 case 0x0c: /* ENHANCED_TIPB_CNTL */
1721 s
->width_intr
= !(value
& 2);
1722 s
->enh_control
= value
& 0x000f;
1725 case 0x10: /* ADDRESS_DBG */
1726 case 0x14: /* DATA_DEBUG_LOW */
1727 case 0x18: /* DATA_DEBUG_HIGH */
1728 case 0x1c: /* DEBUG_CNTR_SIG */
1737 static CPUReadMemoryFunc
*omap_tipb_bridge_readfn
[] = {
1738 omap_badwidth_read16
,
1739 omap_tipb_bridge_read
,
1740 omap_tipb_bridge_read
,
1743 static CPUWriteMemoryFunc
*omap_tipb_bridge_writefn
[] = {
1744 omap_badwidth_write16
,
1745 omap_tipb_bridge_write
,
1746 omap_tipb_bridge_write
,
1749 static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s
*s
)
1751 s
->control
= 0xffff;
1754 s
->enh_control
= 0x000f;
1757 struct omap_tipb_bridge_s
*omap_tipb_bridge_init(target_phys_addr_t base
,
1758 qemu_irq abort_irq
, omap_clk clk
)
1761 struct omap_tipb_bridge_s
*s
= (struct omap_tipb_bridge_s
*)
1762 qemu_mallocz(sizeof(struct omap_tipb_bridge_s
));
1764 s
->abort
= abort_irq
;
1765 omap_tipb_bridge_reset(s
);
1767 iomemtype
= cpu_register_io_memory(0, omap_tipb_bridge_readfn
,
1768 omap_tipb_bridge_writefn
, s
);
1769 cpu_register_physical_memory(base
, 0x100, iomemtype
);
1774 /* Dummy Traffic Controller's Memory Interface */
1775 static uint32_t omap_tcmi_read(void *opaque
, target_phys_addr_t addr
)
1777 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
1781 case 0x00: /* IMIF_PRIO */
1782 case 0x04: /* EMIFS_PRIO */
1783 case 0x08: /* EMIFF_PRIO */
1784 case 0x0c: /* EMIFS_CONFIG */
1785 case 0x10: /* EMIFS_CS0_CONFIG */
1786 case 0x14: /* EMIFS_CS1_CONFIG */
1787 case 0x18: /* EMIFS_CS2_CONFIG */
1788 case 0x1c: /* EMIFS_CS3_CONFIG */
1789 case 0x24: /* EMIFF_MRS */
1790 case 0x28: /* TIMEOUT1 */
1791 case 0x2c: /* TIMEOUT2 */
1792 case 0x30: /* TIMEOUT3 */
1793 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */
1794 case 0x40: /* EMIFS_CFG_DYN_WAIT */
1795 return s
->tcmi_regs
[addr
>> 2];
1797 case 0x20: /* EMIFF_SDRAM_CONFIG */
1798 ret
= s
->tcmi_regs
[addr
>> 2];
1799 s
->tcmi_regs
[addr
>> 2] &= ~1; /* XXX: Clear SLRF on SDRAM access */
1800 /* XXX: We can try using the VGA_DIRTY flag for this */
1808 static void omap_tcmi_write(void *opaque
, target_phys_addr_t addr
,
1811 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
1814 case 0x00: /* IMIF_PRIO */
1815 case 0x04: /* EMIFS_PRIO */
1816 case 0x08: /* EMIFF_PRIO */
1817 case 0x10: /* EMIFS_CS0_CONFIG */
1818 case 0x14: /* EMIFS_CS1_CONFIG */
1819 case 0x18: /* EMIFS_CS2_CONFIG */
1820 case 0x1c: /* EMIFS_CS3_CONFIG */
1821 case 0x20: /* EMIFF_SDRAM_CONFIG */
1822 case 0x24: /* EMIFF_MRS */
1823 case 0x28: /* TIMEOUT1 */
1824 case 0x2c: /* TIMEOUT2 */
1825 case 0x30: /* TIMEOUT3 */
1826 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */
1827 case 0x40: /* EMIFS_CFG_DYN_WAIT */
1828 s
->tcmi_regs
[addr
>> 2] = value
;
1830 case 0x0c: /* EMIFS_CONFIG */
1831 s
->tcmi_regs
[addr
>> 2] = (value
& 0xf) | (1 << 4);
1839 static CPUReadMemoryFunc
*omap_tcmi_readfn
[] = {
1840 omap_badwidth_read32
,
1841 omap_badwidth_read32
,
1845 static CPUWriteMemoryFunc
*omap_tcmi_writefn
[] = {
1846 omap_badwidth_write32
,
1847 omap_badwidth_write32
,
1851 static void omap_tcmi_reset(struct omap_mpu_state_s
*mpu
)
1853 mpu
->tcmi_regs
[0x00 >> 2] = 0x00000000;
1854 mpu
->tcmi_regs
[0x04 >> 2] = 0x00000000;
1855 mpu
->tcmi_regs
[0x08 >> 2] = 0x00000000;
1856 mpu
->tcmi_regs
[0x0c >> 2] = 0x00000010;
1857 mpu
->tcmi_regs
[0x10 >> 2] = 0x0010fffb;
1858 mpu
->tcmi_regs
[0x14 >> 2] = 0x0010fffb;
1859 mpu
->tcmi_regs
[0x18 >> 2] = 0x0010fffb;
1860 mpu
->tcmi_regs
[0x1c >> 2] = 0x0010fffb;
1861 mpu
->tcmi_regs
[0x20 >> 2] = 0x00618800;
1862 mpu
->tcmi_regs
[0x24 >> 2] = 0x00000037;
1863 mpu
->tcmi_regs
[0x28 >> 2] = 0x00000000;
1864 mpu
->tcmi_regs
[0x2c >> 2] = 0x00000000;
1865 mpu
->tcmi_regs
[0x30 >> 2] = 0x00000000;
1866 mpu
->tcmi_regs
[0x3c >> 2] = 0x00000003;
1867 mpu
->tcmi_regs
[0x40 >> 2] = 0x00000000;
1870 static void omap_tcmi_init(target_phys_addr_t base
,
1871 struct omap_mpu_state_s
*mpu
)
1873 int iomemtype
= cpu_register_io_memory(0, omap_tcmi_readfn
,
1874 omap_tcmi_writefn
, mpu
);
1876 cpu_register_physical_memory(base
, 0x100, iomemtype
);
1877 omap_tcmi_reset(mpu
);
1880 /* Digital phase-locked loops control */
1881 static uint32_t omap_dpll_read(void *opaque
, target_phys_addr_t addr
)
1883 struct dpll_ctl_s
*s
= (struct dpll_ctl_s
*) opaque
;
1885 if (addr
== 0x00) /* CTL_REG */
1892 static void omap_dpll_write(void *opaque
, target_phys_addr_t addr
,
1895 struct dpll_ctl_s
*s
= (struct dpll_ctl_s
*) opaque
;
1897 static const int bypass_div
[4] = { 1, 2, 4, 4 };
1900 if (addr
== 0x00) { /* CTL_REG */
1901 /* See omap_ulpd_pm_write() too */
1902 diff
= s
->mode
& value
;
1903 s
->mode
= value
& 0x2fff;
1904 if (diff
& (0x3ff << 2)) {
1905 if (value
& (1 << 4)) { /* PLL_ENABLE */
1906 div
= ((value
>> 5) & 3) + 1; /* PLL_DIV */
1907 mult
= MIN((value
>> 7) & 0x1f, 1); /* PLL_MULT */
1909 div
= bypass_div
[((value
>> 2) & 3)]; /* BYPASS_DIV */
1912 omap_clk_setrate(s
->dpll
, div
, mult
);
1915 /* Enter the desired mode. */
1916 s
->mode
= (s
->mode
& 0xfffe) | ((s
->mode
>> 4) & 1);
1918 /* Act as if the lock is restored. */
1925 static CPUReadMemoryFunc
*omap_dpll_readfn
[] = {
1926 omap_badwidth_read16
,
1928 omap_badwidth_read16
,
1931 static CPUWriteMemoryFunc
*omap_dpll_writefn
[] = {
1932 omap_badwidth_write16
,
1934 omap_badwidth_write16
,
1937 static void omap_dpll_reset(struct dpll_ctl_s
*s
)
1940 omap_clk_setrate(s
->dpll
, 1, 1);
1943 static void omap_dpll_init(struct dpll_ctl_s
*s
, target_phys_addr_t base
,
1946 int iomemtype
= cpu_register_io_memory(0, omap_dpll_readfn
,
1947 omap_dpll_writefn
, s
);
1952 cpu_register_physical_memory(base
, 0x100, iomemtype
);
1956 struct omap_uart_s
{
1957 target_phys_addr_t base
;
1958 SerialState
*serial
; /* TODO */
1959 struct omap_target_agent_s
*ta
;
1971 void omap_uart_reset(struct omap_uart_s
*s
)
1979 struct omap_uart_s
*omap_uart_init(target_phys_addr_t base
,
1980 qemu_irq irq
, omap_clk fclk
, omap_clk iclk
,
1981 qemu_irq txdma
, qemu_irq rxdma
, CharDriverState
*chr
)
1983 struct omap_uart_s
*s
= (struct omap_uart_s
*)
1984 qemu_mallocz(sizeof(struct omap_uart_s
));
1989 s
->serial
= serial_mm_init(base
, 2, irq
, omap_clk_getrate(fclk
)/16,
1990 chr
?: qemu_chr_open("null", "null"), 1);
1995 static uint32_t omap_uart_read(void *opaque
, target_phys_addr_t addr
)
1997 struct omap_uart_s
*s
= (struct omap_uart_s
*) opaque
;
2001 case 0x20: /* MDR1 */
2003 case 0x24: /* MDR2 */
2005 case 0x40: /* SCR */
2007 case 0x44: /* SSR */
2009 case 0x48: /* EBLR */
2011 case 0x50: /* MVR */
2013 case 0x54: /* SYSC */
2014 return s
->syscontrol
;
2015 case 0x58: /* SYSS */
2017 case 0x5c: /* WER */
2019 case 0x60: /* CFPS */
2027 static void omap_uart_write(void *opaque
, target_phys_addr_t addr
,
2030 struct omap_uart_s
*s
= (struct omap_uart_s
*) opaque
;
2034 case 0x20: /* MDR1 */
2035 s
->mdr
[0] = value
& 0x7f;
2037 case 0x24: /* MDR2 */
2038 s
->mdr
[1] = value
& 0xff;
2040 case 0x40: /* SCR */
2041 s
->scr
= value
& 0xff;
2043 case 0x48: /* EBLR */
2044 s
->eblr
= value
& 0xff;
2046 case 0x44: /* SSR */
2047 case 0x50: /* MVR */
2048 case 0x58: /* SYSS */
2051 case 0x54: /* SYSC */
2052 s
->syscontrol
= value
& 0x1d;
2056 case 0x5c: /* WER */
2057 s
->wkup
= value
& 0x7f;
2059 case 0x60: /* CFPS */
2060 s
->cfps
= value
& 0xff;
2067 static CPUReadMemoryFunc
*omap_uart_readfn
[] = {
2070 omap_badwidth_read8
,
2073 static CPUWriteMemoryFunc
*omap_uart_writefn
[] = {
2076 omap_badwidth_write8
,
2079 struct omap_uart_s
*omap2_uart_init(struct omap_target_agent_s
*ta
,
2080 qemu_irq irq
, omap_clk fclk
, omap_clk iclk
,
2081 qemu_irq txdma
, qemu_irq rxdma
, CharDriverState
*chr
)
2083 target_phys_addr_t base
= omap_l4_attach(ta
, 0, 0);
2084 struct omap_uart_s
*s
= omap_uart_init(base
, irq
,
2085 fclk
, iclk
, txdma
, rxdma
, chr
);
2086 int iomemtype
= cpu_register_io_memory(0, omap_uart_readfn
,
2087 omap_uart_writefn
, s
);
2091 cpu_register_physical_memory(base
+ 0x20, 0x100, iomemtype
);
2096 void omap_uart_attach(struct omap_uart_s
*s
, CharDriverState
*chr
)
2098 /* TODO: Should reuse or destroy current s->serial */
2099 s
->serial
= serial_mm_init(s
->base
, 2, s
->irq
,
2100 omap_clk_getrate(s
->fclk
) / 16,
2101 chr
?: qemu_chr_open("null", "null"), 1);
2104 /* MPU Clock/Reset/Power Mode Control */
2105 static uint32_t omap_clkm_read(void *opaque
, target_phys_addr_t addr
)
2107 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
2110 case 0x00: /* ARM_CKCTL */
2111 return s
->clkm
.arm_ckctl
;
2113 case 0x04: /* ARM_IDLECT1 */
2114 return s
->clkm
.arm_idlect1
;
2116 case 0x08: /* ARM_IDLECT2 */
2117 return s
->clkm
.arm_idlect2
;
2119 case 0x0c: /* ARM_EWUPCT */
2120 return s
->clkm
.arm_ewupct
;
2122 case 0x10: /* ARM_RSTCT1 */
2123 return s
->clkm
.arm_rstct1
;
2125 case 0x14: /* ARM_RSTCT2 */
2126 return s
->clkm
.arm_rstct2
;
2128 case 0x18: /* ARM_SYSST */
2129 return (s
->clkm
.clocking_scheme
<< 11) | s
->clkm
.cold_start
;
2131 case 0x1c: /* ARM_CKOUT1 */
2132 return s
->clkm
.arm_ckout1
;
2134 case 0x20: /* ARM_CKOUT2 */
2142 static inline void omap_clkm_ckctl_update(struct omap_mpu_state_s
*s
,
2143 uint16_t diff
, uint16_t value
)
2147 if (diff
& (1 << 14)) { /* ARM_INTHCK_SEL */
2148 if (value
& (1 << 14))
2151 clk
= omap_findclk(s
, "arminth_ck");
2152 omap_clk_reparent(clk
, omap_findclk(s
, "tc_ck"));
2155 if (diff
& (1 << 12)) { /* ARM_TIMXO */
2156 clk
= omap_findclk(s
, "armtim_ck");
2157 if (value
& (1 << 12))
2158 omap_clk_reparent(clk
, omap_findclk(s
, "clkin"));
2160 omap_clk_reparent(clk
, omap_findclk(s
, "ck_gen1"));
2163 if (diff
& (3 << 10)) { /* DSPMMUDIV */
2164 clk
= omap_findclk(s
, "dspmmu_ck");
2165 omap_clk_setrate(clk
, 1 << ((value
>> 10) & 3), 1);
2167 if (diff
& (3 << 8)) { /* TCDIV */
2168 clk
= omap_findclk(s
, "tc_ck");
2169 omap_clk_setrate(clk
, 1 << ((value
>> 8) & 3), 1);
2171 if (diff
& (3 << 6)) { /* DSPDIV */
2172 clk
= omap_findclk(s
, "dsp_ck");
2173 omap_clk_setrate(clk
, 1 << ((value
>> 6) & 3), 1);
2175 if (diff
& (3 << 4)) { /* ARMDIV */
2176 clk
= omap_findclk(s
, "arm_ck");
2177 omap_clk_setrate(clk
, 1 << ((value
>> 4) & 3), 1);
2179 if (diff
& (3 << 2)) { /* LCDDIV */
2180 clk
= omap_findclk(s
, "lcd_ck");
2181 omap_clk_setrate(clk
, 1 << ((value
>> 2) & 3), 1);
2183 if (diff
& (3 << 0)) { /* PERDIV */
2184 clk
= omap_findclk(s
, "armper_ck");
2185 omap_clk_setrate(clk
, 1 << ((value
>> 0) & 3), 1);
2189 static inline void omap_clkm_idlect1_update(struct omap_mpu_state_s
*s
,
2190 uint16_t diff
, uint16_t value
)
2194 if (value
& (1 << 11)) /* SETARM_IDLE */
2195 cpu_interrupt(s
->env
, CPU_INTERRUPT_HALT
);
2196 if (!(value
& (1 << 10))) /* WKUP_MODE */
2197 qemu_system_shutdown_request(); /* XXX: disable wakeup from IRQ */
2199 #define SET_CANIDLE(clock, bit) \
2200 if (diff & (1 << bit)) { \
2201 clk = omap_findclk(s, clock); \
2202 omap_clk_canidle(clk, (value >> bit) & 1); \
2204 SET_CANIDLE("mpuwd_ck", 0) /* IDLWDT_ARM */
2205 SET_CANIDLE("armxor_ck", 1) /* IDLXORP_ARM */
2206 SET_CANIDLE("mpuper_ck", 2) /* IDLPER_ARM */
2207 SET_CANIDLE("lcd_ck", 3) /* IDLLCD_ARM */
2208 SET_CANIDLE("lb_ck", 4) /* IDLLB_ARM */
2209 SET_CANIDLE("hsab_ck", 5) /* IDLHSAB_ARM */
2210 SET_CANIDLE("tipb_ck", 6) /* IDLIF_ARM */
2211 SET_CANIDLE("dma_ck", 6) /* IDLIF_ARM */
2212 SET_CANIDLE("tc_ck", 6) /* IDLIF_ARM */
2213 SET_CANIDLE("dpll1", 7) /* IDLDPLL_ARM */
2214 SET_CANIDLE("dpll2", 7) /* IDLDPLL_ARM */
2215 SET_CANIDLE("dpll3", 7) /* IDLDPLL_ARM */
2216 SET_CANIDLE("mpui_ck", 8) /* IDLAPI_ARM */
2217 SET_CANIDLE("armtim_ck", 9) /* IDLTIM_ARM */
2220 static inline void omap_clkm_idlect2_update(struct omap_mpu_state_s
*s
,
2221 uint16_t diff
, uint16_t value
)
2225 #define SET_ONOFF(clock, bit) \
2226 if (diff & (1 << bit)) { \
2227 clk = omap_findclk(s, clock); \
2228 omap_clk_onoff(clk, (value >> bit) & 1); \
2230 SET_ONOFF("mpuwd_ck", 0) /* EN_WDTCK */
2231 SET_ONOFF("armxor_ck", 1) /* EN_XORPCK */
2232 SET_ONOFF("mpuper_ck", 2) /* EN_PERCK */
2233 SET_ONOFF("lcd_ck", 3) /* EN_LCDCK */
2234 SET_ONOFF("lb_ck", 4) /* EN_LBCK */
2235 SET_ONOFF("hsab_ck", 5) /* EN_HSABCK */
2236 SET_ONOFF("mpui_ck", 6) /* EN_APICK */
2237 SET_ONOFF("armtim_ck", 7) /* EN_TIMCK */
2238 SET_CANIDLE("dma_ck", 8) /* DMACK_REQ */
2239 SET_ONOFF("arm_gpio_ck", 9) /* EN_GPIOCK */
2240 SET_ONOFF("lbfree_ck", 10) /* EN_LBFREECK */
2243 static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s
*s
,
2244 uint16_t diff
, uint16_t value
)
2248 if (diff
& (3 << 4)) { /* TCLKOUT */
2249 clk
= omap_findclk(s
, "tclk_out");
2250 switch ((value
>> 4) & 3) {
2252 omap_clk_reparent(clk
, omap_findclk(s
, "ck_gen3"));
2253 omap_clk_onoff(clk
, 1);
2256 omap_clk_reparent(clk
, omap_findclk(s
, "tc_ck"));
2257 omap_clk_onoff(clk
, 1);
2260 omap_clk_onoff(clk
, 0);
2263 if (diff
& (3 << 2)) { /* DCLKOUT */
2264 clk
= omap_findclk(s
, "dclk_out");
2265 switch ((value
>> 2) & 3) {
2267 omap_clk_reparent(clk
, omap_findclk(s
, "dspmmu_ck"));
2270 omap_clk_reparent(clk
, omap_findclk(s
, "ck_gen2"));
2273 omap_clk_reparent(clk
, omap_findclk(s
, "dsp_ck"));
2276 omap_clk_reparent(clk
, omap_findclk(s
, "ck_ref14"));
2280 if (diff
& (3 << 0)) { /* ACLKOUT */
2281 clk
= omap_findclk(s
, "aclk_out");
2282 switch ((value
>> 0) & 3) {
2284 omap_clk_reparent(clk
, omap_findclk(s
, "ck_gen1"));
2285 omap_clk_onoff(clk
, 1);
2288 omap_clk_reparent(clk
, omap_findclk(s
, "arm_ck"));
2289 omap_clk_onoff(clk
, 1);
2292 omap_clk_reparent(clk
, omap_findclk(s
, "ck_ref14"));
2293 omap_clk_onoff(clk
, 1);
2296 omap_clk_onoff(clk
, 0);
2301 static void omap_clkm_write(void *opaque
, target_phys_addr_t addr
,
2304 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
2307 static const char *clkschemename
[8] = {
2308 "fully synchronous", "fully asynchronous", "synchronous scalable",
2309 "mix mode 1", "mix mode 2", "bypass mode", "mix mode 3", "mix mode 4",
2313 case 0x00: /* ARM_CKCTL */
2314 diff
= s
->clkm
.arm_ckctl
^ value
;
2315 s
->clkm
.arm_ckctl
= value
& 0x7fff;
2316 omap_clkm_ckctl_update(s
, diff
, value
);
2319 case 0x04: /* ARM_IDLECT1 */
2320 diff
= s
->clkm
.arm_idlect1
^ value
;
2321 s
->clkm
.arm_idlect1
= value
& 0x0fff;
2322 omap_clkm_idlect1_update(s
, diff
, value
);
2325 case 0x08: /* ARM_IDLECT2 */
2326 diff
= s
->clkm
.arm_idlect2
^ value
;
2327 s
->clkm
.arm_idlect2
= value
& 0x07ff;
2328 omap_clkm_idlect2_update(s
, diff
, value
);
2331 case 0x0c: /* ARM_EWUPCT */
2332 diff
= s
->clkm
.arm_ewupct
^ value
;
2333 s
->clkm
.arm_ewupct
= value
& 0x003f;
2336 case 0x10: /* ARM_RSTCT1 */
2337 diff
= s
->clkm
.arm_rstct1
^ value
;
2338 s
->clkm
.arm_rstct1
= value
& 0x0007;
2340 qemu_system_reset_request();
2341 s
->clkm
.cold_start
= 0xa;
2343 if (diff
& ~value
& 4) { /* DSP_RST */
2345 omap_tipb_bridge_reset(s
->private_tipb
);
2346 omap_tipb_bridge_reset(s
->public_tipb
);
2348 if (diff
& 2) { /* DSP_EN */
2349 clk
= omap_findclk(s
, "dsp_ck");
2350 omap_clk_canidle(clk
, (~value
>> 1) & 1);
2354 case 0x14: /* ARM_RSTCT2 */
2355 s
->clkm
.arm_rstct2
= value
& 0x0001;
2358 case 0x18: /* ARM_SYSST */
2359 if ((s
->clkm
.clocking_scheme
^ (value
>> 11)) & 7) {
2360 s
->clkm
.clocking_scheme
= (value
>> 11) & 7;
2361 printf("%s: clocking scheme set to %s\n", __FUNCTION__
,
2362 clkschemename
[s
->clkm
.clocking_scheme
]);
2364 s
->clkm
.cold_start
&= value
& 0x3f;
2367 case 0x1c: /* ARM_CKOUT1 */
2368 diff
= s
->clkm
.arm_ckout1
^ value
;
2369 s
->clkm
.arm_ckout1
= value
& 0x003f;
2370 omap_clkm_ckout1_update(s
, diff
, value
);
2373 case 0x20: /* ARM_CKOUT2 */
2379 static CPUReadMemoryFunc
*omap_clkm_readfn
[] = {
2380 omap_badwidth_read16
,
2382 omap_badwidth_read16
,
2385 static CPUWriteMemoryFunc
*omap_clkm_writefn
[] = {
2386 omap_badwidth_write16
,
2388 omap_badwidth_write16
,
2391 static uint32_t omap_clkdsp_read(void *opaque
, target_phys_addr_t addr
)
2393 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
2396 case 0x04: /* DSP_IDLECT1 */
2397 return s
->clkm
.dsp_idlect1
;
2399 case 0x08: /* DSP_IDLECT2 */
2400 return s
->clkm
.dsp_idlect2
;
2402 case 0x14: /* DSP_RSTCT2 */
2403 return s
->clkm
.dsp_rstct2
;
2405 case 0x18: /* DSP_SYSST */
2406 return (s
->clkm
.clocking_scheme
<< 11) | s
->clkm
.cold_start
|
2407 (s
->env
->halted
<< 6); /* Quite useless... */
2414 static inline void omap_clkdsp_idlect1_update(struct omap_mpu_state_s
*s
,
2415 uint16_t diff
, uint16_t value
)
2419 SET_CANIDLE("dspxor_ck", 1); /* IDLXORP_DSP */
2422 static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s
*s
,
2423 uint16_t diff
, uint16_t value
)
2427 SET_ONOFF("dspxor_ck", 1); /* EN_XORPCK */
2430 static void omap_clkdsp_write(void *opaque
, target_phys_addr_t addr
,
2433 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
2437 case 0x04: /* DSP_IDLECT1 */
2438 diff
= s
->clkm
.dsp_idlect1
^ value
;
2439 s
->clkm
.dsp_idlect1
= value
& 0x01f7;
2440 omap_clkdsp_idlect1_update(s
, diff
, value
);
2443 case 0x08: /* DSP_IDLECT2 */
2444 s
->clkm
.dsp_idlect2
= value
& 0x0037;
2445 diff
= s
->clkm
.dsp_idlect1
^ value
;
2446 omap_clkdsp_idlect2_update(s
, diff
, value
);
2449 case 0x14: /* DSP_RSTCT2 */
2450 s
->clkm
.dsp_rstct2
= value
& 0x0001;
2453 case 0x18: /* DSP_SYSST */
2454 s
->clkm
.cold_start
&= value
& 0x3f;
2462 static CPUReadMemoryFunc
*omap_clkdsp_readfn
[] = {
2463 omap_badwidth_read16
,
2465 omap_badwidth_read16
,
2468 static CPUWriteMemoryFunc
*omap_clkdsp_writefn
[] = {
2469 omap_badwidth_write16
,
2471 omap_badwidth_write16
,
2474 static void omap_clkm_reset(struct omap_mpu_state_s
*s
)
2476 if (s
->wdt
&& s
->wdt
->reset
)
2477 s
->clkm
.cold_start
= 0x6;
2478 s
->clkm
.clocking_scheme
= 0;
2479 omap_clkm_ckctl_update(s
, ~0, 0x3000);
2480 s
->clkm
.arm_ckctl
= 0x3000;
2481 omap_clkm_idlect1_update(s
, s
->clkm
.arm_idlect1
^ 0x0400, 0x0400);
2482 s
->clkm
.arm_idlect1
= 0x0400;
2483 omap_clkm_idlect2_update(s
, s
->clkm
.arm_idlect2
^ 0x0100, 0x0100);
2484 s
->clkm
.arm_idlect2
= 0x0100;
2485 s
->clkm
.arm_ewupct
= 0x003f;
2486 s
->clkm
.arm_rstct1
= 0x0000;
2487 s
->clkm
.arm_rstct2
= 0x0000;
2488 s
->clkm
.arm_ckout1
= 0x0015;
2489 s
->clkm
.dpll1_mode
= 0x2002;
2490 omap_clkdsp_idlect1_update(s
, s
->clkm
.dsp_idlect1
^ 0x0040, 0x0040);
2491 s
->clkm
.dsp_idlect1
= 0x0040;
2492 omap_clkdsp_idlect2_update(s
, ~0, 0x0000);
2493 s
->clkm
.dsp_idlect2
= 0x0000;
2494 s
->clkm
.dsp_rstct2
= 0x0000;
2497 static void omap_clkm_init(target_phys_addr_t mpu_base
,
2498 target_phys_addr_t dsp_base
, struct omap_mpu_state_s
*s
)
2500 int iomemtype
[2] = {
2501 cpu_register_io_memory(0, omap_clkm_readfn
, omap_clkm_writefn
, s
),
2502 cpu_register_io_memory(0, omap_clkdsp_readfn
, omap_clkdsp_writefn
, s
),
2505 s
->clkm
.arm_idlect1
= 0x03ff;
2506 s
->clkm
.arm_idlect2
= 0x0100;
2507 s
->clkm
.dsp_idlect1
= 0x0002;
2509 s
->clkm
.cold_start
= 0x3a;
2511 cpu_register_physical_memory(mpu_base
, 0x100, iomemtype
[0]);
2512 cpu_register_physical_memory(dsp_base
, 0x1000, iomemtype
[1]);
2516 struct omap_mpuio_s
{
2520 qemu_irq handler
[16];
2541 static void omap_mpuio_set(void *opaque
, int line
, int level
)
2543 struct omap_mpuio_s
*s
= (struct omap_mpuio_s
*) opaque
;
2544 uint16_t prev
= s
->inputs
;
2547 s
->inputs
|= 1 << line
;
2549 s
->inputs
&= ~(1 << line
);
2551 if (((1 << line
) & s
->dir
& ~s
->mask
) && s
->clk
) {
2552 if ((s
->edge
& s
->inputs
& ~prev
) | (~s
->edge
& ~s
->inputs
& prev
)) {
2553 s
->ints
|= 1 << line
;
2554 qemu_irq_raise(s
->irq
);
2557 if ((s
->event
& (1 << 0)) && /* SET_GPIO_EVENT_MODE */
2558 (s
->event
>> 1) == line
) /* PIN_SELECT */
2559 s
->latch
= s
->inputs
;
2563 static void omap_mpuio_kbd_update(struct omap_mpuio_s
*s
)
2566 uint8_t *row
, rows
= 0, cols
= ~s
->cols
;
2568 for (row
= s
->buttons
+ 4, i
= 1 << 4; i
; row
--, i
>>= 1)
2572 qemu_set_irq(s
->kbd_irq
, rows
&& !s
->kbd_mask
&& s
->clk
);
2573 s
->row_latch
= ~rows
;
2576 static uint32_t omap_mpuio_read(void *opaque
, target_phys_addr_t addr
)
2578 struct omap_mpuio_s
*s
= (struct omap_mpuio_s
*) opaque
;
2579 int offset
= addr
& OMAP_MPUI_REG_MASK
;
2583 case 0x00: /* INPUT_LATCH */
2586 case 0x04: /* OUTPUT_REG */
2589 case 0x08: /* IO_CNTL */
2592 case 0x10: /* KBR_LATCH */
2593 return s
->row_latch
;
2595 case 0x14: /* KBC_REG */
2598 case 0x18: /* GPIO_EVENT_MODE_REG */
2601 case 0x1c: /* GPIO_INT_EDGE_REG */
2604 case 0x20: /* KBD_INT */
2605 return (~s
->row_latch
& 0x1f) && !s
->kbd_mask
;
2607 case 0x24: /* GPIO_INT */
2611 qemu_irq_lower(s
->irq
);
2614 case 0x28: /* KBD_MASKIT */
2617 case 0x2c: /* GPIO_MASKIT */
2620 case 0x30: /* GPIO_DEBOUNCING_REG */
2623 case 0x34: /* GPIO_LATCH_REG */
2631 static void omap_mpuio_write(void *opaque
, target_phys_addr_t addr
,
2634 struct omap_mpuio_s
*s
= (struct omap_mpuio_s
*) opaque
;
2635 int offset
= addr
& OMAP_MPUI_REG_MASK
;
2640 case 0x04: /* OUTPUT_REG */
2641 diff
= (s
->outputs
^ value
) & ~s
->dir
;
2643 while ((ln
= ffs(diff
))) {
2646 qemu_set_irq(s
->handler
[ln
], (value
>> ln
) & 1);
2651 case 0x08: /* IO_CNTL */
2652 diff
= s
->outputs
& (s
->dir
^ value
);
2655 value
= s
->outputs
& ~s
->dir
;
2656 while ((ln
= ffs(diff
))) {
2659 qemu_set_irq(s
->handler
[ln
], (value
>> ln
) & 1);
2664 case 0x14: /* KBC_REG */
2666 omap_mpuio_kbd_update(s
);
2669 case 0x18: /* GPIO_EVENT_MODE_REG */
2670 s
->event
= value
& 0x1f;
2673 case 0x1c: /* GPIO_INT_EDGE_REG */
2677 case 0x28: /* KBD_MASKIT */
2678 s
->kbd_mask
= value
& 1;
2679 omap_mpuio_kbd_update(s
);
2682 case 0x2c: /* GPIO_MASKIT */
2686 case 0x30: /* GPIO_DEBOUNCING_REG */
2687 s
->debounce
= value
& 0x1ff;
2690 case 0x00: /* INPUT_LATCH */
2691 case 0x10: /* KBR_LATCH */
2692 case 0x20: /* KBD_INT */
2693 case 0x24: /* GPIO_INT */
2694 case 0x34: /* GPIO_LATCH_REG */
2704 static CPUReadMemoryFunc
*omap_mpuio_readfn
[] = {
2705 omap_badwidth_read16
,
2707 omap_badwidth_read16
,
2710 static CPUWriteMemoryFunc
*omap_mpuio_writefn
[] = {
2711 omap_badwidth_write16
,
2713 omap_badwidth_write16
,
2716 static void omap_mpuio_reset(struct omap_mpuio_s
*s
)
2728 s
->row_latch
= 0x1f;
2732 static void omap_mpuio_onoff(void *opaque
, int line
, int on
)
2734 struct omap_mpuio_s
*s
= (struct omap_mpuio_s
*) opaque
;
2738 omap_mpuio_kbd_update(s
);
2741 struct omap_mpuio_s
*omap_mpuio_init(target_phys_addr_t base
,
2742 qemu_irq kbd_int
, qemu_irq gpio_int
, qemu_irq wakeup
,
2746 struct omap_mpuio_s
*s
= (struct omap_mpuio_s
*)
2747 qemu_mallocz(sizeof(struct omap_mpuio_s
));
2750 s
->kbd_irq
= kbd_int
;
2752 s
->in
= qemu_allocate_irqs(omap_mpuio_set
, s
, 16);
2753 omap_mpuio_reset(s
);
2755 iomemtype
= cpu_register_io_memory(0, omap_mpuio_readfn
,
2756 omap_mpuio_writefn
, s
);
2757 cpu_register_physical_memory(base
, 0x800, iomemtype
);
2759 omap_clk_adduser(clk
, qemu_allocate_irqs(omap_mpuio_onoff
, s
, 1)[0]);
2764 qemu_irq
*omap_mpuio_in_get(struct omap_mpuio_s
*s
)
2769 void omap_mpuio_out_set(struct omap_mpuio_s
*s
, int line
, qemu_irq handler
)
2771 if (line
>= 16 || line
< 0)
2772 cpu_abort(cpu_single_env
, "%s: No GPIO line %i\n", __FUNCTION__
, line
);
2773 s
->handler
[line
] = handler
;
2776 void omap_mpuio_key(struct omap_mpuio_s
*s
, int row
, int col
, int down
)
2778 if (row
>= 5 || row
< 0)
2779 cpu_abort(cpu_single_env
, "%s: No key %i-%i\n",
2780 __FUNCTION__
, col
, row
);
2783 s
->buttons
[row
] |= 1 << col
;
2785 s
->buttons
[row
] &= ~(1 << col
);
2787 omap_mpuio_kbd_update(s
);
2790 /* General-Purpose I/O */
2791 struct omap_gpio_s
{
2794 qemu_irq handler
[16];
2805 static void omap_gpio_set(void *opaque
, int line
, int level
)
2807 struct omap_gpio_s
*s
= (struct omap_gpio_s
*) opaque
;
2808 uint16_t prev
= s
->inputs
;
2811 s
->inputs
|= 1 << line
;
2813 s
->inputs
&= ~(1 << line
);
2815 if (((s
->edge
& s
->inputs
& ~prev
) | (~s
->edge
& ~s
->inputs
& prev
)) &
2816 (1 << line
) & s
->dir
& ~s
->mask
) {
2817 s
->ints
|= 1 << line
;
2818 qemu_irq_raise(s
->irq
);
2822 static uint32_t omap_gpio_read(void *opaque
, target_phys_addr_t addr
)
2824 struct omap_gpio_s
*s
= (struct omap_gpio_s
*) opaque
;
2825 int offset
= addr
& OMAP_MPUI_REG_MASK
;
2828 case 0x00: /* DATA_INPUT */
2829 return s
->inputs
& s
->pins
;
2831 case 0x04: /* DATA_OUTPUT */
2834 case 0x08: /* DIRECTION_CONTROL */
2837 case 0x0c: /* INTERRUPT_CONTROL */
2840 case 0x10: /* INTERRUPT_MASK */
2843 case 0x14: /* INTERRUPT_STATUS */
2846 case 0x18: /* PIN_CONTROL (not in OMAP310) */
2855 static void omap_gpio_write(void *opaque
, target_phys_addr_t addr
,
2858 struct omap_gpio_s
*s
= (struct omap_gpio_s
*) opaque
;
2859 int offset
= addr
& OMAP_MPUI_REG_MASK
;
2864 case 0x00: /* DATA_INPUT */
2868 case 0x04: /* DATA_OUTPUT */
2869 diff
= (s
->outputs
^ value
) & ~s
->dir
;
2871 while ((ln
= ffs(diff
))) {
2874 qemu_set_irq(s
->handler
[ln
], (value
>> ln
) & 1);
2879 case 0x08: /* DIRECTION_CONTROL */
2880 diff
= s
->outputs
& (s
->dir
^ value
);
2883 value
= s
->outputs
& ~s
->dir
;
2884 while ((ln
= ffs(diff
))) {
2887 qemu_set_irq(s
->handler
[ln
], (value
>> ln
) & 1);
2892 case 0x0c: /* INTERRUPT_CONTROL */
2896 case 0x10: /* INTERRUPT_MASK */
2900 case 0x14: /* INTERRUPT_STATUS */
2903 qemu_irq_lower(s
->irq
);
2906 case 0x18: /* PIN_CONTROL (not in OMAP310 TRM) */
2917 /* *Some* sources say the memory region is 32-bit. */
2918 static CPUReadMemoryFunc
*omap_gpio_readfn
[] = {
2919 omap_badwidth_read16
,
2921 omap_badwidth_read16
,
2924 static CPUWriteMemoryFunc
*omap_gpio_writefn
[] = {
2925 omap_badwidth_write16
,
2927 omap_badwidth_write16
,
2930 static void omap_gpio_reset(struct omap_gpio_s
*s
)
2941 struct omap_gpio_s
*omap_gpio_init(target_phys_addr_t base
,
2942 qemu_irq irq
, omap_clk clk
)
2945 struct omap_gpio_s
*s
= (struct omap_gpio_s
*)
2946 qemu_mallocz(sizeof(struct omap_gpio_s
));
2949 s
->in
= qemu_allocate_irqs(omap_gpio_set
, s
, 16);
2952 iomemtype
= cpu_register_io_memory(0, omap_gpio_readfn
,
2953 omap_gpio_writefn
, s
);
2954 cpu_register_physical_memory(base
, 0x1000, iomemtype
);
2959 qemu_irq
*omap_gpio_in_get(struct omap_gpio_s
*s
)
2964 void omap_gpio_out_set(struct omap_gpio_s
*s
, int line
, qemu_irq handler
)
2966 if (line
>= 16 || line
< 0)
2967 cpu_abort(cpu_single_env
, "%s: No GPIO line %i\n", __FUNCTION__
, line
);
2968 s
->handler
[line
] = handler
;
2971 /* MicroWire Interface */
2972 struct omap_uwire_s
{
2982 struct uwire_slave_s
*chip
[4];
2985 static void omap_uwire_transfer_start(struct omap_uwire_s
*s
)
2987 int chipselect
= (s
->control
>> 10) & 3; /* INDEX */
2988 struct uwire_slave_s
*slave
= s
->chip
[chipselect
];
2990 if ((s
->control
>> 5) & 0x1f) { /* NB_BITS_WR */
2991 if (s
->control
& (1 << 12)) /* CS_CMD */
2992 if (slave
&& slave
->send
)
2993 slave
->send(slave
->opaque
,
2994 s
->txbuf
>> (16 - ((s
->control
>> 5) & 0x1f)));
2995 s
->control
&= ~(1 << 14); /* CSRB */
2996 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
2997 * a DRQ. When is the level IRQ supposed to be reset? */
3000 if ((s
->control
>> 0) & 0x1f) { /* NB_BITS_RD */
3001 if (s
->control
& (1 << 12)) /* CS_CMD */
3002 if (slave
&& slave
->receive
)
3003 s
->rxbuf
= slave
->receive(slave
->opaque
);
3004 s
->control
|= 1 << 15; /* RDRB */
3005 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or
3006 * a DRQ. When is the level IRQ supposed to be reset? */
3010 static uint32_t omap_uwire_read(void *opaque
, target_phys_addr_t addr
)
3012 struct omap_uwire_s
*s
= (struct omap_uwire_s
*) opaque
;
3013 int offset
= addr
& OMAP_MPUI_REG_MASK
;
3016 case 0x00: /* RDR */
3017 s
->control
&= ~(1 << 15); /* RDRB */
3020 case 0x04: /* CSR */
3023 case 0x08: /* SR1 */
3025 case 0x0c: /* SR2 */
3027 case 0x10: /* SR3 */
3029 case 0x14: /* SR4 */
3031 case 0x18: /* SR5 */
3039 static void omap_uwire_write(void *opaque
, target_phys_addr_t addr
,
3042 struct omap_uwire_s
*s
= (struct omap_uwire_s
*) opaque
;
3043 int offset
= addr
& OMAP_MPUI_REG_MASK
;
3046 case 0x00: /* TDR */
3047 s
->txbuf
= value
; /* TD */
3048 if ((s
->setup
[4] & (1 << 2)) && /* AUTO_TX_EN */
3049 ((s
->setup
[4] & (1 << 3)) || /* CS_TOGGLE_TX_EN */
3050 (s
->control
& (1 << 12)))) { /* CS_CMD */
3051 s
->control
|= 1 << 14; /* CSRB */
3052 omap_uwire_transfer_start(s
);
3056 case 0x04: /* CSR */
3057 s
->control
= value
& 0x1fff;
3058 if (value
& (1 << 13)) /* START */
3059 omap_uwire_transfer_start(s
);
3062 case 0x08: /* SR1 */
3063 s
->setup
[0] = value
& 0x003f;
3066 case 0x0c: /* SR2 */
3067 s
->setup
[1] = value
& 0x0fc0;
3070 case 0x10: /* SR3 */
3071 s
->setup
[2] = value
& 0x0003;
3074 case 0x14: /* SR4 */
3075 s
->setup
[3] = value
& 0x0001;
3078 case 0x18: /* SR5 */
3079 s
->setup
[4] = value
& 0x000f;
3088 static CPUReadMemoryFunc
*omap_uwire_readfn
[] = {
3089 omap_badwidth_read16
,
3091 omap_badwidth_read16
,
3094 static CPUWriteMemoryFunc
*omap_uwire_writefn
[] = {
3095 omap_badwidth_write16
,
3097 omap_badwidth_write16
,
3100 static void omap_uwire_reset(struct omap_uwire_s
*s
)
3110 struct omap_uwire_s
*omap_uwire_init(target_phys_addr_t base
,
3111 qemu_irq
*irq
, qemu_irq dma
, omap_clk clk
)
3114 struct omap_uwire_s
*s
= (struct omap_uwire_s
*)
3115 qemu_mallocz(sizeof(struct omap_uwire_s
));
3120 omap_uwire_reset(s
);
3122 iomemtype
= cpu_register_io_memory(0, omap_uwire_readfn
,
3123 omap_uwire_writefn
, s
);
3124 cpu_register_physical_memory(base
, 0x800, iomemtype
);
3129 void omap_uwire_attach(struct omap_uwire_s
*s
,
3130 struct uwire_slave_s
*slave
, int chipselect
)
3132 if (chipselect
< 0 || chipselect
> 3) {
3133 fprintf(stderr
, "%s: Bad chipselect %i\n", __FUNCTION__
, chipselect
);
3137 s
->chip
[chipselect
] = slave
;
3140 /* Pseudonoise Pulse-Width Light Modulator */
3141 static void omap_pwl_update(struct omap_mpu_state_s
*s
)
3143 int output
= (s
->pwl
.clk
&& s
->pwl
.enable
) ? s
->pwl
.level
: 0;
3145 if (output
!= s
->pwl
.output
) {
3146 s
->pwl
.output
= output
;
3147 printf("%s: Backlight now at %i/256\n", __FUNCTION__
, output
);
3151 static uint32_t omap_pwl_read(void *opaque
, target_phys_addr_t addr
)
3153 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
3154 int offset
= addr
& OMAP_MPUI_REG_MASK
;
3157 case 0x00: /* PWL_LEVEL */
3158 return s
->pwl
.level
;
3159 case 0x04: /* PWL_CTRL */
3160 return s
->pwl
.enable
;
3166 static void omap_pwl_write(void *opaque
, target_phys_addr_t addr
,
3169 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
3170 int offset
= addr
& OMAP_MPUI_REG_MASK
;
3173 case 0x00: /* PWL_LEVEL */
3174 s
->pwl
.level
= value
;
3177 case 0x04: /* PWL_CTRL */
3178 s
->pwl
.enable
= value
& 1;
3187 static CPUReadMemoryFunc
*omap_pwl_readfn
[] = {
3189 omap_badwidth_read8
,
3190 omap_badwidth_read8
,
3193 static CPUWriteMemoryFunc
*omap_pwl_writefn
[] = {
3195 omap_badwidth_write8
,
3196 omap_badwidth_write8
,
3199 static void omap_pwl_reset(struct omap_mpu_state_s
*s
)
3208 static void omap_pwl_clk_update(void *opaque
, int line
, int on
)
3210 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
3216 static void omap_pwl_init(target_phys_addr_t base
, struct omap_mpu_state_s
*s
,
3223 iomemtype
= cpu_register_io_memory(0, omap_pwl_readfn
,
3224 omap_pwl_writefn
, s
);
3225 cpu_register_physical_memory(base
, 0x800, iomemtype
);
3227 omap_clk_adduser(clk
, qemu_allocate_irqs(omap_pwl_clk_update
, s
, 1)[0]);
3230 /* Pulse-Width Tone module */
3231 static uint32_t omap_pwt_read(void *opaque
, target_phys_addr_t addr
)
3233 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
3234 int offset
= addr
& OMAP_MPUI_REG_MASK
;
3237 case 0x00: /* FRC */
3239 case 0x04: /* VCR */
3241 case 0x08: /* GCR */
3248 static void omap_pwt_write(void *opaque
, target_phys_addr_t addr
,
3251 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*) opaque
;
3252 int offset
= addr
& OMAP_MPUI_REG_MASK
;
3255 case 0x00: /* FRC */
3256 s
->pwt
.frc
= value
& 0x3f;
3258 case 0x04: /* VRC */
3259 if ((value
^ s
->pwt
.vrc
) & 1) {
3261 printf("%s: %iHz buzz on\n", __FUNCTION__
, (int)
3262 /* 1.5 MHz from a 12-MHz or 13-MHz PWT_CLK */
3263 ((omap_clk_getrate(s
->pwt
.clk
) >> 3) /
3264 /* Pre-multiplexer divider */
3265 ((s
->pwt
.gcr
& 2) ? 1 : 154) /
3266 /* Octave multiplexer */
3267 (2 << (value
& 3)) *
3268 /* 101/107 divider */
3269 ((value
& (1 << 2)) ? 101 : 107) *
3271 ((value
& (1 << 3)) ? 49 : 55) *
3273 ((value
& (1 << 4)) ? 50 : 63) *
3274 /* 80/127 divider */
3275 ((value
& (1 << 5)) ? 80 : 127) /
3276 (107 * 55 * 63 * 127)));
3278 printf("%s: silence!\n", __FUNCTION__
);
3280 s
->pwt
.vrc
= value
& 0x7f;
3282 case 0x08: /* GCR */
3283 s
->pwt
.gcr
= value
& 3;
3291 static CPUReadMemoryFunc
*omap_pwt_readfn
[] = {
3293 omap_badwidth_read8
,
3294 omap_badwidth_read8
,
3297 static CPUWriteMemoryFunc
*omap_pwt_writefn
[] = {
3299 omap_badwidth_write8
,
3300 omap_badwidth_write8
,
3303 static void omap_pwt_reset(struct omap_mpu_state_s
*s
)
3310 static void omap_pwt_init(target_phys_addr_t base
, struct omap_mpu_state_s
*s
,
3318 iomemtype
= cpu_register_io_memory(0, omap_pwt_readfn
,
3319 omap_pwt_writefn
, s
);
3320 cpu_register_physical_memory(base
, 0x800, iomemtype
);
3323 /* Real-time Clock module */
3339 struct tm current_tm
;
3344 static void omap_rtc_interrupts_update(struct omap_rtc_s
*s
)
3346 /* s->alarm is level-triggered */
3347 qemu_set_irq(s
->alarm
, (s
->status
>> 6) & 1);
3350 static void omap_rtc_alarm_update(struct omap_rtc_s
*s
)
3352 s
->alarm_ti
= mktime(&s
->alarm_tm
);
3353 if (s
->alarm_ti
== -1)
3354 printf("%s: conversion failed\n", __FUNCTION__
);
3357 static inline uint8_t omap_rtc_bcd(int num
)
3359 return ((num
/ 10) << 4) | (num
% 10);
3362 static inline int omap_rtc_bin(uint8_t num
)
3364 return (num
& 15) + 10 * (num
>> 4);
3367 static uint32_t omap_rtc_read(void *opaque
, target_phys_addr_t addr
)
3369 struct omap_rtc_s
*s
= (struct omap_rtc_s
*) opaque
;
3370 int offset
= addr
& OMAP_MPUI_REG_MASK
;
3374 case 0x00: /* SECONDS_REG */
3375 return omap_rtc_bcd(s
->current_tm
.tm_sec
);
3377 case 0x04: /* MINUTES_REG */
3378 return omap_rtc_bcd(s
->current_tm
.tm_min
);
3380 case 0x08: /* HOURS_REG */
3382 return ((s
->current_tm
.tm_hour
> 11) << 7) |
3383 omap_rtc_bcd(((s
->current_tm
.tm_hour
- 1) % 12) + 1);
3385 return omap_rtc_bcd(s
->current_tm
.tm_hour
);
3387 case 0x0c: /* DAYS_REG */
3388 return omap_rtc_bcd(s
->current_tm
.tm_mday
);
3390 case 0x10: /* MONTHS_REG */
3391 return omap_rtc_bcd(s
->current_tm
.tm_mon
+ 1);
3393 case 0x14: /* YEARS_REG */
3394 return omap_rtc_bcd(s
->current_tm
.tm_year
% 100);
3396 case 0x18: /* WEEK_REG */
3397 return s
->current_tm
.tm_wday
;
3399 case 0x20: /* ALARM_SECONDS_REG */
3400 return omap_rtc_bcd(s
->alarm_tm
.tm_sec
);
3402 case 0x24: /* ALARM_MINUTES_REG */
3403 return omap_rtc_bcd(s
->alarm_tm
.tm_min
);
3405 case 0x28: /* ALARM_HOURS_REG */
3407 return ((s
->alarm_tm
.tm_hour
> 11) << 7) |
3408 omap_rtc_bcd(((s
->alarm_tm
.tm_hour
- 1) % 12) + 1);
3410 return omap_rtc_bcd(s
->alarm_tm
.tm_hour
);
3412 case 0x2c: /* ALARM_DAYS_REG */
3413 return omap_rtc_bcd(s
->alarm_tm
.tm_mday
);
3415 case 0x30: /* ALARM_MONTHS_REG */
3416 return omap_rtc_bcd(s
->alarm_tm
.tm_mon
+ 1);
3418 case 0x34: /* ALARM_YEARS_REG */
3419 return omap_rtc_bcd(s
->alarm_tm
.tm_year
% 100);
3421 case 0x40: /* RTC_CTRL_REG */
3422 return (s
->pm_am
<< 3) | (s
->auto_comp
<< 2) |
3423 (s
->round
<< 1) | s
->running
;
3425 case 0x44: /* RTC_STATUS_REG */
3430 case 0x48: /* RTC_INTERRUPTS_REG */
3431 return s
->interrupts
;
3433 case 0x4c: /* RTC_COMP_LSB_REG */
3434 return ((uint16_t) s
->comp_reg
) & 0xff;
3436 case 0x50: /* RTC_COMP_MSB_REG */
3437 return ((uint16_t) s
->comp_reg
) >> 8;
3444 static void omap_rtc_write(void *opaque
, target_phys_addr_t addr
,
3447 struct omap_rtc_s
*s
= (struct omap_rtc_s
*) opaque
;
3448 int offset
= addr
& OMAP_MPUI_REG_MASK
;
3453 case 0x00: /* SECONDS_REG */
3455 printf("RTC SEC_REG <-- %02x\n", value
);
3457 s
->ti
-= s
->current_tm
.tm_sec
;
3458 s
->ti
+= omap_rtc_bin(value
);
3461 case 0x04: /* MINUTES_REG */
3463 printf("RTC MIN_REG <-- %02x\n", value
);
3465 s
->ti
-= s
->current_tm
.tm_min
* 60;
3466 s
->ti
+= omap_rtc_bin(value
) * 60;
3469 case 0x08: /* HOURS_REG */
3471 printf("RTC HRS_REG <-- %02x\n", value
);
3473 s
->ti
-= s
->current_tm
.tm_hour
* 3600;
3475 s
->ti
+= (omap_rtc_bin(value
& 0x3f) & 12) * 3600;
3476 s
->ti
+= ((value
>> 7) & 1) * 43200;
3478 s
->ti
+= omap_rtc_bin(value
& 0x3f) * 3600;
3481 case 0x0c: /* DAYS_REG */
3483 printf("RTC DAY_REG <-- %02x\n", value
);
3485 s
->ti
-= s
->current_tm
.tm_mday
* 86400;
3486 s
->ti
+= omap_rtc_bin(value
) * 86400;
3489 case 0x10: /* MONTHS_REG */
3491 printf("RTC MTH_REG <-- %02x\n", value
);
3493 memcpy(&new_tm
, &s
->current_tm
, sizeof(new_tm
));
3494 new_tm
.tm_mon
= omap_rtc_bin(value
);
3495 ti
[0] = mktime(&s
->current_tm
);
3496 ti
[1] = mktime(&new_tm
);
3498 if (ti
[0] != -1 && ti
[1] != -1) {
3502 /* A less accurate version */
3503 s
->ti
-= s
->current_tm
.tm_mon
* 2592000;
3504 s
->ti
+= omap_rtc_bin(value
) * 2592000;
3508 case 0x14: /* YEARS_REG */
3510 printf("RTC YRS_REG <-- %02x\n", value
);
3512 memcpy(&new_tm
, &s
->current_tm
, sizeof(new_tm
));
3513 new_tm
.tm_year
+= omap_rtc_bin(value
) - (new_tm
.tm_year
% 100);
3514 ti
[0] = mktime(&s
->current_tm
);
3515 ti
[1] = mktime(&new_tm
);
3517 if (ti
[0] != -1 && ti
[1] != -1) {
3521 /* A less accurate version */
3522 s
->ti
-= (s
->current_tm
.tm_year
% 100) * 31536000;
3523 s
->ti
+= omap_rtc_bin(value
) * 31536000;
3527 case 0x18: /* WEEK_REG */
3528 return; /* Ignored */
3530 case 0x20: /* ALARM_SECONDS_REG */
3532 printf("ALM SEC_REG <-- %02x\n", value
);
3534 s
->alarm_tm
.tm_sec
= omap_rtc_bin(value
);
3535 omap_rtc_alarm_update(s
);
3538 case 0x24: /* ALARM_MINUTES_REG */
3540 printf("ALM MIN_REG <-- %02x\n", value
);
3542 s
->alarm_tm
.tm_min
= omap_rtc_bin(value
);
3543 omap_rtc_alarm_update(s
);
3546 case 0x28: /* ALARM_HOURS_REG */
3548 printf("ALM HRS_REG <-- %02x\n", value
);
3551 s
->alarm_tm
.tm_hour
=
3552 ((omap_rtc_bin(value
& 0x3f)) % 12) +
3553 ((value
>> 7) & 1) * 12;
3555 s
->alarm_tm
.tm_hour
= omap_rtc_bin(value
);
3556 omap_rtc_alarm_update(s
);
3559 case 0x2c: /* ALARM_DAYS_REG */
3561 printf("ALM DAY_REG <-- %02x\n", value
);
3563 s
->alarm_tm
.tm_mday
= omap_rtc_bin(value
);
3564 omap_rtc_alarm_update(s
);
3567 case 0x30: /* ALARM_MONTHS_REG */
3569 printf("ALM MON_REG <-- %02x\n", value
);
3571 s
->alarm_tm
.tm_mon
= omap_rtc_bin(value
);
3572 omap_rtc_alarm_update(s
);
3575 case 0x34: /* ALARM_YEARS_REG */
3577 printf("ALM YRS_REG <-- %02x\n", value
);
3579 s
->alarm_tm
.tm_year
= omap_rtc_bin(value
);
3580 omap_rtc_alarm_update(s
);
3583 case 0x40: /* RTC_CTRL_REG */
3585 printf("RTC CONTROL <-- %02x\n", value
);
3587 s
->pm_am
= (value
>> 3) & 1;
3588 s
->auto_comp
= (value
>> 2) & 1;
3589 s
->round
= (value
>> 1) & 1;
3590 s
->running
= value
& 1;
3592 s
->status
|= s
->running
<< 1;
3595 case 0x44: /* RTC_STATUS_REG */
3597 printf("RTC STATUSL <-- %02x\n", value
);
3599 s
->status
&= ~((value
& 0xc0) ^ 0x80);
3600 omap_rtc_interrupts_update(s
);
3603 case 0x48: /* RTC_INTERRUPTS_REG */
3605 printf("RTC INTRS <-- %02x\n", value
);
3607 s
->interrupts
= value
;
3610 case 0x4c: /* RTC_COMP_LSB_REG */
3612 printf("RTC COMPLSB <-- %02x\n", value
);
3614 s
->comp_reg
&= 0xff00;
3615 s
->comp_reg
|= 0x00ff & value
;
3618 case 0x50: /* RTC_COMP_MSB_REG */
3620 printf("RTC COMPMSB <-- %02x\n", value
);
3622 s
->comp_reg
&= 0x00ff;
3623 s
->comp_reg
|= 0xff00 & (value
<< 8);
3632 static CPUReadMemoryFunc
*omap_rtc_readfn
[] = {
3634 omap_badwidth_read8
,
3635 omap_badwidth_read8
,
3638 static CPUWriteMemoryFunc
*omap_rtc_writefn
[] = {
3640 omap_badwidth_write8
,
3641 omap_badwidth_write8
,
3644 static void omap_rtc_tick(void *opaque
)
3646 struct omap_rtc_s
*s
= opaque
;
3649 /* Round to nearest full minute. */
3650 if (s
->current_tm
.tm_sec
< 30)
3651 s
->ti
-= s
->current_tm
.tm_sec
;
3653 s
->ti
+= 60 - s
->current_tm
.tm_sec
;
3658 memcpy(&s
->current_tm
, localtime(&s
->ti
), sizeof(s
->current_tm
));
3660 if ((s
->interrupts
& 0x08) && s
->ti
== s
->alarm_ti
) {
3662 omap_rtc_interrupts_update(s
);
3665 if (s
->interrupts
& 0x04)
3666 switch (s
->interrupts
& 3) {
3669 qemu_irq_pulse(s
->irq
);
3672 if (s
->current_tm
.tm_sec
)
3675 qemu_irq_pulse(s
->irq
);
3678 if (s
->current_tm
.tm_sec
|| s
->current_tm
.tm_min
)
3681 qemu_irq_pulse(s
->irq
);
3684 if (s
->current_tm
.tm_sec
||
3685 s
->current_tm
.tm_min
|| s
->current_tm
.tm_hour
)
3688 qemu_irq_pulse(s
->irq
);
3698 * Every full hour add a rough approximation of the compensation
3699 * register to the 32kHz Timer (which drives the RTC) value.
3701 if (s
->auto_comp
&& !s
->current_tm
.tm_sec
&& !s
->current_tm
.tm_min
)
3702 s
->tick
+= s
->comp_reg
* 1000 / 32768;
3704 qemu_mod_timer(s
->clk
, s
->tick
);
3707 static void omap_rtc_reset(struct omap_rtc_s
*s
)
3717 s
->tick
= qemu_get_clock(rt_clock
);
3718 memset(&s
->alarm_tm
, 0, sizeof(s
->alarm_tm
));
3719 s
->alarm_tm
.tm_mday
= 0x01;
3721 qemu_get_timedate(&tm
, 0);
3722 s
->ti
= mktime(&tm
);
3724 omap_rtc_alarm_update(s
);
3728 struct omap_rtc_s
*omap_rtc_init(target_phys_addr_t base
,
3729 qemu_irq
*irq
, omap_clk clk
)
3732 struct omap_rtc_s
*s
= (struct omap_rtc_s
*)
3733 qemu_mallocz(sizeof(struct omap_rtc_s
));
3737 s
->clk
= qemu_new_timer(rt_clock
, omap_rtc_tick
, s
);
3741 iomemtype
= cpu_register_io_memory(0, omap_rtc_readfn
,
3742 omap_rtc_writefn
, s
);
3743 cpu_register_physical_memory(base
, 0x800, iomemtype
);
3748 /* Multi-channel Buffered Serial Port interfaces */
3749 struct omap_mcbsp_s
{
3768 struct i2s_codec_s
*codec
;
3769 QEMUTimer
*source_timer
;
3770 QEMUTimer
*sink_timer
;
3773 static void omap_mcbsp_intr_update(struct omap_mcbsp_s
*s
)
3777 switch ((s
->spcr
[0] >> 4) & 3) { /* RINTM */
3779 irq
= (s
->spcr
[0] >> 1) & 1; /* RRDY */
3782 irq
= (s
->spcr
[0] >> 3) & 1; /* RSYNCERR */
3790 qemu_irq_pulse(s
->rxirq
);
3792 switch ((s
->spcr
[1] >> 4) & 3) { /* XINTM */
3794 irq
= (s
->spcr
[1] >> 1) & 1; /* XRDY */
3797 irq
= (s
->spcr
[1] >> 3) & 1; /* XSYNCERR */
3805 qemu_irq_pulse(s
->txirq
);
3808 static void omap_mcbsp_rx_newdata(struct omap_mcbsp_s
*s
)
3810 if ((s
->spcr
[0] >> 1) & 1) /* RRDY */
3811 s
->spcr
[0] |= 1 << 2; /* RFULL */
3812 s
->spcr
[0] |= 1 << 1; /* RRDY */
3813 qemu_irq_raise(s
->rxdrq
);
3814 omap_mcbsp_intr_update(s
);
3817 static void omap_mcbsp_source_tick(void *opaque
)
3819 struct omap_mcbsp_s
*s
= (struct omap_mcbsp_s
*) opaque
;
3820 static const int bps
[8] = { 0, 1, 1, 2, 2, 2, -255, -255 };
3825 printf("%s: Rx FIFO overrun\n", __FUNCTION__
);
3827 s
->rx_req
= s
->rx_rate
<< bps
[(s
->rcr
[0] >> 5) & 7];
3829 omap_mcbsp_rx_newdata(s
);
3830 qemu_mod_timer(s
->source_timer
, qemu_get_clock(vm_clock
) + ticks_per_sec
);
3833 static void omap_mcbsp_rx_start(struct omap_mcbsp_s
*s
)
3835 if (!s
->codec
|| !s
->codec
->rts
)
3836 omap_mcbsp_source_tick(s
);
3837 else if (s
->codec
->in
.len
) {
3838 s
->rx_req
= s
->codec
->in
.len
;
3839 omap_mcbsp_rx_newdata(s
);
3843 static void omap_mcbsp_rx_stop(struct omap_mcbsp_s
*s
)
3845 qemu_del_timer(s
->source_timer
);
3848 static void omap_mcbsp_rx_done(struct omap_mcbsp_s
*s
)
3850 s
->spcr
[0] &= ~(1 << 1); /* RRDY */
3851 qemu_irq_lower(s
->rxdrq
);
3852 omap_mcbsp_intr_update(s
);
3855 static void omap_mcbsp_tx_newdata(struct omap_mcbsp_s
*s
)
3857 s
->spcr
[1] |= 1 << 1; /* XRDY */
3858 qemu_irq_raise(s
->txdrq
);
3859 omap_mcbsp_intr_update(s
);
3862 static void omap_mcbsp_sink_tick(void *opaque
)
3864 struct omap_mcbsp_s
*s
= (struct omap_mcbsp_s
*) opaque
;
3865 static const int bps
[8] = { 0, 1, 1, 2, 2, 2, -255, -255 };
3870 printf("%s: Tx FIFO underrun\n", __FUNCTION__
);
3872 s
->tx_req
= s
->tx_rate
<< bps
[(s
->xcr
[0] >> 5) & 7];
3874 omap_mcbsp_tx_newdata(s
);
3875 qemu_mod_timer(s
->sink_timer
, qemu_get_clock(vm_clock
) + ticks_per_sec
);
3878 static void omap_mcbsp_tx_start(struct omap_mcbsp_s
*s
)
3880 if (!s
->codec
|| !s
->codec
->cts
)
3881 omap_mcbsp_sink_tick(s
);
3882 else if (s
->codec
->out
.size
) {
3883 s
->tx_req
= s
->codec
->out
.size
;
3884 omap_mcbsp_tx_newdata(s
);
3888 static void omap_mcbsp_tx_done(struct omap_mcbsp_s
*s
)
3890 s
->spcr
[1] &= ~(1 << 1); /* XRDY */
3891 qemu_irq_lower(s
->txdrq
);
3892 omap_mcbsp_intr_update(s
);
3893 if (s
->codec
&& s
->codec
->cts
)
3894 s
->codec
->tx_swallow(s
->codec
->opaque
);
3897 static void omap_mcbsp_tx_stop(struct omap_mcbsp_s
*s
)
3900 omap_mcbsp_tx_done(s
);
3901 qemu_del_timer(s
->sink_timer
);
3904 static void omap_mcbsp_req_update(struct omap_mcbsp_s
*s
)
3906 int prev_rx_rate
, prev_tx_rate
;
3907 int rx_rate
= 0, tx_rate
= 0;
3908 int cpu_rate
= 1500000; /* XXX */
3910 /* TODO: check CLKSTP bit */
3911 if (s
->spcr
[1] & (1 << 6)) { /* GRST */
3912 if (s
->spcr
[0] & (1 << 0)) { /* RRST */
3913 if ((s
->srgr
[1] & (1 << 13)) && /* CLKSM */
3914 (s
->pcr
& (1 << 8))) { /* CLKRM */
3915 if (~s
->pcr
& (1 << 7)) /* SCLKME */
3916 rx_rate
= cpu_rate
/
3917 ((s
->srgr
[0] & 0xff) + 1); /* CLKGDV */
3920 rx_rate
= s
->codec
->rx_rate
;
3923 if (s
->spcr
[1] & (1 << 0)) { /* XRST */
3924 if ((s
->srgr
[1] & (1 << 13)) && /* CLKSM */
3925 (s
->pcr
& (1 << 9))) { /* CLKXM */
3926 if (~s
->pcr
& (1 << 7)) /* SCLKME */
3927 tx_rate
= cpu_rate
/
3928 ((s
->srgr
[0] & 0xff) + 1); /* CLKGDV */
3931 tx_rate
= s
->codec
->tx_rate
;
3934 prev_tx_rate
= s
->tx_rate
;
3935 prev_rx_rate
= s
->rx_rate
;
3936 s
->tx_rate
= tx_rate
;
3937 s
->rx_rate
= rx_rate
;
3940 s
->codec
->set_rate(s
->codec
->opaque
, rx_rate
, tx_rate
);
3942 if (!prev_tx_rate
&& tx_rate
)
3943 omap_mcbsp_tx_start(s
);
3944 else if (s
->tx_rate
&& !tx_rate
)
3945 omap_mcbsp_tx_stop(s
);
3947 if (!prev_rx_rate
&& rx_rate
)
3948 omap_mcbsp_rx_start(s
);
3949 else if (prev_tx_rate
&& !tx_rate
)
3950 omap_mcbsp_rx_stop(s
);
3953 static uint32_t omap_mcbsp_read(void *opaque
, target_phys_addr_t addr
)
3955 struct omap_mcbsp_s
*s
= (struct omap_mcbsp_s
*) opaque
;
3956 int offset
= addr
& OMAP_MPUI_REG_MASK
;
3960 case 0x00: /* DRR2 */
3961 if (((s
->rcr
[0] >> 5) & 7) < 3) /* RWDLEN1 */
3964 case 0x02: /* DRR1 */
3965 if (s
->rx_req
< 2) {
3966 printf("%s: Rx FIFO underrun\n", __FUNCTION__
);
3967 omap_mcbsp_rx_done(s
);
3970 if (s
->codec
&& s
->codec
->in
.len
>= 2) {
3971 ret
= s
->codec
->in
.fifo
[s
->codec
->in
.start
++] << 8;
3972 ret
|= s
->codec
->in
.fifo
[s
->codec
->in
.start
++];
3973 s
->codec
->in
.len
-= 2;
3977 omap_mcbsp_rx_done(s
);
3982 case 0x04: /* DXR2 */
3983 case 0x06: /* DXR1 */
3986 case 0x08: /* SPCR2 */
3988 case 0x0a: /* SPCR1 */
3990 case 0x0c: /* RCR2 */
3992 case 0x0e: /* RCR1 */
3994 case 0x10: /* XCR2 */
3996 case 0x12: /* XCR1 */
3998 case 0x14: /* SRGR2 */
4000 case 0x16: /* SRGR1 */
4002 case 0x18: /* MCR2 */
4004 case 0x1a: /* MCR1 */
4006 case 0x1c: /* RCERA */
4008 case 0x1e: /* RCERB */
4010 case 0x20: /* XCERA */
4012 case 0x22: /* XCERB */
4014 case 0x24: /* PCR0 */
4016 case 0x26: /* RCERC */
4018 case 0x28: /* RCERD */
4020 case 0x2a: /* XCERC */
4022 case 0x2c: /* XCERD */
4024 case 0x2e: /* RCERE */
4026 case 0x30: /* RCERF */
4028 case 0x32: /* XCERE */
4030 case 0x34: /* XCERF */
4032 case 0x36: /* RCERG */
4034 case 0x38: /* RCERH */
4036 case 0x3a: /* XCERG */
4038 case 0x3c: /* XCERH */
4046 static void omap_mcbsp_writeh(void *opaque
, target_phys_addr_t addr
,
4049 struct omap_mcbsp_s
*s
= (struct omap_mcbsp_s
*) opaque
;
4050 int offset
= addr
& OMAP_MPUI_REG_MASK
;
4053 case 0x00: /* DRR2 */
4054 case 0x02: /* DRR1 */
4058 case 0x04: /* DXR2 */
4059 if (((s
->xcr
[0] >> 5) & 7) < 3) /* XWDLEN1 */
4062 case 0x06: /* DXR1 */
4063 if (s
->tx_req
> 1) {
4065 if (s
->codec
&& s
->codec
->cts
) {
4066 s
->codec
->out
.fifo
[s
->codec
->out
.len
++] = (value
>> 8) & 0xff;
4067 s
->codec
->out
.fifo
[s
->codec
->out
.len
++] = (value
>> 0) & 0xff;
4070 omap_mcbsp_tx_done(s
);
4072 printf("%s: Tx FIFO overrun\n", __FUNCTION__
);
4075 case 0x08: /* SPCR2 */
4076 s
->spcr
[1] &= 0x0002;
4077 s
->spcr
[1] |= 0x03f9 & value
;
4078 s
->spcr
[1] |= 0x0004 & (value
<< 2); /* XEMPTY := XRST */
4079 if (~value
& 1) /* XRST */
4081 omap_mcbsp_req_update(s
);
4083 case 0x0a: /* SPCR1 */
4084 s
->spcr
[0] &= 0x0006;
4085 s
->spcr
[0] |= 0xf8f9 & value
;
4086 if (value
& (1 << 15)) /* DLB */
4087 printf("%s: Digital Loopback mode enable attempt\n", __FUNCTION__
);
4088 if (~value
& 1) { /* RRST */
4091 omap_mcbsp_rx_done(s
);
4093 omap_mcbsp_req_update(s
);
4096 case 0x0c: /* RCR2 */
4097 s
->rcr
[1] = value
& 0xffff;
4099 case 0x0e: /* RCR1 */
4100 s
->rcr
[0] = value
& 0x7fe0;
4102 case 0x10: /* XCR2 */
4103 s
->xcr
[1] = value
& 0xffff;
4105 case 0x12: /* XCR1 */
4106 s
->xcr
[0] = value
& 0x7fe0;
4108 case 0x14: /* SRGR2 */
4109 s
->srgr
[1] = value
& 0xffff;
4110 omap_mcbsp_req_update(s
);
4112 case 0x16: /* SRGR1 */
4113 s
->srgr
[0] = value
& 0xffff;
4114 omap_mcbsp_req_update(s
);
4116 case 0x18: /* MCR2 */
4117 s
->mcr
[1] = value
& 0x03e3;
4118 if (value
& 3) /* XMCM */
4119 printf("%s: Tx channel selection mode enable attempt\n",
4122 case 0x1a: /* MCR1 */
4123 s
->mcr
[0] = value
& 0x03e1;
4124 if (value
& 1) /* RMCM */
4125 printf("%s: Rx channel selection mode enable attempt\n",
4128 case 0x1c: /* RCERA */
4129 s
->rcer
[0] = value
& 0xffff;
4131 case 0x1e: /* RCERB */
4132 s
->rcer
[1] = value
& 0xffff;
4134 case 0x20: /* XCERA */
4135 s
->xcer
[0] = value
& 0xffff;
4137 case 0x22: /* XCERB */
4138 s
->xcer
[1] = value
& 0xffff;
4140 case 0x24: /* PCR0 */
4141 s
->pcr
= value
& 0x7faf;
4143 case 0x26: /* RCERC */
4144 s
->rcer
[2] = value
& 0xffff;
4146 case 0x28: /* RCERD */
4147 s
->rcer
[3] = value
& 0xffff;
4149 case 0x2a: /* XCERC */
4150 s
->xcer
[2] = value
& 0xffff;
4152 case 0x2c: /* XCERD */
4153 s
->xcer
[3] = value
& 0xffff;
4155 case 0x2e: /* RCERE */
4156 s
->rcer
[4] = value
& 0xffff;
4158 case 0x30: /* RCERF */
4159 s
->rcer
[5] = value
& 0xffff;
4161 case 0x32: /* XCERE */
4162 s
->xcer
[4] = value
& 0xffff;
4164 case 0x34: /* XCERF */
4165 s
->xcer
[5] = value
& 0xffff;
4167 case 0x36: /* RCERG */
4168 s
->rcer
[6] = value
& 0xffff;
4170 case 0x38: /* RCERH */
4171 s
->rcer
[7] = value
& 0xffff;
4173 case 0x3a: /* XCERG */
4174 s
->xcer
[6] = value
& 0xffff;
4176 case 0x3c: /* XCERH */
4177 s
->xcer
[7] = value
& 0xffff;
4184 static void omap_mcbsp_writew(void *opaque
, target_phys_addr_t addr
,
4187 struct omap_mcbsp_s
*s
= (struct omap_mcbsp_s
*) opaque
;
4188 int offset
= addr
& OMAP_MPUI_REG_MASK
;
4190 if (offset
== 0x04) { /* DXR */
4191 if (((s
->xcr
[0] >> 5) & 7) < 3) /* XWDLEN1 */
4193 if (s
->tx_req
> 3) {
4195 if (s
->codec
&& s
->codec
->cts
) {
4196 s
->codec
->out
.fifo
[s
->codec
->out
.len
++] =
4197 (value
>> 24) & 0xff;
4198 s
->codec
->out
.fifo
[s
->codec
->out
.len
++] =
4199 (value
>> 16) & 0xff;
4200 s
->codec
->out
.fifo
[s
->codec
->out
.len
++] =
4201 (value
>> 8) & 0xff;
4202 s
->codec
->out
.fifo
[s
->codec
->out
.len
++] =
4203 (value
>> 0) & 0xff;
4206 omap_mcbsp_tx_done(s
);
4208 printf("%s: Tx FIFO overrun\n", __FUNCTION__
);
4212 omap_badwidth_write16(opaque
, addr
, value
);
4215 static CPUReadMemoryFunc
*omap_mcbsp_readfn
[] = {
4216 omap_badwidth_read16
,
4218 omap_badwidth_read16
,
4221 static CPUWriteMemoryFunc
*omap_mcbsp_writefn
[] = {
4222 omap_badwidth_write16
,
4227 static void omap_mcbsp_reset(struct omap_mcbsp_s
*s
)
4229 memset(&s
->spcr
, 0, sizeof(s
->spcr
));
4230 memset(&s
->rcr
, 0, sizeof(s
->rcr
));
4231 memset(&s
->xcr
, 0, sizeof(s
->xcr
));
4232 s
->srgr
[0] = 0x0001;
4233 s
->srgr
[1] = 0x2000;
4234 memset(&s
->mcr
, 0, sizeof(s
->mcr
));
4235 memset(&s
->pcr
, 0, sizeof(s
->pcr
));
4236 memset(&s
->rcer
, 0, sizeof(s
->rcer
));
4237 memset(&s
->xcer
, 0, sizeof(s
->xcer
));
4242 qemu_del_timer(s
->source_timer
);
4243 qemu_del_timer(s
->sink_timer
);
4246 struct omap_mcbsp_s
*omap_mcbsp_init(target_phys_addr_t base
,
4247 qemu_irq
*irq
, qemu_irq
*dma
, omap_clk clk
)
4250 struct omap_mcbsp_s
*s
= (struct omap_mcbsp_s
*)
4251 qemu_mallocz(sizeof(struct omap_mcbsp_s
));
4257 s
->sink_timer
= qemu_new_timer(vm_clock
, omap_mcbsp_sink_tick
, s
);
4258 s
->source_timer
= qemu_new_timer(vm_clock
, omap_mcbsp_source_tick
, s
);
4259 omap_mcbsp_reset(s
);
4261 iomemtype
= cpu_register_io_memory(0, omap_mcbsp_readfn
,
4262 omap_mcbsp_writefn
, s
);
4263 cpu_register_physical_memory(base
, 0x800, iomemtype
);
4268 static void omap_mcbsp_i2s_swallow(void *opaque
, int line
, int level
)
4270 struct omap_mcbsp_s
*s
= (struct omap_mcbsp_s
*) opaque
;
4273 s
->rx_req
= s
->codec
->in
.len
;
4274 omap_mcbsp_rx_newdata(s
);
4278 static void omap_mcbsp_i2s_start(void *opaque
, int line
, int level
)
4280 struct omap_mcbsp_s
*s
= (struct omap_mcbsp_s
*) opaque
;
4283 s
->tx_req
= s
->codec
->out
.size
;
4284 omap_mcbsp_tx_newdata(s
);
4288 void omap_mcbsp_i2s_attach(struct omap_mcbsp_s
*s
, struct i2s_codec_s
*slave
)
4291 slave
->rx_swallow
= qemu_allocate_irqs(omap_mcbsp_i2s_swallow
, s
, 1)[0];
4292 slave
->tx_start
= qemu_allocate_irqs(omap_mcbsp_i2s_start
, s
, 1)[0];
4295 /* LED Pulse Generators */
4307 static void omap_lpg_tick(void *opaque
)
4309 struct omap_lpg_s
*s
= opaque
;
4312 qemu_mod_timer(s
->tm
, qemu_get_clock(rt_clock
) + s
->period
- s
->on
);
4314 qemu_mod_timer(s
->tm
, qemu_get_clock(rt_clock
) + s
->on
);
4316 s
->cycle
= !s
->cycle
;
4317 printf("%s: LED is %s\n", __FUNCTION__
, s
->cycle
? "on" : "off");
4320 static void omap_lpg_update(struct omap_lpg_s
*s
)
4322 int64_t on
, period
= 1, ticks
= 1000;
4323 static const int per
[8] = { 1, 2, 4, 8, 12, 16, 20, 24 };
4325 if (~s
->control
& (1 << 6)) /* LPGRES */
4327 else if (s
->control
& (1 << 7)) /* PERM_ON */
4330 period
= muldiv64(ticks
, per
[s
->control
& 7], /* PERCTRL */
4332 on
= (s
->clk
&& s
->power
) ? muldiv64(ticks
,
4333 per
[(s
->control
>> 3) & 7], 256) : 0; /* ONCTRL */
4336 qemu_del_timer(s
->tm
);
4337 if (on
== period
&& s
->on
< s
->period
)
4338 printf("%s: LED is on\n", __FUNCTION__
);
4339 else if (on
== 0 && s
->on
)
4340 printf("%s: LED is off\n", __FUNCTION__
);
4341 else if (on
&& (on
!= s
->on
|| period
!= s
->period
)) {
4353 static void omap_lpg_reset(struct omap_lpg_s
*s
)
4361 static uint32_t omap_lpg_read(void *opaque
, target_phys_addr_t addr
)
4363 struct omap_lpg_s
*s
= (struct omap_lpg_s
*) opaque
;
4364 int offset
= addr
& OMAP_MPUI_REG_MASK
;
4367 case 0x00: /* LCR */
4370 case 0x04: /* PMR */
4378 static void omap_lpg_write(void *opaque
, target_phys_addr_t addr
,
4381 struct omap_lpg_s
*s
= (struct omap_lpg_s
*) opaque
;
4382 int offset
= addr
& OMAP_MPUI_REG_MASK
;
4385 case 0x00: /* LCR */
4386 if (~value
& (1 << 6)) /* LPGRES */
4388 s
->control
= value
& 0xff;
4392 case 0x04: /* PMR */
4393 s
->power
= value
& 0x01;
4403 static CPUReadMemoryFunc
*omap_lpg_readfn
[] = {
4405 omap_badwidth_read8
,
4406 omap_badwidth_read8
,
4409 static CPUWriteMemoryFunc
*omap_lpg_writefn
[] = {
4411 omap_badwidth_write8
,
4412 omap_badwidth_write8
,
4415 static void omap_lpg_clk_update(void *opaque
, int line
, int on
)
4417 struct omap_lpg_s
*s
= (struct omap_lpg_s
*) opaque
;
4423 struct omap_lpg_s
*omap_lpg_init(target_phys_addr_t base
, omap_clk clk
)
4426 struct omap_lpg_s
*s
= (struct omap_lpg_s
*)
4427 qemu_mallocz(sizeof(struct omap_lpg_s
));
4429 s
->tm
= qemu_new_timer(rt_clock
, omap_lpg_tick
, s
);
4433 iomemtype
= cpu_register_io_memory(0, omap_lpg_readfn
,
4434 omap_lpg_writefn
, s
);
4435 cpu_register_physical_memory(base
, 0x800, iomemtype
);
4437 omap_clk_adduser(clk
, qemu_allocate_irqs(omap_lpg_clk_update
, s
, 1)[0]);
4442 /* MPUI Peripheral Bridge configuration */
4443 static uint32_t omap_mpui_io_read(void *opaque
, target_phys_addr_t addr
)
4445 if (addr
== OMAP_MPUI_BASE
) /* CMR */
4452 static CPUReadMemoryFunc
*omap_mpui_io_readfn
[] = {
4453 omap_badwidth_read16
,
4455 omap_badwidth_read16
,
4458 static CPUWriteMemoryFunc
*omap_mpui_io_writefn
[] = {
4459 omap_badwidth_write16
,
4460 omap_badwidth_write16
,
4461 omap_badwidth_write16
,
4464 static void omap_setup_mpui_io(struct omap_mpu_state_s
*mpu
)
4466 int iomemtype
= cpu_register_io_memory(0, omap_mpui_io_readfn
,
4467 omap_mpui_io_writefn
, mpu
);
4468 cpu_register_physical_memory(OMAP_MPUI_BASE
, 0x7fff, iomemtype
);
4471 /* General chip reset */
4472 static void omap1_mpu_reset(void *opaque
)
4474 struct omap_mpu_state_s
*mpu
= (struct omap_mpu_state_s
*) opaque
;
4476 omap_inth_reset(mpu
->ih
[0]);
4477 omap_inth_reset(mpu
->ih
[1]);
4478 omap_dma_reset(mpu
->dma
);
4479 omap_mpu_timer_reset(mpu
->timer
[0]);
4480 omap_mpu_timer_reset(mpu
->timer
[1]);
4481 omap_mpu_timer_reset(mpu
->timer
[2]);
4482 omap_wd_timer_reset(mpu
->wdt
);
4483 omap_os_timer_reset(mpu
->os_timer
);
4484 omap_lcdc_reset(mpu
->lcd
);
4485 omap_ulpd_pm_reset(mpu
);
4486 omap_pin_cfg_reset(mpu
);
4487 omap_mpui_reset(mpu
);
4488 omap_tipb_bridge_reset(mpu
->private_tipb
);
4489 omap_tipb_bridge_reset(mpu
->public_tipb
);
4490 omap_dpll_reset(&mpu
->dpll
[0]);
4491 omap_dpll_reset(&mpu
->dpll
[1]);
4492 omap_dpll_reset(&mpu
->dpll
[2]);
4493 omap_uart_reset(mpu
->uart
[0]);
4494 omap_uart_reset(mpu
->uart
[1]);
4495 omap_uart_reset(mpu
->uart
[2]);
4496 omap_mmc_reset(mpu
->mmc
);
4497 omap_mpuio_reset(mpu
->mpuio
);
4498 omap_gpio_reset(mpu
->gpio
);
4499 omap_uwire_reset(mpu
->microwire
);
4500 omap_pwl_reset(mpu
);
4501 omap_pwt_reset(mpu
);
4502 omap_i2c_reset(mpu
->i2c
[0]);
4503 omap_rtc_reset(mpu
->rtc
);
4504 omap_mcbsp_reset(mpu
->mcbsp1
);
4505 omap_mcbsp_reset(mpu
->mcbsp2
);
4506 omap_mcbsp_reset(mpu
->mcbsp3
);
4507 omap_lpg_reset(mpu
->led
[0]);
4508 omap_lpg_reset(mpu
->led
[1]);
4509 omap_clkm_reset(mpu
);
4510 cpu_reset(mpu
->env
);
4513 static const struct omap_map_s
{
4514 target_phys_addr_t phys_dsp
;
4515 target_phys_addr_t phys_mpu
;
4518 } omap15xx_dsp_mm
[] = {
4520 { 0xe1010000, 0xfffb0000, 0x800, "UART1 BT" }, /* CS0 */
4521 { 0xe1010800, 0xfffb0800, 0x800, "UART2 COM" }, /* CS1 */
4522 { 0xe1011800, 0xfffb1800, 0x800, "McBSP1 audio" }, /* CS3 */
4523 { 0xe1012000, 0xfffb2000, 0x800, "MCSI2 communication" }, /* CS4 */
4524 { 0xe1012800, 0xfffb2800, 0x800, "MCSI1 BT u-Law" }, /* CS5 */
4525 { 0xe1013000, 0xfffb3000, 0x800, "uWire" }, /* CS6 */
4526 { 0xe1013800, 0xfffb3800, 0x800, "I^2C" }, /* CS7 */
4527 { 0xe1014000, 0xfffb4000, 0x800, "USB W2FC" }, /* CS8 */
4528 { 0xe1014800, 0xfffb4800, 0x800, "RTC" }, /* CS9 */
4529 { 0xe1015000, 0xfffb5000, 0x800, "MPUIO" }, /* CS10 */
4530 { 0xe1015800, 0xfffb5800, 0x800, "PWL" }, /* CS11 */
4531 { 0xe1016000, 0xfffb6000, 0x800, "PWT" }, /* CS12 */
4532 { 0xe1017000, 0xfffb7000, 0x800, "McBSP3" }, /* CS14 */
4533 { 0xe1017800, 0xfffb7800, 0x800, "MMC" }, /* CS15 */
4534 { 0xe1019000, 0xfffb9000, 0x800, "32-kHz timer" }, /* CS18 */
4535 { 0xe1019800, 0xfffb9800, 0x800, "UART3" }, /* CS19 */
4536 { 0xe101c800, 0xfffbc800, 0x800, "TIPB switches" }, /* CS25 */
4538 { 0xe101e000, 0xfffce000, 0x800, "GPIOs" }, /* CS28 */
4543 static void omap_setup_dsp_mapping(const struct omap_map_s
*map
)
4547 for (; map
->phys_dsp
; map
++) {
4548 io
= cpu_get_physical_page_desc(map
->phys_mpu
);
4550 cpu_register_physical_memory(map
->phys_dsp
, map
->size
, io
);
4554 void omap_mpu_wakeup(void *opaque
, int irq
, int req
)
4556 struct omap_mpu_state_s
*mpu
= (struct omap_mpu_state_s
*) opaque
;
4558 if (mpu
->env
->halted
)
4559 cpu_interrupt(mpu
->env
, CPU_INTERRUPT_EXITTB
);
4562 static const struct dma_irq_map omap1_dma_irq_map
[] = {
4563 { 0, OMAP_INT_DMA_CH0_6
},
4564 { 0, OMAP_INT_DMA_CH1_7
},
4565 { 0, OMAP_INT_DMA_CH2_8
},
4566 { 0, OMAP_INT_DMA_CH3
},
4567 { 0, OMAP_INT_DMA_CH4
},
4568 { 0, OMAP_INT_DMA_CH5
},
4569 { 1, OMAP_INT_1610_DMA_CH6
},
4570 { 1, OMAP_INT_1610_DMA_CH7
},
4571 { 1, OMAP_INT_1610_DMA_CH8
},
4572 { 1, OMAP_INT_1610_DMA_CH9
},
4573 { 1, OMAP_INT_1610_DMA_CH10
},
4574 { 1, OMAP_INT_1610_DMA_CH11
},
4575 { 1, OMAP_INT_1610_DMA_CH12
},
4576 { 1, OMAP_INT_1610_DMA_CH13
},
4577 { 1, OMAP_INT_1610_DMA_CH14
},
4578 { 1, OMAP_INT_1610_DMA_CH15
}
4581 /* DMA ports for OMAP1 */
4582 static int omap_validate_emiff_addr(struct omap_mpu_state_s
*s
,
4583 target_phys_addr_t addr
)
4585 return addr
>= OMAP_EMIFF_BASE
&& addr
< OMAP_EMIFF_BASE
+ s
->sdram_size
;
4588 static int omap_validate_emifs_addr(struct omap_mpu_state_s
*s
,
4589 target_phys_addr_t addr
)
4591 return addr
>= OMAP_EMIFS_BASE
&& addr
< OMAP_EMIFF_BASE
;
4594 static int omap_validate_imif_addr(struct omap_mpu_state_s
*s
,
4595 target_phys_addr_t addr
)
4597 return addr
>= OMAP_IMIF_BASE
&& addr
< OMAP_IMIF_BASE
+ s
->sram_size
;
4600 static int omap_validate_tipb_addr(struct omap_mpu_state_s
*s
,
4601 target_phys_addr_t addr
)
4603 return addr
>= 0xfffb0000 && addr
< 0xffff0000;
4606 static int omap_validate_local_addr(struct omap_mpu_state_s
*s
,
4607 target_phys_addr_t addr
)
4609 return addr
>= OMAP_LOCALBUS_BASE
&& addr
< OMAP_LOCALBUS_BASE
+ 0x1000000;
4612 static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s
*s
,
4613 target_phys_addr_t addr
)
4615 return addr
>= 0xe1010000 && addr
< 0xe1020004;
4618 struct omap_mpu_state_s
*omap310_mpu_init(unsigned long sdram_size
,
4619 DisplayState
*ds
, const char *core
)
4622 struct omap_mpu_state_s
*s
= (struct omap_mpu_state_s
*)
4623 qemu_mallocz(sizeof(struct omap_mpu_state_s
));
4624 ram_addr_t imif_base
, emiff_base
;
4626 qemu_irq dma_irqs
[6];
4633 s
->mpu_model
= omap310
;
4634 s
->env
= cpu_init(core
);
4636 fprintf(stderr
, "Unable to find CPU definition\n");
4639 s
->sdram_size
= sdram_size
;
4640 s
->sram_size
= OMAP15XX_SRAM_SIZE
;
4642 s
->wakeup
= qemu_allocate_irqs(omap_mpu_wakeup
, s
, 1)[0];
4647 /* Memory-mapped stuff */
4648 cpu_register_physical_memory(OMAP_EMIFF_BASE
, s
->sdram_size
,
4649 (emiff_base
= qemu_ram_alloc(s
->sdram_size
)) | IO_MEM_RAM
);
4650 cpu_register_physical_memory(OMAP_IMIF_BASE
, s
->sram_size
,
4651 (imif_base
= qemu_ram_alloc(s
->sram_size
)) | IO_MEM_RAM
);
4653 omap_clkm_init(0xfffece00, 0xe1008000, s
);
4655 cpu_irq
= arm_pic_init_cpu(s
->env
);
4656 s
->ih
[0] = omap_inth_init(0xfffecb00, 0x100, 1, &s
->irq
[0],
4657 cpu_irq
[ARM_PIC_CPU_IRQ
], cpu_irq
[ARM_PIC_CPU_FIQ
],
4658 omap_findclk(s
, "arminth_ck"));
4659 s
->ih
[1] = omap_inth_init(0xfffe0000, 0x800, 1, &s
->irq
[1],
4660 s
->ih
[0]->pins
[OMAP_INT_15XX_IH2_IRQ
], NULL
,
4661 omap_findclk(s
, "arminth_ck"));
4663 for (i
= 0; i
< 6; i
++)
4665 s
->irq
[omap1_dma_irq_map
[i
].ih
][omap1_dma_irq_map
[i
].intr
];
4666 s
->dma
= omap_dma_init(0xfffed800, dma_irqs
, s
->irq
[0][OMAP_INT_DMA_LCD
],
4667 s
, omap_findclk(s
, "dma_ck"), omap_dma_3_1
);
4669 s
->port
[emiff
].addr_valid
= omap_validate_emiff_addr
;
4670 s
->port
[emifs
].addr_valid
= omap_validate_emifs_addr
;
4671 s
->port
[imif
].addr_valid
= omap_validate_imif_addr
;
4672 s
->port
[tipb
].addr_valid
= omap_validate_tipb_addr
;
4673 s
->port
[local
].addr_valid
= omap_validate_local_addr
;
4674 s
->port
[tipb_mpui
].addr_valid
= omap_validate_tipb_mpui_addr
;
4676 /* Register SDRAM and SRAM DMA ports for fast transfers. */
4677 soc_dma_port_add_mem_ram(s
->dma
,
4678 emiff_base
, OMAP_EMIFF_BASE
, s
->sdram_size
);
4679 soc_dma_port_add_mem_ram(s
->dma
,
4680 imif_base
, OMAP_IMIF_BASE
, s
->sram_size
);
4682 s
->timer
[0] = omap_mpu_timer_init(0xfffec500,
4683 s
->irq
[0][OMAP_INT_TIMER1
],
4684 omap_findclk(s
, "mputim_ck"));
4685 s
->timer
[1] = omap_mpu_timer_init(0xfffec600,
4686 s
->irq
[0][OMAP_INT_TIMER2
],
4687 omap_findclk(s
, "mputim_ck"));
4688 s
->timer
[2] = omap_mpu_timer_init(0xfffec700,
4689 s
->irq
[0][OMAP_INT_TIMER3
],
4690 omap_findclk(s
, "mputim_ck"));
4692 s
->wdt
= omap_wd_timer_init(0xfffec800,
4693 s
->irq
[0][OMAP_INT_WD_TIMER
],
4694 omap_findclk(s
, "armwdt_ck"));
4696 s
->os_timer
= omap_os_timer_init(0xfffb9000,
4697 s
->irq
[1][OMAP_INT_OS_TIMER
],
4698 omap_findclk(s
, "clk32-kHz"));
4700 s
->lcd
= omap_lcdc_init(0xfffec000, s
->irq
[0][OMAP_INT_LCD_CTRL
],
4701 omap_dma_get_lcdch(s
->dma
), ds
, imif_base
, emiff_base
,
4702 omap_findclk(s
, "lcd_ck"));
4704 omap_ulpd_pm_init(0xfffe0800, s
);
4705 omap_pin_cfg_init(0xfffe1000, s
);
4708 omap_mpui_init(0xfffec900, s
);
4710 s
->private_tipb
= omap_tipb_bridge_init(0xfffeca00,
4711 s
->irq
[0][OMAP_INT_BRIDGE_PRIV
],
4712 omap_findclk(s
, "tipb_ck"));
4713 s
->public_tipb
= omap_tipb_bridge_init(0xfffed300,
4714 s
->irq
[0][OMAP_INT_BRIDGE_PUB
],
4715 omap_findclk(s
, "tipb_ck"));
4717 omap_tcmi_init(0xfffecc00, s
);
4719 s
->uart
[0] = omap_uart_init(0xfffb0000, s
->irq
[1][OMAP_INT_UART1
],
4720 omap_findclk(s
, "uart1_ck"),
4721 omap_findclk(s
, "uart1_ck"),
4722 s
->drq
[OMAP_DMA_UART1_TX
], s
->drq
[OMAP_DMA_UART1_RX
],
4724 s
->uart
[1] = omap_uart_init(0xfffb0800, s
->irq
[1][OMAP_INT_UART2
],
4725 omap_findclk(s
, "uart2_ck"),
4726 omap_findclk(s
, "uart2_ck"),
4727 s
->drq
[OMAP_DMA_UART2_TX
], s
->drq
[OMAP_DMA_UART2_RX
],
4728 serial_hds
[0] ? serial_hds
[1] : 0);
4729 s
->uart
[2] = omap_uart_init(0xe1019800, s
->irq
[0][OMAP_INT_UART3
],
4730 omap_findclk(s
, "uart3_ck"),
4731 omap_findclk(s
, "uart3_ck"),
4732 s
->drq
[OMAP_DMA_UART3_TX
], s
->drq
[OMAP_DMA_UART3_RX
],
4733 serial_hds
[0] && serial_hds
[1] ? serial_hds
[2] : 0);
4735 omap_dpll_init(&s
->dpll
[0], 0xfffecf00, omap_findclk(s
, "dpll1"));
4736 omap_dpll_init(&s
->dpll
[1], 0xfffed000, omap_findclk(s
, "dpll2"));
4737 omap_dpll_init(&s
->dpll
[2], 0xfffed100, omap_findclk(s
, "dpll3"));
4739 sdindex
= drive_get_index(IF_SD
, 0, 0);
4740 if (sdindex
== -1) {
4741 fprintf(stderr
, "qemu: missing SecureDigital device\n");
4744 s
->mmc
= omap_mmc_init(0xfffb7800, drives_table
[sdindex
].bdrv
,
4745 s
->irq
[1][OMAP_INT_OQN
], &s
->drq
[OMAP_DMA_MMC_TX
],
4746 omap_findclk(s
, "mmc_ck"));
4748 s
->mpuio
= omap_mpuio_init(0xfffb5000,
4749 s
->irq
[1][OMAP_INT_KEYBOARD
], s
->irq
[1][OMAP_INT_MPUIO
],
4750 s
->wakeup
, omap_findclk(s
, "clk32-kHz"));
4752 s
->gpio
= omap_gpio_init(0xfffce000, s
->irq
[0][OMAP_INT_GPIO_BANK1
],
4753 omap_findclk(s
, "arm_gpio_ck"));
4755 s
->microwire
= omap_uwire_init(0xfffb3000, &s
->irq
[1][OMAP_INT_uWireTX
],
4756 s
->drq
[OMAP_DMA_UWIRE_TX
], omap_findclk(s
, "mpuper_ck"));
4758 omap_pwl_init(0xfffb5800, s
, omap_findclk(s
, "armxor_ck"));
4759 omap_pwt_init(0xfffb6000, s
, omap_findclk(s
, "armxor_ck"));
4761 s
->i2c
[0] = omap_i2c_init(0xfffb3800, s
->irq
[1][OMAP_INT_I2C
],
4762 &s
->drq
[OMAP_DMA_I2C_RX
], omap_findclk(s
, "mpuper_ck"));
4764 s
->rtc
= omap_rtc_init(0xfffb4800, &s
->irq
[1][OMAP_INT_RTC_TIMER
],
4765 omap_findclk(s
, "clk32-kHz"));
4767 s
->mcbsp1
= omap_mcbsp_init(0xfffb1800, &s
->irq
[1][OMAP_INT_McBSP1TX
],
4768 &s
->drq
[OMAP_DMA_MCBSP1_TX
], omap_findclk(s
, "dspxor_ck"));
4769 s
->mcbsp2
= omap_mcbsp_init(0xfffb1000, &s
->irq
[0][OMAP_INT_310_McBSP2_TX
],
4770 &s
->drq
[OMAP_DMA_MCBSP2_TX
], omap_findclk(s
, "mpuper_ck"));
4771 s
->mcbsp3
= omap_mcbsp_init(0xfffb7000, &s
->irq
[1][OMAP_INT_McBSP3TX
],
4772 &s
->drq
[OMAP_DMA_MCBSP3_TX
], omap_findclk(s
, "dspxor_ck"));
4774 s
->led
[0] = omap_lpg_init(0xfffbd000, omap_findclk(s
, "clk32-kHz"));
4775 s
->led
[1] = omap_lpg_init(0xfffbd800, omap_findclk(s
, "clk32-kHz"));
4777 /* Register mappings not currenlty implemented:
4778 * MCSI2 Comm fffb2000 - fffb27ff (not mapped on OMAP310)
4779 * MCSI1 Bluetooth fffb2800 - fffb2fff (not mapped on OMAP310)
4780 * USB W2FC fffb4000 - fffb47ff
4781 * Camera Interface fffb6800 - fffb6fff
4782 * USB Host fffba000 - fffba7ff
4783 * FAC fffba800 - fffbafff
4784 * HDQ/1-Wire fffbc000 - fffbc7ff
4785 * TIPB switches fffbc800 - fffbcfff
4786 * Mailbox fffcf000 - fffcf7ff
4787 * Local bus IF fffec100 - fffec1ff
4788 * Local bus MMU fffec200 - fffec2ff
4789 * DSP MMU fffed200 - fffed2ff
4792 omap_setup_dsp_mapping(omap15xx_dsp_mm
);
4793 omap_setup_mpui_io(s
);
4795 qemu_register_reset(omap1_mpu_reset
, s
);