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[qemu.git] / hw / omap_dma.c
1 /*
2 * TI OMAP DMA gigacell.
3 *
4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
5 * Copyright (C) 2007-2008 Lauro Ramos Venancio <lauro.venancio@indt.org.br>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22 #include "qemu-common.h"
23 #include "qemu-timer.h"
24 #include "omap.h"
25 #include "irq.h"
26 #include "soc_dma.h"
27
28 struct omap_dma_channel_s {
29 /* transfer data */
30 int burst[2];
31 int pack[2];
32 int endian[2];
33 int endian_lock[2];
34 int translate[2];
35 enum omap_dma_port port[2];
36 target_phys_addr_t addr[2];
37 omap_dma_addressing_t mode[2];
38 uint32_t elements;
39 uint16_t frames;
40 int32_t frame_index[2];
41 int16_t element_index[2];
42 int data_type;
43
44 /* transfer type */
45 int transparent_copy;
46 int constant_fill;
47 uint32_t color;
48 int prefetch;
49
50 /* auto init and linked channel data */
51 int end_prog;
52 int repeat;
53 int auto_init;
54 int link_enabled;
55 int link_next_ch;
56
57 /* interruption data */
58 int interrupts;
59 int status;
60 int cstatus;
61
62 /* state data */
63 int active;
64 int enable;
65 int sync;
66 int src_sync;
67 int pending_request;
68 int waiting_end_prog;
69 uint16_t cpc;
70 int set_update;
71
72 /* sync type */
73 int fs;
74 int bs;
75
76 /* compatibility */
77 int omap_3_1_compatible_disable;
78
79 qemu_irq irq;
80 struct omap_dma_channel_s *sibling;
81
82 struct omap_dma_reg_set_s {
83 target_phys_addr_t src, dest;
84 int frame;
85 int element;
86 int pck_element;
87 int frame_delta[2];
88 int elem_delta[2];
89 int frames;
90 int elements;
91 int pck_elements;
92 } active_set;
93
94 struct soc_dma_ch_s *dma;
95
96 /* unused parameters */
97 int write_mode;
98 int priority;
99 int interleave_disabled;
100 int type;
101 int suspend;
102 int buf_disable;
103 };
104
105 struct omap_dma_s {
106 struct soc_dma_s *dma;
107
108 struct omap_mpu_state_s *mpu;
109 target_phys_addr_t base;
110 omap_clk clk;
111 qemu_irq irq[4];
112 void (*intr_update)(struct omap_dma_s *s);
113 enum omap_dma_model model;
114 int omap_3_1_mapping_disabled;
115
116 uint32_t gcr;
117 uint32_t ocp;
118 uint32_t caps[5];
119 uint32_t irqen[4];
120 uint32_t irqstat[4];
121
122 int chans;
123 struct omap_dma_channel_s ch[32];
124 struct omap_dma_lcd_channel_s lcd_ch;
125 };
126
127 /* Interrupts */
128 #define TIMEOUT_INTR (1 << 0)
129 #define EVENT_DROP_INTR (1 << 1)
130 #define HALF_FRAME_INTR (1 << 2)
131 #define END_FRAME_INTR (1 << 3)
132 #define LAST_FRAME_INTR (1 << 4)
133 #define END_BLOCK_INTR (1 << 5)
134 #define SYNC (1 << 6)
135 #define END_PKT_INTR (1 << 7)
136 #define TRANS_ERR_INTR (1 << 8)
137 #define MISALIGN_INTR (1 << 11)
138
139 static inline void omap_dma_interrupts_update(struct omap_dma_s *s)
140 {
141 return s->intr_update(s);
142 }
143
144 static void omap_dma_channel_load(struct omap_dma_channel_s *ch)
145 {
146 struct omap_dma_reg_set_s *a = &ch->active_set;
147 int i, normal;
148 int omap_3_1 = !ch->omap_3_1_compatible_disable;
149
150 /*
151 * TODO: verify address ranges and alignment
152 * TODO: port endianness
153 */
154
155 a->src = ch->addr[0];
156 a->dest = ch->addr[1];
157 a->frames = ch->frames;
158 a->elements = ch->elements;
159 a->pck_elements = ch->frame_index[!ch->src_sync];
160 a->frame = 0;
161 a->element = 0;
162 a->pck_element = 0;
163
164 if (unlikely(!ch->elements || !ch->frames)) {
165 printf("%s: bad DMA request\n", __FUNCTION__);
166 return;
167 }
168
169 for (i = 0; i < 2; i ++)
170 switch (ch->mode[i]) {
171 case constant:
172 a->elem_delta[i] = 0;
173 a->frame_delta[i] = 0;
174 break;
175 case post_incremented:
176 a->elem_delta[i] = ch->data_type;
177 a->frame_delta[i] = 0;
178 break;
179 case single_index:
180 a->elem_delta[i] = ch->data_type +
181 ch->element_index[omap_3_1 ? 0 : i] - 1;
182 a->frame_delta[i] = 0;
183 break;
184 case double_index:
185 a->elem_delta[i] = ch->data_type +
186 ch->element_index[omap_3_1 ? 0 : i] - 1;
187 a->frame_delta[i] = ch->frame_index[omap_3_1 ? 0 : i] -
188 ch->element_index[omap_3_1 ? 0 : i];
189 break;
190 default:
191 break;
192 }
193
194 normal = !ch->transparent_copy && !ch->constant_fill &&
195 /* FIFO is big-endian so either (ch->endian[n] == 1) OR
196 * (ch->endian_lock[n] == 1) mean no endianism conversion. */
197 (ch->endian[0] | ch->endian_lock[0]) ==
198 (ch->endian[1] | ch->endian_lock[1]);
199 for (i = 0; i < 2; i ++) {
200 /* TODO: for a->frame_delta[i] > 0 still use the fast path, just
201 * limit min_elems in omap_dma_transfer_setup to the nearest frame
202 * end. */
203 if (!a->elem_delta[i] && normal &&
204 (a->frames == 1 || !a->frame_delta[i]))
205 ch->dma->type[i] = soc_dma_access_const;
206 else if (a->elem_delta[i] == ch->data_type && normal &&
207 (a->frames == 1 || !a->frame_delta[i]))
208 ch->dma->type[i] = soc_dma_access_linear;
209 else
210 ch->dma->type[i] = soc_dma_access_other;
211
212 ch->dma->vaddr[i] = ch->addr[i];
213 }
214 soc_dma_ch_update(ch->dma);
215 }
216
217 static void omap_dma_activate_channel(struct omap_dma_s *s,
218 struct omap_dma_channel_s *ch)
219 {
220 if (!ch->active) {
221 if (ch->set_update) {
222 /* It's not clear when the active set is supposed to be
223 * loaded from registers. We're already loading it when the
224 * channel is enabled, and for some guests this is not enough
225 * but that may be also because of a race condition (no
226 * delays in qemu) in the guest code, which we're just
227 * working around here. */
228 omap_dma_channel_load(ch);
229 ch->set_update = 0;
230 }
231
232 ch->active = 1;
233 soc_dma_set_request(ch->dma, 1);
234 if (ch->sync)
235 ch->status |= SYNC;
236 }
237 }
238
239 static void omap_dma_deactivate_channel(struct omap_dma_s *s,
240 struct omap_dma_channel_s *ch)
241 {
242 /* Update cpc */
243 ch->cpc = ch->active_set.dest & 0xffff;
244
245 if (ch->pending_request && !ch->waiting_end_prog && ch->enable) {
246 /* Don't deactivate the channel */
247 ch->pending_request = 0;
248 return;
249 }
250
251 /* Don't deactive the channel if it is synchronized and the DMA request is
252 active */
253 if (ch->sync && ch->enable && (s->dma->drqbmp & (1 << ch->sync)))
254 return;
255
256 if (ch->active) {
257 ch->active = 0;
258 ch->status &= ~SYNC;
259 soc_dma_set_request(ch->dma, 0);
260 }
261 }
262
263 static void omap_dma_enable_channel(struct omap_dma_s *s,
264 struct omap_dma_channel_s *ch)
265 {
266 if (!ch->enable) {
267 ch->enable = 1;
268 ch->waiting_end_prog = 0;
269 omap_dma_channel_load(ch);
270 /* TODO: theoretically if ch->sync && ch->prefetch &&
271 * !s->dma->drqbmp[ch->sync], we should also activate and fetch
272 * from source and then stall until signalled. */
273 if ((!ch->sync) || (s->dma->drqbmp & (1 << ch->sync)))
274 omap_dma_activate_channel(s, ch);
275 }
276 }
277
278 static void omap_dma_disable_channel(struct omap_dma_s *s,
279 struct omap_dma_channel_s *ch)
280 {
281 if (ch->enable) {
282 ch->enable = 0;
283 /* Discard any pending request */
284 ch->pending_request = 0;
285 omap_dma_deactivate_channel(s, ch);
286 }
287 }
288
289 static void omap_dma_channel_end_prog(struct omap_dma_s *s,
290 struct omap_dma_channel_s *ch)
291 {
292 if (ch->waiting_end_prog) {
293 ch->waiting_end_prog = 0;
294 if (!ch->sync || ch->pending_request) {
295 ch->pending_request = 0;
296 omap_dma_activate_channel(s, ch);
297 }
298 }
299 }
300
301 static void omap_dma_interrupts_3_1_update(struct omap_dma_s *s)
302 {
303 struct omap_dma_channel_s *ch = s->ch;
304
305 /* First three interrupts are shared between two channels each. */
306 if (ch[0].status | ch[6].status)
307 qemu_irq_raise(ch[0].irq);
308 if (ch[1].status | ch[7].status)
309 qemu_irq_raise(ch[1].irq);
310 if (ch[2].status | ch[8].status)
311 qemu_irq_raise(ch[2].irq);
312 if (ch[3].status)
313 qemu_irq_raise(ch[3].irq);
314 if (ch[4].status)
315 qemu_irq_raise(ch[4].irq);
316 if (ch[5].status)
317 qemu_irq_raise(ch[5].irq);
318 }
319
320 static void omap_dma_interrupts_3_2_update(struct omap_dma_s *s)
321 {
322 struct omap_dma_channel_s *ch = s->ch;
323 int i;
324
325 for (i = s->chans; i; ch ++, i --)
326 if (ch->status)
327 qemu_irq_raise(ch->irq);
328 }
329
330 static void omap_dma_enable_3_1_mapping(struct omap_dma_s *s)
331 {
332 s->omap_3_1_mapping_disabled = 0;
333 s->chans = 9;
334 s->intr_update = omap_dma_interrupts_3_1_update;
335 }
336
337 static void omap_dma_disable_3_1_mapping(struct omap_dma_s *s)
338 {
339 s->omap_3_1_mapping_disabled = 1;
340 s->chans = 16;
341 s->intr_update = omap_dma_interrupts_3_2_update;
342 }
343
344 static void omap_dma_process_request(struct omap_dma_s *s, int request)
345 {
346 int channel;
347 int drop_event = 0;
348 struct omap_dma_channel_s *ch = s->ch;
349
350 for (channel = 0; channel < s->chans; channel ++, ch ++) {
351 if (ch->enable && ch->sync == request) {
352 if (!ch->active)
353 omap_dma_activate_channel(s, ch);
354 else if (!ch->pending_request)
355 ch->pending_request = 1;
356 else {
357 /* Request collision */
358 /* Second request received while processing other request */
359 ch->status |= EVENT_DROP_INTR;
360 drop_event = 1;
361 }
362 }
363 }
364
365 if (drop_event)
366 omap_dma_interrupts_update(s);
367 }
368
369 static void omap_dma_transfer_generic(struct soc_dma_ch_s *dma)
370 {
371 uint8_t value[4];
372 struct omap_dma_channel_s *ch = dma->opaque;
373 struct omap_dma_reg_set_s *a = &ch->active_set;
374 int bytes = dma->bytes;
375 #ifdef MULTI_REQ
376 uint16_t status = ch->status;
377 #endif
378
379 do {
380 /* Transfer a single element */
381 /* FIXME: check the endianness */
382 if (!ch->constant_fill)
383 cpu_physical_memory_read(a->src, value, ch->data_type);
384 else
385 *(uint32_t *) value = ch->color;
386
387 if (!ch->transparent_copy || *(uint32_t *) value != ch->color)
388 cpu_physical_memory_write(a->dest, value, ch->data_type);
389
390 a->src += a->elem_delta[0];
391 a->dest += a->elem_delta[1];
392 a->element ++;
393
394 #ifndef MULTI_REQ
395 if (a->element == a->elements) {
396 /* End of Frame */
397 a->element = 0;
398 a->src += a->frame_delta[0];
399 a->dest += a->frame_delta[1];
400 a->frame ++;
401
402 /* If the channel is async, update cpc */
403 if (!ch->sync)
404 ch->cpc = a->dest & 0xffff;
405 }
406 } while ((bytes -= ch->data_type));
407 #else
408 /* If the channel is element synchronized, deactivate it */
409 if (ch->sync && !ch->fs && !ch->bs)
410 omap_dma_deactivate_channel(s, ch);
411
412 /* If it is the last frame, set the LAST_FRAME interrupt */
413 if (a->element == 1 && a->frame == a->frames - 1)
414 if (ch->interrupts & LAST_FRAME_INTR)
415 ch->status |= LAST_FRAME_INTR;
416
417 /* If the half of the frame was reached, set the HALF_FRAME
418 interrupt */
419 if (a->element == (a->elements >> 1))
420 if (ch->interrupts & HALF_FRAME_INTR)
421 ch->status |= HALF_FRAME_INTR;
422
423 if (ch->fs && ch->bs) {
424 a->pck_element ++;
425 /* Check if a full packet has beed transferred. */
426 if (a->pck_element == a->pck_elements) {
427 a->pck_element = 0;
428
429 /* Set the END_PKT interrupt */
430 if ((ch->interrupts & END_PKT_INTR) && !ch->src_sync)
431 ch->status |= END_PKT_INTR;
432
433 /* If the channel is packet-synchronized, deactivate it */
434 if (ch->sync)
435 omap_dma_deactivate_channel(s, ch);
436 }
437 }
438
439 if (a->element == a->elements) {
440 /* End of Frame */
441 a->element = 0;
442 a->src += a->frame_delta[0];
443 a->dest += a->frame_delta[1];
444 a->frame ++;
445
446 /* If the channel is frame synchronized, deactivate it */
447 if (ch->sync && ch->fs && !ch->bs)
448 omap_dma_deactivate_channel(s, ch);
449
450 /* If the channel is async, update cpc */
451 if (!ch->sync)
452 ch->cpc = a->dest & 0xffff;
453
454 /* Set the END_FRAME interrupt */
455 if (ch->interrupts & END_FRAME_INTR)
456 ch->status |= END_FRAME_INTR;
457
458 if (a->frame == a->frames) {
459 /* End of Block */
460 /* Disable the channel */
461
462 if (ch->omap_3_1_compatible_disable) {
463 omap_dma_disable_channel(s, ch);
464 if (ch->link_enabled)
465 omap_dma_enable_channel(s,
466 &s->ch[ch->link_next_ch]);
467 } else {
468 if (!ch->auto_init)
469 omap_dma_disable_channel(s, ch);
470 else if (ch->repeat || ch->end_prog)
471 omap_dma_channel_load(ch);
472 else {
473 ch->waiting_end_prog = 1;
474 omap_dma_deactivate_channel(s, ch);
475 }
476 }
477
478 if (ch->interrupts & END_BLOCK_INTR)
479 ch->status |= END_BLOCK_INTR;
480 }
481 }
482 } while (status == ch->status && ch->active);
483
484 omap_dma_interrupts_update(s);
485 #endif
486 }
487
488 enum {
489 omap_dma_intr_element_sync,
490 omap_dma_intr_last_frame,
491 omap_dma_intr_half_frame,
492 omap_dma_intr_frame,
493 omap_dma_intr_frame_sync,
494 omap_dma_intr_packet,
495 omap_dma_intr_packet_sync,
496 omap_dma_intr_block,
497 __omap_dma_intr_last,
498 };
499
500 static void omap_dma_transfer_setup(struct soc_dma_ch_s *dma)
501 {
502 struct omap_dma_port_if_s *src_p, *dest_p;
503 struct omap_dma_reg_set_s *a;
504 struct omap_dma_channel_s *ch = dma->opaque;
505 struct omap_dma_s *s = dma->dma->opaque;
506 int frames, min_elems, elements[__omap_dma_intr_last];
507
508 a = &ch->active_set;
509
510 src_p = &s->mpu->port[ch->port[0]];
511 dest_p = &s->mpu->port[ch->port[1]];
512 if ((!ch->constant_fill && !src_p->addr_valid(s->mpu, a->src)) ||
513 (!dest_p->addr_valid(s->mpu, a->dest))) {
514 #if 0
515 /* Bus time-out */
516 if (ch->interrupts & TIMEOUT_INTR)
517 ch->status |= TIMEOUT_INTR;
518 omap_dma_deactivate_channel(s, ch);
519 continue;
520 #endif
521 printf("%s: Bus time-out in DMA%i operation\n",
522 __FUNCTION__, dma->num);
523 }
524
525 min_elems = INT_MAX;
526
527 /* Check all the conditions that terminate the transfer starting
528 * with those that can occur the soonest. */
529 #define INTR_CHECK(cond, id, nelements) \
530 if (cond) { \
531 elements[id] = nelements; \
532 if (elements[id] < min_elems) \
533 min_elems = elements[id]; \
534 } else \
535 elements[id] = INT_MAX;
536
537 /* Elements */
538 INTR_CHECK(
539 ch->sync && !ch->fs && !ch->bs,
540 omap_dma_intr_element_sync,
541 1)
542
543 /* Frames */
544 /* TODO: for transfers where entire frames can be read and written
545 * using memcpy() but a->frame_delta is non-zero, try to still do
546 * transfers using soc_dma but limit min_elems to a->elements - ...
547 * See also the TODO in omap_dma_channel_load. */
548 INTR_CHECK(
549 (ch->interrupts & LAST_FRAME_INTR) &&
550 ((a->frame < a->frames - 1) || !a->element),
551 omap_dma_intr_last_frame,
552 (a->frames - a->frame - 2) * a->elements +
553 (a->elements - a->element + 1))
554 INTR_CHECK(
555 ch->interrupts & HALF_FRAME_INTR,
556 omap_dma_intr_half_frame,
557 (a->elements >> 1) +
558 (a->element >= (a->elements >> 1) ? a->elements : 0) -
559 a->element)
560 INTR_CHECK(
561 ch->sync && ch->fs && (ch->interrupts & END_FRAME_INTR),
562 omap_dma_intr_frame,
563 a->elements - a->element)
564 INTR_CHECK(
565 ch->sync && ch->fs && !ch->bs,
566 omap_dma_intr_frame_sync,
567 a->elements - a->element)
568
569 /* Packets */
570 INTR_CHECK(
571 ch->fs && ch->bs &&
572 (ch->interrupts & END_PKT_INTR) && !ch->src_sync,
573 omap_dma_intr_packet,
574 a->pck_elements - a->pck_element)
575 INTR_CHECK(
576 ch->fs && ch->bs && ch->sync,
577 omap_dma_intr_packet_sync,
578 a->pck_elements - a->pck_element)
579
580 /* Blocks */
581 INTR_CHECK(
582 1,
583 omap_dma_intr_block,
584 (a->frames - a->frame - 1) * a->elements +
585 (a->elements - a->element))
586
587 dma->bytes = min_elems * ch->data_type;
588
589 /* Set appropriate interrupts and/or deactivate channels */
590
591 #ifdef MULTI_REQ
592 /* TODO: should all of this only be done if dma->update, and otherwise
593 * inside omap_dma_transfer_generic below - check what's faster. */
594 if (dma->update) {
595 #endif
596
597 /* If the channel is element synchronized, deactivate it */
598 if (min_elems == elements[omap_dma_intr_element_sync])
599 omap_dma_deactivate_channel(s, ch);
600
601 /* If it is the last frame, set the LAST_FRAME interrupt */
602 if (min_elems == elements[omap_dma_intr_last_frame])
603 ch->status |= LAST_FRAME_INTR;
604
605 /* If exactly half of the frame was reached, set the HALF_FRAME
606 interrupt */
607 if (min_elems == elements[omap_dma_intr_half_frame])
608 ch->status |= HALF_FRAME_INTR;
609
610 /* If a full packet has been transferred, set the END_PKT interrupt */
611 if (min_elems == elements[omap_dma_intr_packet])
612 ch->status |= END_PKT_INTR;
613
614 /* If the channel is packet-synchronized, deactivate it */
615 if (min_elems == elements[omap_dma_intr_packet_sync])
616 omap_dma_deactivate_channel(s, ch);
617
618 /* If the channel is frame synchronized, deactivate it */
619 if (min_elems == elements[omap_dma_intr_frame_sync])
620 omap_dma_deactivate_channel(s, ch);
621
622 /* Set the END_FRAME interrupt */
623 if (min_elems == elements[omap_dma_intr_frame])
624 ch->status |= END_FRAME_INTR;
625
626 if (min_elems == elements[omap_dma_intr_block]) {
627 /* End of Block */
628 /* Disable the channel */
629
630 if (ch->omap_3_1_compatible_disable) {
631 omap_dma_disable_channel(s, ch);
632 if (ch->link_enabled)
633 omap_dma_enable_channel(s, &s->ch[ch->link_next_ch]);
634 } else {
635 if (!ch->auto_init)
636 omap_dma_disable_channel(s, ch);
637 else if (ch->repeat || ch->end_prog)
638 omap_dma_channel_load(ch);
639 else {
640 ch->waiting_end_prog = 1;
641 omap_dma_deactivate_channel(s, ch);
642 }
643 }
644
645 if (ch->interrupts & END_BLOCK_INTR)
646 ch->status |= END_BLOCK_INTR;
647 }
648
649 /* Update packet number */
650 if (ch->fs && ch->bs) {
651 a->pck_element += min_elems;
652 a->pck_element %= a->pck_elements;
653 }
654
655 /* TODO: check if we really need to update anything here or perhaps we
656 * can skip part of this. */
657 #ifndef MULTI_REQ
658 if (dma->update) {
659 #endif
660 a->element += min_elems;
661
662 frames = a->element / a->elements;
663 a->element = a->element % a->elements;
664 a->frame += frames;
665 a->src += min_elems * a->elem_delta[0] + frames * a->frame_delta[0];
666 a->dest += min_elems * a->elem_delta[1] + frames * a->frame_delta[1];
667
668 /* If the channel is async, update cpc */
669 if (!ch->sync && frames)
670 ch->cpc = a->dest & 0xffff;
671 }
672
673 omap_dma_interrupts_update(s);
674 }
675
676 void omap_dma_reset(struct soc_dma_s *dma)
677 {
678 int i;
679 struct omap_dma_s *s = dma->opaque;
680
681 soc_dma_reset(s->dma);
682 if (s->model < omap_dma_4)
683 s->gcr = 0x0004;
684 else
685 s->gcr = 0x00010010;
686 s->ocp = 0x00000000;
687 memset(&s->irqstat, 0, sizeof(s->irqstat));
688 memset(&s->irqen, 0, sizeof(s->irqen));
689 s->lcd_ch.src = emiff;
690 s->lcd_ch.condition = 0;
691 s->lcd_ch.interrupts = 0;
692 s->lcd_ch.dual = 0;
693 if (s->model < omap_dma_4)
694 omap_dma_enable_3_1_mapping(s);
695 for (i = 0; i < s->chans; i ++) {
696 s->ch[i].suspend = 0;
697 s->ch[i].prefetch = 0;
698 s->ch[i].buf_disable = 0;
699 s->ch[i].src_sync = 0;
700 memset(&s->ch[i].burst, 0, sizeof(s->ch[i].burst));
701 memset(&s->ch[i].port, 0, sizeof(s->ch[i].port));
702 memset(&s->ch[i].mode, 0, sizeof(s->ch[i].mode));
703 memset(&s->ch[i].frame_index, 0, sizeof(s->ch[i].frame_index));
704 memset(&s->ch[i].element_index, 0, sizeof(s->ch[i].element_index));
705 memset(&s->ch[i].endian, 0, sizeof(s->ch[i].endian));
706 memset(&s->ch[i].endian_lock, 0, sizeof(s->ch[i].endian_lock));
707 memset(&s->ch[i].translate, 0, sizeof(s->ch[i].translate));
708 s->ch[i].write_mode = 0;
709 s->ch[i].data_type = 0;
710 s->ch[i].transparent_copy = 0;
711 s->ch[i].constant_fill = 0;
712 s->ch[i].color = 0x00000000;
713 s->ch[i].end_prog = 0;
714 s->ch[i].repeat = 0;
715 s->ch[i].auto_init = 0;
716 s->ch[i].link_enabled = 0;
717 if (s->model < omap_dma_4)
718 s->ch[i].interrupts = 0x0003;
719 else
720 s->ch[i].interrupts = 0x0000;
721 s->ch[i].status = 0;
722 s->ch[i].cstatus = 0;
723 s->ch[i].active = 0;
724 s->ch[i].enable = 0;
725 s->ch[i].sync = 0;
726 s->ch[i].pending_request = 0;
727 s->ch[i].waiting_end_prog = 0;
728 s->ch[i].cpc = 0x0000;
729 s->ch[i].fs = 0;
730 s->ch[i].bs = 0;
731 s->ch[i].omap_3_1_compatible_disable = 0;
732 memset(&s->ch[i].active_set, 0, sizeof(s->ch[i].active_set));
733 s->ch[i].priority = 0;
734 s->ch[i].interleave_disabled = 0;
735 s->ch[i].type = 0;
736 }
737 }
738
739 static int omap_dma_ch_reg_read(struct omap_dma_s *s,
740 struct omap_dma_channel_s *ch, int reg, uint16_t *value)
741 {
742 switch (reg) {
743 case 0x00: /* SYS_DMA_CSDP_CH0 */
744 *value = (ch->burst[1] << 14) |
745 (ch->pack[1] << 13) |
746 (ch->port[1] << 9) |
747 (ch->burst[0] << 7) |
748 (ch->pack[0] << 6) |
749 (ch->port[0] << 2) |
750 (ch->data_type >> 1);
751 break;
752
753 case 0x02: /* SYS_DMA_CCR_CH0 */
754 if (s->model <= omap_dma_3_1)
755 *value = 0 << 10; /* FIFO_FLUSH reads as 0 */
756 else
757 *value = ch->omap_3_1_compatible_disable << 10;
758 *value |= (ch->mode[1] << 14) |
759 (ch->mode[0] << 12) |
760 (ch->end_prog << 11) |
761 (ch->repeat << 9) |
762 (ch->auto_init << 8) |
763 (ch->enable << 7) |
764 (ch->priority << 6) |
765 (ch->fs << 5) | ch->sync;
766 break;
767
768 case 0x04: /* SYS_DMA_CICR_CH0 */
769 *value = ch->interrupts;
770 break;
771
772 case 0x06: /* SYS_DMA_CSR_CH0 */
773 *value = ch->status;
774 ch->status &= SYNC;
775 if (!ch->omap_3_1_compatible_disable && ch->sibling) {
776 *value |= (ch->sibling->status & 0x3f) << 6;
777 ch->sibling->status &= SYNC;
778 }
779 qemu_irq_lower(ch->irq);
780 break;
781
782 case 0x08: /* SYS_DMA_CSSA_L_CH0 */
783 *value = ch->addr[0] & 0x0000ffff;
784 break;
785
786 case 0x0a: /* SYS_DMA_CSSA_U_CH0 */
787 *value = ch->addr[0] >> 16;
788 break;
789
790 case 0x0c: /* SYS_DMA_CDSA_L_CH0 */
791 *value = ch->addr[1] & 0x0000ffff;
792 break;
793
794 case 0x0e: /* SYS_DMA_CDSA_U_CH0 */
795 *value = ch->addr[1] >> 16;
796 break;
797
798 case 0x10: /* SYS_DMA_CEN_CH0 */
799 *value = ch->elements;
800 break;
801
802 case 0x12: /* SYS_DMA_CFN_CH0 */
803 *value = ch->frames;
804 break;
805
806 case 0x14: /* SYS_DMA_CFI_CH0 */
807 *value = ch->frame_index[0];
808 break;
809
810 case 0x16: /* SYS_DMA_CEI_CH0 */
811 *value = ch->element_index[0];
812 break;
813
814 case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */
815 if (ch->omap_3_1_compatible_disable)
816 *value = ch->active_set.src & 0xffff; /* CSAC */
817 else
818 *value = ch->cpc;
819 break;
820
821 case 0x1a: /* DMA_CDAC */
822 *value = ch->active_set.dest & 0xffff; /* CDAC */
823 break;
824
825 case 0x1c: /* DMA_CDEI */
826 *value = ch->element_index[1];
827 break;
828
829 case 0x1e: /* DMA_CDFI */
830 *value = ch->frame_index[1];
831 break;
832
833 case 0x20: /* DMA_COLOR_L */
834 *value = ch->color & 0xffff;
835 break;
836
837 case 0x22: /* DMA_COLOR_U */
838 *value = ch->color >> 16;
839 break;
840
841 case 0x24: /* DMA_CCR2 */
842 *value = (ch->bs << 2) |
843 (ch->transparent_copy << 1) |
844 ch->constant_fill;
845 break;
846
847 case 0x28: /* DMA_CLNK_CTRL */
848 *value = (ch->link_enabled << 15) |
849 (ch->link_next_ch & 0xf);
850 break;
851
852 case 0x2a: /* DMA_LCH_CTRL */
853 *value = (ch->interleave_disabled << 15) |
854 ch->type;
855 break;
856
857 default:
858 return 1;
859 }
860 return 0;
861 }
862
863 static int omap_dma_ch_reg_write(struct omap_dma_s *s,
864 struct omap_dma_channel_s *ch, int reg, uint16_t value)
865 {
866 switch (reg) {
867 case 0x00: /* SYS_DMA_CSDP_CH0 */
868 ch->burst[1] = (value & 0xc000) >> 14;
869 ch->pack[1] = (value & 0x2000) >> 13;
870 ch->port[1] = (enum omap_dma_port) ((value & 0x1e00) >> 9);
871 ch->burst[0] = (value & 0x0180) >> 7;
872 ch->pack[0] = (value & 0x0040) >> 6;
873 ch->port[0] = (enum omap_dma_port) ((value & 0x003c) >> 2);
874 ch->data_type = 1 << (value & 3);
875 if (ch->port[0] >= __omap_dma_port_last)
876 printf("%s: invalid DMA port %i\n", __FUNCTION__,
877 ch->port[0]);
878 if (ch->port[1] >= __omap_dma_port_last)
879 printf("%s: invalid DMA port %i\n", __FUNCTION__,
880 ch->port[1]);
881 if ((value & 3) == 3)
882 printf("%s: bad data_type for DMA channel\n", __FUNCTION__);
883 break;
884
885 case 0x02: /* SYS_DMA_CCR_CH0 */
886 ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14);
887 ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12);
888 ch->end_prog = (value & 0x0800) >> 11;
889 if (s->model >= omap_dma_3_2)
890 ch->omap_3_1_compatible_disable = (value >> 10) & 0x1;
891 ch->repeat = (value & 0x0200) >> 9;
892 ch->auto_init = (value & 0x0100) >> 8;
893 ch->priority = (value & 0x0040) >> 6;
894 ch->fs = (value & 0x0020) >> 5;
895 ch->sync = value & 0x001f;
896
897 if (value & 0x0080)
898 omap_dma_enable_channel(s, ch);
899 else
900 omap_dma_disable_channel(s, ch);
901
902 if (ch->end_prog)
903 omap_dma_channel_end_prog(s, ch);
904
905 break;
906
907 case 0x04: /* SYS_DMA_CICR_CH0 */
908 ch->interrupts = value & 0x3f;
909 break;
910
911 case 0x06: /* SYS_DMA_CSR_CH0 */
912 OMAP_RO_REG((target_phys_addr_t) reg);
913 break;
914
915 case 0x08: /* SYS_DMA_CSSA_L_CH0 */
916 ch->addr[0] &= 0xffff0000;
917 ch->addr[0] |= value;
918 break;
919
920 case 0x0a: /* SYS_DMA_CSSA_U_CH0 */
921 ch->addr[0] &= 0x0000ffff;
922 ch->addr[0] |= (uint32_t) value << 16;
923 break;
924
925 case 0x0c: /* SYS_DMA_CDSA_L_CH0 */
926 ch->addr[1] &= 0xffff0000;
927 ch->addr[1] |= value;
928 break;
929
930 case 0x0e: /* SYS_DMA_CDSA_U_CH0 */
931 ch->addr[1] &= 0x0000ffff;
932 ch->addr[1] |= (uint32_t) value << 16;
933 break;
934
935 case 0x10: /* SYS_DMA_CEN_CH0 */
936 ch->elements = value;
937 break;
938
939 case 0x12: /* SYS_DMA_CFN_CH0 */
940 ch->frames = value;
941 break;
942
943 case 0x14: /* SYS_DMA_CFI_CH0 */
944 ch->frame_index[0] = (int16_t) value;
945 break;
946
947 case 0x16: /* SYS_DMA_CEI_CH0 */
948 ch->element_index[0] = (int16_t) value;
949 break;
950
951 case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */
952 OMAP_RO_REG((target_phys_addr_t) reg);
953 break;
954
955 case 0x1c: /* DMA_CDEI */
956 ch->element_index[1] = (int16_t) value;
957 break;
958
959 case 0x1e: /* DMA_CDFI */
960 ch->frame_index[1] = (int16_t) value;
961 break;
962
963 case 0x20: /* DMA_COLOR_L */
964 ch->color &= 0xffff0000;
965 ch->color |= value;
966 break;
967
968 case 0x22: /* DMA_COLOR_U */
969 ch->color &= 0xffff;
970 ch->color |= value << 16;
971 break;
972
973 case 0x24: /* DMA_CCR2 */
974 ch->bs = (value >> 2) & 0x1;
975 ch->transparent_copy = (value >> 1) & 0x1;
976 ch->constant_fill = value & 0x1;
977 break;
978
979 case 0x28: /* DMA_CLNK_CTRL */
980 ch->link_enabled = (value >> 15) & 0x1;
981 if (value & (1 << 14)) { /* Stop_Lnk */
982 ch->link_enabled = 0;
983 omap_dma_disable_channel(s, ch);
984 }
985 ch->link_next_ch = value & 0x1f;
986 break;
987
988 case 0x2a: /* DMA_LCH_CTRL */
989 ch->interleave_disabled = (value >> 15) & 0x1;
990 ch->type = value & 0xf;
991 break;
992
993 default:
994 return 1;
995 }
996 return 0;
997 }
998
999 static int omap_dma_3_2_lcd_write(struct omap_dma_lcd_channel_s *s, int offset,
1000 uint16_t value)
1001 {
1002 switch (offset) {
1003 case 0xbc0: /* DMA_LCD_CSDP */
1004 s->brust_f2 = (value >> 14) & 0x3;
1005 s->pack_f2 = (value >> 13) & 0x1;
1006 s->data_type_f2 = (1 << ((value >> 11) & 0x3));
1007 s->brust_f1 = (value >> 7) & 0x3;
1008 s->pack_f1 = (value >> 6) & 0x1;
1009 s->data_type_f1 = (1 << ((value >> 0) & 0x3));
1010 break;
1011
1012 case 0xbc2: /* DMA_LCD_CCR */
1013 s->mode_f2 = (value >> 14) & 0x3;
1014 s->mode_f1 = (value >> 12) & 0x3;
1015 s->end_prog = (value >> 11) & 0x1;
1016 s->omap_3_1_compatible_disable = (value >> 10) & 0x1;
1017 s->repeat = (value >> 9) & 0x1;
1018 s->auto_init = (value >> 8) & 0x1;
1019 s->running = (value >> 7) & 0x1;
1020 s->priority = (value >> 6) & 0x1;
1021 s->bs = (value >> 4) & 0x1;
1022 break;
1023
1024 case 0xbc4: /* DMA_LCD_CTRL */
1025 s->dst = (value >> 8) & 0x1;
1026 s->src = ((value >> 6) & 0x3) << 1;
1027 s->condition = 0;
1028 /* Assume no bus errors and thus no BUS_ERROR irq bits. */
1029 s->interrupts = (value >> 1) & 1;
1030 s->dual = value & 1;
1031 break;
1032
1033 case 0xbc8: /* TOP_B1_L */
1034 s->src_f1_top &= 0xffff0000;
1035 s->src_f1_top |= 0x0000ffff & value;
1036 break;
1037
1038 case 0xbca: /* TOP_B1_U */
1039 s->src_f1_top &= 0x0000ffff;
1040 s->src_f1_top |= value << 16;
1041 break;
1042
1043 case 0xbcc: /* BOT_B1_L */
1044 s->src_f1_bottom &= 0xffff0000;
1045 s->src_f1_bottom |= 0x0000ffff & value;
1046 break;
1047
1048 case 0xbce: /* BOT_B1_U */
1049 s->src_f1_bottom &= 0x0000ffff;
1050 s->src_f1_bottom |= (uint32_t) value << 16;
1051 break;
1052
1053 case 0xbd0: /* TOP_B2_L */
1054 s->src_f2_top &= 0xffff0000;
1055 s->src_f2_top |= 0x0000ffff & value;
1056 break;
1057
1058 case 0xbd2: /* TOP_B2_U */
1059 s->src_f2_top &= 0x0000ffff;
1060 s->src_f2_top |= (uint32_t) value << 16;
1061 break;
1062
1063 case 0xbd4: /* BOT_B2_L */
1064 s->src_f2_bottom &= 0xffff0000;
1065 s->src_f2_bottom |= 0x0000ffff & value;
1066 break;
1067
1068 case 0xbd6: /* BOT_B2_U */
1069 s->src_f2_bottom &= 0x0000ffff;
1070 s->src_f2_bottom |= (uint32_t) value << 16;
1071 break;
1072
1073 case 0xbd8: /* DMA_LCD_SRC_EI_B1 */
1074 s->element_index_f1 = value;
1075 break;
1076
1077 case 0xbda: /* DMA_LCD_SRC_FI_B1_L */
1078 s->frame_index_f1 &= 0xffff0000;
1079 s->frame_index_f1 |= 0x0000ffff & value;
1080 break;
1081
1082 case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */
1083 s->frame_index_f1 &= 0x0000ffff;
1084 s->frame_index_f1 |= (uint32_t) value << 16;
1085 break;
1086
1087 case 0xbdc: /* DMA_LCD_SRC_EI_B2 */
1088 s->element_index_f2 = value;
1089 break;
1090
1091 case 0xbde: /* DMA_LCD_SRC_FI_B2_L */
1092 s->frame_index_f2 &= 0xffff0000;
1093 s->frame_index_f2 |= 0x0000ffff & value;
1094 break;
1095
1096 case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */
1097 s->frame_index_f2 &= 0x0000ffff;
1098 s->frame_index_f2 |= (uint32_t) value << 16;
1099 break;
1100
1101 case 0xbe0: /* DMA_LCD_SRC_EN_B1 */
1102 s->elements_f1 = value;
1103 break;
1104
1105 case 0xbe4: /* DMA_LCD_SRC_FN_B1 */
1106 s->frames_f1 = value;
1107 break;
1108
1109 case 0xbe2: /* DMA_LCD_SRC_EN_B2 */
1110 s->elements_f2 = value;
1111 break;
1112
1113 case 0xbe6: /* DMA_LCD_SRC_FN_B2 */
1114 s->frames_f2 = value;
1115 break;
1116
1117 case 0xbea: /* DMA_LCD_LCH_CTRL */
1118 s->lch_type = value & 0xf;
1119 break;
1120
1121 default:
1122 return 1;
1123 }
1124 return 0;
1125 }
1126
1127 static int omap_dma_3_2_lcd_read(struct omap_dma_lcd_channel_s *s, int offset,
1128 uint16_t *ret)
1129 {
1130 switch (offset) {
1131 case 0xbc0: /* DMA_LCD_CSDP */
1132 *ret = (s->brust_f2 << 14) |
1133 (s->pack_f2 << 13) |
1134 ((s->data_type_f2 >> 1) << 11) |
1135 (s->brust_f1 << 7) |
1136 (s->pack_f1 << 6) |
1137 ((s->data_type_f1 >> 1) << 0);
1138 break;
1139
1140 case 0xbc2: /* DMA_LCD_CCR */
1141 *ret = (s->mode_f2 << 14) |
1142 (s->mode_f1 << 12) |
1143 (s->end_prog << 11) |
1144 (s->omap_3_1_compatible_disable << 10) |
1145 (s->repeat << 9) |
1146 (s->auto_init << 8) |
1147 (s->running << 7) |
1148 (s->priority << 6) |
1149 (s->bs << 4);
1150 break;
1151
1152 case 0xbc4: /* DMA_LCD_CTRL */
1153 qemu_irq_lower(s->irq);
1154 *ret = (s->dst << 8) |
1155 ((s->src & 0x6) << 5) |
1156 (s->condition << 3) |
1157 (s->interrupts << 1) |
1158 s->dual;
1159 break;
1160
1161 case 0xbc8: /* TOP_B1_L */
1162 *ret = s->src_f1_top & 0xffff;
1163 break;
1164
1165 case 0xbca: /* TOP_B1_U */
1166 *ret = s->src_f1_top >> 16;
1167 break;
1168
1169 case 0xbcc: /* BOT_B1_L */
1170 *ret = s->src_f1_bottom & 0xffff;
1171 break;
1172
1173 case 0xbce: /* BOT_B1_U */
1174 *ret = s->src_f1_bottom >> 16;
1175 break;
1176
1177 case 0xbd0: /* TOP_B2_L */
1178 *ret = s->src_f2_top & 0xffff;
1179 break;
1180
1181 case 0xbd2: /* TOP_B2_U */
1182 *ret = s->src_f2_top >> 16;
1183 break;
1184
1185 case 0xbd4: /* BOT_B2_L */
1186 *ret = s->src_f2_bottom & 0xffff;
1187 break;
1188
1189 case 0xbd6: /* BOT_B2_U */
1190 *ret = s->src_f2_bottom >> 16;
1191 break;
1192
1193 case 0xbd8: /* DMA_LCD_SRC_EI_B1 */
1194 *ret = s->element_index_f1;
1195 break;
1196
1197 case 0xbda: /* DMA_LCD_SRC_FI_B1_L */
1198 *ret = s->frame_index_f1 & 0xffff;
1199 break;
1200
1201 case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */
1202 *ret = s->frame_index_f1 >> 16;
1203 break;
1204
1205 case 0xbdc: /* DMA_LCD_SRC_EI_B2 */
1206 *ret = s->element_index_f2;
1207 break;
1208
1209 case 0xbde: /* DMA_LCD_SRC_FI_B2_L */
1210 *ret = s->frame_index_f2 & 0xffff;
1211 break;
1212
1213 case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */
1214 *ret = s->frame_index_f2 >> 16;
1215 break;
1216
1217 case 0xbe0: /* DMA_LCD_SRC_EN_B1 */
1218 *ret = s->elements_f1;
1219 break;
1220
1221 case 0xbe4: /* DMA_LCD_SRC_FN_B1 */
1222 *ret = s->frames_f1;
1223 break;
1224
1225 case 0xbe2: /* DMA_LCD_SRC_EN_B2 */
1226 *ret = s->elements_f2;
1227 break;
1228
1229 case 0xbe6: /* DMA_LCD_SRC_FN_B2 */
1230 *ret = s->frames_f2;
1231 break;
1232
1233 case 0xbea: /* DMA_LCD_LCH_CTRL */
1234 *ret = s->lch_type;
1235 break;
1236
1237 default:
1238 return 1;
1239 }
1240 return 0;
1241 }
1242
1243 static int omap_dma_3_1_lcd_write(struct omap_dma_lcd_channel_s *s, int offset,
1244 uint16_t value)
1245 {
1246 switch (offset) {
1247 case 0x300: /* SYS_DMA_LCD_CTRL */
1248 s->src = (value & 0x40) ? imif : emiff;
1249 s->condition = 0;
1250 /* Assume no bus errors and thus no BUS_ERROR irq bits. */
1251 s->interrupts = (value >> 1) & 1;
1252 s->dual = value & 1;
1253 break;
1254
1255 case 0x302: /* SYS_DMA_LCD_TOP_F1_L */
1256 s->src_f1_top &= 0xffff0000;
1257 s->src_f1_top |= 0x0000ffff & value;
1258 break;
1259
1260 case 0x304: /* SYS_DMA_LCD_TOP_F1_U */
1261 s->src_f1_top &= 0x0000ffff;
1262 s->src_f1_top |= value << 16;
1263 break;
1264
1265 case 0x306: /* SYS_DMA_LCD_BOT_F1_L */
1266 s->src_f1_bottom &= 0xffff0000;
1267 s->src_f1_bottom |= 0x0000ffff & value;
1268 break;
1269
1270 case 0x308: /* SYS_DMA_LCD_BOT_F1_U */
1271 s->src_f1_bottom &= 0x0000ffff;
1272 s->src_f1_bottom |= value << 16;
1273 break;
1274
1275 case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */
1276 s->src_f2_top &= 0xffff0000;
1277 s->src_f2_top |= 0x0000ffff & value;
1278 break;
1279
1280 case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */
1281 s->src_f2_top &= 0x0000ffff;
1282 s->src_f2_top |= value << 16;
1283 break;
1284
1285 case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */
1286 s->src_f2_bottom &= 0xffff0000;
1287 s->src_f2_bottom |= 0x0000ffff & value;
1288 break;
1289
1290 case 0x310: /* SYS_DMA_LCD_BOT_F2_U */
1291 s->src_f2_bottom &= 0x0000ffff;
1292 s->src_f2_bottom |= value << 16;
1293 break;
1294
1295 default:
1296 return 1;
1297 }
1298 return 0;
1299 }
1300
1301 static int omap_dma_3_1_lcd_read(struct omap_dma_lcd_channel_s *s, int offset,
1302 uint16_t *ret)
1303 {
1304 int i;
1305
1306 switch (offset) {
1307 case 0x300: /* SYS_DMA_LCD_CTRL */
1308 i = s->condition;
1309 s->condition = 0;
1310 qemu_irq_lower(s->irq);
1311 *ret = ((s->src == imif) << 6) | (i << 3) |
1312 (s->interrupts << 1) | s->dual;
1313 break;
1314
1315 case 0x302: /* SYS_DMA_LCD_TOP_F1_L */
1316 *ret = s->src_f1_top & 0xffff;
1317 break;
1318
1319 case 0x304: /* SYS_DMA_LCD_TOP_F1_U */
1320 *ret = s->src_f1_top >> 16;
1321 break;
1322
1323 case 0x306: /* SYS_DMA_LCD_BOT_F1_L */
1324 *ret = s->src_f1_bottom & 0xffff;
1325 break;
1326
1327 case 0x308: /* SYS_DMA_LCD_BOT_F1_U */
1328 *ret = s->src_f1_bottom >> 16;
1329 break;
1330
1331 case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */
1332 *ret = s->src_f2_top & 0xffff;
1333 break;
1334
1335 case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */
1336 *ret = s->src_f2_top >> 16;
1337 break;
1338
1339 case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */
1340 *ret = s->src_f2_bottom & 0xffff;
1341 break;
1342
1343 case 0x310: /* SYS_DMA_LCD_BOT_F2_U */
1344 *ret = s->src_f2_bottom >> 16;
1345 break;
1346
1347 default:
1348 return 1;
1349 }
1350 return 0;
1351 }
1352
1353 static int omap_dma_sys_write(struct omap_dma_s *s, int offset, uint16_t value)
1354 {
1355 switch (offset) {
1356 case 0x400: /* SYS_DMA_GCR */
1357 s->gcr = value;
1358 break;
1359
1360 case 0x404: /* DMA_GSCR */
1361 if (value & 0x8)
1362 omap_dma_disable_3_1_mapping(s);
1363 else
1364 omap_dma_enable_3_1_mapping(s);
1365 break;
1366
1367 case 0x408: /* DMA_GRST */
1368 if (value & 0x1)
1369 omap_dma_reset(s->dma);
1370 break;
1371
1372 default:
1373 return 1;
1374 }
1375 return 0;
1376 }
1377
1378 static int omap_dma_sys_read(struct omap_dma_s *s, int offset,
1379 uint16_t *ret)
1380 {
1381 switch (offset) {
1382 case 0x400: /* SYS_DMA_GCR */
1383 *ret = s->gcr;
1384 break;
1385
1386 case 0x404: /* DMA_GSCR */
1387 *ret = s->omap_3_1_mapping_disabled << 3;
1388 break;
1389
1390 case 0x408: /* DMA_GRST */
1391 *ret = 0;
1392 break;
1393
1394 case 0x442: /* DMA_HW_ID */
1395 case 0x444: /* DMA_PCh2_ID */
1396 case 0x446: /* DMA_PCh0_ID */
1397 case 0x448: /* DMA_PCh1_ID */
1398 case 0x44a: /* DMA_PChG_ID */
1399 case 0x44c: /* DMA_PChD_ID */
1400 *ret = 1;
1401 break;
1402
1403 case 0x44e: /* DMA_CAPS_0_U */
1404 *ret = (s->caps[0] >> 16) & 0xffff;
1405 break;
1406 case 0x450: /* DMA_CAPS_0_L */
1407 *ret = (s->caps[0] >> 0) & 0xffff;
1408 break;
1409
1410 case 0x452: /* DMA_CAPS_1_U */
1411 *ret = (s->caps[1] >> 16) & 0xffff;
1412 break;
1413 case 0x454: /* DMA_CAPS_1_L */
1414 *ret = (s->caps[1] >> 0) & 0xffff;
1415 break;
1416
1417 case 0x456: /* DMA_CAPS_2 */
1418 *ret = s->caps[2];
1419 break;
1420
1421 case 0x458: /* DMA_CAPS_3 */
1422 *ret = s->caps[3];
1423 break;
1424
1425 case 0x45a: /* DMA_CAPS_4 */
1426 *ret = s->caps[4];
1427 break;
1428
1429 case 0x460: /* DMA_PCh2_SR */
1430 case 0x480: /* DMA_PCh0_SR */
1431 case 0x482: /* DMA_PCh1_SR */
1432 case 0x4c0: /* DMA_PChD_SR_0 */
1433 printf("%s: Physical Channel Status Registers not implemented.\n",
1434 __FUNCTION__);
1435 *ret = 0xff;
1436 break;
1437
1438 default:
1439 return 1;
1440 }
1441 return 0;
1442 }
1443
1444 static uint32_t omap_dma_read(void *opaque, target_phys_addr_t addr)
1445 {
1446 struct omap_dma_s *s = (struct omap_dma_s *) opaque;
1447 int reg, ch, offset = addr - s->base;
1448 uint16_t ret;
1449
1450 switch (offset) {
1451 case 0x300 ... 0x3fe:
1452 if (s->model <= omap_dma_3_1 || !s->omap_3_1_mapping_disabled) {
1453 if (omap_dma_3_1_lcd_read(&s->lcd_ch, offset, &ret))
1454 break;
1455 return ret;
1456 }
1457 /* Fall through. */
1458 case 0x000 ... 0x2fe:
1459 reg = offset & 0x3f;
1460 ch = (offset >> 6) & 0x0f;
1461 if (omap_dma_ch_reg_read(s, &s->ch[ch], reg, &ret))
1462 break;
1463 return ret;
1464
1465 case 0x404 ... 0x4fe:
1466 if (s->model <= omap_dma_3_1)
1467 break;
1468 /* Fall through. */
1469 case 0x400:
1470 if (omap_dma_sys_read(s, offset, &ret))
1471 break;
1472 return ret;
1473
1474 case 0xb00 ... 0xbfe:
1475 if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) {
1476 if (omap_dma_3_2_lcd_read(&s->lcd_ch, offset, &ret))
1477 break;
1478 return ret;
1479 }
1480 break;
1481 }
1482
1483 OMAP_BAD_REG(addr);
1484 return 0;
1485 }
1486
1487 static void omap_dma_write(void *opaque, target_phys_addr_t addr,
1488 uint32_t value)
1489 {
1490 struct omap_dma_s *s = (struct omap_dma_s *) opaque;
1491 int reg, ch, offset = addr - s->base;
1492
1493 switch (offset) {
1494 case 0x300 ... 0x3fe:
1495 if (s->model <= omap_dma_3_1 || !s->omap_3_1_mapping_disabled) {
1496 if (omap_dma_3_1_lcd_write(&s->lcd_ch, offset, value))
1497 break;
1498 return;
1499 }
1500 /* Fall through. */
1501 case 0x000 ... 0x2fe:
1502 reg = offset & 0x3f;
1503 ch = (offset >> 6) & 0x0f;
1504 if (omap_dma_ch_reg_write(s, &s->ch[ch], reg, value))
1505 break;
1506 return;
1507
1508 case 0x404 ... 0x4fe:
1509 if (s->model <= omap_dma_3_1)
1510 break;
1511 case 0x400:
1512 /* Fall through. */
1513 if (omap_dma_sys_write(s, offset, value))
1514 break;
1515 return;
1516
1517 case 0xb00 ... 0xbfe:
1518 if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) {
1519 if (omap_dma_3_2_lcd_write(&s->lcd_ch, offset, value))
1520 break;
1521 return;
1522 }
1523 break;
1524 }
1525
1526 OMAP_BAD_REG(addr);
1527 }
1528
1529 static CPUReadMemoryFunc *omap_dma_readfn[] = {
1530 omap_badwidth_read16,
1531 omap_dma_read,
1532 omap_badwidth_read16,
1533 };
1534
1535 static CPUWriteMemoryFunc *omap_dma_writefn[] = {
1536 omap_badwidth_write16,
1537 omap_dma_write,
1538 omap_badwidth_write16,
1539 };
1540
1541 static void omap_dma_request(void *opaque, int drq, int req)
1542 {
1543 struct omap_dma_s *s = (struct omap_dma_s *) opaque;
1544 /* The request pins are level triggered in QEMU. */
1545 if (req) {
1546 if (~s->dma->drqbmp & (1 << drq)) {
1547 s->dma->drqbmp |= 1 << drq;
1548 omap_dma_process_request(s, drq);
1549 }
1550 } else
1551 s->dma->drqbmp &= ~(1 << drq);
1552 }
1553
1554 /* XXX: this won't be needed once soc_dma knows about clocks. */
1555 static void omap_dma_clk_update(void *opaque, int line, int on)
1556 {
1557 struct omap_dma_s *s = (struct omap_dma_s *) opaque;
1558 int i;
1559
1560 s->dma->freq = omap_clk_getrate(s->clk);
1561
1562 for (i = 0; i < s->chans; i ++)
1563 if (s->ch[i].active)
1564 soc_dma_set_request(s->ch[i].dma, on);
1565 }
1566
1567 static void omap_dma_setcaps(struct omap_dma_s *s)
1568 {
1569 switch (s->model) {
1570 default:
1571 case omap_dma_3_1:
1572 break;
1573 case omap_dma_3_2:
1574 case omap_dma_4:
1575 /* XXX Only available for sDMA */
1576 s->caps[0] =
1577 (1 << 19) | /* Constant Fill Capability */
1578 (1 << 18); /* Transparent BLT Capability */
1579 s->caps[1] =
1580 (1 << 1); /* 1-bit palettized capability (DMA 3.2 only) */
1581 s->caps[2] =
1582 (1 << 8) | /* SEPARATE_SRC_AND_DST_INDEX_CPBLTY */
1583 (1 << 7) | /* DST_DOUBLE_INDEX_ADRS_CPBLTY */
1584 (1 << 6) | /* DST_SINGLE_INDEX_ADRS_CPBLTY */
1585 (1 << 5) | /* DST_POST_INCRMNT_ADRS_CPBLTY */
1586 (1 << 4) | /* DST_CONST_ADRS_CPBLTY */
1587 (1 << 3) | /* SRC_DOUBLE_INDEX_ADRS_CPBLTY */
1588 (1 << 2) | /* SRC_SINGLE_INDEX_ADRS_CPBLTY */
1589 (1 << 1) | /* SRC_POST_INCRMNT_ADRS_CPBLTY */
1590 (1 << 0); /* SRC_CONST_ADRS_CPBLTY */
1591 s->caps[3] =
1592 (1 << 6) | /* BLOCK_SYNCHR_CPBLTY (DMA 4 only) */
1593 (1 << 7) | /* PKT_SYNCHR_CPBLTY (DMA 4 only) */
1594 (1 << 5) | /* CHANNEL_CHAINING_CPBLTY */
1595 (1 << 4) | /* LCh_INTERLEAVE_CPBLTY */
1596 (1 << 3) | /* AUTOINIT_REPEAT_CPBLTY (DMA 3.2 only) */
1597 (1 << 2) | /* AUTOINIT_ENDPROG_CPBLTY (DMA 3.2 only) */
1598 (1 << 1) | /* FRAME_SYNCHR_CPBLTY */
1599 (1 << 0); /* ELMNT_SYNCHR_CPBLTY */
1600 s->caps[4] =
1601 (1 << 7) | /* PKT_INTERRUPT_CPBLTY (DMA 4 only) */
1602 (1 << 6) | /* SYNC_STATUS_CPBLTY */
1603 (1 << 5) | /* BLOCK_INTERRUPT_CPBLTY */
1604 (1 << 4) | /* LAST_FRAME_INTERRUPT_CPBLTY */
1605 (1 << 3) | /* FRAME_INTERRUPT_CPBLTY */
1606 (1 << 2) | /* HALF_FRAME_INTERRUPT_CPBLTY */
1607 (1 << 1) | /* EVENT_DROP_INTERRUPT_CPBLTY */
1608 (1 << 0); /* TIMEOUT_INTERRUPT_CPBLTY (DMA 3.2 only) */
1609 break;
1610 }
1611 }
1612
1613 struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
1614 qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
1615 enum omap_dma_model model)
1616 {
1617 int iomemtype, num_irqs, memsize, i;
1618 struct omap_dma_s *s = (struct omap_dma_s *)
1619 qemu_mallocz(sizeof(struct omap_dma_s));
1620
1621 if (model <= omap_dma_3_1) {
1622 num_irqs = 6;
1623 memsize = 0x800;
1624 } else {
1625 num_irqs = 16;
1626 memsize = 0xc00;
1627 }
1628 s->base = base;
1629 s->model = model;
1630 s->mpu = mpu;
1631 s->clk = clk;
1632 s->lcd_ch.irq = lcd_irq;
1633 s->lcd_ch.mpu = mpu;
1634
1635 s->dma = soc_dma_init((model <= omap_dma_3_1) ? 9 : 16);
1636 s->dma->freq = omap_clk_getrate(clk);
1637 s->dma->transfer_fn = omap_dma_transfer_generic;
1638 s->dma->setup_fn = omap_dma_transfer_setup;
1639 s->dma->drq = qemu_allocate_irqs(omap_dma_request, s, 32);
1640 s->dma->opaque = s;
1641
1642 while (num_irqs --)
1643 s->ch[num_irqs].irq = irqs[num_irqs];
1644 for (i = 0; i < 3; i ++) {
1645 s->ch[i].sibling = &s->ch[i + 6];
1646 s->ch[i + 6].sibling = &s->ch[i];
1647 }
1648 for (i = (model <= omap_dma_3_1) ? 8 : 15; i >= 0; i --) {
1649 s->ch[i].dma = &s->dma->ch[i];
1650 s->dma->ch[i].opaque = &s->ch[i];
1651 }
1652
1653 omap_dma_setcaps(s);
1654 omap_clk_adduser(s->clk, qemu_allocate_irqs(omap_dma_clk_update, s, 1)[0]);
1655 omap_dma_reset(s->dma);
1656 omap_dma_clk_update(s, 0, 1);
1657
1658 iomemtype = cpu_register_io_memory(0, omap_dma_readfn,
1659 omap_dma_writefn, s);
1660 cpu_register_physical_memory(s->base, memsize, iomemtype);
1661
1662 mpu->drq = s->dma->drq;
1663
1664 return s->dma;
1665 }
1666
1667 static void omap_dma_interrupts_4_update(struct omap_dma_s *s)
1668 {
1669 struct omap_dma_channel_s *ch = s->ch;
1670 uint32_t bmp, bit;
1671
1672 for (bmp = 0, bit = 1; bit; ch ++, bit <<= 1)
1673 if (ch->status) {
1674 bmp |= bit;
1675 ch->cstatus |= ch->status;
1676 ch->status = 0;
1677 }
1678 if ((s->irqstat[0] |= s->irqen[0] & bmp))
1679 qemu_irq_raise(s->irq[0]);
1680 if ((s->irqstat[1] |= s->irqen[1] & bmp))
1681 qemu_irq_raise(s->irq[1]);
1682 if ((s->irqstat[2] |= s->irqen[2] & bmp))
1683 qemu_irq_raise(s->irq[2]);
1684 if ((s->irqstat[3] |= s->irqen[3] & bmp))
1685 qemu_irq_raise(s->irq[3]);
1686 }
1687
1688 static uint32_t omap_dma4_read(void *opaque, target_phys_addr_t addr)
1689 {
1690 struct omap_dma_s *s = (struct omap_dma_s *) opaque;
1691 int irqn = 0, chnum, offset = addr - s->base;
1692 struct omap_dma_channel_s *ch;
1693
1694 switch (offset) {
1695 case 0x00: /* DMA4_REVISION */
1696 return 0x40;
1697
1698 case 0x14: /* DMA4_IRQSTATUS_L3 */
1699 irqn ++;
1700 case 0x10: /* DMA4_IRQSTATUS_L2 */
1701 irqn ++;
1702 case 0x0c: /* DMA4_IRQSTATUS_L1 */
1703 irqn ++;
1704 case 0x08: /* DMA4_IRQSTATUS_L0 */
1705 return s->irqstat[irqn];
1706
1707 case 0x24: /* DMA4_IRQENABLE_L3 */
1708 irqn ++;
1709 case 0x20: /* DMA4_IRQENABLE_L2 */
1710 irqn ++;
1711 case 0x1c: /* DMA4_IRQENABLE_L1 */
1712 irqn ++;
1713 case 0x18: /* DMA4_IRQENABLE_L0 */
1714 return s->irqen[irqn];
1715
1716 case 0x28: /* DMA4_SYSSTATUS */
1717 return 1; /* RESETDONE */
1718
1719 case 0x2c: /* DMA4_OCP_SYSCONFIG */
1720 return s->ocp;
1721
1722 case 0x64: /* DMA4_CAPS_0 */
1723 return s->caps[0];
1724 case 0x6c: /* DMA4_CAPS_2 */
1725 return s->caps[2];
1726 case 0x70: /* DMA4_CAPS_3 */
1727 return s->caps[3];
1728 case 0x74: /* DMA4_CAPS_4 */
1729 return s->caps[4];
1730
1731 case 0x78: /* DMA4_GCR */
1732 return s->gcr;
1733
1734 case 0x80 ... 0xfff:
1735 offset -= 0x80;
1736 chnum = offset / 0x60;
1737 ch = s->ch + chnum;
1738 offset -= chnum * 0x60;
1739 break;
1740
1741 default:
1742 OMAP_BAD_REG(addr);
1743 return 0;
1744 }
1745
1746 /* Per-channel registers */
1747 switch (offset) {
1748 case 0x00: /* DMA4_CCR */
1749 return (ch->buf_disable << 25) |
1750 (ch->src_sync << 24) |
1751 (ch->prefetch << 23) |
1752 ((ch->sync & 0x60) << 14) |
1753 (ch->bs << 18) |
1754 (ch->transparent_copy << 17) |
1755 (ch->constant_fill << 16) |
1756 (ch->mode[1] << 14) |
1757 (ch->mode[0] << 12) |
1758 (0 << 10) | (0 << 9) |
1759 (ch->suspend << 8) |
1760 (ch->enable << 7) |
1761 (ch->priority << 6) |
1762 (ch->fs << 5) | (ch->sync & 0x1f);
1763
1764 case 0x04: /* DMA4_CLNK_CTRL */
1765 return (ch->link_enabled << 15) | ch->link_next_ch;
1766
1767 case 0x08: /* DMA4_CICR */
1768 return ch->interrupts;
1769
1770 case 0x0c: /* DMA4_CSR */
1771 return ch->cstatus;
1772
1773 case 0x10: /* DMA4_CSDP */
1774 return (ch->endian[0] << 21) |
1775 (ch->endian_lock[0] << 20) |
1776 (ch->endian[1] << 19) |
1777 (ch->endian_lock[1] << 18) |
1778 (ch->write_mode << 16) |
1779 (ch->burst[1] << 14) |
1780 (ch->pack[1] << 13) |
1781 (ch->translate[1] << 9) |
1782 (ch->burst[0] << 7) |
1783 (ch->pack[0] << 6) |
1784 (ch->translate[0] << 2) |
1785 (ch->data_type >> 1);
1786
1787 case 0x14: /* DMA4_CEN */
1788 return ch->elements;
1789
1790 case 0x18: /* DMA4_CFN */
1791 return ch->frames;
1792
1793 case 0x1c: /* DMA4_CSSA */
1794 return ch->addr[0];
1795
1796 case 0x20: /* DMA4_CDSA */
1797 return ch->addr[1];
1798
1799 case 0x24: /* DMA4_CSEI */
1800 return ch->element_index[0];
1801
1802 case 0x28: /* DMA4_CSFI */
1803 return ch->frame_index[0];
1804
1805 case 0x2c: /* DMA4_CDEI */
1806 return ch->element_index[1];
1807
1808 case 0x30: /* DMA4_CDFI */
1809 return ch->frame_index[1];
1810
1811 case 0x34: /* DMA4_CSAC */
1812 return ch->active_set.src & 0xffff;
1813
1814 case 0x38: /* DMA4_CDAC */
1815 return ch->active_set.dest & 0xffff;
1816
1817 case 0x3c: /* DMA4_CCEN */
1818 return ch->active_set.element;
1819
1820 case 0x40: /* DMA4_CCFN */
1821 return ch->active_set.frame;
1822
1823 case 0x44: /* DMA4_COLOR */
1824 /* XXX only in sDMA */
1825 return ch->color;
1826
1827 default:
1828 OMAP_BAD_REG(addr);
1829 return 0;
1830 }
1831 }
1832
1833 static void omap_dma4_write(void *opaque, target_phys_addr_t addr,
1834 uint32_t value)
1835 {
1836 struct omap_dma_s *s = (struct omap_dma_s *) opaque;
1837 int chnum, irqn = 0, offset = addr - s->base;
1838 struct omap_dma_channel_s *ch;
1839
1840 switch (offset) {
1841 case 0x14: /* DMA4_IRQSTATUS_L3 */
1842 irqn ++;
1843 case 0x10: /* DMA4_IRQSTATUS_L2 */
1844 irqn ++;
1845 case 0x0c: /* DMA4_IRQSTATUS_L1 */
1846 irqn ++;
1847 case 0x08: /* DMA4_IRQSTATUS_L0 */
1848 s->irqstat[irqn] &= ~value;
1849 if (!s->irqstat[irqn])
1850 qemu_irq_lower(s->irq[irqn]);
1851 return;
1852
1853 case 0x24: /* DMA4_IRQENABLE_L3 */
1854 irqn ++;
1855 case 0x20: /* DMA4_IRQENABLE_L2 */
1856 irqn ++;
1857 case 0x1c: /* DMA4_IRQENABLE_L1 */
1858 irqn ++;
1859 case 0x18: /* DMA4_IRQENABLE_L0 */
1860 s->irqen[irqn] = value;
1861 return;
1862
1863 case 0x2c: /* DMA4_OCP_SYSCONFIG */
1864 if (value & 2) /* SOFTRESET */
1865 omap_dma_reset(s->dma);
1866 s->ocp = value & 0x3321;
1867 if (((s->ocp >> 12) & 3) == 3) /* MIDLEMODE */
1868 fprintf(stderr, "%s: invalid DMA power mode\n", __FUNCTION__);
1869 return;
1870
1871 case 0x78: /* DMA4_GCR */
1872 s->gcr = value & 0x00ff00ff;
1873 if ((value & 0xff) == 0x00) /* MAX_CHANNEL_FIFO_DEPTH */
1874 fprintf(stderr, "%s: wrong FIFO depth in GCR\n", __FUNCTION__);
1875 return;
1876
1877 case 0x80 ... 0xfff:
1878 offset -= 0x80;
1879 chnum = offset / 0x60;
1880 ch = s->ch + chnum;
1881 offset -= chnum * 0x60;
1882 break;
1883
1884 case 0x00: /* DMA4_REVISION */
1885 case 0x28: /* DMA4_SYSSTATUS */
1886 case 0x64: /* DMA4_CAPS_0 */
1887 case 0x6c: /* DMA4_CAPS_2 */
1888 case 0x70: /* DMA4_CAPS_3 */
1889 case 0x74: /* DMA4_CAPS_4 */
1890 OMAP_RO_REG(addr);
1891 return;
1892
1893 default:
1894 OMAP_BAD_REG(addr);
1895 return;
1896 }
1897
1898 /* Per-channel registers */
1899 switch (offset) {
1900 case 0x00: /* DMA4_CCR */
1901 ch->buf_disable = (value >> 25) & 1;
1902 ch->src_sync = (value >> 24) & 1; /* XXX For CamDMA must be 1 */
1903 if (ch->buf_disable && !ch->src_sync)
1904 fprintf(stderr, "%s: Buffering disable is not allowed in "
1905 "destination synchronised mode\n", __FUNCTION__);
1906 ch->prefetch = (value >> 23) & 1;
1907 ch->bs = (value >> 18) & 1;
1908 ch->transparent_copy = (value >> 17) & 1;
1909 ch->constant_fill = (value >> 16) & 1;
1910 ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14);
1911 ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12);
1912 ch->suspend = (value & 0x0100) >> 8;
1913 ch->priority = (value & 0x0040) >> 6;
1914 ch->fs = (value & 0x0020) >> 5;
1915 if (ch->fs && ch->bs && ch->mode[0] && ch->mode[1])
1916 fprintf(stderr, "%s: For a packet transfer at least one port "
1917 "must be constant-addressed\n", __FUNCTION__);
1918 ch->sync = (value & 0x001f) | ((value >> 14) & 0x0060);
1919 /* XXX must be 0x01 for CamDMA */
1920
1921 if (value & 0x0080)
1922 omap_dma_enable_channel(s, ch);
1923 else
1924 omap_dma_disable_channel(s, ch);
1925
1926 break;
1927
1928 case 0x04: /* DMA4_CLNK_CTRL */
1929 ch->link_enabled = (value >> 15) & 0x1;
1930 ch->link_next_ch = value & 0x1f;
1931 break;
1932
1933 case 0x08: /* DMA4_CICR */
1934 ch->interrupts = value & 0x09be;
1935 break;
1936
1937 case 0x0c: /* DMA4_CSR */
1938 ch->cstatus &= ~value;
1939 break;
1940
1941 case 0x10: /* DMA4_CSDP */
1942 ch->endian[0] =(value >> 21) & 1;
1943 ch->endian_lock[0] =(value >> 20) & 1;
1944 ch->endian[1] =(value >> 19) & 1;
1945 ch->endian_lock[1] =(value >> 18) & 1;
1946 if (ch->endian[0] != ch->endian[1])
1947 fprintf(stderr, "%s: DMA endiannes conversion enable attempt\n",
1948 __FUNCTION__);
1949 ch->write_mode = (value >> 16) & 3;
1950 ch->burst[1] = (value & 0xc000) >> 14;
1951 ch->pack[1] = (value & 0x2000) >> 13;
1952 ch->translate[1] = (value & 0x1e00) >> 9;
1953 ch->burst[0] = (value & 0x0180) >> 7;
1954 ch->pack[0] = (value & 0x0040) >> 6;
1955 ch->translate[0] = (value & 0x003c) >> 2;
1956 if (ch->translate[0] | ch->translate[1])
1957 fprintf(stderr, "%s: bad MReqAddressTranslate sideband signal\n",
1958 __FUNCTION__);
1959 ch->data_type = 1 << (value & 3);
1960 if ((value & 3) == 3)
1961 printf("%s: bad data_type for DMA channel\n", __FUNCTION__);
1962 break;
1963
1964 case 0x14: /* DMA4_CEN */
1965 ch->set_update = 1;
1966 ch->elements = value & 0xffffff;
1967 break;
1968
1969 case 0x18: /* DMA4_CFN */
1970 ch->frames = value & 0xffff;
1971 ch->set_update = 1;
1972 break;
1973
1974 case 0x1c: /* DMA4_CSSA */
1975 ch->addr[0] = (target_phys_addr_t) (uint32_t) value;
1976 ch->set_update = 1;
1977 break;
1978
1979 case 0x20: /* DMA4_CDSA */
1980 ch->addr[1] = (target_phys_addr_t) (uint32_t) value;
1981 ch->set_update = 1;
1982 break;
1983
1984 case 0x24: /* DMA4_CSEI */
1985 ch->element_index[0] = (int16_t) value;
1986 ch->set_update = 1;
1987 break;
1988
1989 case 0x28: /* DMA4_CSFI */
1990 ch->frame_index[0] = (int32_t) value;
1991 ch->set_update = 1;
1992 break;
1993
1994 case 0x2c: /* DMA4_CDEI */
1995 ch->element_index[1] = (int16_t) value;
1996 ch->set_update = 1;
1997 break;
1998
1999 case 0x30: /* DMA4_CDFI */
2000 ch->frame_index[1] = (int32_t) value;
2001 ch->set_update = 1;
2002 break;
2003
2004 case 0x44: /* DMA4_COLOR */
2005 /* XXX only in sDMA */
2006 ch->color = value;
2007 break;
2008
2009 case 0x34: /* DMA4_CSAC */
2010 case 0x38: /* DMA4_CDAC */
2011 case 0x3c: /* DMA4_CCEN */
2012 case 0x40: /* DMA4_CCFN */
2013 OMAP_RO_REG(addr);
2014 break;
2015
2016 default:
2017 OMAP_BAD_REG(addr);
2018 }
2019 }
2020
2021 static CPUReadMemoryFunc *omap_dma4_readfn[] = {
2022 omap_badwidth_read16,
2023 omap_dma4_read,
2024 omap_dma4_read,
2025 };
2026
2027 static CPUWriteMemoryFunc *omap_dma4_writefn[] = {
2028 omap_badwidth_write16,
2029 omap_dma4_write,
2030 omap_dma4_write,
2031 };
2032
2033 struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,
2034 struct omap_mpu_state_s *mpu, int fifo,
2035 int chans, omap_clk iclk, omap_clk fclk)
2036 {
2037 int iomemtype, i;
2038 struct omap_dma_s *s = (struct omap_dma_s *)
2039 qemu_mallocz(sizeof(struct omap_dma_s));
2040
2041 s->base = base;
2042 s->model = omap_dma_4;
2043 s->chans = chans;
2044 s->mpu = mpu;
2045 s->clk = fclk;
2046
2047 s->dma = soc_dma_init(s->chans);
2048 s->dma->freq = omap_clk_getrate(fclk);
2049 s->dma->transfer_fn = omap_dma_transfer_generic;
2050 s->dma->setup_fn = omap_dma_transfer_setup;
2051 s->dma->drq = qemu_allocate_irqs(omap_dma_request, s, 64);
2052 s->dma->opaque = s;
2053 for (i = 0; i < s->chans; i ++) {
2054 s->ch[i].dma = &s->dma->ch[i];
2055 s->dma->ch[i].opaque = &s->ch[i];
2056 }
2057
2058 memcpy(&s->irq, irqs, sizeof(s->irq));
2059 s->intr_update = omap_dma_interrupts_4_update;
2060
2061 omap_dma_setcaps(s);
2062 omap_clk_adduser(s->clk, qemu_allocate_irqs(omap_dma_clk_update, s, 1)[0]);
2063 omap_dma_reset(s->dma);
2064 omap_dma_clk_update(s, 0, !!s->dma->freq);
2065
2066 iomemtype = cpu_register_io_memory(0, omap_dma4_readfn,
2067 omap_dma4_writefn, s);
2068 cpu_register_physical_memory(s->base, 0x1000, iomemtype);
2069
2070 mpu->drq = s->dma->drq;
2071
2072 return s->dma;
2073 }
2074
2075 struct omap_dma_lcd_channel_s *omap_dma_get_lcdch(struct soc_dma_s *dma)
2076 {
2077 struct omap_dma_s *s = dma->opaque;
2078
2079 return &s->lcd_ch;
2080 }
Qemu copy for testing