hw/omap_intc.c

   1 /*
   2  * TI OMAP interrupt controller emulation.
   3  *
   4  * Copyright (C) 2006-2008 Andrzej Zaborowski  <balrog@zabor.org>
   5  * Copyright (C) 2007-2008 Nokia Corporation
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 or
  10  * (at your option) version 3 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20 #include "hw.h"
  21 #include "omap.h"
  22 #include "exec-memory.h"
  23
  24 /* Interrupt Handlers */
  25 struct omap_intr_handler_bank_s {
  26     uint32_t irqs;
  27     uint32_t inputs;
  28     uint32_t mask;
  29     uint32_t fiq;
  30     uint32_t sens_edge;
  31     uint32_t swi;
  32     unsigned char priority[32];
  33 };
  34
  35 struct omap_intr_handler_s {
  36     qemu_irq *pins;
  37     qemu_irq parent_intr[2];
  38     MemoryRegion mmio;
  39     unsigned char nbanks;
  40     int level_only;
  41
  42     /* state */
  43     uint32_t new_agr[2];
  44     int sir_intr[2];
  45     int autoidle;
  46     uint32_t mask;
  47     struct omap_intr_handler_bank_s bank[];
  48 };
  49
  50 inline qemu_irq omap_inth_get_pin(struct omap_intr_handler_s *s, int n)
  51 {
  52     return s->pins[n];
  53 }
  54
  55 static void omap_inth_sir_update(struct omap_intr_handler_s *s, int is_fiq)
  56 {
  57     int i, j, sir_intr, p_intr, p, f;
  58     uint32_t level;
  59     sir_intr = 0;
  60     p_intr = 255;
  61
  62     /* Find the interrupt line with the highest dynamic priority.
  63      * Note: 0 denotes the hightest priority.
  64      * If all interrupts have the same priority, the default order is IRQ_N,
  65      * IRQ_N-1,...,IRQ_0. */
  66     for (j = 0; j < s->nbanks; ++j) {
  67         level = s->bank[j].irqs & ~s->bank[j].mask &
  68                 (is_fiq ? s->bank[j].fiq : ~s->bank[j].fiq);
  69         for (f = ffs(level), i = f - 1, level >>= f - 1; f; i += f,
  70                         level >>= f) {
  71             p = s->bank[j].priority[i];
  72             if (p <= p_intr) {
  73                 p_intr = p;
  74                 sir_intr = 32 * j + i;
  75             }
  76             f = ffs(level >> 1);
  77         }
  78     }
  79     s->sir_intr[is_fiq] = sir_intr;
  80 }
  81
  82 static inline void omap_inth_update(struct omap_intr_handler_s *s, int is_fiq)
  83 {
  84     int i;
  85     uint32_t has_intr = 0;
  86
  87     for (i = 0; i < s->nbanks; ++i)
  88         has_intr |= s->bank[i].irqs & ~s->bank[i].mask &
  89                 (is_fiq ? s->bank[i].fiq : ~s->bank[i].fiq);
  90
  91     if (s->new_agr[is_fiq] & has_intr & s->mask) {
  92         s->new_agr[is_fiq] = 0;
  93         omap_inth_sir_update(s, is_fiq);
  94         qemu_set_irq(s->parent_intr[is_fiq], 1);
  95     }
  96 }
  97
  98 #define INT_FALLING_EDGE        0
  99 #define INT_LOW_LEVEL           1
 100
 101 static void omap_set_intr(void *opaque, int irq, int req)
 102 {
 103     struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque;
 104     uint32_t rise;
 105
 106     struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5];
 107     int n = irq & 31;
 108
 109     if (req) {
 110         rise = ~bank->irqs & (1 << n);
 111         if (~bank->sens_edge & (1 << n))
 112             rise &= ~bank->inputs;
 113
 114         bank->inputs |= (1 << n);
 115         if (rise) {
 116             bank->irqs |= rise;
 117             omap_inth_update(ih, 0);
 118             omap_inth_update(ih, 1);
 119         }
 120     } else {
 121         rise = bank->sens_edge & bank->irqs & (1 << n);
 122         bank->irqs &= ~rise;
 123         bank->inputs &= ~(1 << n);
 124     }
 125 }
 126
 127 /* Simplified version with no edge detection */
 128 static void omap_set_intr_noedge(void *opaque, int irq, int req)
 129 {
 130     struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque;
 131     uint32_t rise;
 132
 133     struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5];
 134     int n = irq & 31;
 135
 136     if (req) {
 137         rise = ~bank->inputs & (1 << n);
 138         if (rise) {
 139             bank->irqs |= bank->inputs |= rise;
 140             omap_inth_update(ih, 0);
 141             omap_inth_update(ih, 1);
 142         }
 143     } else
 144         bank->irqs = (bank->inputs &= ~(1 << n)) | bank->swi;
 145 }
 146
 147 static uint64_t omap_inth_read(void *opaque, target_phys_addr_t addr,
 148                                unsigned size)
 149 {
 150     struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
 151     int i, offset = addr;
 152     int bank_no = offset >> 8;
 153     int line_no;
 154     struct omap_intr_handler_bank_s *bank = &s->bank[bank_no];
 155     offset &= 0xff;
 156
 157     switch (offset) {
 158     case 0x00:  /* ITR */
 159         return bank->irqs;
 160
 161     case 0x04:  /* MIR */
 162         return bank->mask;
 163
 164     case 0x10:  /* SIR_IRQ_CODE */
 165     case 0x14:  /* SIR_FIQ_CODE */
 166         if (bank_no != 0)
 167             break;
 168         line_no = s->sir_intr[(offset - 0x10) >> 2];
 169         bank = &s->bank[line_no >> 5];
 170         i = line_no & 31;
 171         if (((bank->sens_edge >> i) & 1) == INT_FALLING_EDGE)
 172             bank->irqs &= ~(1 << i);
 173         return line_no;
 174
 175     case 0x18:  /* CONTROL_REG */
 176         if (bank_no != 0)
 177             break;
 178         return 0;
 179
 180     case 0x1c:  /* ILR0 */
 181     case 0x20:  /* ILR1 */
 182     case 0x24:  /* ILR2 */
 183     case 0x28:  /* ILR3 */
 184     case 0x2c:  /* ILR4 */
 185     case 0x30:  /* ILR5 */
 186     case 0x34:  /* ILR6 */
 187     case 0x38:  /* ILR7 */
 188     case 0x3c:  /* ILR8 */
 189     case 0x40:  /* ILR9 */
 190     case 0x44:  /* ILR10 */
 191     case 0x48:  /* ILR11 */
 192     case 0x4c:  /* ILR12 */
 193     case 0x50:  /* ILR13 */
 194     case 0x54:  /* ILR14 */
 195     case 0x58:  /* ILR15 */
 196     case 0x5c:  /* ILR16 */
 197     case 0x60:  /* ILR17 */
 198     case 0x64:  /* ILR18 */
 199     case 0x68:  /* ILR19 */
 200     case 0x6c:  /* ILR20 */
 201     case 0x70:  /* ILR21 */
 202     case 0x74:  /* ILR22 */
 203     case 0x78:  /* ILR23 */
 204     case 0x7c:  /* ILR24 */
 205     case 0x80:  /* ILR25 */
 206     case 0x84:  /* ILR26 */
 207     case 0x88:  /* ILR27 */
 208     case 0x8c:  /* ILR28 */
 209     case 0x90:  /* ILR29 */
 210     case 0x94:  /* ILR30 */
 211     case 0x98:  /* ILR31 */
 212         i = (offset - 0x1c) >> 2;
 213         return (bank->priority[i] << 2) |
 214                 (((bank->sens_edge >> i) & 1) << 1) |
 215                 ((bank->fiq >> i) & 1);
 216
 217     case 0x9c:  /* ISR */
 218         return 0x00000000;
 219
 220     }
 221     OMAP_BAD_REG(addr);
 222     return 0;
 223 }
 224
 225 static void omap_inth_write(void *opaque, target_phys_addr_t addr,
 226                             uint64_t value, unsigned size)
 227 {
 228     struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
 229     int i, offset = addr;
 230     int bank_no = offset >> 8;
 231     struct omap_intr_handler_bank_s *bank = &s->bank[bank_no];
 232     offset &= 0xff;
 233
 234     switch (offset) {
 235     case 0x00:  /* ITR */
 236         /* Important: ignore the clearing if the IRQ is level-triggered and
 237            the input bit is 1 */
 238         bank->irqs &= value | (bank->inputs & bank->sens_edge);
 239         return;
 240
 241     case 0x04:  /* MIR */
 242         bank->mask = value;
 243         omap_inth_update(s, 0);
 244         omap_inth_update(s, 1);
 245         return;
 246
 247     case 0x10:  /* SIR_IRQ_CODE */
 248     case 0x14:  /* SIR_FIQ_CODE */
 249         OMAP_RO_REG(addr);
 250         break;
 251
 252     case 0x18:  /* CONTROL_REG */
 253         if (bank_no != 0)
 254             break;
 255         if (value & 2) {
 256             qemu_set_irq(s->parent_intr[1], 0);
 257             s->new_agr[1] = ~0;
 258             omap_inth_update(s, 1);
 259         }
 260         if (value & 1) {
 261             qemu_set_irq(s->parent_intr[0], 0);
 262             s->new_agr[0] = ~0;
 263             omap_inth_update(s, 0);
 264         }
 265         return;
 266
 267     case 0x1c:  /* ILR0 */
 268     case 0x20:  /* ILR1 */
 269     case 0x24:  /* ILR2 */
 270     case 0x28:  /* ILR3 */
 271     case 0x2c:  /* ILR4 */
 272     case 0x30:  /* ILR5 */
 273     case 0x34:  /* ILR6 */
 274     case 0x38:  /* ILR7 */
 275     case 0x3c:  /* ILR8 */
 276     case 0x40:  /* ILR9 */
 277     case 0x44:  /* ILR10 */
 278     case 0x48:  /* ILR11 */
 279     case 0x4c:  /* ILR12 */
 280     case 0x50:  /* ILR13 */
 281     case 0x54:  /* ILR14 */
 282     case 0x58:  /* ILR15 */
 283     case 0x5c:  /* ILR16 */
 284     case 0x60:  /* ILR17 */
 285     case 0x64:  /* ILR18 */
 286     case 0x68:  /* ILR19 */
 287     case 0x6c:  /* ILR20 */
 288     case 0x70:  /* ILR21 */
 289     case 0x74:  /* ILR22 */
 290     case 0x78:  /* ILR23 */
 291     case 0x7c:  /* ILR24 */
 292     case 0x80:  /* ILR25 */
 293     case 0x84:  /* ILR26 */
 294     case 0x88:  /* ILR27 */
 295     case 0x8c:  /* ILR28 */
 296     case 0x90:  /* ILR29 */
 297     case 0x94:  /* ILR30 */
 298     case 0x98:  /* ILR31 */
 299         i = (offset - 0x1c) >> 2;
 300         bank->priority[i] = (value >> 2) & 0x1f;
 301         bank->sens_edge &= ~(1 << i);
 302         bank->sens_edge |= ((value >> 1) & 1) << i;
 303         bank->fiq &= ~(1 << i);
 304         bank->fiq |= (value & 1) << i;
 305         return;
 306
 307     case 0x9c:  /* ISR */
 308         for (i = 0; i < 32; i ++)
 309             if (value & (1 << i)) {
 310                 omap_set_intr(s, 32 * bank_no + i, 1);
 311                 return;
 312             }
 313         return;
 314     }
 315     OMAP_BAD_REG(addr);
 316 }
 317
 318 static const MemoryRegionOps omap_inth_mem_ops = {
 319     .read = omap_inth_read,
 320     .write = omap_inth_write,
 321     .endianness = DEVICE_NATIVE_ENDIAN,
 322     .valid = {
 323         .min_access_size = 4,
 324         .max_access_size = 4,
 325     },
 326 };
 327
 328 void omap_inth_reset(struct omap_intr_handler_s *s)
 329 {
 330     int i;
 331
 332     for (i = 0; i < s->nbanks; ++i){
 333         s->bank[i].irqs = 0x00000000;
 334         s->bank[i].mask = 0xffffffff;
 335         s->bank[i].sens_edge = 0x00000000;
 336         s->bank[i].fiq = 0x00000000;
 337         s->bank[i].inputs = 0x00000000;
 338         s->bank[i].swi = 0x00000000;
 339         memset(s->bank[i].priority, 0, sizeof(s->bank[i].priority));
 340
 341         if (s->level_only)
 342             s->bank[i].sens_edge = 0xffffffff;
 343     }
 344
 345     s->new_agr[0] = ~0;
 346     s->new_agr[1] = ~0;
 347     s->sir_intr[0] = 0;
 348     s->sir_intr[1] = 0;
 349     s->autoidle = 0;
 350     s->mask = ~0;
 351
 352     qemu_set_irq(s->parent_intr[0], 0);
 353     qemu_set_irq(s->parent_intr[1], 0);
 354 }
 355
 356 struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
 357                 unsigned long size, unsigned char nbanks, qemu_irq **pins,
 358                 qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk)
 359 {
 360     struct omap_intr_handler_s *s = (struct omap_intr_handler_s *)
 361             g_malloc0(sizeof(struct omap_intr_handler_s) +
 362                             sizeof(struct omap_intr_handler_bank_s) * nbanks);
 363
 364     s->parent_intr[0] = parent_irq;
 365     s->parent_intr[1] = parent_fiq;
 366     s->nbanks = nbanks;
 367     s->pins = qemu_allocate_irqs(omap_set_intr, s, nbanks * 32);
 368     if (pins)
 369         *pins = s->pins;
 370
 371     memory_region_init_io(&s->mmio, &omap_inth_mem_ops, s, "omap-intc", size);
 372     memory_region_add_subregion(get_system_memory(), base, &s->mmio);
 373
 374     omap_inth_reset(s);
 375
 376     return s;
 377 }
 378
 379 static uint64_t omap2_inth_read(void *opaque, target_phys_addr_t addr,
 380                                 unsigned size)
 381 {
 382     struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
 383     int offset = addr;
 384     int bank_no, line_no;
 385     struct omap_intr_handler_bank_s *bank = NULL;
 386
 387     if ((offset & 0xf80) == 0x80) {
 388         bank_no = (offset & 0x60) >> 5;
 389         if (bank_no < s->nbanks) {
 390             offset &= ~0x60;
 391             bank = &s->bank[bank_no];
 392         }
 393     }
 394
 395     switch (offset) {
 396     case 0x00:  /* INTC_REVISION */
 397         return 0x21;
 398
 399     case 0x10:  /* INTC_SYSCONFIG */
 400         return (s->autoidle >> 2) & 1;
 401
 402     case 0x14:  /* INTC_SYSSTATUS */
 403         return 1;                                               /* RESETDONE */
 404
 405     case 0x40:  /* INTC_SIR_IRQ */
 406         return s->sir_intr[0];
 407
 408     case 0x44:  /* INTC_SIR_FIQ */
 409         return s->sir_intr[1];
 410
 411     case 0x48:  /* INTC_CONTROL */
 412         return (!s->mask) << 2;                                 /* GLOBALMASK */
 413
 414     case 0x4c:  /* INTC_PROTECTION */
 415         return 0;
 416
 417     case 0x50:  /* INTC_IDLE */
 418         return s->autoidle & 3;
 419
 420     /* Per-bank registers */
 421     case 0x80:  /* INTC_ITR */
 422         return bank->inputs;
 423
 424     case 0x84:  /* INTC_MIR */
 425         return bank->mask;
 426
 427     case 0x88:  /* INTC_MIR_CLEAR */
 428     case 0x8c:  /* INTC_MIR_SET */
 429         return 0;
 430
 431     case 0x90:  /* INTC_ISR_SET */
 432         return bank->swi;
 433
 434     case 0x94:  /* INTC_ISR_CLEAR */
 435         return 0;
 436
 437     case 0x98:  /* INTC_PENDING_IRQ */
 438         return bank->irqs & ~bank->mask & ~bank->fiq;
 439
 440     case 0x9c:  /* INTC_PENDING_FIQ */
 441         return bank->irqs & ~bank->mask & bank->fiq;
 442
 443     /* Per-line registers */
 444     case 0x100 ... 0x300:       /* INTC_ILR */
 445         bank_no = (offset - 0x100) >> 7;
 446         if (bank_no > s->nbanks)
 447             break;
 448         bank = &s->bank[bank_no];
 449         line_no = (offset & 0x7f) >> 2;
 450         return (bank->priority[line_no] << 2) |
 451                 ((bank->fiq >> line_no) & 1);
 452     }
 453     OMAP_BAD_REG(addr);
 454     return 0;
 455 }
 456
 457 static void omap2_inth_write(void *opaque, target_phys_addr_t addr,
 458                              uint64_t value, unsigned size)
 459 {
 460     struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
 461     int offset = addr;
 462     int bank_no, line_no;
 463     struct omap_intr_handler_bank_s *bank = NULL;
 464
 465     if ((offset & 0xf80) == 0x80) {
 466         bank_no = (offset & 0x60) >> 5;
 467         if (bank_no < s->nbanks) {
 468             offset &= ~0x60;
 469             bank = &s->bank[bank_no];
 470         }
 471     }
 472
 473     switch (offset) {
 474     case 0x10:  /* INTC_SYSCONFIG */
 475         s->autoidle &= 4;
 476         s->autoidle |= (value & 1) << 2;
 477         if (value & 2)                                          /* SOFTRESET */
 478             omap_inth_reset(s);
 479         return;
 480
 481     case 0x48:  /* INTC_CONTROL */
 482         s->mask = (value & 4) ? 0 : ~0;                         /* GLOBALMASK */
 483         if (value & 2) {                                        /* NEWFIQAGR */
 484             qemu_set_irq(s->parent_intr[1], 0);
 485             s->new_agr[1] = ~0;
 486             omap_inth_update(s, 1);
 487         }
 488         if (value & 1) {                                        /* NEWIRQAGR */
 489             qemu_set_irq(s->parent_intr[0], 0);
 490             s->new_agr[0] = ~0;
 491             omap_inth_update(s, 0);
 492         }
 493         return;
 494
 495     case 0x4c:  /* INTC_PROTECTION */
 496         /* TODO: Make a bitmap (or sizeof(char)map) of access privileges
 497          * for every register, see Chapter 3 and 4 for privileged mode.  */
 498         if (value & 1)
 499             fprintf(stderr, "%s: protection mode enable attempt\n",
 500                             __FUNCTION__);
 501         return;
 502
 503     case 0x50:  /* INTC_IDLE */
 504         s->autoidle &= ~3;
 505         s->autoidle |= value & 3;
 506         return;
 507
 508     /* Per-bank registers */
 509     case 0x84:  /* INTC_MIR */
 510         bank->mask = value;
 511         omap_inth_update(s, 0);
 512         omap_inth_update(s, 1);
 513         return;
 514
 515     case 0x88:  /* INTC_MIR_CLEAR */
 516         bank->mask &= ~value;
 517         omap_inth_update(s, 0);
 518         omap_inth_update(s, 1);
 519         return;
 520
 521     case 0x8c:  /* INTC_MIR_SET */
 522         bank->mask |= value;
 523         return;
 524
 525     case 0x90:  /* INTC_ISR_SET */
 526         bank->irqs |= bank->swi |= value;
 527         omap_inth_update(s, 0);
 528         omap_inth_update(s, 1);
 529         return;
 530
 531     case 0x94:  /* INTC_ISR_CLEAR */
 532         bank->swi &= ~value;
 533         bank->irqs = bank->swi & bank->inputs;
 534         return;
 535
 536     /* Per-line registers */
 537     case 0x100 ... 0x300:       /* INTC_ILR */
 538         bank_no = (offset - 0x100) >> 7;
 539         if (bank_no > s->nbanks)
 540             break;
 541         bank = &s->bank[bank_no];
 542         line_no = (offset & 0x7f) >> 2;
 543         bank->priority[line_no] = (value >> 2) & 0x3f;
 544         bank->fiq &= ~(1 << line_no);
 545         bank->fiq |= (value & 1) << line_no;
 546         return;
 547
 548     case 0x00:  /* INTC_REVISION */
 549     case 0x14:  /* INTC_SYSSTATUS */
 550     case 0x40:  /* INTC_SIR_IRQ */
 551     case 0x44:  /* INTC_SIR_FIQ */
 552     case 0x80:  /* INTC_ITR */
 553     case 0x98:  /* INTC_PENDING_IRQ */
 554     case 0x9c:  /* INTC_PENDING_FIQ */
 555         OMAP_RO_REG(addr);
 556         return;
 557     }
 558     OMAP_BAD_REG(addr);
 559 }
 560
 561 static const MemoryRegionOps omap2_inth_mem_ops = {
 562     .read = omap2_inth_read,
 563     .write = omap2_inth_write,
 564     .endianness = DEVICE_NATIVE_ENDIAN,
 565     .valid = {
 566         .min_access_size = 4,
 567         .max_access_size = 4,
 568     },
 569 };
 570
 571 struct omap_intr_handler_s *omap2_inth_init(target_phys_addr_t base,
 572                 int size, int nbanks, qemu_irq **pins,
 573                 qemu_irq parent_irq, qemu_irq parent_fiq,
 574                 omap_clk fclk, omap_clk iclk)
 575 {
 576     struct omap_intr_handler_s *s = (struct omap_intr_handler_s *)
 577             g_malloc0(sizeof(struct omap_intr_handler_s) +
 578                             sizeof(struct omap_intr_handler_bank_s) * nbanks);
 579
 580     s->parent_intr[0] = parent_irq;
 581     s->parent_intr[1] = parent_fiq;
 582     s->nbanks = nbanks;
 583     s->level_only = 1;
 584     s->pins = qemu_allocate_irqs(omap_set_intr_noedge, s, nbanks * 32);
 585     if (pins)
 586         *pins = s->pins;
 587
 588     memory_region_init_io(&s->mmio, &omap2_inth_mem_ops, s, "omap2-intc", size);
 589     memory_region_add_subregion(get_system_memory(), base, &s->mmio);
 590
 591     omap_inth_reset(s);
 592
 593     return s;
 594 }