]>
git.proxmox.com Git - mirror_qemu.git/blob - hw/omap_uart.c
2 * TI OMAP processors UART emulation.
4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
5 * Copyright (C) 2007-2009 Nokia Corporation
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu-char.h"
23 /* We use pc-style serial ports. */
28 target_phys_addr_t base
;
29 SerialState
*serial
; /* TODO */
30 struct omap_target_agent_s
*ta
;
43 void omap_uart_reset(struct omap_uart_s
*s
)
52 struct omap_uart_s
*omap_uart_init(target_phys_addr_t base
,
53 qemu_irq irq
, omap_clk fclk
, omap_clk iclk
,
54 qemu_irq txdma
, qemu_irq rxdma
,
55 const char *label
, CharDriverState
*chr
)
57 struct omap_uart_s
*s
= (struct omap_uart_s
*)
58 g_malloc0(sizeof(struct omap_uart_s
));
63 s
->serial
= serial_mm_init(base
, 2, irq
, omap_clk_getrate(fclk
)/16,
64 chr
?: qemu_chr_new(label
, "null", NULL
), 1,
65 DEVICE_NATIVE_ENDIAN
);
69 static uint32_t omap_uart_read(void *opaque
, target_phys_addr_t addr
)
71 struct omap_uart_s
*s
= (struct omap_uart_s
*) opaque
;
83 case 0x48: /* EBLR (OMAP2) */
85 case 0x4C: /* OSC_12M_SEL (OMAP1) */
89 case 0x54: /* SYSC (OMAP2) */
91 case 0x58: /* SYSS (OMAP2) */
93 case 0x5c: /* WER (OMAP2) */
95 case 0x60: /* CFPS (OMAP2) */
103 static void omap_uart_write(void *opaque
, target_phys_addr_t addr
,
106 struct omap_uart_s
*s
= (struct omap_uart_s
*) opaque
;
110 case 0x20: /* MDR1 */
111 s
->mdr
[0] = value
& 0x7f;
113 case 0x24: /* MDR2 */
114 s
->mdr
[1] = value
& 0xff;
117 s
->scr
= value
& 0xff;
119 case 0x48: /* EBLR (OMAP2) */
120 s
->eblr
= value
& 0xff;
122 case 0x4C: /* OSC_12M_SEL (OMAP1) */
123 s
->clksel
= value
& 1;
127 case 0x58: /* SYSS (OMAP2) */
130 case 0x54: /* SYSC (OMAP2) */
131 s
->syscontrol
= value
& 0x1d;
135 case 0x5c: /* WER (OMAP2) */
136 s
->wkup
= value
& 0x7f;
138 case 0x60: /* CFPS (OMAP2) */
139 s
->cfps
= value
& 0xff;
146 static CPUReadMemoryFunc
* const omap_uart_readfn
[] = {
152 static CPUWriteMemoryFunc
* const omap_uart_writefn
[] = {
155 omap_badwidth_write8
,
158 struct omap_uart_s
*omap2_uart_init(struct omap_target_agent_s
*ta
,
159 qemu_irq irq
, omap_clk fclk
, omap_clk iclk
,
160 qemu_irq txdma
, qemu_irq rxdma
,
161 const char *label
, CharDriverState
*chr
)
163 target_phys_addr_t base
= omap_l4_attach(ta
, 0, 0);
164 struct omap_uart_s
*s
= omap_uart_init(base
, irq
,
165 fclk
, iclk
, txdma
, rxdma
, label
, chr
);
166 int iomemtype
= cpu_register_io_memory(omap_uart_readfn
,
167 omap_uart_writefn
, s
, DEVICE_NATIVE_ENDIAN
);
171 cpu_register_physical_memory(base
+ 0x20, 0x100, iomemtype
);
176 void omap_uart_attach(struct omap_uart_s
*s
, CharDriverState
*chr
)
178 /* TODO: Should reuse or destroy current s->serial */
179 s
->serial
= serial_mm_init(s
->base
, 2, s
->irq
,
180 omap_clk_getrate(s
->fclk
) / 16,
181 chr
?: qemu_chr_new("null", "null", NULL
), 1,
182 DEVICE_NATIVE_ENDIAN
);