4 * Copyright (c) 2004 Jocelyn Mayer
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 * Based on OpenPic implementations:
28 * - Intel GW80314 I/O companion chip developer's manual
29 * - Motorola MPC8245 & MPC8540 user manuals.
30 * - Motorola MCP750 (aka Raven) programmer manual.
31 * - Motorola Harrier programmer manuel
33 * Serial interrupts, as implemented in Raven chipset are not supported yet.
41 //#define DEBUG_OPENPIC
44 #define DPRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while (0)
46 #define DPRINTF(fmt, ...) do { } while (0)
49 #define USE_MPCxxx /* Intel model is broken, for now */
51 #if defined (USE_INTEL_GW80314)
52 /* Intel GW80314 I/O Companion chip */
62 #define VID (0x00000000)
64 #elif defined(USE_MPCxxx)
73 #define VID 0x03 /* MPIC version ID */
74 #define VENI 0x00000000 /* Vendor ID */
82 #define OPENPIC_MAX_CPU 2
83 #define OPENPIC_MAX_IRQ 64
84 #define OPENPIC_EXT_IRQ 48
85 #define OPENPIC_MAX_TMR MAX_TMR
86 #define OPENPIC_MAX_IPI MAX_IPI
88 /* Interrupt definitions */
89 #define OPENPIC_IRQ_FE (OPENPIC_EXT_IRQ) /* Internal functional IRQ */
90 #define OPENPIC_IRQ_ERR (OPENPIC_EXT_IRQ + 1) /* Error IRQ */
91 #define OPENPIC_IRQ_TIM0 (OPENPIC_EXT_IRQ + 2) /* First timer IRQ */
92 #if OPENPIC_MAX_IPI > 0
93 #define OPENPIC_IRQ_IPI0 (OPENPIC_IRQ_TIM0 + OPENPIC_MAX_TMR) /* First IPI IRQ */
94 #define OPENPIC_IRQ_DBL0 (OPENPIC_IRQ_IPI0 + (OPENPIC_MAX_CPU * OPENPIC_MAX_IPI)) /* First doorbell IRQ */
96 #define OPENPIC_IRQ_DBL0 (OPENPIC_IRQ_TIM0 + OPENPIC_MAX_TMR) /* First doorbell IRQ */
97 #define OPENPIC_IRQ_MBX0 (OPENPIC_IRQ_DBL0 + OPENPIC_MAX_DBL) /* First mailbox IRQ */
101 #define MPIC_MAX_CPU 1
102 #define MPIC_MAX_EXT 12
103 #define MPIC_MAX_INT 64
104 #define MPIC_MAX_MSG 4
105 #define MPIC_MAX_MSI 8
106 #define MPIC_MAX_TMR MAX_TMR
107 #define MPIC_MAX_IPI MAX_IPI
108 #define MPIC_MAX_IRQ (MPIC_MAX_EXT + MPIC_MAX_INT + MPIC_MAX_TMR + MPIC_MAX_MSG + MPIC_MAX_MSI + (MPIC_MAX_IPI * MPIC_MAX_CPU))
110 /* Interrupt definitions */
111 #define MPIC_EXT_IRQ 0
112 #define MPIC_INT_IRQ (MPIC_EXT_IRQ + MPIC_MAX_EXT)
113 #define MPIC_TMR_IRQ (MPIC_INT_IRQ + MPIC_MAX_INT)
114 #define MPIC_MSG_IRQ (MPIC_TMR_IRQ + MPIC_MAX_TMR)
115 #define MPIC_MSI_IRQ (MPIC_MSG_IRQ + MPIC_MAX_MSG)
116 #define MPIC_IPI_IRQ (MPIC_MSI_IRQ + MPIC_MAX_MSI)
118 #define MPIC_GLB_REG_START 0x0
119 #define MPIC_GLB_REG_SIZE 0x10F0
120 #define MPIC_TMR_REG_START 0x10F0
121 #define MPIC_TMR_REG_SIZE 0x220
122 #define MPIC_EXT_REG_START 0x10000
123 #define MPIC_EXT_REG_SIZE 0x180
124 #define MPIC_INT_REG_START 0x10200
125 #define MPIC_INT_REG_SIZE 0x800
126 #define MPIC_MSG_REG_START 0x11600
127 #define MPIC_MSG_REG_SIZE 0x100
128 #define MPIC_MSI_REG_START 0x11C00
129 #define MPIC_MSI_REG_SIZE 0x100
130 #define MPIC_CPU_REG_START 0x20000
131 #define MPIC_CPU_REG_SIZE 0x100 + ((MAX_CPU - 1) * 0x1000)
142 #error "Please select which OpenPic implementation is to be emulated"
145 #define OPENPIC_PAGE_SIZE 4096
147 #define BF_WIDTH(_bits_) \
148 (((_bits_) + (sizeof(uint32_t) * 8) - 1) / (sizeof(uint32_t) * 8))
150 static inline void set_bit (uint32_t *field
, int bit
)
152 field
[bit
>> 5] |= 1 << (bit
& 0x1F);
155 static inline void reset_bit (uint32_t *field
, int bit
)
157 field
[bit
>> 5] &= ~(1 << (bit
& 0x1F));
160 static inline int test_bit (uint32_t *field
, int bit
)
162 return (field
[bit
>> 5] & 1 << (bit
& 0x1F)) != 0;
165 static int get_current_cpu(void)
167 return cpu_single_env
->cpu_index
;
170 static uint32_t openpic_cpu_read_internal(void *opaque
, target_phys_addr_t addr
,
172 static void openpic_cpu_write_internal(void *opaque
, target_phys_addr_t addr
,
173 uint32_t val
, int idx
);
182 typedef struct IRQ_queue_t
{
183 uint32_t queue
[BF_WIDTH(MAX_IRQ
)];
188 typedef struct IRQ_src_t
{
189 uint32_t ipvp
; /* IRQ vector/priority register */
190 uint32_t ide
; /* IRQ destination register */
193 int pending
; /* TRUE if IRQ is pending */
203 #define IPVP_PRIORITY_MASK (0x1F << 16)
204 #define IPVP_PRIORITY(_ipvpr_) ((int)(((_ipvpr_) & IPVP_PRIORITY_MASK) >> 16))
205 #define IPVP_VECTOR_MASK ((1 << VECTOR_BITS) - 1)
206 #define IPVP_VECTOR(_ipvpr_) ((_ipvpr_) & IPVP_VECTOR_MASK)
208 typedef struct IRQ_dst_t
{
210 uint32_t pctp
; /* CPU current task priority */
211 uint32_t pcsr
; /* CPU sensitivity register */
213 IRQ_queue_t servicing
;
217 typedef struct openpic_t
{
220 /* Global registers */
221 uint32_t frep
; /* Feature reporting register */
222 uint32_t glbc
; /* Global configuration register */
223 uint32_t micr
; /* MPIC interrupt configuration register */
224 uint32_t veni
; /* Vendor identification register */
225 uint32_t pint
; /* Processor initialization register */
226 uint32_t spve
; /* Spurious vector register */
227 uint32_t tifr
; /* Timer frequency reporting register */
228 /* Source registers */
229 IRQ_src_t src
[MAX_IRQ
];
230 /* Local registers per output pin */
231 IRQ_dst_t dst
[MAX_CPU
];
233 /* Timer registers */
235 uint32_t ticc
; /* Global timer current count register */
236 uint32_t tibc
; /* Global timer base count register */
239 /* Doorbell registers */
240 uint32_t dar
; /* Doorbell activate register */
242 uint32_t dmr
; /* Doorbell messaging register */
243 } doorbells
[MAX_DBL
];
246 /* Mailbox registers */
248 uint32_t mbr
; /* Mailbox register */
249 } mailboxes
[MAX_MAILBOXES
];
251 /* IRQ out is used when in bypass mode (not implemented) */
256 void (*reset
) (void *);
257 void (*irq_raise
) (struct openpic_t
*, int, IRQ_src_t
*);
260 static inline void IRQ_setbit (IRQ_queue_t
*q
, int n_IRQ
)
262 set_bit(q
->queue
, n_IRQ
);
265 static inline void IRQ_resetbit (IRQ_queue_t
*q
, int n_IRQ
)
267 reset_bit(q
->queue
, n_IRQ
);
270 static inline int IRQ_testbit (IRQ_queue_t
*q
, int n_IRQ
)
272 return test_bit(q
->queue
, n_IRQ
);
275 static void IRQ_check (openpic_t
*opp
, IRQ_queue_t
*q
)
282 for (i
= 0; i
< opp
->max_irq
; i
++) {
283 if (IRQ_testbit(q
, i
)) {
284 DPRINTF("IRQ_check: irq %d set ipvp_pr=%d pr=%d\n",
285 i
, IPVP_PRIORITY(opp
->src
[i
].ipvp
), priority
);
286 if (IPVP_PRIORITY(opp
->src
[i
].ipvp
) > priority
) {
288 priority
= IPVP_PRIORITY(opp
->src
[i
].ipvp
);
293 q
->priority
= priority
;
296 static int IRQ_get_next (openpic_t
*opp
, IRQ_queue_t
*q
)
306 static void IRQ_local_pipe (openpic_t
*opp
, int n_CPU
, int n_IRQ
)
312 dst
= &opp
->dst
[n_CPU
];
313 src
= &opp
->src
[n_IRQ
];
314 priority
= IPVP_PRIORITY(src
->ipvp
);
315 if (priority
<= dst
->pctp
) {
316 /* Too low priority */
317 DPRINTF("%s: IRQ %d has too low priority on CPU %d\n",
318 __func__
, n_IRQ
, n_CPU
);
321 if (IRQ_testbit(&dst
->raised
, n_IRQ
)) {
323 DPRINTF("%s: IRQ %d was missed on CPU %d\n",
324 __func__
, n_IRQ
, n_CPU
);
327 set_bit(&src
->ipvp
, IPVP_ACTIVITY
);
328 IRQ_setbit(&dst
->raised
, n_IRQ
);
329 if (priority
< dst
->raised
.priority
) {
330 /* An higher priority IRQ is already raised */
331 DPRINTF("%s: IRQ %d is hidden by raised IRQ %d on CPU %d\n",
332 __func__
, n_IRQ
, dst
->raised
.next
, n_CPU
);
335 IRQ_get_next(opp
, &dst
->raised
);
336 if (IRQ_get_next(opp
, &dst
->servicing
) != -1 &&
337 priority
<= dst
->servicing
.priority
) {
338 DPRINTF("%s: IRQ %d is hidden by servicing IRQ %d on CPU %d\n",
339 __func__
, n_IRQ
, dst
->servicing
.next
, n_CPU
);
340 /* Already servicing a higher priority IRQ */
343 DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n", n_CPU
, n_IRQ
);
344 opp
->irq_raise(opp
, n_CPU
, src
);
347 /* update pic state because registers for n_IRQ have changed value */
348 static void openpic_update_irq(openpic_t
*opp
, int n_IRQ
)
353 src
= &opp
->src
[n_IRQ
];
357 DPRINTF("%s: IRQ %d is not pending\n", __func__
, n_IRQ
);
360 if (test_bit(&src
->ipvp
, IPVP_MASK
)) {
361 /* Interrupt source is disabled */
362 DPRINTF("%s: IRQ %d is disabled\n", __func__
, n_IRQ
);
365 if (IPVP_PRIORITY(src
->ipvp
) == 0) {
366 /* Priority set to zero */
367 DPRINTF("%s: IRQ %d has 0 priority\n", __func__
, n_IRQ
);
370 if (test_bit(&src
->ipvp
, IPVP_ACTIVITY
)) {
371 /* IRQ already active */
372 DPRINTF("%s: IRQ %d is already active\n", __func__
, n_IRQ
);
375 if (src
->ide
== 0x00000000) {
377 DPRINTF("%s: IRQ %d has no target\n", __func__
, n_IRQ
);
381 if (src
->ide
== (1 << src
->last_cpu
)) {
382 /* Only one CPU is allowed to receive this IRQ */
383 IRQ_local_pipe(opp
, src
->last_cpu
, n_IRQ
);
384 } else if (!test_bit(&src
->ipvp
, IPVP_MODE
)) {
385 /* Directed delivery mode */
386 for (i
= 0; i
< opp
->nb_cpus
; i
++) {
387 if (test_bit(&src
->ide
, i
))
388 IRQ_local_pipe(opp
, i
, n_IRQ
);
391 /* Distributed delivery mode */
392 for (i
= src
->last_cpu
+ 1; i
!= src
->last_cpu
; i
++) {
393 if (i
== opp
->nb_cpus
)
395 if (test_bit(&src
->ide
, i
)) {
396 IRQ_local_pipe(opp
, i
, n_IRQ
);
404 static void openpic_set_irq(void *opaque
, int n_IRQ
, int level
)
406 openpic_t
*opp
= opaque
;
409 src
= &opp
->src
[n_IRQ
];
410 DPRINTF("openpic: set irq %d = %d ipvp=%08x\n",
411 n_IRQ
, level
, src
->ipvp
);
412 if (test_bit(&src
->ipvp
, IPVP_SENSE
)) {
413 /* level-sensitive irq */
414 src
->pending
= level
;
416 reset_bit(&src
->ipvp
, IPVP_ACTIVITY
);
418 /* edge-sensitive irq */
422 openpic_update_irq(opp
, n_IRQ
);
425 static void openpic_reset (void *opaque
)
427 openpic_t
*opp
= (openpic_t
*)opaque
;
430 opp
->glbc
= 0x80000000;
431 /* Initialise controller registers */
432 opp
->frep
= ((OPENPIC_EXT_IRQ
- 1) << 16) | ((MAX_CPU
- 1) << 8) | VID
;
434 opp
->pint
= 0x00000000;
435 opp
->spve
= 0x000000FF;
436 opp
->tifr
= 0x003F7A00;
438 opp
->micr
= 0x00000000;
439 /* Initialise IRQ sources */
440 for (i
= 0; i
< opp
->max_irq
; i
++) {
441 opp
->src
[i
].ipvp
= 0xA0000000;
442 opp
->src
[i
].ide
= 0x00000000;
444 /* Initialise IRQ destinations */
445 for (i
= 0; i
< MAX_CPU
; i
++) {
446 opp
->dst
[i
].pctp
= 0x0000000F;
447 opp
->dst
[i
].pcsr
= 0x00000000;
448 memset(&opp
->dst
[i
].raised
, 0, sizeof(IRQ_queue_t
));
449 opp
->dst
[i
].raised
.next
= -1;
450 memset(&opp
->dst
[i
].servicing
, 0, sizeof(IRQ_queue_t
));
451 opp
->dst
[i
].servicing
.next
= -1;
453 /* Initialise timers */
454 for (i
= 0; i
< MAX_TMR
; i
++) {
455 opp
->timers
[i
].ticc
= 0x00000000;
456 opp
->timers
[i
].tibc
= 0x80000000;
458 /* Initialise doorbells */
460 opp
->dar
= 0x00000000;
461 for (i
= 0; i
< MAX_DBL
; i
++) {
462 opp
->doorbells
[i
].dmr
= 0x00000000;
465 /* Initialise mailboxes */
467 for (i
= 0; i
< MAX_MBX
; i
++) { /* ? */
468 opp
->mailboxes
[i
].mbr
= 0x00000000;
471 /* Go out of RESET state */
472 opp
->glbc
= 0x00000000;
475 static inline uint32_t read_IRQreg_ide(openpic_t
*opp
, int n_IRQ
)
477 return opp
->src
[n_IRQ
].ide
;
480 static inline uint32_t read_IRQreg_ipvp(openpic_t
*opp
, int n_IRQ
)
482 return opp
->src
[n_IRQ
].ipvp
;
485 static inline void write_IRQreg_ide(openpic_t
*opp
, int n_IRQ
, uint32_t val
)
489 tmp
= val
& 0xC0000000;
490 tmp
|= val
& ((1ULL << MAX_CPU
) - 1);
491 opp
->src
[n_IRQ
].ide
= tmp
;
492 DPRINTF("Set IDE %d to 0x%08x\n", n_IRQ
, opp
->src
[n_IRQ
].ide
);
495 static inline void write_IRQreg_ipvp(openpic_t
*opp
, int n_IRQ
, uint32_t val
)
497 /* NOTE: not fully accurate for special IRQs, but simple and sufficient */
498 /* ACTIVITY bit is read-only */
499 opp
->src
[n_IRQ
].ipvp
= (opp
->src
[n_IRQ
].ipvp
& 0x40000000)
500 | (val
& 0x800F00FF);
501 openpic_update_irq(opp
, n_IRQ
);
502 DPRINTF("Set IPVP %d to 0x%08x -> 0x%08x\n", n_IRQ
, val
,
503 opp
->src
[n_IRQ
].ipvp
);
506 #if 0 // Code provision for Intel model
508 static uint32_t read_doorbell_register (openpic_t
*opp
,
509 int n_dbl
, uint32_t offset
)
514 case DBL_IPVP_OFFSET
:
515 retval
= read_IRQreg_ipvp(opp
, IRQ_DBL0
+ n_dbl
);
518 retval
= read_IRQreg_ide(opp
, IRQ_DBL0
+ n_dbl
);
521 retval
= opp
->doorbells
[n_dbl
].dmr
;
528 static void write_doorbell_register (penpic_t
*opp
, int n_dbl
,
529 uint32_t offset
, uint32_t value
)
532 case DBL_IVPR_OFFSET
:
533 write_IRQreg_ipvp(opp
, IRQ_DBL0
+ n_dbl
, value
);
536 write_IRQreg_ide(opp
, IRQ_DBL0
+ n_dbl
, value
);
539 opp
->doorbells
[n_dbl
].dmr
= value
;
546 static uint32_t read_mailbox_register (openpic_t
*opp
,
547 int n_mbx
, uint32_t offset
)
553 retval
= opp
->mailboxes
[n_mbx
].mbr
;
555 case MBX_IVPR_OFFSET
:
556 retval
= read_IRQreg_ipvp(opp
, IRQ_MBX0
+ n_mbx
);
559 retval
= read_IRQreg_ide(opp
, IRQ_MBX0
+ n_mbx
);
566 static void write_mailbox_register (openpic_t
*opp
, int n_mbx
,
567 uint32_t address
, uint32_t value
)
571 opp
->mailboxes
[n_mbx
].mbr
= value
;
573 case MBX_IVPR_OFFSET
:
574 write_IRQreg_ipvp(opp
, IRQ_MBX0
+ n_mbx
, value
);
577 write_IRQreg_ide(opp
, IRQ_MBX0
+ n_mbx
, value
);
582 #endif /* 0 : Code provision for Intel model */
584 static void openpic_gbl_write (void *opaque
, target_phys_addr_t addr
, uint32_t val
)
586 openpic_t
*opp
= opaque
;
590 DPRINTF("%s: addr " TARGET_FMT_plx
" <= %08x\n", __func__
, addr
, val
);
602 openpic_cpu_write_internal(opp
, addr
, val
, get_current_cpu());
604 case 0x1000: /* FREP */
606 case 0x1020: /* GLBC */
607 if (val
& 0x80000000 && opp
->reset
)
609 opp
->glbc
= val
& ~0x80000000;
611 case 0x1080: /* VENI */
613 case 0x1090: /* PINT */
614 for (idx
= 0; idx
< opp
->nb_cpus
; idx
++) {
615 if ((val
& (1 << idx
)) && !(opp
->pint
& (1 << idx
))) {
616 DPRINTF("Raise OpenPIC RESET output for CPU %d\n", idx
);
617 dst
= &opp
->dst
[idx
];
618 qemu_irq_raise(dst
->irqs
[OPENPIC_OUTPUT_RESET
]);
619 } else if (!(val
& (1 << idx
)) && (opp
->pint
& (1 << idx
))) {
620 DPRINTF("Lower OpenPIC RESET output for CPU %d\n", idx
);
621 dst
= &opp
->dst
[idx
];
622 qemu_irq_lower(dst
->irqs
[OPENPIC_OUTPUT_RESET
]);
627 case 0x10A0: /* IPI_IPVP */
633 idx
= (addr
- 0x10A0) >> 4;
634 write_IRQreg_ipvp(opp
, opp
->irq_ipi0
+ idx
, val
);
637 case 0x10E0: /* SPVE */
638 opp
->spve
= val
& 0x000000FF;
640 case 0x10F0: /* TIFR */
648 static uint32_t openpic_gbl_read (void *opaque
, target_phys_addr_t addr
)
650 openpic_t
*opp
= opaque
;
653 DPRINTF("%s: addr " TARGET_FMT_plx
"\n", __func__
, addr
);
658 case 0x1000: /* FREP */
661 case 0x1020: /* GLBC */
664 case 0x1080: /* VENI */
667 case 0x1090: /* PINT */
678 retval
= openpic_cpu_read_internal(opp
, addr
, get_current_cpu());
680 case 0x10A0: /* IPI_IPVP */
686 idx
= (addr
- 0x10A0) >> 4;
687 retval
= read_IRQreg_ipvp(opp
, opp
->irq_ipi0
+ idx
);
690 case 0x10E0: /* SPVE */
693 case 0x10F0: /* TIFR */
699 DPRINTF("%s: => %08x\n", __func__
, retval
);
704 static void openpic_timer_write (void *opaque
, uint32_t addr
, uint32_t val
)
706 openpic_t
*opp
= opaque
;
709 DPRINTF("%s: addr %08x <= %08x\n", __func__
, addr
, val
);
714 idx
= (addr
& 0xFFF0) >> 6;
717 case 0x00: /* TICC */
719 case 0x10: /* TIBC */
720 if ((opp
->timers
[idx
].ticc
& 0x80000000) != 0 &&
721 (val
& 0x80000000) == 0 &&
722 (opp
->timers
[idx
].tibc
& 0x80000000) != 0)
723 opp
->timers
[idx
].ticc
&= ~0x80000000;
724 opp
->timers
[idx
].tibc
= val
;
726 case 0x20: /* TIVP */
727 write_IRQreg_ipvp(opp
, opp
->irq_tim0
+ idx
, val
);
729 case 0x30: /* TIDE */
730 write_IRQreg_ide(opp
, opp
->irq_tim0
+ idx
, val
);
735 static uint32_t openpic_timer_read (void *opaque
, uint32_t addr
)
737 openpic_t
*opp
= opaque
;
741 DPRINTF("%s: addr %08x\n", __func__
, addr
);
747 idx
= (addr
& 0xFFF0) >> 6;
750 case 0x00: /* TICC */
751 retval
= opp
->timers
[idx
].ticc
;
753 case 0x10: /* TIBC */
754 retval
= opp
->timers
[idx
].tibc
;
756 case 0x20: /* TIPV */
757 retval
= read_IRQreg_ipvp(opp
, opp
->irq_tim0
+ idx
);
759 case 0x30: /* TIDE */
760 retval
= read_IRQreg_ide(opp
, opp
->irq_tim0
+ idx
);
763 DPRINTF("%s: => %08x\n", __func__
, retval
);
768 static void openpic_src_write (void *opaque
, uint32_t addr
, uint32_t val
)
770 openpic_t
*opp
= opaque
;
773 DPRINTF("%s: addr %08x <= %08x\n", __func__
, addr
, val
);
776 addr
= addr
& 0xFFF0;
779 /* EXDE / IFEDE / IEEDE */
780 write_IRQreg_ide(opp
, idx
, val
);
782 /* EXVP / IFEVP / IEEVP */
783 write_IRQreg_ipvp(opp
, idx
, val
);
787 static uint32_t openpic_src_read (void *opaque
, uint32_t addr
)
789 openpic_t
*opp
= opaque
;
793 DPRINTF("%s: addr %08x\n", __func__
, addr
);
797 addr
= addr
& 0xFFF0;
800 /* EXDE / IFEDE / IEEDE */
801 retval
= read_IRQreg_ide(opp
, idx
);
803 /* EXVP / IFEVP / IEEVP */
804 retval
= read_IRQreg_ipvp(opp
, idx
);
806 DPRINTF("%s: => %08x\n", __func__
, retval
);
811 static void openpic_cpu_write_internal(void *opaque
, target_phys_addr_t addr
,
812 uint32_t val
, int idx
)
814 openpic_t
*opp
= opaque
;
819 DPRINTF("%s: cpu %d addr " TARGET_FMT_plx
" <= %08x\n", __func__
, idx
,
823 dst
= &opp
->dst
[idx
];
827 case 0x40: /* IPIDR */
831 idx
= (addr
- 0x40) >> 4;
832 /* we use IDE as mask which CPUs to deliver the IPI to still. */
833 write_IRQreg_ide(opp
, opp
->irq_ipi0
+ idx
,
834 opp
->src
[opp
->irq_ipi0
+ idx
].ide
| val
);
835 openpic_set_irq(opp
, opp
->irq_ipi0
+ idx
, 1);
836 openpic_set_irq(opp
, opp
->irq_ipi0
+ idx
, 0);
839 case 0x80: /* PCTP */
840 dst
->pctp
= val
& 0x0000000F;
842 case 0x90: /* WHOAMI */
843 /* Read-only register */
845 case 0xA0: /* PIAC */
846 /* Read-only register */
848 case 0xB0: /* PEOI */
850 s_IRQ
= IRQ_get_next(opp
, &dst
->servicing
);
851 IRQ_resetbit(&dst
->servicing
, s_IRQ
);
852 dst
->servicing
.next
= -1;
853 /* Set up next servicing IRQ */
854 s_IRQ
= IRQ_get_next(opp
, &dst
->servicing
);
855 /* Check queued interrupts. */
856 n_IRQ
= IRQ_get_next(opp
, &dst
->raised
);
857 src
= &opp
->src
[n_IRQ
];
860 IPVP_PRIORITY(src
->ipvp
) > dst
->servicing
.priority
)) {
861 DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n",
863 opp
->irq_raise(opp
, idx
, src
);
871 static void openpic_cpu_write(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
873 openpic_cpu_write_internal(opaque
, addr
, val
, (addr
& 0x1f000) >> 12);
876 static uint32_t openpic_cpu_read_internal(void *opaque
, target_phys_addr_t addr
,
879 openpic_t
*opp
= opaque
;
885 DPRINTF("%s: cpu %d addr " TARGET_FMT_plx
"\n", __func__
, idx
, addr
);
889 dst
= &opp
->dst
[idx
];
892 case 0x80: /* PCTP */
895 case 0x90: /* WHOAMI */
898 case 0xA0: /* PIAC */
899 DPRINTF("Lower OpenPIC INT output\n");
900 qemu_irq_lower(dst
->irqs
[OPENPIC_OUTPUT_INT
]);
901 n_IRQ
= IRQ_get_next(opp
, &dst
->raised
);
902 DPRINTF("PIAC: irq=%d\n", n_IRQ
);
904 /* No more interrupt pending */
905 retval
= IPVP_VECTOR(opp
->spve
);
907 src
= &opp
->src
[n_IRQ
];
908 if (!test_bit(&src
->ipvp
, IPVP_ACTIVITY
) ||
909 !(IPVP_PRIORITY(src
->ipvp
) > dst
->pctp
)) {
910 /* - Spurious level-sensitive IRQ
911 * - Priorities has been changed
912 * and the pending IRQ isn't allowed anymore
914 reset_bit(&src
->ipvp
, IPVP_ACTIVITY
);
915 retval
= IPVP_VECTOR(opp
->spve
);
917 /* IRQ enter servicing state */
918 IRQ_setbit(&dst
->servicing
, n_IRQ
);
919 retval
= IPVP_VECTOR(src
->ipvp
);
921 IRQ_resetbit(&dst
->raised
, n_IRQ
);
922 dst
->raised
.next
= -1;
923 if (!test_bit(&src
->ipvp
, IPVP_SENSE
)) {
924 /* edge-sensitive IRQ */
925 reset_bit(&src
->ipvp
, IPVP_ACTIVITY
);
929 if ((n_IRQ
>= opp
->irq_ipi0
) && (n_IRQ
< (opp
->irq_ipi0
+ MAX_IPI
))) {
930 src
->ide
&= ~(1 << idx
);
931 if (src
->ide
&& !test_bit(&src
->ipvp
, IPVP_SENSE
)) {
932 /* trigger on CPUs that didn't know about it yet */
933 openpic_set_irq(opp
, n_IRQ
, 1);
934 openpic_set_irq(opp
, n_IRQ
, 0);
935 /* if all CPUs knew about it, set active bit again */
936 set_bit(&src
->ipvp
, IPVP_ACTIVITY
);
941 case 0xB0: /* PEOI */
947 DPRINTF("%s: => %08x\n", __func__
, retval
);
952 static uint32_t openpic_cpu_read(void *opaque
, target_phys_addr_t addr
)
954 return openpic_cpu_read_internal(opaque
, addr
, (addr
& 0x1f000) >> 12);
957 static void openpic_buggy_write (void *opaque
,
958 target_phys_addr_t addr
, uint32_t val
)
960 printf("Invalid OPENPIC write access !\n");
963 static uint32_t openpic_buggy_read (void *opaque
, target_phys_addr_t addr
)
965 printf("Invalid OPENPIC read access !\n");
970 static void openpic_writel (void *opaque
,
971 target_phys_addr_t addr
, uint32_t val
)
973 openpic_t
*opp
= opaque
;
976 DPRINTF("%s: offset %08x val: %08x\n", __func__
, (int)addr
, val
);
978 /* Global registers */
979 openpic_gbl_write(opp
, addr
, val
);
980 } else if (addr
< 0x10000) {
981 /* Timers registers */
982 openpic_timer_write(opp
, addr
, val
);
983 } else if (addr
< 0x20000) {
984 /* Source registers */
985 openpic_src_write(opp
, addr
, val
);
988 openpic_cpu_write(opp
, addr
, val
);
992 static uint32_t openpic_readl (void *opaque
,target_phys_addr_t addr
)
994 openpic_t
*opp
= opaque
;
998 DPRINTF("%s: offset %08x\n", __func__
, (int)addr
);
1000 /* Global registers */
1001 retval
= openpic_gbl_read(opp
, addr
);
1002 } else if (addr
< 0x10000) {
1003 /* Timers registers */
1004 retval
= openpic_timer_read(opp
, addr
);
1005 } else if (addr
< 0x20000) {
1006 /* Source registers */
1007 retval
= openpic_src_read(opp
, addr
);
1010 retval
= openpic_cpu_read(opp
, addr
);
1016 static uint64_t openpic_read(void *opaque
, target_phys_addr_t addr
,
1019 openpic_t
*opp
= opaque
;
1022 case 4: return openpic_readl(opp
, addr
);
1023 default: return openpic_buggy_read(opp
, addr
);
1027 static void openpic_write(void *opaque
, target_phys_addr_t addr
,
1028 uint64_t data
, unsigned size
)
1030 openpic_t
*opp
= opaque
;
1033 case 4: return openpic_writel(opp
, addr
, data
);
1034 default: return openpic_buggy_write(opp
, addr
, data
);
1038 static const MemoryRegionOps openpic_ops
= {
1039 .read
= openpic_read
,
1040 .write
= openpic_write
,
1041 .endianness
= DEVICE_LITTLE_ENDIAN
,
1044 static void openpic_save_IRQ_queue(QEMUFile
* f
, IRQ_queue_t
*q
)
1048 for (i
= 0; i
< BF_WIDTH(MAX_IRQ
); i
++)
1049 qemu_put_be32s(f
, &q
->queue
[i
]);
1051 qemu_put_sbe32s(f
, &q
->next
);
1052 qemu_put_sbe32s(f
, &q
->priority
);
1055 static void openpic_save(QEMUFile
* f
, void *opaque
)
1057 openpic_t
*opp
= (openpic_t
*)opaque
;
1060 qemu_put_be32s(f
, &opp
->frep
);
1061 qemu_put_be32s(f
, &opp
->glbc
);
1062 qemu_put_be32s(f
, &opp
->micr
);
1063 qemu_put_be32s(f
, &opp
->veni
);
1064 qemu_put_be32s(f
, &opp
->pint
);
1065 qemu_put_be32s(f
, &opp
->spve
);
1066 qemu_put_be32s(f
, &opp
->tifr
);
1068 for (i
= 0; i
< opp
->max_irq
; i
++) {
1069 qemu_put_be32s(f
, &opp
->src
[i
].ipvp
);
1070 qemu_put_be32s(f
, &opp
->src
[i
].ide
);
1071 qemu_put_sbe32s(f
, &opp
->src
[i
].type
);
1072 qemu_put_sbe32s(f
, &opp
->src
[i
].last_cpu
);
1073 qemu_put_sbe32s(f
, &opp
->src
[i
].pending
);
1076 qemu_put_sbe32s(f
, &opp
->nb_cpus
);
1078 for (i
= 0; i
< opp
->nb_cpus
; i
++) {
1079 qemu_put_be32s(f
, &opp
->dst
[i
].tfrr
);
1080 qemu_put_be32s(f
, &opp
->dst
[i
].pctp
);
1081 qemu_put_be32s(f
, &opp
->dst
[i
].pcsr
);
1082 openpic_save_IRQ_queue(f
, &opp
->dst
[i
].raised
);
1083 openpic_save_IRQ_queue(f
, &opp
->dst
[i
].servicing
);
1086 for (i
= 0; i
< MAX_TMR
; i
++) {
1087 qemu_put_be32s(f
, &opp
->timers
[i
].ticc
);
1088 qemu_put_be32s(f
, &opp
->timers
[i
].tibc
);
1092 qemu_put_be32s(f
, &opp
->dar
);
1094 for (i
= 0; i
< MAX_DBL
; i
++) {
1095 qemu_put_be32s(f
, &opp
->doorbells
[i
].dmr
);
1100 for (i
= 0; i
< MAX_MAILBOXES
; i
++) {
1101 qemu_put_be32s(f
, &opp
->mailboxes
[i
].mbr
);
1105 pci_device_save(&opp
->pci_dev
, f
);
1108 static void openpic_load_IRQ_queue(QEMUFile
* f
, IRQ_queue_t
*q
)
1112 for (i
= 0; i
< BF_WIDTH(MAX_IRQ
); i
++)
1113 qemu_get_be32s(f
, &q
->queue
[i
]);
1115 qemu_get_sbe32s(f
, &q
->next
);
1116 qemu_get_sbe32s(f
, &q
->priority
);
1119 static int openpic_load(QEMUFile
* f
, void *opaque
, int version_id
)
1121 openpic_t
*opp
= (openpic_t
*)opaque
;
1124 if (version_id
!= 1)
1127 qemu_get_be32s(f
, &opp
->frep
);
1128 qemu_get_be32s(f
, &opp
->glbc
);
1129 qemu_get_be32s(f
, &opp
->micr
);
1130 qemu_get_be32s(f
, &opp
->veni
);
1131 qemu_get_be32s(f
, &opp
->pint
);
1132 qemu_get_be32s(f
, &opp
->spve
);
1133 qemu_get_be32s(f
, &opp
->tifr
);
1135 for (i
= 0; i
< opp
->max_irq
; i
++) {
1136 qemu_get_be32s(f
, &opp
->src
[i
].ipvp
);
1137 qemu_get_be32s(f
, &opp
->src
[i
].ide
);
1138 qemu_get_sbe32s(f
, &opp
->src
[i
].type
);
1139 qemu_get_sbe32s(f
, &opp
->src
[i
].last_cpu
);
1140 qemu_get_sbe32s(f
, &opp
->src
[i
].pending
);
1143 qemu_get_sbe32s(f
, &opp
->nb_cpus
);
1145 for (i
= 0; i
< opp
->nb_cpus
; i
++) {
1146 qemu_get_be32s(f
, &opp
->dst
[i
].tfrr
);
1147 qemu_get_be32s(f
, &opp
->dst
[i
].pctp
);
1148 qemu_get_be32s(f
, &opp
->dst
[i
].pcsr
);
1149 openpic_load_IRQ_queue(f
, &opp
->dst
[i
].raised
);
1150 openpic_load_IRQ_queue(f
, &opp
->dst
[i
].servicing
);
1153 for (i
= 0; i
< MAX_TMR
; i
++) {
1154 qemu_get_be32s(f
, &opp
->timers
[i
].ticc
);
1155 qemu_get_be32s(f
, &opp
->timers
[i
].tibc
);
1159 qemu_get_be32s(f
, &opp
->dar
);
1161 for (i
= 0; i
< MAX_DBL
; i
++) {
1162 qemu_get_be32s(f
, &opp
->doorbells
[i
].dmr
);
1167 for (i
= 0; i
< MAX_MAILBOXES
; i
++) {
1168 qemu_get_be32s(f
, &opp
->mailboxes
[i
].mbr
);
1172 return pci_device_load(&opp
->pci_dev
, f
);
1175 static void openpic_irq_raise(openpic_t
*opp
, int n_CPU
, IRQ_src_t
*src
)
1177 qemu_irq_raise(opp
->dst
[n_CPU
].irqs
[OPENPIC_OUTPUT_INT
]);
1180 qemu_irq
*openpic_init (PCIBus
*bus
, MemoryRegion
**pmem
, int nb_cpus
,
1181 qemu_irq
**irqs
, qemu_irq irq_out
)
1187 /* XXX: for now, only one CPU is supported */
1191 opp
= (openpic_t
*)pci_register_device(bus
, "OpenPIC", sizeof(openpic_t
),
1193 pci_conf
= opp
->pci_dev
.config
;
1194 pci_config_set_vendor_id(pci_conf
, PCI_VENDOR_ID_IBM
);
1195 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_IBM_OPENPIC2
);
1196 pci_config_set_class(pci_conf
, PCI_CLASS_SYSTEM_OTHER
); // FIXME?
1197 pci_conf
[0x3d] = 0x00; // no interrupt pin
1199 memory_region_init_io(&opp
->mem
, &openpic_ops
, opp
, "openpic", 0x40000);
1200 #if 0 // Don't implement ISU for now
1201 opp_io_memory
= cpu_register_io_memory(openpic_src_read
,
1202 openpic_src_write
, NULL
1203 DEVICE_NATIVE_ENDIAN
);
1204 cpu_register_physical_memory(isu_base
, 0x20 * (EXT_IRQ
+ 2),
1208 /* Register I/O spaces */
1209 pci_register_bar(&opp
->pci_dev
, 0,
1210 PCI_BASE_ADDRESS_SPACE_MEMORY
, &opp
->mem
);
1212 opp
= g_malloc0(sizeof(openpic_t
));
1213 memory_region_init_io(&opp
->mem
, &openpic_ops
, opp
, "openpic", 0x40000);
1216 // isu_base &= 0xFFFC0000;
1217 opp
->nb_cpus
= nb_cpus
;
1218 opp
->max_irq
= OPENPIC_MAX_IRQ
;
1219 opp
->irq_ipi0
= OPENPIC_IRQ_IPI0
;
1220 opp
->irq_tim0
= OPENPIC_IRQ_TIM0
;
1222 for (i
= 0; i
< OPENPIC_EXT_IRQ
; i
++) {
1223 opp
->src
[i
].type
= IRQ_EXTERNAL
;
1225 for (; i
< OPENPIC_IRQ_TIM0
; i
++) {
1226 opp
->src
[i
].type
= IRQ_SPECIAL
;
1229 m
= OPENPIC_IRQ_IPI0
;
1231 m
= OPENPIC_IRQ_DBL0
;
1233 for (; i
< m
; i
++) {
1234 opp
->src
[i
].type
= IRQ_TIMER
;
1236 for (; i
< OPENPIC_MAX_IRQ
; i
++) {
1237 opp
->src
[i
].type
= IRQ_INTERNAL
;
1239 for (i
= 0; i
< nb_cpus
; i
++)
1240 opp
->dst
[i
].irqs
= irqs
[i
];
1241 opp
->irq_out
= irq_out
;
1243 register_savevm(&opp
->pci_dev
.qdev
, "openpic", 0, 2,
1244 openpic_save
, openpic_load
, opp
);
1245 qemu_register_reset(openpic_reset
, opp
);
1247 opp
->irq_raise
= openpic_irq_raise
;
1248 opp
->reset
= openpic_reset
;
1253 return qemu_allocate_irqs(openpic_set_irq
, opp
, opp
->max_irq
);
1256 static void mpic_irq_raise(openpic_t
*mpp
, int n_CPU
, IRQ_src_t
*src
)
1258 int n_ci
= IDR_CI0
- n_CPU
;
1260 if(test_bit(&src
->ide
, n_ci
)) {
1261 qemu_irq_raise(mpp
->dst
[n_CPU
].irqs
[OPENPIC_OUTPUT_CINT
]);
1264 qemu_irq_raise(mpp
->dst
[n_CPU
].irqs
[OPENPIC_OUTPUT_INT
]);
1268 static void mpic_reset (void *opaque
)
1270 openpic_t
*mpp
= (openpic_t
*)opaque
;
1273 mpp
->glbc
= 0x80000000;
1274 /* Initialise controller registers */
1275 mpp
->frep
= 0x004f0002 | ((mpp
->nb_cpus
- 1) << 8);
1277 mpp
->pint
= 0x00000000;
1278 mpp
->spve
= 0x0000FFFF;
1279 /* Initialise IRQ sources */
1280 for (i
= 0; i
< mpp
->max_irq
; i
++) {
1281 mpp
->src
[i
].ipvp
= 0x80800000;
1282 mpp
->src
[i
].ide
= 0x00000001;
1284 /* Set IDE for IPIs to 0 so we don't get spurious interrupts */
1285 for (i
= mpp
->irq_ipi0
; i
< (mpp
->irq_ipi0
+ MAX_IPI
); i
++) {
1286 mpp
->src
[i
].ide
= 0;
1288 /* Initialise IRQ destinations */
1289 for (i
= 0; i
< MAX_CPU
; i
++) {
1290 mpp
->dst
[i
].pctp
= 0x0000000F;
1291 mpp
->dst
[i
].tfrr
= 0x00000000;
1292 memset(&mpp
->dst
[i
].raised
, 0, sizeof(IRQ_queue_t
));
1293 mpp
->dst
[i
].raised
.next
= -1;
1294 memset(&mpp
->dst
[i
].servicing
, 0, sizeof(IRQ_queue_t
));
1295 mpp
->dst
[i
].servicing
.next
= -1;
1297 /* Initialise timers */
1298 for (i
= 0; i
< MAX_TMR
; i
++) {
1299 mpp
->timers
[i
].ticc
= 0x00000000;
1300 mpp
->timers
[i
].tibc
= 0x80000000;
1302 /* Go out of RESET state */
1303 mpp
->glbc
= 0x00000000;
1306 static void mpic_timer_write (void *opaque
, target_phys_addr_t addr
, uint32_t val
)
1308 openpic_t
*mpp
= opaque
;
1311 DPRINTF("%s: addr " TARGET_FMT_plx
" <= %08x\n", __func__
, addr
, val
);
1316 idx
= (addr
>> 6) & 0x3;
1317 switch (addr
& 0x30) {
1318 case 0x00: /* gtccr */
1320 case 0x10: /* gtbcr */
1321 if ((mpp
->timers
[idx
].ticc
& 0x80000000) != 0 &&
1322 (val
& 0x80000000) == 0 &&
1323 (mpp
->timers
[idx
].tibc
& 0x80000000) != 0)
1324 mpp
->timers
[idx
].ticc
&= ~0x80000000;
1325 mpp
->timers
[idx
].tibc
= val
;
1327 case 0x20: /* GTIVPR */
1328 write_IRQreg_ipvp(mpp
, MPIC_TMR_IRQ
+ idx
, val
);
1330 case 0x30: /* GTIDR & TFRR */
1331 if ((addr
& 0xF0) == 0xF0)
1332 mpp
->dst
[cpu
].tfrr
= val
;
1334 write_IRQreg_ide(mpp
, MPIC_TMR_IRQ
+ idx
, val
);
1339 static uint32_t mpic_timer_read (void *opaque
, target_phys_addr_t addr
)
1341 openpic_t
*mpp
= opaque
;
1345 DPRINTF("%s: addr " TARGET_FMT_plx
"\n", __func__
, addr
);
1346 retval
= 0xFFFFFFFF;
1351 idx
= (addr
>> 6) & 0x3;
1352 switch (addr
& 0x30) {
1353 case 0x00: /* gtccr */
1354 retval
= mpp
->timers
[idx
].ticc
;
1356 case 0x10: /* gtbcr */
1357 retval
= mpp
->timers
[idx
].tibc
;
1359 case 0x20: /* TIPV */
1360 retval
= read_IRQreg_ipvp(mpp
, MPIC_TMR_IRQ
+ idx
);
1362 case 0x30: /* TIDR */
1363 if ((addr
&0xF0) == 0XF0)
1364 retval
= mpp
->dst
[cpu
].tfrr
;
1366 retval
= read_IRQreg_ide(mpp
, MPIC_TMR_IRQ
+ idx
);
1369 DPRINTF("%s: => %08x\n", __func__
, retval
);
1374 static void mpic_src_ext_write (void *opaque
, target_phys_addr_t addr
,
1377 openpic_t
*mpp
= opaque
;
1378 int idx
= MPIC_EXT_IRQ
;
1380 DPRINTF("%s: addr " TARGET_FMT_plx
" <= %08x\n", __func__
, addr
, val
);
1384 addr
-= MPIC_EXT_REG_START
& (OPENPIC_PAGE_SIZE
- 1);
1385 if (addr
< MPIC_EXT_REG_SIZE
) {
1386 idx
+= (addr
& 0xFFF0) >> 5;
1388 /* EXDE / IFEDE / IEEDE */
1389 write_IRQreg_ide(mpp
, idx
, val
);
1391 /* EXVP / IFEVP / IEEVP */
1392 write_IRQreg_ipvp(mpp
, idx
, val
);
1397 static uint32_t mpic_src_ext_read (void *opaque
, target_phys_addr_t addr
)
1399 openpic_t
*mpp
= opaque
;
1401 int idx
= MPIC_EXT_IRQ
;
1403 DPRINTF("%s: addr " TARGET_FMT_plx
"\n", __func__
, addr
);
1404 retval
= 0xFFFFFFFF;
1408 addr
-= MPIC_EXT_REG_START
& (OPENPIC_PAGE_SIZE
- 1);
1409 if (addr
< MPIC_EXT_REG_SIZE
) {
1410 idx
+= (addr
& 0xFFF0) >> 5;
1412 /* EXDE / IFEDE / IEEDE */
1413 retval
= read_IRQreg_ide(mpp
, idx
);
1415 /* EXVP / IFEVP / IEEVP */
1416 retval
= read_IRQreg_ipvp(mpp
, idx
);
1418 DPRINTF("%s: => %08x\n", __func__
, retval
);
1424 static void mpic_src_int_write (void *opaque
, target_phys_addr_t addr
,
1427 openpic_t
*mpp
= opaque
;
1428 int idx
= MPIC_INT_IRQ
;
1430 DPRINTF("%s: addr " TARGET_FMT_plx
" <= %08x\n", __func__
, addr
, val
);
1434 addr
-= MPIC_INT_REG_START
& (OPENPIC_PAGE_SIZE
- 1);
1435 if (addr
< MPIC_INT_REG_SIZE
) {
1436 idx
+= (addr
& 0xFFF0) >> 5;
1438 /* EXDE / IFEDE / IEEDE */
1439 write_IRQreg_ide(mpp
, idx
, val
);
1441 /* EXVP / IFEVP / IEEVP */
1442 write_IRQreg_ipvp(mpp
, idx
, val
);
1447 static uint32_t mpic_src_int_read (void *opaque
, target_phys_addr_t addr
)
1449 openpic_t
*mpp
= opaque
;
1451 int idx
= MPIC_INT_IRQ
;
1453 DPRINTF("%s: addr " TARGET_FMT_plx
"\n", __func__
, addr
);
1454 retval
= 0xFFFFFFFF;
1458 addr
-= MPIC_INT_REG_START
& (OPENPIC_PAGE_SIZE
- 1);
1459 if (addr
< MPIC_INT_REG_SIZE
) {
1460 idx
+= (addr
& 0xFFF0) >> 5;
1462 /* EXDE / IFEDE / IEEDE */
1463 retval
= read_IRQreg_ide(mpp
, idx
);
1465 /* EXVP / IFEVP / IEEVP */
1466 retval
= read_IRQreg_ipvp(mpp
, idx
);
1468 DPRINTF("%s: => %08x\n", __func__
, retval
);
1474 static void mpic_src_msg_write (void *opaque
, target_phys_addr_t addr
,
1477 openpic_t
*mpp
= opaque
;
1478 int idx
= MPIC_MSG_IRQ
;
1480 DPRINTF("%s: addr " TARGET_FMT_plx
" <= %08x\n", __func__
, addr
, val
);
1484 addr
-= MPIC_MSG_REG_START
& (OPENPIC_PAGE_SIZE
- 1);
1485 if (addr
< MPIC_MSG_REG_SIZE
) {
1486 idx
+= (addr
& 0xFFF0) >> 5;
1488 /* EXDE / IFEDE / IEEDE */
1489 write_IRQreg_ide(mpp
, idx
, val
);
1491 /* EXVP / IFEVP / IEEVP */
1492 write_IRQreg_ipvp(mpp
, idx
, val
);
1497 static uint32_t mpic_src_msg_read (void *opaque
, target_phys_addr_t addr
)
1499 openpic_t
*mpp
= opaque
;
1501 int idx
= MPIC_MSG_IRQ
;
1503 DPRINTF("%s: addr " TARGET_FMT_plx
"\n", __func__
, addr
);
1504 retval
= 0xFFFFFFFF;
1508 addr
-= MPIC_MSG_REG_START
& (OPENPIC_PAGE_SIZE
- 1);
1509 if (addr
< MPIC_MSG_REG_SIZE
) {
1510 idx
+= (addr
& 0xFFF0) >> 5;
1512 /* EXDE / IFEDE / IEEDE */
1513 retval
= read_IRQreg_ide(mpp
, idx
);
1515 /* EXVP / IFEVP / IEEVP */
1516 retval
= read_IRQreg_ipvp(mpp
, idx
);
1518 DPRINTF("%s: => %08x\n", __func__
, retval
);
1524 static void mpic_src_msi_write (void *opaque
, target_phys_addr_t addr
,
1527 openpic_t
*mpp
= opaque
;
1528 int idx
= MPIC_MSI_IRQ
;
1530 DPRINTF("%s: addr " TARGET_FMT_plx
" <= %08x\n", __func__
, addr
, val
);
1534 addr
-= MPIC_MSI_REG_START
& (OPENPIC_PAGE_SIZE
- 1);
1535 if (addr
< MPIC_MSI_REG_SIZE
) {
1536 idx
+= (addr
& 0xFFF0) >> 5;
1538 /* EXDE / IFEDE / IEEDE */
1539 write_IRQreg_ide(mpp
, idx
, val
);
1541 /* EXVP / IFEVP / IEEVP */
1542 write_IRQreg_ipvp(mpp
, idx
, val
);
1546 static uint32_t mpic_src_msi_read (void *opaque
, target_phys_addr_t addr
)
1548 openpic_t
*mpp
= opaque
;
1550 int idx
= MPIC_MSI_IRQ
;
1552 DPRINTF("%s: addr " TARGET_FMT_plx
"\n", __func__
, addr
);
1553 retval
= 0xFFFFFFFF;
1557 addr
-= MPIC_MSI_REG_START
& (OPENPIC_PAGE_SIZE
- 1);
1558 if (addr
< MPIC_MSI_REG_SIZE
) {
1559 idx
+= (addr
& 0xFFF0) >> 5;
1561 /* EXDE / IFEDE / IEEDE */
1562 retval
= read_IRQreg_ide(mpp
, idx
);
1564 /* EXVP / IFEVP / IEEVP */
1565 retval
= read_IRQreg_ipvp(mpp
, idx
);
1567 DPRINTF("%s: => %08x\n", __func__
, retval
);
1573 static CPUWriteMemoryFunc
* const mpic_glb_write
[] = {
1574 &openpic_buggy_write
,
1575 &openpic_buggy_write
,
1579 static CPUReadMemoryFunc
* const mpic_glb_read
[] = {
1580 &openpic_buggy_read
,
1581 &openpic_buggy_read
,
1585 static CPUWriteMemoryFunc
* const mpic_tmr_write
[] = {
1586 &openpic_buggy_write
,
1587 &openpic_buggy_write
,
1591 static CPUReadMemoryFunc
* const mpic_tmr_read
[] = {
1592 &openpic_buggy_read
,
1593 &openpic_buggy_read
,
1597 static CPUWriteMemoryFunc
* const mpic_cpu_write
[] = {
1598 &openpic_buggy_write
,
1599 &openpic_buggy_write
,
1603 static CPUReadMemoryFunc
* const mpic_cpu_read
[] = {
1604 &openpic_buggy_read
,
1605 &openpic_buggy_read
,
1609 static CPUWriteMemoryFunc
* const mpic_ext_write
[] = {
1610 &openpic_buggy_write
,
1611 &openpic_buggy_write
,
1612 &mpic_src_ext_write
,
1615 static CPUReadMemoryFunc
* const mpic_ext_read
[] = {
1616 &openpic_buggy_read
,
1617 &openpic_buggy_read
,
1621 static CPUWriteMemoryFunc
* const mpic_int_write
[] = {
1622 &openpic_buggy_write
,
1623 &openpic_buggy_write
,
1624 &mpic_src_int_write
,
1627 static CPUReadMemoryFunc
* const mpic_int_read
[] = {
1628 &openpic_buggy_read
,
1629 &openpic_buggy_read
,
1633 static CPUWriteMemoryFunc
* const mpic_msg_write
[] = {
1634 &openpic_buggy_write
,
1635 &openpic_buggy_write
,
1636 &mpic_src_msg_write
,
1639 static CPUReadMemoryFunc
* const mpic_msg_read
[] = {
1640 &openpic_buggy_read
,
1641 &openpic_buggy_read
,
1644 static CPUWriteMemoryFunc
* const mpic_msi_write
[] = {
1645 &openpic_buggy_write
,
1646 &openpic_buggy_write
,
1647 &mpic_src_msi_write
,
1650 static CPUReadMemoryFunc
* const mpic_msi_read
[] = {
1651 &openpic_buggy_read
,
1652 &openpic_buggy_read
,
1656 qemu_irq
*mpic_init (target_phys_addr_t base
, int nb_cpus
,
1657 qemu_irq
**irqs
, qemu_irq irq_out
)
1662 CPUReadMemoryFunc
* const *read
;
1663 CPUWriteMemoryFunc
* const *write
;
1664 target_phys_addr_t start_addr
;
1667 {mpic_glb_read
, mpic_glb_write
, MPIC_GLB_REG_START
, MPIC_GLB_REG_SIZE
},
1668 {mpic_tmr_read
, mpic_tmr_write
, MPIC_TMR_REG_START
, MPIC_TMR_REG_SIZE
},
1669 {mpic_ext_read
, mpic_ext_write
, MPIC_EXT_REG_START
, MPIC_EXT_REG_SIZE
},
1670 {mpic_int_read
, mpic_int_write
, MPIC_INT_REG_START
, MPIC_INT_REG_SIZE
},
1671 {mpic_msg_read
, mpic_msg_write
, MPIC_MSG_REG_START
, MPIC_MSG_REG_SIZE
},
1672 {mpic_msi_read
, mpic_msi_write
, MPIC_MSI_REG_START
, MPIC_MSI_REG_SIZE
},
1673 {mpic_cpu_read
, mpic_cpu_write
, MPIC_CPU_REG_START
, MPIC_CPU_REG_SIZE
},
1676 mpp
= g_malloc0(sizeof(openpic_t
));
1678 for (i
= 0; i
< sizeof(list
)/sizeof(list
[0]); i
++) {
1681 mem_index
= cpu_register_io_memory(list
[i
].read
, list
[i
].write
, mpp
,
1683 if (mem_index
< 0) {
1686 cpu_register_physical_memory(base
+ list
[i
].start_addr
,
1687 list
[i
].size
, mem_index
);
1690 mpp
->nb_cpus
= nb_cpus
;
1691 mpp
->max_irq
= MPIC_MAX_IRQ
;
1692 mpp
->irq_ipi0
= MPIC_IPI_IRQ
;
1693 mpp
->irq_tim0
= MPIC_TMR_IRQ
;
1695 for (i
= 0; i
< nb_cpus
; i
++)
1696 mpp
->dst
[i
].irqs
= irqs
[i
];
1697 mpp
->irq_out
= irq_out
;
1699 mpp
->irq_raise
= mpic_irq_raise
;
1700 mpp
->reset
= mpic_reset
;
1702 register_savevm(NULL
, "mpic", 0, 2, openpic_save
, openpic_load
, mpp
);
1703 qemu_register_reset(mpic_reset
, mpp
);
1705 return qemu_allocate_irqs(openpic_set_irq
, mpp
, mpp
->max_irq
);