4 * Copyright (c) 2004 Jocelyn Mayer
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 * Based on OpenPic implementations:
28 * - Intel GW80314 I/O companion chip developer's manual
29 * - Motorola MPC8245 & MPC8540 user manuals.
30 * - Motorola MCP750 (aka Raven) programmer manual.
31 * - Motorola Harrier programmer manuel
33 * Serial interrupts, as implemented in Raven chipset are not supported yet.
41 //#define DEBUG_OPENPIC
44 #define DPRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while (0)
46 #define DPRINTF(fmt, ...) do { } while (0)
49 #define USE_MPCxxx /* Intel model is broken, for now */
51 #if defined (USE_INTEL_GW80314)
52 /* Intel GW80314 I/O Companion chip */
62 #define VID (0x00000000)
64 #elif defined(USE_MPCxxx)
73 #define VID 0x03 /* MPIC version ID */
74 #define VENI 0x00000000 /* Vendor ID */
82 #define OPENPIC_MAX_CPU 2
83 #define OPENPIC_MAX_IRQ 64
84 #define OPENPIC_EXT_IRQ 48
85 #define OPENPIC_MAX_TMR MAX_TMR
86 #define OPENPIC_MAX_IPI MAX_IPI
88 /* Interrupt definitions */
89 #define OPENPIC_IRQ_FE (OPENPIC_EXT_IRQ) /* Internal functional IRQ */
90 #define OPENPIC_IRQ_ERR (OPENPIC_EXT_IRQ + 1) /* Error IRQ */
91 #define OPENPIC_IRQ_TIM0 (OPENPIC_EXT_IRQ + 2) /* First timer IRQ */
92 #if OPENPIC_MAX_IPI > 0
93 #define OPENPIC_IRQ_IPI0 (OPENPIC_IRQ_TIM0 + OPENPIC_MAX_TMR) /* First IPI IRQ */
94 #define OPENPIC_IRQ_DBL0 (OPENPIC_IRQ_IPI0 + (OPENPIC_MAX_CPU * OPENPIC_MAX_IPI)) /* First doorbell IRQ */
96 #define OPENPIC_IRQ_DBL0 (OPENPIC_IRQ_TIM0 + OPENPIC_MAX_TMR) /* First doorbell IRQ */
97 #define OPENPIC_IRQ_MBX0 (OPENPIC_IRQ_DBL0 + OPENPIC_MAX_DBL) /* First mailbox IRQ */
101 #define MPIC_MAX_CPU 1
102 #define MPIC_MAX_EXT 12
103 #define MPIC_MAX_INT 64
104 #define MPIC_MAX_MSG 4
105 #define MPIC_MAX_MSI 8
106 #define MPIC_MAX_TMR MAX_TMR
107 #define MPIC_MAX_IPI MAX_IPI
108 #define MPIC_MAX_IRQ (MPIC_MAX_EXT + MPIC_MAX_INT + MPIC_MAX_TMR + MPIC_MAX_MSG + MPIC_MAX_MSI + (MPIC_MAX_IPI * MPIC_MAX_CPU))
110 /* Interrupt definitions */
111 #define MPIC_EXT_IRQ 0
112 #define MPIC_INT_IRQ (MPIC_EXT_IRQ + MPIC_MAX_EXT)
113 #define MPIC_TMR_IRQ (MPIC_INT_IRQ + MPIC_MAX_INT)
114 #define MPIC_MSG_IRQ (MPIC_TMR_IRQ + MPIC_MAX_TMR)
115 #define MPIC_MSI_IRQ (MPIC_MSG_IRQ + MPIC_MAX_MSG)
116 #define MPIC_IPI_IRQ (MPIC_MSI_IRQ + MPIC_MAX_MSI)
118 #define MPIC_GLB_REG_START 0x0
119 #define MPIC_GLB_REG_SIZE 0x10F0
120 #define MPIC_TMR_REG_START 0x10F0
121 #define MPIC_TMR_REG_SIZE 0x220
122 #define MPIC_EXT_REG_START 0x10000
123 #define MPIC_EXT_REG_SIZE 0x180
124 #define MPIC_INT_REG_START 0x10200
125 #define MPIC_INT_REG_SIZE 0x800
126 #define MPIC_MSG_REG_START 0x11600
127 #define MPIC_MSG_REG_SIZE 0x100
128 #define MPIC_MSI_REG_START 0x11C00
129 #define MPIC_MSI_REG_SIZE 0x100
130 #define MPIC_CPU_REG_START 0x20000
131 #define MPIC_CPU_REG_SIZE 0x100 + ((MAX_CPU - 1) * 0x1000)
142 #error "Please select which OpenPic implementation is to be emulated"
145 #define OPENPIC_PAGE_SIZE 4096
147 #define BF_WIDTH(_bits_) \
148 (((_bits_) + (sizeof(uint32_t) * 8) - 1) / (sizeof(uint32_t) * 8))
150 static inline void set_bit (uint32_t *field
, int bit
)
152 field
[bit
>> 5] |= 1 << (bit
& 0x1F);
155 static inline void reset_bit (uint32_t *field
, int bit
)
157 field
[bit
>> 5] &= ~(1 << (bit
& 0x1F));
160 static inline int test_bit (uint32_t *field
, int bit
)
162 return (field
[bit
>> 5] & 1 << (bit
& 0x1F)) != 0;
165 static int get_current_cpu(void)
167 return cpu_single_env
->cpu_index
;
170 static uint32_t openpic_cpu_read_internal(void *opaque
, target_phys_addr_t addr
,
172 static void openpic_cpu_write_internal(void *opaque
, target_phys_addr_t addr
,
173 uint32_t val
, int idx
);
182 typedef struct IRQ_queue_t
{
183 uint32_t queue
[BF_WIDTH(MAX_IRQ
)];
188 typedef struct IRQ_src_t
{
189 uint32_t ipvp
; /* IRQ vector/priority register */
190 uint32_t ide
; /* IRQ destination register */
193 int pending
; /* TRUE if IRQ is pending */
203 #define IPVP_PRIORITY_MASK (0x1F << 16)
204 #define IPVP_PRIORITY(_ipvpr_) ((int)(((_ipvpr_) & IPVP_PRIORITY_MASK) >> 16))
205 #define IPVP_VECTOR_MASK ((1 << VECTOR_BITS) - 1)
206 #define IPVP_VECTOR(_ipvpr_) ((_ipvpr_) & IPVP_VECTOR_MASK)
208 typedef struct IRQ_dst_t
{
210 uint32_t pctp
; /* CPU current task priority */
211 uint32_t pcsr
; /* CPU sensitivity register */
213 IRQ_queue_t servicing
;
217 typedef struct openpic_t
{
220 /* Global registers */
221 uint32_t frep
; /* Feature reporting register */
222 uint32_t glbc
; /* Global configuration register */
223 uint32_t micr
; /* MPIC interrupt configuration register */
224 uint32_t veni
; /* Vendor identification register */
225 uint32_t pint
; /* Processor initialization register */
226 uint32_t spve
; /* Spurious vector register */
227 uint32_t tifr
; /* Timer frequency reporting register */
228 /* Source registers */
229 IRQ_src_t src
[MAX_IRQ
];
230 /* Local registers per output pin */
231 IRQ_dst_t dst
[MAX_CPU
];
233 /* Timer registers */
235 uint32_t ticc
; /* Global timer current count register */
236 uint32_t tibc
; /* Global timer base count register */
239 /* Doorbell registers */
240 uint32_t dar
; /* Doorbell activate register */
242 uint32_t dmr
; /* Doorbell messaging register */
243 } doorbells
[MAX_DBL
];
246 /* Mailbox registers */
248 uint32_t mbr
; /* Mailbox register */
249 } mailboxes
[MAX_MAILBOXES
];
251 /* IRQ out is used when in bypass mode (not implemented) */
256 void (*reset
) (void *);
257 void (*irq_raise
) (struct openpic_t
*, int, IRQ_src_t
*);
260 static inline void IRQ_setbit (IRQ_queue_t
*q
, int n_IRQ
)
262 set_bit(q
->queue
, n_IRQ
);
265 static inline void IRQ_resetbit (IRQ_queue_t
*q
, int n_IRQ
)
267 reset_bit(q
->queue
, n_IRQ
);
270 static inline int IRQ_testbit (IRQ_queue_t
*q
, int n_IRQ
)
272 return test_bit(q
->queue
, n_IRQ
);
275 static void IRQ_check (openpic_t
*opp
, IRQ_queue_t
*q
)
282 for (i
= 0; i
< opp
->max_irq
; i
++) {
283 if (IRQ_testbit(q
, i
)) {
284 DPRINTF("IRQ_check: irq %d set ipvp_pr=%d pr=%d\n",
285 i
, IPVP_PRIORITY(opp
->src
[i
].ipvp
), priority
);
286 if (IPVP_PRIORITY(opp
->src
[i
].ipvp
) > priority
) {
288 priority
= IPVP_PRIORITY(opp
->src
[i
].ipvp
);
293 q
->priority
= priority
;
296 static int IRQ_get_next (openpic_t
*opp
, IRQ_queue_t
*q
)
306 static void IRQ_local_pipe (openpic_t
*opp
, int n_CPU
, int n_IRQ
)
312 dst
= &opp
->dst
[n_CPU
];
313 src
= &opp
->src
[n_IRQ
];
314 priority
= IPVP_PRIORITY(src
->ipvp
);
315 if (priority
<= dst
->pctp
) {
316 /* Too low priority */
317 DPRINTF("%s: IRQ %d has too low priority on CPU %d\n",
318 __func__
, n_IRQ
, n_CPU
);
321 if (IRQ_testbit(&dst
->raised
, n_IRQ
)) {
323 DPRINTF("%s: IRQ %d was missed on CPU %d\n",
324 __func__
, n_IRQ
, n_CPU
);
327 set_bit(&src
->ipvp
, IPVP_ACTIVITY
);
328 IRQ_setbit(&dst
->raised
, n_IRQ
);
329 if (priority
< dst
->raised
.priority
) {
330 /* An higher priority IRQ is already raised */
331 DPRINTF("%s: IRQ %d is hidden by raised IRQ %d on CPU %d\n",
332 __func__
, n_IRQ
, dst
->raised
.next
, n_CPU
);
335 IRQ_get_next(opp
, &dst
->raised
);
336 if (IRQ_get_next(opp
, &dst
->servicing
) != -1 &&
337 priority
<= dst
->servicing
.priority
) {
338 DPRINTF("%s: IRQ %d is hidden by servicing IRQ %d on CPU %d\n",
339 __func__
, n_IRQ
, dst
->servicing
.next
, n_CPU
);
340 /* Already servicing a higher priority IRQ */
343 DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n", n_CPU
, n_IRQ
);
344 opp
->irq_raise(opp
, n_CPU
, src
);
347 /* update pic state because registers for n_IRQ have changed value */
348 static void openpic_update_irq(openpic_t
*opp
, int n_IRQ
)
353 src
= &opp
->src
[n_IRQ
];
357 DPRINTF("%s: IRQ %d is not pending\n", __func__
, n_IRQ
);
360 if (test_bit(&src
->ipvp
, IPVP_MASK
)) {
361 /* Interrupt source is disabled */
362 DPRINTF("%s: IRQ %d is disabled\n", __func__
, n_IRQ
);
365 if (IPVP_PRIORITY(src
->ipvp
) == 0) {
366 /* Priority set to zero */
367 DPRINTF("%s: IRQ %d has 0 priority\n", __func__
, n_IRQ
);
370 if (test_bit(&src
->ipvp
, IPVP_ACTIVITY
)) {
371 /* IRQ already active */
372 DPRINTF("%s: IRQ %d is already active\n", __func__
, n_IRQ
);
375 if (src
->ide
== 0x00000000) {
377 DPRINTF("%s: IRQ %d has no target\n", __func__
, n_IRQ
);
381 if (src
->ide
== (1 << src
->last_cpu
)) {
382 /* Only one CPU is allowed to receive this IRQ */
383 IRQ_local_pipe(opp
, src
->last_cpu
, n_IRQ
);
384 } else if (!test_bit(&src
->ipvp
, IPVP_MODE
)) {
385 /* Directed delivery mode */
386 for (i
= 0; i
< opp
->nb_cpus
; i
++) {
387 if (test_bit(&src
->ide
, i
))
388 IRQ_local_pipe(opp
, i
, n_IRQ
);
391 /* Distributed delivery mode */
392 for (i
= src
->last_cpu
+ 1; i
!= src
->last_cpu
; i
++) {
393 if (i
== opp
->nb_cpus
)
395 if (test_bit(&src
->ide
, i
)) {
396 IRQ_local_pipe(opp
, i
, n_IRQ
);
404 static void openpic_set_irq(void *opaque
, int n_IRQ
, int level
)
406 openpic_t
*opp
= opaque
;
409 src
= &opp
->src
[n_IRQ
];
410 DPRINTF("openpic: set irq %d = %d ipvp=%08x\n",
411 n_IRQ
, level
, src
->ipvp
);
412 if (test_bit(&src
->ipvp
, IPVP_SENSE
)) {
413 /* level-sensitive irq */
414 src
->pending
= level
;
416 reset_bit(&src
->ipvp
, IPVP_ACTIVITY
);
418 /* edge-sensitive irq */
422 openpic_update_irq(opp
, n_IRQ
);
425 static void openpic_reset (void *opaque
)
427 openpic_t
*opp
= (openpic_t
*)opaque
;
430 opp
->glbc
= 0x80000000;
431 /* Initialise controller registers */
432 opp
->frep
= ((OPENPIC_EXT_IRQ
- 1) << 16) | ((MAX_CPU
- 1) << 8) | VID
;
434 opp
->pint
= 0x00000000;
435 opp
->spve
= 0x000000FF;
436 opp
->tifr
= 0x003F7A00;
438 opp
->micr
= 0x00000000;
439 /* Initialise IRQ sources */
440 for (i
= 0; i
< opp
->max_irq
; i
++) {
441 opp
->src
[i
].ipvp
= 0xA0000000;
442 opp
->src
[i
].ide
= 0x00000000;
444 /* Initialise IRQ destinations */
445 for (i
= 0; i
< MAX_CPU
; i
++) {
446 opp
->dst
[i
].pctp
= 0x0000000F;
447 opp
->dst
[i
].pcsr
= 0x00000000;
448 memset(&opp
->dst
[i
].raised
, 0, sizeof(IRQ_queue_t
));
449 opp
->dst
[i
].raised
.next
= -1;
450 memset(&opp
->dst
[i
].servicing
, 0, sizeof(IRQ_queue_t
));
451 opp
->dst
[i
].servicing
.next
= -1;
453 /* Initialise timers */
454 for (i
= 0; i
< MAX_TMR
; i
++) {
455 opp
->timers
[i
].ticc
= 0x00000000;
456 opp
->timers
[i
].tibc
= 0x80000000;
458 /* Initialise doorbells */
460 opp
->dar
= 0x00000000;
461 for (i
= 0; i
< MAX_DBL
; i
++) {
462 opp
->doorbells
[i
].dmr
= 0x00000000;
465 /* Initialise mailboxes */
467 for (i
= 0; i
< MAX_MBX
; i
++) { /* ? */
468 opp
->mailboxes
[i
].mbr
= 0x00000000;
471 /* Go out of RESET state */
472 opp
->glbc
= 0x00000000;
475 static inline uint32_t read_IRQreg (openpic_t
*opp
, int n_IRQ
, uint32_t reg
)
481 retval
= opp
->src
[n_IRQ
].ipvp
;
484 retval
= opp
->src
[n_IRQ
].ide
;
491 static inline void write_IRQreg (openpic_t
*opp
, int n_IRQ
,
492 uint32_t reg
, uint32_t val
)
498 /* NOTE: not fully accurate for special IRQs, but simple and
500 /* ACTIVITY bit is read-only */
501 opp
->src
[n_IRQ
].ipvp
=
502 (opp
->src
[n_IRQ
].ipvp
& 0x40000000) |
504 openpic_update_irq(opp
, n_IRQ
);
505 DPRINTF("Set IPVP %d to 0x%08x -> 0x%08x\n",
506 n_IRQ
, val
, opp
->src
[n_IRQ
].ipvp
);
509 tmp
= val
& 0xC0000000;
510 tmp
|= val
& ((1 << MAX_CPU
) - 1);
511 opp
->src
[n_IRQ
].ide
= tmp
;
512 DPRINTF("Set IDE %d to 0x%08x\n", n_IRQ
, opp
->src
[n_IRQ
].ide
);
517 #if 0 // Code provision for Intel model
519 static uint32_t read_doorbell_register (openpic_t
*opp
,
520 int n_dbl
, uint32_t offset
)
525 case DBL_IPVP_OFFSET
:
526 retval
= read_IRQreg(opp
, IRQ_DBL0
+ n_dbl
, IRQ_IPVP
);
529 retval
= read_IRQreg(opp
, IRQ_DBL0
+ n_dbl
, IRQ_IDE
);
532 retval
= opp
->doorbells
[n_dbl
].dmr
;
539 static void write_doorbell_register (penpic_t
*opp
, int n_dbl
,
540 uint32_t offset
, uint32_t value
)
543 case DBL_IVPR_OFFSET
:
544 write_IRQreg(opp
, IRQ_DBL0
+ n_dbl
, IRQ_IPVP
, value
);
547 write_IRQreg(opp
, IRQ_DBL0
+ n_dbl
, IRQ_IDE
, value
);
550 opp
->doorbells
[n_dbl
].dmr
= value
;
557 static uint32_t read_mailbox_register (openpic_t
*opp
,
558 int n_mbx
, uint32_t offset
)
564 retval
= opp
->mailboxes
[n_mbx
].mbr
;
566 case MBX_IVPR_OFFSET
:
567 retval
= read_IRQreg(opp
, IRQ_MBX0
+ n_mbx
, IRQ_IPVP
);
570 retval
= read_IRQreg(opp
, IRQ_MBX0
+ n_mbx
, IRQ_IDE
);
577 static void write_mailbox_register (openpic_t
*opp
, int n_mbx
,
578 uint32_t address
, uint32_t value
)
582 opp
->mailboxes
[n_mbx
].mbr
= value
;
584 case MBX_IVPR_OFFSET
:
585 write_IRQreg(opp
, IRQ_MBX0
+ n_mbx
, IRQ_IPVP
, value
);
588 write_IRQreg(opp
, IRQ_MBX0
+ n_mbx
, IRQ_IDE
, value
);
593 #endif /* 0 : Code provision for Intel model */
595 static void openpic_gbl_write (void *opaque
, target_phys_addr_t addr
, uint32_t val
)
597 openpic_t
*opp
= opaque
;
601 DPRINTF("%s: addr " TARGET_FMT_plx
" <= %08x\n", __func__
, addr
, val
);
613 openpic_cpu_write_internal(opp
, addr
, val
, get_current_cpu());
615 case 0x1000: /* FREP */
617 case 0x1020: /* GLBC */
618 if (val
& 0x80000000 && opp
->reset
)
620 opp
->glbc
= val
& ~0x80000000;
622 case 0x1080: /* VENI */
624 case 0x1090: /* PINT */
625 for (idx
= 0; idx
< opp
->nb_cpus
; idx
++) {
626 if ((val
& (1 << idx
)) && !(opp
->pint
& (1 << idx
))) {
627 DPRINTF("Raise OpenPIC RESET output for CPU %d\n", idx
);
628 dst
= &opp
->dst
[idx
];
629 qemu_irq_raise(dst
->irqs
[OPENPIC_OUTPUT_RESET
]);
630 } else if (!(val
& (1 << idx
)) && (opp
->pint
& (1 << idx
))) {
631 DPRINTF("Lower OpenPIC RESET output for CPU %d\n", idx
);
632 dst
= &opp
->dst
[idx
];
633 qemu_irq_lower(dst
->irqs
[OPENPIC_OUTPUT_RESET
]);
638 case 0x10A0: /* IPI_IPVP */
644 idx
= (addr
- 0x10A0) >> 4;
645 write_IRQreg(opp
, opp
->irq_ipi0
+ idx
, IRQ_IPVP
, val
);
648 case 0x10E0: /* SPVE */
649 opp
->spve
= val
& 0x000000FF;
651 case 0x10F0: /* TIFR */
659 static uint32_t openpic_gbl_read (void *opaque
, target_phys_addr_t addr
)
661 openpic_t
*opp
= opaque
;
664 DPRINTF("%s: addr " TARGET_FMT_plx
"\n", __func__
, addr
);
669 case 0x1000: /* FREP */
672 case 0x1020: /* GLBC */
675 case 0x1080: /* VENI */
678 case 0x1090: /* PINT */
689 retval
= openpic_cpu_read_internal(opp
, addr
, get_current_cpu());
691 case 0x10A0: /* IPI_IPVP */
697 idx
= (addr
- 0x10A0) >> 4;
698 retval
= read_IRQreg(opp
, opp
->irq_ipi0
+ idx
, IRQ_IPVP
);
701 case 0x10E0: /* SPVE */
704 case 0x10F0: /* TIFR */
710 DPRINTF("%s: => %08x\n", __func__
, retval
);
715 static void openpic_timer_write (void *opaque
, uint32_t addr
, uint32_t val
)
717 openpic_t
*opp
= opaque
;
720 DPRINTF("%s: addr %08x <= %08x\n", __func__
, addr
, val
);
725 idx
= (addr
& 0xFFF0) >> 6;
728 case 0x00: /* TICC */
730 case 0x10: /* TIBC */
731 if ((opp
->timers
[idx
].ticc
& 0x80000000) != 0 &&
732 (val
& 0x80000000) == 0 &&
733 (opp
->timers
[idx
].tibc
& 0x80000000) != 0)
734 opp
->timers
[idx
].ticc
&= ~0x80000000;
735 opp
->timers
[idx
].tibc
= val
;
737 case 0x20: /* TIVP */
738 write_IRQreg(opp
, opp
->irq_tim0
+ idx
, IRQ_IPVP
, val
);
740 case 0x30: /* TIDE */
741 write_IRQreg(opp
, opp
->irq_tim0
+ idx
, IRQ_IDE
, val
);
746 static uint32_t openpic_timer_read (void *opaque
, uint32_t addr
)
748 openpic_t
*opp
= opaque
;
752 DPRINTF("%s: addr %08x\n", __func__
, addr
);
758 idx
= (addr
& 0xFFF0) >> 6;
761 case 0x00: /* TICC */
762 retval
= opp
->timers
[idx
].ticc
;
764 case 0x10: /* TIBC */
765 retval
= opp
->timers
[idx
].tibc
;
767 case 0x20: /* TIPV */
768 retval
= read_IRQreg(opp
, opp
->irq_tim0
+ idx
, IRQ_IPVP
);
770 case 0x30: /* TIDE */
771 retval
= read_IRQreg(opp
, opp
->irq_tim0
+ idx
, IRQ_IDE
);
774 DPRINTF("%s: => %08x\n", __func__
, retval
);
779 static void openpic_src_write (void *opaque
, uint32_t addr
, uint32_t val
)
781 openpic_t
*opp
= opaque
;
784 DPRINTF("%s: addr %08x <= %08x\n", __func__
, addr
, val
);
787 addr
= addr
& 0xFFF0;
790 /* EXDE / IFEDE / IEEDE */
791 write_IRQreg(opp
, idx
, IRQ_IDE
, val
);
793 /* EXVP / IFEVP / IEEVP */
794 write_IRQreg(opp
, idx
, IRQ_IPVP
, val
);
798 static uint32_t openpic_src_read (void *opaque
, uint32_t addr
)
800 openpic_t
*opp
= opaque
;
804 DPRINTF("%s: addr %08x\n", __func__
, addr
);
808 addr
= addr
& 0xFFF0;
811 /* EXDE / IFEDE / IEEDE */
812 retval
= read_IRQreg(opp
, idx
, IRQ_IDE
);
814 /* EXVP / IFEVP / IEEVP */
815 retval
= read_IRQreg(opp
, idx
, IRQ_IPVP
);
817 DPRINTF("%s: => %08x\n", __func__
, retval
);
822 static void openpic_cpu_write_internal(void *opaque
, target_phys_addr_t addr
,
823 uint32_t val
, int idx
)
825 openpic_t
*opp
= opaque
;
830 DPRINTF("%s: cpu %d addr " TARGET_FMT_plx
" <= %08x\n", __func__
, idx
,
834 dst
= &opp
->dst
[idx
];
838 case 0x40: /* IPIDR */
842 idx
= (addr
- 0x40) >> 4;
843 /* we use IDE as mask which CPUs to deliver the IPI to still. */
844 write_IRQreg(opp
, opp
->irq_ipi0
+ idx
, IRQ_IDE
,
845 opp
->src
[opp
->irq_ipi0
+ idx
].ide
| val
);
846 openpic_set_irq(opp
, opp
->irq_ipi0
+ idx
, 1);
847 openpic_set_irq(opp
, opp
->irq_ipi0
+ idx
, 0);
850 case 0x80: /* PCTP */
851 dst
->pctp
= val
& 0x0000000F;
853 case 0x90: /* WHOAMI */
854 /* Read-only register */
856 case 0xA0: /* PIAC */
857 /* Read-only register */
859 case 0xB0: /* PEOI */
861 s_IRQ
= IRQ_get_next(opp
, &dst
->servicing
);
862 IRQ_resetbit(&dst
->servicing
, s_IRQ
);
863 dst
->servicing
.next
= -1;
864 /* Set up next servicing IRQ */
865 s_IRQ
= IRQ_get_next(opp
, &dst
->servicing
);
866 /* Check queued interrupts. */
867 n_IRQ
= IRQ_get_next(opp
, &dst
->raised
);
868 src
= &opp
->src
[n_IRQ
];
871 IPVP_PRIORITY(src
->ipvp
) > dst
->servicing
.priority
)) {
872 DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n",
874 opp
->irq_raise(opp
, idx
, src
);
882 static void openpic_cpu_write(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
884 openpic_cpu_write_internal(opaque
, addr
, val
, (addr
& 0x1f000) >> 12);
887 static uint32_t openpic_cpu_read_internal(void *opaque
, target_phys_addr_t addr
,
890 openpic_t
*opp
= opaque
;
896 DPRINTF("%s: cpu %d addr " TARGET_FMT_plx
"\n", __func__
, idx
, addr
);
900 dst
= &opp
->dst
[idx
];
903 case 0x80: /* PCTP */
906 case 0x90: /* WHOAMI */
909 case 0xA0: /* PIAC */
910 DPRINTF("Lower OpenPIC INT output\n");
911 qemu_irq_lower(dst
->irqs
[OPENPIC_OUTPUT_INT
]);
912 n_IRQ
= IRQ_get_next(opp
, &dst
->raised
);
913 DPRINTF("PIAC: irq=%d\n", n_IRQ
);
915 /* No more interrupt pending */
916 retval
= IPVP_VECTOR(opp
->spve
);
918 src
= &opp
->src
[n_IRQ
];
919 if (!test_bit(&src
->ipvp
, IPVP_ACTIVITY
) ||
920 !(IPVP_PRIORITY(src
->ipvp
) > dst
->pctp
)) {
921 /* - Spurious level-sensitive IRQ
922 * - Priorities has been changed
923 * and the pending IRQ isn't allowed anymore
925 reset_bit(&src
->ipvp
, IPVP_ACTIVITY
);
926 retval
= IPVP_VECTOR(opp
->spve
);
928 /* IRQ enter servicing state */
929 IRQ_setbit(&dst
->servicing
, n_IRQ
);
930 retval
= IPVP_VECTOR(src
->ipvp
);
932 IRQ_resetbit(&dst
->raised
, n_IRQ
);
933 dst
->raised
.next
= -1;
934 if (!test_bit(&src
->ipvp
, IPVP_SENSE
)) {
935 /* edge-sensitive IRQ */
936 reset_bit(&src
->ipvp
, IPVP_ACTIVITY
);
940 if ((n_IRQ
>= opp
->irq_ipi0
) && (n_IRQ
< (opp
->irq_ipi0
+ MAX_IPI
))) {
941 src
->ide
&= ~(1 << idx
);
942 if (src
->ide
&& !test_bit(&src
->ipvp
, IPVP_SENSE
)) {
943 /* trigger on CPUs that didn't know about it yet */
944 openpic_set_irq(opp
, n_IRQ
, 1);
945 openpic_set_irq(opp
, n_IRQ
, 0);
946 /* if all CPUs knew about it, set active bit again */
947 set_bit(&src
->ipvp
, IPVP_ACTIVITY
);
952 case 0xB0: /* PEOI */
958 DPRINTF("%s: => %08x\n", __func__
, retval
);
963 static uint32_t openpic_cpu_read(void *opaque
, target_phys_addr_t addr
)
965 return openpic_cpu_read_internal(opaque
, addr
, (addr
& 0x1f000) >> 12);
968 static void openpic_buggy_write (void *opaque
,
969 target_phys_addr_t addr
, uint32_t val
)
971 printf("Invalid OPENPIC write access !\n");
974 static uint32_t openpic_buggy_read (void *opaque
, target_phys_addr_t addr
)
976 printf("Invalid OPENPIC read access !\n");
981 static void openpic_writel (void *opaque
,
982 target_phys_addr_t addr
, uint32_t val
)
984 openpic_t
*opp
= opaque
;
987 DPRINTF("%s: offset %08x val: %08x\n", __func__
, (int)addr
, val
);
989 /* Global registers */
990 openpic_gbl_write(opp
, addr
, val
);
991 } else if (addr
< 0x10000) {
992 /* Timers registers */
993 openpic_timer_write(opp
, addr
, val
);
994 } else if (addr
< 0x20000) {
995 /* Source registers */
996 openpic_src_write(opp
, addr
, val
);
999 openpic_cpu_write(opp
, addr
, val
);
1003 static uint32_t openpic_readl (void *opaque
,target_phys_addr_t addr
)
1005 openpic_t
*opp
= opaque
;
1009 DPRINTF("%s: offset %08x\n", __func__
, (int)addr
);
1010 if (addr
< 0x1100) {
1011 /* Global registers */
1012 retval
= openpic_gbl_read(opp
, addr
);
1013 } else if (addr
< 0x10000) {
1014 /* Timers registers */
1015 retval
= openpic_timer_read(opp
, addr
);
1016 } else if (addr
< 0x20000) {
1017 /* Source registers */
1018 retval
= openpic_src_read(opp
, addr
);
1021 retval
= openpic_cpu_read(opp
, addr
);
1027 static uint64_t openpic_read(void *opaque
, target_phys_addr_t addr
,
1030 openpic_t
*opp
= opaque
;
1033 case 4: return openpic_readl(opp
, addr
);
1034 default: return openpic_buggy_read(opp
, addr
);
1038 static void openpic_write(void *opaque
, target_phys_addr_t addr
,
1039 uint64_t data
, unsigned size
)
1041 openpic_t
*opp
= opaque
;
1044 case 4: return openpic_writel(opp
, addr
, data
);
1045 default: return openpic_buggy_write(opp
, addr
, data
);
1049 static const MemoryRegionOps openpic_ops
= {
1050 .read
= openpic_read
,
1051 .write
= openpic_write
,
1052 .endianness
= DEVICE_LITTLE_ENDIAN
,
1055 static void openpic_save_IRQ_queue(QEMUFile
* f
, IRQ_queue_t
*q
)
1059 for (i
= 0; i
< BF_WIDTH(MAX_IRQ
); i
++)
1060 qemu_put_be32s(f
, &q
->queue
[i
]);
1062 qemu_put_sbe32s(f
, &q
->next
);
1063 qemu_put_sbe32s(f
, &q
->priority
);
1066 static void openpic_save(QEMUFile
* f
, void *opaque
)
1068 openpic_t
*opp
= (openpic_t
*)opaque
;
1071 qemu_put_be32s(f
, &opp
->frep
);
1072 qemu_put_be32s(f
, &opp
->glbc
);
1073 qemu_put_be32s(f
, &opp
->micr
);
1074 qemu_put_be32s(f
, &opp
->veni
);
1075 qemu_put_be32s(f
, &opp
->pint
);
1076 qemu_put_be32s(f
, &opp
->spve
);
1077 qemu_put_be32s(f
, &opp
->tifr
);
1079 for (i
= 0; i
< opp
->max_irq
; i
++) {
1080 qemu_put_be32s(f
, &opp
->src
[i
].ipvp
);
1081 qemu_put_be32s(f
, &opp
->src
[i
].ide
);
1082 qemu_put_sbe32s(f
, &opp
->src
[i
].type
);
1083 qemu_put_sbe32s(f
, &opp
->src
[i
].last_cpu
);
1084 qemu_put_sbe32s(f
, &opp
->src
[i
].pending
);
1087 qemu_put_sbe32s(f
, &opp
->nb_cpus
);
1089 for (i
= 0; i
< opp
->nb_cpus
; i
++) {
1090 qemu_put_be32s(f
, &opp
->dst
[i
].tfrr
);
1091 qemu_put_be32s(f
, &opp
->dst
[i
].pctp
);
1092 qemu_put_be32s(f
, &opp
->dst
[i
].pcsr
);
1093 openpic_save_IRQ_queue(f
, &opp
->dst
[i
].raised
);
1094 openpic_save_IRQ_queue(f
, &opp
->dst
[i
].servicing
);
1097 for (i
= 0; i
< MAX_TMR
; i
++) {
1098 qemu_put_be32s(f
, &opp
->timers
[i
].ticc
);
1099 qemu_put_be32s(f
, &opp
->timers
[i
].tibc
);
1103 qemu_put_be32s(f
, &opp
->dar
);
1105 for (i
= 0; i
< MAX_DBL
; i
++) {
1106 qemu_put_be32s(f
, &opp
->doorbells
[i
].dmr
);
1111 for (i
= 0; i
< MAX_MAILBOXES
; i
++) {
1112 qemu_put_be32s(f
, &opp
->mailboxes
[i
].mbr
);
1116 pci_device_save(&opp
->pci_dev
, f
);
1119 static void openpic_load_IRQ_queue(QEMUFile
* f
, IRQ_queue_t
*q
)
1123 for (i
= 0; i
< BF_WIDTH(MAX_IRQ
); i
++)
1124 qemu_get_be32s(f
, &q
->queue
[i
]);
1126 qemu_get_sbe32s(f
, &q
->next
);
1127 qemu_get_sbe32s(f
, &q
->priority
);
1130 static int openpic_load(QEMUFile
* f
, void *opaque
, int version_id
)
1132 openpic_t
*opp
= (openpic_t
*)opaque
;
1135 if (version_id
!= 1)
1138 qemu_get_be32s(f
, &opp
->frep
);
1139 qemu_get_be32s(f
, &opp
->glbc
);
1140 qemu_get_be32s(f
, &opp
->micr
);
1141 qemu_get_be32s(f
, &opp
->veni
);
1142 qemu_get_be32s(f
, &opp
->pint
);
1143 qemu_get_be32s(f
, &opp
->spve
);
1144 qemu_get_be32s(f
, &opp
->tifr
);
1146 for (i
= 0; i
< opp
->max_irq
; i
++) {
1147 qemu_get_be32s(f
, &opp
->src
[i
].ipvp
);
1148 qemu_get_be32s(f
, &opp
->src
[i
].ide
);
1149 qemu_get_sbe32s(f
, &opp
->src
[i
].type
);
1150 qemu_get_sbe32s(f
, &opp
->src
[i
].last_cpu
);
1151 qemu_get_sbe32s(f
, &opp
->src
[i
].pending
);
1154 qemu_get_sbe32s(f
, &opp
->nb_cpus
);
1156 for (i
= 0; i
< opp
->nb_cpus
; i
++) {
1157 qemu_get_be32s(f
, &opp
->dst
[i
].tfrr
);
1158 qemu_get_be32s(f
, &opp
->dst
[i
].pctp
);
1159 qemu_get_be32s(f
, &opp
->dst
[i
].pcsr
);
1160 openpic_load_IRQ_queue(f
, &opp
->dst
[i
].raised
);
1161 openpic_load_IRQ_queue(f
, &opp
->dst
[i
].servicing
);
1164 for (i
= 0; i
< MAX_TMR
; i
++) {
1165 qemu_get_be32s(f
, &opp
->timers
[i
].ticc
);
1166 qemu_get_be32s(f
, &opp
->timers
[i
].tibc
);
1170 qemu_get_be32s(f
, &opp
->dar
);
1172 for (i
= 0; i
< MAX_DBL
; i
++) {
1173 qemu_get_be32s(f
, &opp
->doorbells
[i
].dmr
);
1178 for (i
= 0; i
< MAX_MAILBOXES
; i
++) {
1179 qemu_get_be32s(f
, &opp
->mailboxes
[i
].mbr
);
1183 return pci_device_load(&opp
->pci_dev
, f
);
1186 static void openpic_irq_raise(openpic_t
*opp
, int n_CPU
, IRQ_src_t
*src
)
1188 qemu_irq_raise(opp
->dst
[n_CPU
].irqs
[OPENPIC_OUTPUT_INT
]);
1191 qemu_irq
*openpic_init (PCIBus
*bus
, MemoryRegion
**pmem
, int nb_cpus
,
1192 qemu_irq
**irqs
, qemu_irq irq_out
)
1198 /* XXX: for now, only one CPU is supported */
1202 opp
= (openpic_t
*)pci_register_device(bus
, "OpenPIC", sizeof(openpic_t
),
1204 pci_conf
= opp
->pci_dev
.config
;
1205 pci_config_set_vendor_id(pci_conf
, PCI_VENDOR_ID_IBM
);
1206 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_IBM_OPENPIC2
);
1207 pci_config_set_class(pci_conf
, PCI_CLASS_SYSTEM_OTHER
); // FIXME?
1208 pci_conf
[0x3d] = 0x00; // no interrupt pin
1210 memory_region_init_io(&opp
->mem
, &openpic_ops
, opp
, "openpic", 0x40000);
1211 #if 0 // Don't implement ISU for now
1212 opp_io_memory
= cpu_register_io_memory(openpic_src_read
,
1213 openpic_src_write
, NULL
1214 DEVICE_NATIVE_ENDIAN
);
1215 cpu_register_physical_memory(isu_base
, 0x20 * (EXT_IRQ
+ 2),
1219 /* Register I/O spaces */
1220 pci_register_bar(&opp
->pci_dev
, 0,
1221 PCI_BASE_ADDRESS_SPACE_MEMORY
, &opp
->mem
);
1223 opp
= g_malloc0(sizeof(openpic_t
));
1224 memory_region_init_io(&opp
->mem
, &openpic_ops
, opp
, "openpic", 0x40000);
1227 // isu_base &= 0xFFFC0000;
1228 opp
->nb_cpus
= nb_cpus
;
1229 opp
->max_irq
= OPENPIC_MAX_IRQ
;
1230 opp
->irq_ipi0
= OPENPIC_IRQ_IPI0
;
1231 opp
->irq_tim0
= OPENPIC_IRQ_TIM0
;
1233 for (i
= 0; i
< OPENPIC_EXT_IRQ
; i
++) {
1234 opp
->src
[i
].type
= IRQ_EXTERNAL
;
1236 for (; i
< OPENPIC_IRQ_TIM0
; i
++) {
1237 opp
->src
[i
].type
= IRQ_SPECIAL
;
1240 m
= OPENPIC_IRQ_IPI0
;
1242 m
= OPENPIC_IRQ_DBL0
;
1244 for (; i
< m
; i
++) {
1245 opp
->src
[i
].type
= IRQ_TIMER
;
1247 for (; i
< OPENPIC_MAX_IRQ
; i
++) {
1248 opp
->src
[i
].type
= IRQ_INTERNAL
;
1250 for (i
= 0; i
< nb_cpus
; i
++)
1251 opp
->dst
[i
].irqs
= irqs
[i
];
1252 opp
->irq_out
= irq_out
;
1254 register_savevm(&opp
->pci_dev
.qdev
, "openpic", 0, 2,
1255 openpic_save
, openpic_load
, opp
);
1256 qemu_register_reset(openpic_reset
, opp
);
1258 opp
->irq_raise
= openpic_irq_raise
;
1259 opp
->reset
= openpic_reset
;
1264 return qemu_allocate_irqs(openpic_set_irq
, opp
, opp
->max_irq
);
1267 static void mpic_irq_raise(openpic_t
*mpp
, int n_CPU
, IRQ_src_t
*src
)
1269 int n_ci
= IDR_CI0
- n_CPU
;
1271 if(test_bit(&src
->ide
, n_ci
)) {
1272 qemu_irq_raise(mpp
->dst
[n_CPU
].irqs
[OPENPIC_OUTPUT_CINT
]);
1275 qemu_irq_raise(mpp
->dst
[n_CPU
].irqs
[OPENPIC_OUTPUT_INT
]);
1279 static void mpic_reset (void *opaque
)
1281 openpic_t
*mpp
= (openpic_t
*)opaque
;
1284 mpp
->glbc
= 0x80000000;
1285 /* Initialise controller registers */
1286 mpp
->frep
= 0x004f0002;
1288 mpp
->pint
= 0x00000000;
1289 mpp
->spve
= 0x0000FFFF;
1290 /* Initialise IRQ sources */
1291 for (i
= 0; i
< mpp
->max_irq
; i
++) {
1292 mpp
->src
[i
].ipvp
= 0x80800000;
1293 mpp
->src
[i
].ide
= 0x00000001;
1295 /* Set IDE for IPIs to 0 so we don't get spurious interrupts */
1296 for (i
= mpp
->irq_ipi0
; i
< (mpp
->irq_ipi0
+ MAX_IPI
); i
++) {
1297 mpp
->src
[i
].ide
= 0;
1299 /* Initialise IRQ destinations */
1300 for (i
= 0; i
< MAX_CPU
; i
++) {
1301 mpp
->dst
[i
].pctp
= 0x0000000F;
1302 mpp
->dst
[i
].tfrr
= 0x00000000;
1303 memset(&mpp
->dst
[i
].raised
, 0, sizeof(IRQ_queue_t
));
1304 mpp
->dst
[i
].raised
.next
= -1;
1305 memset(&mpp
->dst
[i
].servicing
, 0, sizeof(IRQ_queue_t
));
1306 mpp
->dst
[i
].servicing
.next
= -1;
1308 /* Initialise timers */
1309 for (i
= 0; i
< MAX_TMR
; i
++) {
1310 mpp
->timers
[i
].ticc
= 0x00000000;
1311 mpp
->timers
[i
].tibc
= 0x80000000;
1313 /* Go out of RESET state */
1314 mpp
->glbc
= 0x00000000;
1317 static void mpic_timer_write (void *opaque
, target_phys_addr_t addr
, uint32_t val
)
1319 openpic_t
*mpp
= opaque
;
1322 DPRINTF("%s: addr " TARGET_FMT_plx
" <= %08x\n", __func__
, addr
, val
);
1327 idx
= (addr
>> 6) & 0x3;
1328 switch (addr
& 0x30) {
1329 case 0x00: /* gtccr */
1331 case 0x10: /* gtbcr */
1332 if ((mpp
->timers
[idx
].ticc
& 0x80000000) != 0 &&
1333 (val
& 0x80000000) == 0 &&
1334 (mpp
->timers
[idx
].tibc
& 0x80000000) != 0)
1335 mpp
->timers
[idx
].ticc
&= ~0x80000000;
1336 mpp
->timers
[idx
].tibc
= val
;
1338 case 0x20: /* GTIVPR */
1339 write_IRQreg(mpp
, MPIC_TMR_IRQ
+ idx
, IRQ_IPVP
, val
);
1341 case 0x30: /* GTIDR & TFRR */
1342 if ((addr
& 0xF0) == 0xF0)
1343 mpp
->dst
[cpu
].tfrr
= val
;
1345 write_IRQreg(mpp
, MPIC_TMR_IRQ
+ idx
, IRQ_IDE
, val
);
1350 static uint32_t mpic_timer_read (void *opaque
, target_phys_addr_t addr
)
1352 openpic_t
*mpp
= opaque
;
1356 DPRINTF("%s: addr " TARGET_FMT_plx
"\n", __func__
, addr
);
1357 retval
= 0xFFFFFFFF;
1362 idx
= (addr
>> 6) & 0x3;
1363 switch (addr
& 0x30) {
1364 case 0x00: /* gtccr */
1365 retval
= mpp
->timers
[idx
].ticc
;
1367 case 0x10: /* gtbcr */
1368 retval
= mpp
->timers
[idx
].tibc
;
1370 case 0x20: /* TIPV */
1371 retval
= read_IRQreg(mpp
, MPIC_TMR_IRQ
+ idx
, IRQ_IPVP
);
1373 case 0x30: /* TIDR */
1374 if ((addr
&0xF0) == 0XF0)
1375 retval
= mpp
->dst
[cpu
].tfrr
;
1377 retval
= read_IRQreg(mpp
, MPIC_TMR_IRQ
+ idx
, IRQ_IDE
);
1380 DPRINTF("%s: => %08x\n", __func__
, retval
);
1385 static void mpic_src_ext_write (void *opaque
, target_phys_addr_t addr
,
1388 openpic_t
*mpp
= opaque
;
1389 int idx
= MPIC_EXT_IRQ
;
1391 DPRINTF("%s: addr " TARGET_FMT_plx
" <= %08x\n", __func__
, addr
, val
);
1395 addr
-= MPIC_EXT_REG_START
& (OPENPIC_PAGE_SIZE
- 1);
1396 if (addr
< MPIC_EXT_REG_SIZE
) {
1397 idx
+= (addr
& 0xFFF0) >> 5;
1399 /* EXDE / IFEDE / IEEDE */
1400 write_IRQreg(mpp
, idx
, IRQ_IDE
, val
);
1402 /* EXVP / IFEVP / IEEVP */
1403 write_IRQreg(mpp
, idx
, IRQ_IPVP
, val
);
1408 static uint32_t mpic_src_ext_read (void *opaque
, target_phys_addr_t addr
)
1410 openpic_t
*mpp
= opaque
;
1412 int idx
= MPIC_EXT_IRQ
;
1414 DPRINTF("%s: addr " TARGET_FMT_plx
"\n", __func__
, addr
);
1415 retval
= 0xFFFFFFFF;
1419 addr
-= MPIC_EXT_REG_START
& (OPENPIC_PAGE_SIZE
- 1);
1420 if (addr
< MPIC_EXT_REG_SIZE
) {
1421 idx
+= (addr
& 0xFFF0) >> 5;
1423 /* EXDE / IFEDE / IEEDE */
1424 retval
= read_IRQreg(mpp
, idx
, IRQ_IDE
);
1426 /* EXVP / IFEVP / IEEVP */
1427 retval
= read_IRQreg(mpp
, idx
, IRQ_IPVP
);
1429 DPRINTF("%s: => %08x\n", __func__
, retval
);
1435 static void mpic_src_int_write (void *opaque
, target_phys_addr_t addr
,
1438 openpic_t
*mpp
= opaque
;
1439 int idx
= MPIC_INT_IRQ
;
1441 DPRINTF("%s: addr " TARGET_FMT_plx
" <= %08x\n", __func__
, addr
, val
);
1445 addr
-= MPIC_INT_REG_START
& (OPENPIC_PAGE_SIZE
- 1);
1446 if (addr
< MPIC_INT_REG_SIZE
) {
1447 idx
+= (addr
& 0xFFF0) >> 5;
1449 /* EXDE / IFEDE / IEEDE */
1450 write_IRQreg(mpp
, idx
, IRQ_IDE
, val
);
1452 /* EXVP / IFEVP / IEEVP */
1453 write_IRQreg(mpp
, idx
, IRQ_IPVP
, val
);
1458 static uint32_t mpic_src_int_read (void *opaque
, target_phys_addr_t addr
)
1460 openpic_t
*mpp
= opaque
;
1462 int idx
= MPIC_INT_IRQ
;
1464 DPRINTF("%s: addr " TARGET_FMT_plx
"\n", __func__
, addr
);
1465 retval
= 0xFFFFFFFF;
1469 addr
-= MPIC_INT_REG_START
& (OPENPIC_PAGE_SIZE
- 1);
1470 if (addr
< MPIC_INT_REG_SIZE
) {
1471 idx
+= (addr
& 0xFFF0) >> 5;
1473 /* EXDE / IFEDE / IEEDE */
1474 retval
= read_IRQreg(mpp
, idx
, IRQ_IDE
);
1476 /* EXVP / IFEVP / IEEVP */
1477 retval
= read_IRQreg(mpp
, idx
, IRQ_IPVP
);
1479 DPRINTF("%s: => %08x\n", __func__
, retval
);
1485 static void mpic_src_msg_write (void *opaque
, target_phys_addr_t addr
,
1488 openpic_t
*mpp
= opaque
;
1489 int idx
= MPIC_MSG_IRQ
;
1491 DPRINTF("%s: addr " TARGET_FMT_plx
" <= %08x\n", __func__
, addr
, val
);
1495 addr
-= MPIC_MSG_REG_START
& (OPENPIC_PAGE_SIZE
- 1);
1496 if (addr
< MPIC_MSG_REG_SIZE
) {
1497 idx
+= (addr
& 0xFFF0) >> 5;
1499 /* EXDE / IFEDE / IEEDE */
1500 write_IRQreg(mpp
, idx
, IRQ_IDE
, val
);
1502 /* EXVP / IFEVP / IEEVP */
1503 write_IRQreg(mpp
, idx
, IRQ_IPVP
, val
);
1508 static uint32_t mpic_src_msg_read (void *opaque
, target_phys_addr_t addr
)
1510 openpic_t
*mpp
= opaque
;
1512 int idx
= MPIC_MSG_IRQ
;
1514 DPRINTF("%s: addr " TARGET_FMT_plx
"\n", __func__
, addr
);
1515 retval
= 0xFFFFFFFF;
1519 addr
-= MPIC_MSG_REG_START
& (OPENPIC_PAGE_SIZE
- 1);
1520 if (addr
< MPIC_MSG_REG_SIZE
) {
1521 idx
+= (addr
& 0xFFF0) >> 5;
1523 /* EXDE / IFEDE / IEEDE */
1524 retval
= read_IRQreg(mpp
, idx
, IRQ_IDE
);
1526 /* EXVP / IFEVP / IEEVP */
1527 retval
= read_IRQreg(mpp
, idx
, IRQ_IPVP
);
1529 DPRINTF("%s: => %08x\n", __func__
, retval
);
1535 static void mpic_src_msi_write (void *opaque
, target_phys_addr_t addr
,
1538 openpic_t
*mpp
= opaque
;
1539 int idx
= MPIC_MSI_IRQ
;
1541 DPRINTF("%s: addr " TARGET_FMT_plx
" <= %08x\n", __func__
, addr
, val
);
1545 addr
-= MPIC_MSI_REG_START
& (OPENPIC_PAGE_SIZE
- 1);
1546 if (addr
< MPIC_MSI_REG_SIZE
) {
1547 idx
+= (addr
& 0xFFF0) >> 5;
1549 /* EXDE / IFEDE / IEEDE */
1550 write_IRQreg(mpp
, idx
, IRQ_IDE
, val
);
1552 /* EXVP / IFEVP / IEEVP */
1553 write_IRQreg(mpp
, idx
, IRQ_IPVP
, val
);
1557 static uint32_t mpic_src_msi_read (void *opaque
, target_phys_addr_t addr
)
1559 openpic_t
*mpp
= opaque
;
1561 int idx
= MPIC_MSI_IRQ
;
1563 DPRINTF("%s: addr " TARGET_FMT_plx
"\n", __func__
, addr
);
1564 retval
= 0xFFFFFFFF;
1568 addr
-= MPIC_MSI_REG_START
& (OPENPIC_PAGE_SIZE
- 1);
1569 if (addr
< MPIC_MSI_REG_SIZE
) {
1570 idx
+= (addr
& 0xFFF0) >> 5;
1572 /* EXDE / IFEDE / IEEDE */
1573 retval
= read_IRQreg(mpp
, idx
, IRQ_IDE
);
1575 /* EXVP / IFEVP / IEEVP */
1576 retval
= read_IRQreg(mpp
, idx
, IRQ_IPVP
);
1578 DPRINTF("%s: => %08x\n", __func__
, retval
);
1584 static CPUWriteMemoryFunc
* const mpic_glb_write
[] = {
1585 &openpic_buggy_write
,
1586 &openpic_buggy_write
,
1590 static CPUReadMemoryFunc
* const mpic_glb_read
[] = {
1591 &openpic_buggy_read
,
1592 &openpic_buggy_read
,
1596 static CPUWriteMemoryFunc
* const mpic_tmr_write
[] = {
1597 &openpic_buggy_write
,
1598 &openpic_buggy_write
,
1602 static CPUReadMemoryFunc
* const mpic_tmr_read
[] = {
1603 &openpic_buggy_read
,
1604 &openpic_buggy_read
,
1608 static CPUWriteMemoryFunc
* const mpic_cpu_write
[] = {
1609 &openpic_buggy_write
,
1610 &openpic_buggy_write
,
1614 static CPUReadMemoryFunc
* const mpic_cpu_read
[] = {
1615 &openpic_buggy_read
,
1616 &openpic_buggy_read
,
1620 static CPUWriteMemoryFunc
* const mpic_ext_write
[] = {
1621 &openpic_buggy_write
,
1622 &openpic_buggy_write
,
1623 &mpic_src_ext_write
,
1626 static CPUReadMemoryFunc
* const mpic_ext_read
[] = {
1627 &openpic_buggy_read
,
1628 &openpic_buggy_read
,
1632 static CPUWriteMemoryFunc
* const mpic_int_write
[] = {
1633 &openpic_buggy_write
,
1634 &openpic_buggy_write
,
1635 &mpic_src_int_write
,
1638 static CPUReadMemoryFunc
* const mpic_int_read
[] = {
1639 &openpic_buggy_read
,
1640 &openpic_buggy_read
,
1644 static CPUWriteMemoryFunc
* const mpic_msg_write
[] = {
1645 &openpic_buggy_write
,
1646 &openpic_buggy_write
,
1647 &mpic_src_msg_write
,
1650 static CPUReadMemoryFunc
* const mpic_msg_read
[] = {
1651 &openpic_buggy_read
,
1652 &openpic_buggy_read
,
1655 static CPUWriteMemoryFunc
* const mpic_msi_write
[] = {
1656 &openpic_buggy_write
,
1657 &openpic_buggy_write
,
1658 &mpic_src_msi_write
,
1661 static CPUReadMemoryFunc
* const mpic_msi_read
[] = {
1662 &openpic_buggy_read
,
1663 &openpic_buggy_read
,
1667 qemu_irq
*mpic_init (target_phys_addr_t base
, int nb_cpus
,
1668 qemu_irq
**irqs
, qemu_irq irq_out
)
1673 CPUReadMemoryFunc
* const *read
;
1674 CPUWriteMemoryFunc
* const *write
;
1675 target_phys_addr_t start_addr
;
1678 {mpic_glb_read
, mpic_glb_write
, MPIC_GLB_REG_START
, MPIC_GLB_REG_SIZE
},
1679 {mpic_tmr_read
, mpic_tmr_write
, MPIC_TMR_REG_START
, MPIC_TMR_REG_SIZE
},
1680 {mpic_ext_read
, mpic_ext_write
, MPIC_EXT_REG_START
, MPIC_EXT_REG_SIZE
},
1681 {mpic_int_read
, mpic_int_write
, MPIC_INT_REG_START
, MPIC_INT_REG_SIZE
},
1682 {mpic_msg_read
, mpic_msg_write
, MPIC_MSG_REG_START
, MPIC_MSG_REG_SIZE
},
1683 {mpic_msi_read
, mpic_msi_write
, MPIC_MSI_REG_START
, MPIC_MSI_REG_SIZE
},
1684 {mpic_cpu_read
, mpic_cpu_write
, MPIC_CPU_REG_START
, MPIC_CPU_REG_SIZE
},
1687 /* XXX: for now, only one CPU is supported */
1691 mpp
= g_malloc0(sizeof(openpic_t
));
1693 for (i
= 0; i
< sizeof(list
)/sizeof(list
[0]); i
++) {
1696 mem_index
= cpu_register_io_memory(list
[i
].read
, list
[i
].write
, mpp
,
1698 if (mem_index
< 0) {
1701 cpu_register_physical_memory(base
+ list
[i
].start_addr
,
1702 list
[i
].size
, mem_index
);
1705 mpp
->nb_cpus
= nb_cpus
;
1706 mpp
->max_irq
= MPIC_MAX_IRQ
;
1707 mpp
->irq_ipi0
= MPIC_IPI_IRQ
;
1708 mpp
->irq_tim0
= MPIC_TMR_IRQ
;
1710 for (i
= 0; i
< nb_cpus
; i
++)
1711 mpp
->dst
[i
].irqs
= irqs
[i
];
1712 mpp
->irq_out
= irq_out
;
1714 mpp
->irq_raise
= mpic_irq_raise
;
1715 mpp
->reset
= mpic_reset
;
1717 register_savevm(NULL
, "mpic", 0, 2, openpic_save
, openpic_load
, mpp
);
1718 qemu_register_reset(mpic_reset
, mpp
);
1720 return qemu_allocate_irqs(openpic_set_irq
, mpp
, mpp
->max_irq
);