4 * Copyright (c) 2004 Jocelyn Mayer
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 * Based on OpenPic implementations:
28 * - Intel GW80314 I/O companion chip developer's manual
29 * - Motorola MPC8245 & MPC8540 user manuals.
30 * - Motorola MCP750 (aka Raven) programmer manual.
31 * - Motorola Harrier programmer manuel
33 * Serial interrupts, as implemented in Raven chipset are not supported yet.
41 //#define DEBUG_OPENPIC
44 #define DPRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while (0)
46 #define DPRINTF(fmt, ...) do { } while (0)
49 #define USE_MPCxxx /* Intel model is broken, for now */
51 #if defined (USE_INTEL_GW80314)
52 /* Intel GW80314 I/O Companion chip */
62 #define VID (0x00000000)
64 #elif defined(USE_MPCxxx)
73 #define VID 0x03 /* MPIC version ID */
74 #define VENI 0x00000000 /* Vendor ID */
82 #define OPENPIC_MAX_CPU 2
83 #define OPENPIC_MAX_IRQ 64
84 #define OPENPIC_EXT_IRQ 48
85 #define OPENPIC_MAX_TMR MAX_TMR
86 #define OPENPIC_MAX_IPI MAX_IPI
88 /* Interrupt definitions */
89 #define OPENPIC_IRQ_FE (OPENPIC_EXT_IRQ) /* Internal functional IRQ */
90 #define OPENPIC_IRQ_ERR (OPENPIC_EXT_IRQ + 1) /* Error IRQ */
91 #define OPENPIC_IRQ_TIM0 (OPENPIC_EXT_IRQ + 2) /* First timer IRQ */
92 #if OPENPIC_MAX_IPI > 0
93 #define OPENPIC_IRQ_IPI0 (OPENPIC_IRQ_TIM0 + OPENPIC_MAX_TMR) /* First IPI IRQ */
94 #define OPENPIC_IRQ_DBL0 (OPENPIC_IRQ_IPI0 + (OPENPIC_MAX_CPU * OPENPIC_MAX_IPI)) /* First doorbell IRQ */
96 #define OPENPIC_IRQ_DBL0 (OPENPIC_IRQ_TIM0 + OPENPIC_MAX_TMR) /* First doorbell IRQ */
97 #define OPENPIC_IRQ_MBX0 (OPENPIC_IRQ_DBL0 + OPENPIC_MAX_DBL) /* First mailbox IRQ */
101 #define MPIC_MAX_CPU 1
102 #define MPIC_MAX_EXT 12
103 #define MPIC_MAX_INT 64
104 #define MPIC_MAX_MSG 4
105 #define MPIC_MAX_MSI 8
106 #define MPIC_MAX_TMR MAX_TMR
107 #define MPIC_MAX_IPI MAX_IPI
108 #define MPIC_MAX_IRQ (MPIC_MAX_EXT + MPIC_MAX_INT + MPIC_MAX_TMR + MPIC_MAX_MSG + MPIC_MAX_MSI + (MPIC_MAX_IPI * MPIC_MAX_CPU))
110 /* Interrupt definitions */
111 #define MPIC_EXT_IRQ 0
112 #define MPIC_INT_IRQ (MPIC_EXT_IRQ + MPIC_MAX_EXT)
113 #define MPIC_TMR_IRQ (MPIC_INT_IRQ + MPIC_MAX_INT)
114 #define MPIC_MSG_IRQ (MPIC_TMR_IRQ + MPIC_MAX_TMR)
115 #define MPIC_MSI_IRQ (MPIC_MSG_IRQ + MPIC_MAX_MSG)
116 #define MPIC_IPI_IRQ (MPIC_MSI_IRQ + MPIC_MAX_MSI)
118 #define MPIC_GLB_REG_START 0x0
119 #define MPIC_GLB_REG_SIZE 0x10F0
120 #define MPIC_TMR_REG_START 0x10F0
121 #define MPIC_TMR_REG_SIZE 0x220
122 #define MPIC_EXT_REG_START 0x10000
123 #define MPIC_EXT_REG_SIZE 0x180
124 #define MPIC_INT_REG_START 0x10200
125 #define MPIC_INT_REG_SIZE 0x800
126 #define MPIC_MSG_REG_START 0x11600
127 #define MPIC_MSG_REG_SIZE 0x100
128 #define MPIC_MSI_REG_START 0x11C00
129 #define MPIC_MSI_REG_SIZE 0x100
130 #define MPIC_CPU_REG_START 0x20000
131 #define MPIC_CPU_REG_SIZE 0x100 + ((MAX_CPU - 1) * 0x1000)
142 #error "Please select which OpenPic implementation is to be emulated"
145 #define OPENPIC_PAGE_SIZE 4096
147 #define BF_WIDTH(_bits_) \
148 (((_bits_) + (sizeof(uint32_t) * 8) - 1) / (sizeof(uint32_t) * 8))
150 static inline void set_bit (uint32_t *field
, int bit
)
152 field
[bit
>> 5] |= 1 << (bit
& 0x1F);
155 static inline void reset_bit (uint32_t *field
, int bit
)
157 field
[bit
>> 5] &= ~(1 << (bit
& 0x1F));
160 static inline int test_bit (uint32_t *field
, int bit
)
162 return (field
[bit
>> 5] & 1 << (bit
& 0x1F)) != 0;
165 static int get_current_cpu(void)
167 return cpu_single_env
->cpu_index
;
170 static uint32_t openpic_cpu_read_internal(void *opaque
, target_phys_addr_t addr
,
172 static void openpic_cpu_write_internal(void *opaque
, target_phys_addr_t addr
,
173 uint32_t val
, int idx
);
182 typedef struct IRQ_queue_t
{
183 uint32_t queue
[BF_WIDTH(MAX_IRQ
)];
188 typedef struct IRQ_src_t
{
189 uint32_t ipvp
; /* IRQ vector/priority register */
190 uint32_t ide
; /* IRQ destination register */
193 int pending
; /* TRUE if IRQ is pending */
203 #define IPVP_PRIORITY_MASK (0x1F << 16)
204 #define IPVP_PRIORITY(_ipvpr_) ((int)(((_ipvpr_) & IPVP_PRIORITY_MASK) >> 16))
205 #define IPVP_VECTOR_MASK ((1 << VECTOR_BITS) - 1)
206 #define IPVP_VECTOR(_ipvpr_) ((_ipvpr_) & IPVP_VECTOR_MASK)
208 typedef struct IRQ_dst_t
{
210 uint32_t pctp
; /* CPU current task priority */
211 uint32_t pcsr
; /* CPU sensitivity register */
213 IRQ_queue_t servicing
;
217 typedef struct openpic_t
{
220 /* Global registers */
221 uint32_t frep
; /* Feature reporting register */
222 uint32_t glbc
; /* Global configuration register */
223 uint32_t micr
; /* MPIC interrupt configuration register */
224 uint32_t veni
; /* Vendor identification register */
225 uint32_t pint
; /* Processor initialization register */
226 uint32_t spve
; /* Spurious vector register */
227 uint32_t tifr
; /* Timer frequency reporting register */
228 /* Source registers */
229 IRQ_src_t src
[MAX_IRQ
];
230 /* Local registers per output pin */
231 IRQ_dst_t dst
[MAX_CPU
];
233 /* Timer registers */
235 uint32_t ticc
; /* Global timer current count register */
236 uint32_t tibc
; /* Global timer base count register */
239 /* Doorbell registers */
240 uint32_t dar
; /* Doorbell activate register */
242 uint32_t dmr
; /* Doorbell messaging register */
243 } doorbells
[MAX_DBL
];
246 /* Mailbox registers */
248 uint32_t mbr
; /* Mailbox register */
249 } mailboxes
[MAX_MAILBOXES
];
251 /* IRQ out is used when in bypass mode (not implemented) */
256 void (*reset
) (void *);
257 void (*irq_raise
) (struct openpic_t
*, int, IRQ_src_t
*);
260 static inline void IRQ_setbit (IRQ_queue_t
*q
, int n_IRQ
)
262 set_bit(q
->queue
, n_IRQ
);
265 static inline void IRQ_resetbit (IRQ_queue_t
*q
, int n_IRQ
)
267 reset_bit(q
->queue
, n_IRQ
);
270 static inline int IRQ_testbit (IRQ_queue_t
*q
, int n_IRQ
)
272 return test_bit(q
->queue
, n_IRQ
);
275 static void IRQ_check (openpic_t
*opp
, IRQ_queue_t
*q
)
282 for (i
= 0; i
< opp
->max_irq
; i
++) {
283 if (IRQ_testbit(q
, i
)) {
284 DPRINTF("IRQ_check: irq %d set ipvp_pr=%d pr=%d\n",
285 i
, IPVP_PRIORITY(opp
->src
[i
].ipvp
), priority
);
286 if (IPVP_PRIORITY(opp
->src
[i
].ipvp
) > priority
) {
288 priority
= IPVP_PRIORITY(opp
->src
[i
].ipvp
);
293 q
->priority
= priority
;
296 static int IRQ_get_next (openpic_t
*opp
, IRQ_queue_t
*q
)
306 static void IRQ_local_pipe (openpic_t
*opp
, int n_CPU
, int n_IRQ
)
312 dst
= &opp
->dst
[n_CPU
];
313 src
= &opp
->src
[n_IRQ
];
314 priority
= IPVP_PRIORITY(src
->ipvp
);
315 if (priority
<= dst
->pctp
) {
316 /* Too low priority */
317 DPRINTF("%s: IRQ %d has too low priority on CPU %d\n",
318 __func__
, n_IRQ
, n_CPU
);
321 if (IRQ_testbit(&dst
->raised
, n_IRQ
)) {
323 DPRINTF("%s: IRQ %d was missed on CPU %d\n",
324 __func__
, n_IRQ
, n_CPU
);
327 set_bit(&src
->ipvp
, IPVP_ACTIVITY
);
328 IRQ_setbit(&dst
->raised
, n_IRQ
);
329 if (priority
< dst
->raised
.priority
) {
330 /* An higher priority IRQ is already raised */
331 DPRINTF("%s: IRQ %d is hidden by raised IRQ %d on CPU %d\n",
332 __func__
, n_IRQ
, dst
->raised
.next
, n_CPU
);
335 IRQ_get_next(opp
, &dst
->raised
);
336 if (IRQ_get_next(opp
, &dst
->servicing
) != -1 &&
337 priority
<= dst
->servicing
.priority
) {
338 DPRINTF("%s: IRQ %d is hidden by servicing IRQ %d on CPU %d\n",
339 __func__
, n_IRQ
, dst
->servicing
.next
, n_CPU
);
340 /* Already servicing a higher priority IRQ */
343 DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n", n_CPU
, n_IRQ
);
344 opp
->irq_raise(opp
, n_CPU
, src
);
347 /* update pic state because registers for n_IRQ have changed value */
348 static void openpic_update_irq(openpic_t
*opp
, int n_IRQ
)
353 src
= &opp
->src
[n_IRQ
];
357 DPRINTF("%s: IRQ %d is not pending\n", __func__
, n_IRQ
);
360 if (test_bit(&src
->ipvp
, IPVP_MASK
)) {
361 /* Interrupt source is disabled */
362 DPRINTF("%s: IRQ %d is disabled\n", __func__
, n_IRQ
);
365 if (IPVP_PRIORITY(src
->ipvp
) == 0) {
366 /* Priority set to zero */
367 DPRINTF("%s: IRQ %d has 0 priority\n", __func__
, n_IRQ
);
370 if (test_bit(&src
->ipvp
, IPVP_ACTIVITY
)) {
371 /* IRQ already active */
372 DPRINTF("%s: IRQ %d is already active\n", __func__
, n_IRQ
);
375 if (src
->ide
== 0x00000000) {
377 DPRINTF("%s: IRQ %d has no target\n", __func__
, n_IRQ
);
381 if (src
->ide
== (1 << src
->last_cpu
)) {
382 /* Only one CPU is allowed to receive this IRQ */
383 IRQ_local_pipe(opp
, src
->last_cpu
, n_IRQ
);
384 } else if (!test_bit(&src
->ipvp
, IPVP_MODE
)) {
385 /* Directed delivery mode */
386 for (i
= 0; i
< opp
->nb_cpus
; i
++) {
387 if (test_bit(&src
->ide
, i
))
388 IRQ_local_pipe(opp
, i
, n_IRQ
);
391 /* Distributed delivery mode */
392 for (i
= src
->last_cpu
+ 1; i
!= src
->last_cpu
; i
++) {
393 if (i
== opp
->nb_cpus
)
395 if (test_bit(&src
->ide
, i
)) {
396 IRQ_local_pipe(opp
, i
, n_IRQ
);
404 static void openpic_set_irq(void *opaque
, int n_IRQ
, int level
)
406 openpic_t
*opp
= opaque
;
409 src
= &opp
->src
[n_IRQ
];
410 DPRINTF("openpic: set irq %d = %d ipvp=%08x\n",
411 n_IRQ
, level
, src
->ipvp
);
412 if (test_bit(&src
->ipvp
, IPVP_SENSE
)) {
413 /* level-sensitive irq */
414 src
->pending
= level
;
416 reset_bit(&src
->ipvp
, IPVP_ACTIVITY
);
418 /* edge-sensitive irq */
422 openpic_update_irq(opp
, n_IRQ
);
425 static void openpic_reset (void *opaque
)
427 openpic_t
*opp
= (openpic_t
*)opaque
;
430 opp
->glbc
= 0x80000000;
431 /* Initialise controller registers */
432 opp
->frep
= ((OPENPIC_EXT_IRQ
- 1) << 16) | ((MAX_CPU
- 1) << 8) | VID
;
434 opp
->pint
= 0x00000000;
435 opp
->spve
= 0x000000FF;
436 opp
->tifr
= 0x003F7A00;
438 opp
->micr
= 0x00000000;
439 /* Initialise IRQ sources */
440 for (i
= 0; i
< opp
->max_irq
; i
++) {
441 opp
->src
[i
].ipvp
= 0xA0000000;
442 opp
->src
[i
].ide
= 0x00000000;
444 /* Initialise IRQ destinations */
445 for (i
= 0; i
< MAX_CPU
; i
++) {
446 opp
->dst
[i
].pctp
= 0x0000000F;
447 opp
->dst
[i
].pcsr
= 0x00000000;
448 memset(&opp
->dst
[i
].raised
, 0, sizeof(IRQ_queue_t
));
449 opp
->dst
[i
].raised
.next
= -1;
450 memset(&opp
->dst
[i
].servicing
, 0, sizeof(IRQ_queue_t
));
451 opp
->dst
[i
].servicing
.next
= -1;
453 /* Initialise timers */
454 for (i
= 0; i
< MAX_TMR
; i
++) {
455 opp
->timers
[i
].ticc
= 0x00000000;
456 opp
->timers
[i
].tibc
= 0x80000000;
458 /* Initialise doorbells */
460 opp
->dar
= 0x00000000;
461 for (i
= 0; i
< MAX_DBL
; i
++) {
462 opp
->doorbells
[i
].dmr
= 0x00000000;
465 /* Initialise mailboxes */
467 for (i
= 0; i
< MAX_MBX
; i
++) { /* ? */
468 opp
->mailboxes
[i
].mbr
= 0x00000000;
471 /* Go out of RESET state */
472 opp
->glbc
= 0x00000000;
475 static inline uint32_t read_IRQreg_ide(openpic_t
*opp
, int n_IRQ
)
477 return opp
->src
[n_IRQ
].ide
;
480 static inline uint32_t read_IRQreg_ipvp(openpic_t
*opp
, int n_IRQ
)
482 return opp
->src
[n_IRQ
].ipvp
;
485 static inline void write_IRQreg (openpic_t
*opp
, int n_IRQ
,
486 uint32_t reg
, uint32_t val
)
492 /* NOTE: not fully accurate for special IRQs, but simple and
494 /* ACTIVITY bit is read-only */
495 opp
->src
[n_IRQ
].ipvp
=
496 (opp
->src
[n_IRQ
].ipvp
& 0x40000000) |
498 openpic_update_irq(opp
, n_IRQ
);
499 DPRINTF("Set IPVP %d to 0x%08x -> 0x%08x\n",
500 n_IRQ
, val
, opp
->src
[n_IRQ
].ipvp
);
503 tmp
= val
& 0xC0000000;
504 tmp
|= val
& ((1ULL << MAX_CPU
) - 1);
505 opp
->src
[n_IRQ
].ide
= tmp
;
506 DPRINTF("Set IDE %d to 0x%08x\n", n_IRQ
, opp
->src
[n_IRQ
].ide
);
511 #if 0 // Code provision for Intel model
513 static uint32_t read_doorbell_register (openpic_t
*opp
,
514 int n_dbl
, uint32_t offset
)
519 case DBL_IPVP_OFFSET
:
520 retval
= read_IRQreg_ipvp(opp
, IRQ_DBL0
+ n_dbl
);
523 retval
= read_IRQreg_ide(opp
, IRQ_DBL0
+ n_dbl
);
526 retval
= opp
->doorbells
[n_dbl
].dmr
;
533 static void write_doorbell_register (penpic_t
*opp
, int n_dbl
,
534 uint32_t offset
, uint32_t value
)
537 case DBL_IVPR_OFFSET
:
538 write_IRQreg(opp
, IRQ_DBL0
+ n_dbl
, IRQ_IPVP
, value
);
541 write_IRQreg(opp
, IRQ_DBL0
+ n_dbl
, IRQ_IDE
, value
);
544 opp
->doorbells
[n_dbl
].dmr
= value
;
551 static uint32_t read_mailbox_register (openpic_t
*opp
,
552 int n_mbx
, uint32_t offset
)
558 retval
= opp
->mailboxes
[n_mbx
].mbr
;
560 case MBX_IVPR_OFFSET
:
561 retval
= read_IRQreg_ipvp(opp
, IRQ_MBX0
+ n_mbx
);
564 retval
= read_IRQreg_ide(opp
, IRQ_MBX0
+ n_mbx
);
571 static void write_mailbox_register (openpic_t
*opp
, int n_mbx
,
572 uint32_t address
, uint32_t value
)
576 opp
->mailboxes
[n_mbx
].mbr
= value
;
578 case MBX_IVPR_OFFSET
:
579 write_IRQreg(opp
, IRQ_MBX0
+ n_mbx
, IRQ_IPVP
, value
);
582 write_IRQreg(opp
, IRQ_MBX0
+ n_mbx
, IRQ_IDE
, value
);
587 #endif /* 0 : Code provision for Intel model */
589 static void openpic_gbl_write (void *opaque
, target_phys_addr_t addr
, uint32_t val
)
591 openpic_t
*opp
= opaque
;
595 DPRINTF("%s: addr " TARGET_FMT_plx
" <= %08x\n", __func__
, addr
, val
);
607 openpic_cpu_write_internal(opp
, addr
, val
, get_current_cpu());
609 case 0x1000: /* FREP */
611 case 0x1020: /* GLBC */
612 if (val
& 0x80000000 && opp
->reset
)
614 opp
->glbc
= val
& ~0x80000000;
616 case 0x1080: /* VENI */
618 case 0x1090: /* PINT */
619 for (idx
= 0; idx
< opp
->nb_cpus
; idx
++) {
620 if ((val
& (1 << idx
)) && !(opp
->pint
& (1 << idx
))) {
621 DPRINTF("Raise OpenPIC RESET output for CPU %d\n", idx
);
622 dst
= &opp
->dst
[idx
];
623 qemu_irq_raise(dst
->irqs
[OPENPIC_OUTPUT_RESET
]);
624 } else if (!(val
& (1 << idx
)) && (opp
->pint
& (1 << idx
))) {
625 DPRINTF("Lower OpenPIC RESET output for CPU %d\n", idx
);
626 dst
= &opp
->dst
[idx
];
627 qemu_irq_lower(dst
->irqs
[OPENPIC_OUTPUT_RESET
]);
632 case 0x10A0: /* IPI_IPVP */
638 idx
= (addr
- 0x10A0) >> 4;
639 write_IRQreg(opp
, opp
->irq_ipi0
+ idx
, IRQ_IPVP
, val
);
642 case 0x10E0: /* SPVE */
643 opp
->spve
= val
& 0x000000FF;
645 case 0x10F0: /* TIFR */
653 static uint32_t openpic_gbl_read (void *opaque
, target_phys_addr_t addr
)
655 openpic_t
*opp
= opaque
;
658 DPRINTF("%s: addr " TARGET_FMT_plx
"\n", __func__
, addr
);
663 case 0x1000: /* FREP */
666 case 0x1020: /* GLBC */
669 case 0x1080: /* VENI */
672 case 0x1090: /* PINT */
683 retval
= openpic_cpu_read_internal(opp
, addr
, get_current_cpu());
685 case 0x10A0: /* IPI_IPVP */
691 idx
= (addr
- 0x10A0) >> 4;
692 retval
= read_IRQreg_ipvp(opp
, opp
->irq_ipi0
+ idx
);
695 case 0x10E0: /* SPVE */
698 case 0x10F0: /* TIFR */
704 DPRINTF("%s: => %08x\n", __func__
, retval
);
709 static void openpic_timer_write (void *opaque
, uint32_t addr
, uint32_t val
)
711 openpic_t
*opp
= opaque
;
714 DPRINTF("%s: addr %08x <= %08x\n", __func__
, addr
, val
);
719 idx
= (addr
& 0xFFF0) >> 6;
722 case 0x00: /* TICC */
724 case 0x10: /* TIBC */
725 if ((opp
->timers
[idx
].ticc
& 0x80000000) != 0 &&
726 (val
& 0x80000000) == 0 &&
727 (opp
->timers
[idx
].tibc
& 0x80000000) != 0)
728 opp
->timers
[idx
].ticc
&= ~0x80000000;
729 opp
->timers
[idx
].tibc
= val
;
731 case 0x20: /* TIVP */
732 write_IRQreg(opp
, opp
->irq_tim0
+ idx
, IRQ_IPVP
, val
);
734 case 0x30: /* TIDE */
735 write_IRQreg(opp
, opp
->irq_tim0
+ idx
, IRQ_IDE
, val
);
740 static uint32_t openpic_timer_read (void *opaque
, uint32_t addr
)
742 openpic_t
*opp
= opaque
;
746 DPRINTF("%s: addr %08x\n", __func__
, addr
);
752 idx
= (addr
& 0xFFF0) >> 6;
755 case 0x00: /* TICC */
756 retval
= opp
->timers
[idx
].ticc
;
758 case 0x10: /* TIBC */
759 retval
= opp
->timers
[idx
].tibc
;
761 case 0x20: /* TIPV */
762 retval
= read_IRQreg_ipvp(opp
, opp
->irq_tim0
+ idx
);
764 case 0x30: /* TIDE */
765 retval
= read_IRQreg_ide(opp
, opp
->irq_tim0
+ idx
);
768 DPRINTF("%s: => %08x\n", __func__
, retval
);
773 static void openpic_src_write (void *opaque
, uint32_t addr
, uint32_t val
)
775 openpic_t
*opp
= opaque
;
778 DPRINTF("%s: addr %08x <= %08x\n", __func__
, addr
, val
);
781 addr
= addr
& 0xFFF0;
784 /* EXDE / IFEDE / IEEDE */
785 write_IRQreg(opp
, idx
, IRQ_IDE
, val
);
787 /* EXVP / IFEVP / IEEVP */
788 write_IRQreg(opp
, idx
, IRQ_IPVP
, val
);
792 static uint32_t openpic_src_read (void *opaque
, uint32_t addr
)
794 openpic_t
*opp
= opaque
;
798 DPRINTF("%s: addr %08x\n", __func__
, addr
);
802 addr
= addr
& 0xFFF0;
805 /* EXDE / IFEDE / IEEDE */
806 retval
= read_IRQreg_ide(opp
, idx
);
808 /* EXVP / IFEVP / IEEVP */
809 retval
= read_IRQreg_ipvp(opp
, idx
);
811 DPRINTF("%s: => %08x\n", __func__
, retval
);
816 static void openpic_cpu_write_internal(void *opaque
, target_phys_addr_t addr
,
817 uint32_t val
, int idx
)
819 openpic_t
*opp
= opaque
;
824 DPRINTF("%s: cpu %d addr " TARGET_FMT_plx
" <= %08x\n", __func__
, idx
,
828 dst
= &opp
->dst
[idx
];
832 case 0x40: /* IPIDR */
836 idx
= (addr
- 0x40) >> 4;
837 /* we use IDE as mask which CPUs to deliver the IPI to still. */
838 write_IRQreg(opp
, opp
->irq_ipi0
+ idx
, IRQ_IDE
,
839 opp
->src
[opp
->irq_ipi0
+ idx
].ide
| val
);
840 openpic_set_irq(opp
, opp
->irq_ipi0
+ idx
, 1);
841 openpic_set_irq(opp
, opp
->irq_ipi0
+ idx
, 0);
844 case 0x80: /* PCTP */
845 dst
->pctp
= val
& 0x0000000F;
847 case 0x90: /* WHOAMI */
848 /* Read-only register */
850 case 0xA0: /* PIAC */
851 /* Read-only register */
853 case 0xB0: /* PEOI */
855 s_IRQ
= IRQ_get_next(opp
, &dst
->servicing
);
856 IRQ_resetbit(&dst
->servicing
, s_IRQ
);
857 dst
->servicing
.next
= -1;
858 /* Set up next servicing IRQ */
859 s_IRQ
= IRQ_get_next(opp
, &dst
->servicing
);
860 /* Check queued interrupts. */
861 n_IRQ
= IRQ_get_next(opp
, &dst
->raised
);
862 src
= &opp
->src
[n_IRQ
];
865 IPVP_PRIORITY(src
->ipvp
) > dst
->servicing
.priority
)) {
866 DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n",
868 opp
->irq_raise(opp
, idx
, src
);
876 static void openpic_cpu_write(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
878 openpic_cpu_write_internal(opaque
, addr
, val
, (addr
& 0x1f000) >> 12);
881 static uint32_t openpic_cpu_read_internal(void *opaque
, target_phys_addr_t addr
,
884 openpic_t
*opp
= opaque
;
890 DPRINTF("%s: cpu %d addr " TARGET_FMT_plx
"\n", __func__
, idx
, addr
);
894 dst
= &opp
->dst
[idx
];
897 case 0x80: /* PCTP */
900 case 0x90: /* WHOAMI */
903 case 0xA0: /* PIAC */
904 DPRINTF("Lower OpenPIC INT output\n");
905 qemu_irq_lower(dst
->irqs
[OPENPIC_OUTPUT_INT
]);
906 n_IRQ
= IRQ_get_next(opp
, &dst
->raised
);
907 DPRINTF("PIAC: irq=%d\n", n_IRQ
);
909 /* No more interrupt pending */
910 retval
= IPVP_VECTOR(opp
->spve
);
912 src
= &opp
->src
[n_IRQ
];
913 if (!test_bit(&src
->ipvp
, IPVP_ACTIVITY
) ||
914 !(IPVP_PRIORITY(src
->ipvp
) > dst
->pctp
)) {
915 /* - Spurious level-sensitive IRQ
916 * - Priorities has been changed
917 * and the pending IRQ isn't allowed anymore
919 reset_bit(&src
->ipvp
, IPVP_ACTIVITY
);
920 retval
= IPVP_VECTOR(opp
->spve
);
922 /* IRQ enter servicing state */
923 IRQ_setbit(&dst
->servicing
, n_IRQ
);
924 retval
= IPVP_VECTOR(src
->ipvp
);
926 IRQ_resetbit(&dst
->raised
, n_IRQ
);
927 dst
->raised
.next
= -1;
928 if (!test_bit(&src
->ipvp
, IPVP_SENSE
)) {
929 /* edge-sensitive IRQ */
930 reset_bit(&src
->ipvp
, IPVP_ACTIVITY
);
934 if ((n_IRQ
>= opp
->irq_ipi0
) && (n_IRQ
< (opp
->irq_ipi0
+ MAX_IPI
))) {
935 src
->ide
&= ~(1 << idx
);
936 if (src
->ide
&& !test_bit(&src
->ipvp
, IPVP_SENSE
)) {
937 /* trigger on CPUs that didn't know about it yet */
938 openpic_set_irq(opp
, n_IRQ
, 1);
939 openpic_set_irq(opp
, n_IRQ
, 0);
940 /* if all CPUs knew about it, set active bit again */
941 set_bit(&src
->ipvp
, IPVP_ACTIVITY
);
946 case 0xB0: /* PEOI */
952 DPRINTF("%s: => %08x\n", __func__
, retval
);
957 static uint32_t openpic_cpu_read(void *opaque
, target_phys_addr_t addr
)
959 return openpic_cpu_read_internal(opaque
, addr
, (addr
& 0x1f000) >> 12);
962 static void openpic_buggy_write (void *opaque
,
963 target_phys_addr_t addr
, uint32_t val
)
965 printf("Invalid OPENPIC write access !\n");
968 static uint32_t openpic_buggy_read (void *opaque
, target_phys_addr_t addr
)
970 printf("Invalid OPENPIC read access !\n");
975 static void openpic_writel (void *opaque
,
976 target_phys_addr_t addr
, uint32_t val
)
978 openpic_t
*opp
= opaque
;
981 DPRINTF("%s: offset %08x val: %08x\n", __func__
, (int)addr
, val
);
983 /* Global registers */
984 openpic_gbl_write(opp
, addr
, val
);
985 } else if (addr
< 0x10000) {
986 /* Timers registers */
987 openpic_timer_write(opp
, addr
, val
);
988 } else if (addr
< 0x20000) {
989 /* Source registers */
990 openpic_src_write(opp
, addr
, val
);
993 openpic_cpu_write(opp
, addr
, val
);
997 static uint32_t openpic_readl (void *opaque
,target_phys_addr_t addr
)
999 openpic_t
*opp
= opaque
;
1003 DPRINTF("%s: offset %08x\n", __func__
, (int)addr
);
1004 if (addr
< 0x1100) {
1005 /* Global registers */
1006 retval
= openpic_gbl_read(opp
, addr
);
1007 } else if (addr
< 0x10000) {
1008 /* Timers registers */
1009 retval
= openpic_timer_read(opp
, addr
);
1010 } else if (addr
< 0x20000) {
1011 /* Source registers */
1012 retval
= openpic_src_read(opp
, addr
);
1015 retval
= openpic_cpu_read(opp
, addr
);
1021 static uint64_t openpic_read(void *opaque
, target_phys_addr_t addr
,
1024 openpic_t
*opp
= opaque
;
1027 case 4: return openpic_readl(opp
, addr
);
1028 default: return openpic_buggy_read(opp
, addr
);
1032 static void openpic_write(void *opaque
, target_phys_addr_t addr
,
1033 uint64_t data
, unsigned size
)
1035 openpic_t
*opp
= opaque
;
1038 case 4: return openpic_writel(opp
, addr
, data
);
1039 default: return openpic_buggy_write(opp
, addr
, data
);
1043 static const MemoryRegionOps openpic_ops
= {
1044 .read
= openpic_read
,
1045 .write
= openpic_write
,
1046 .endianness
= DEVICE_LITTLE_ENDIAN
,
1049 static void openpic_save_IRQ_queue(QEMUFile
* f
, IRQ_queue_t
*q
)
1053 for (i
= 0; i
< BF_WIDTH(MAX_IRQ
); i
++)
1054 qemu_put_be32s(f
, &q
->queue
[i
]);
1056 qemu_put_sbe32s(f
, &q
->next
);
1057 qemu_put_sbe32s(f
, &q
->priority
);
1060 static void openpic_save(QEMUFile
* f
, void *opaque
)
1062 openpic_t
*opp
= (openpic_t
*)opaque
;
1065 qemu_put_be32s(f
, &opp
->frep
);
1066 qemu_put_be32s(f
, &opp
->glbc
);
1067 qemu_put_be32s(f
, &opp
->micr
);
1068 qemu_put_be32s(f
, &opp
->veni
);
1069 qemu_put_be32s(f
, &opp
->pint
);
1070 qemu_put_be32s(f
, &opp
->spve
);
1071 qemu_put_be32s(f
, &opp
->tifr
);
1073 for (i
= 0; i
< opp
->max_irq
; i
++) {
1074 qemu_put_be32s(f
, &opp
->src
[i
].ipvp
);
1075 qemu_put_be32s(f
, &opp
->src
[i
].ide
);
1076 qemu_put_sbe32s(f
, &opp
->src
[i
].type
);
1077 qemu_put_sbe32s(f
, &opp
->src
[i
].last_cpu
);
1078 qemu_put_sbe32s(f
, &opp
->src
[i
].pending
);
1081 qemu_put_sbe32s(f
, &opp
->nb_cpus
);
1083 for (i
= 0; i
< opp
->nb_cpus
; i
++) {
1084 qemu_put_be32s(f
, &opp
->dst
[i
].tfrr
);
1085 qemu_put_be32s(f
, &opp
->dst
[i
].pctp
);
1086 qemu_put_be32s(f
, &opp
->dst
[i
].pcsr
);
1087 openpic_save_IRQ_queue(f
, &opp
->dst
[i
].raised
);
1088 openpic_save_IRQ_queue(f
, &opp
->dst
[i
].servicing
);
1091 for (i
= 0; i
< MAX_TMR
; i
++) {
1092 qemu_put_be32s(f
, &opp
->timers
[i
].ticc
);
1093 qemu_put_be32s(f
, &opp
->timers
[i
].tibc
);
1097 qemu_put_be32s(f
, &opp
->dar
);
1099 for (i
= 0; i
< MAX_DBL
; i
++) {
1100 qemu_put_be32s(f
, &opp
->doorbells
[i
].dmr
);
1105 for (i
= 0; i
< MAX_MAILBOXES
; i
++) {
1106 qemu_put_be32s(f
, &opp
->mailboxes
[i
].mbr
);
1110 pci_device_save(&opp
->pci_dev
, f
);
1113 static void openpic_load_IRQ_queue(QEMUFile
* f
, IRQ_queue_t
*q
)
1117 for (i
= 0; i
< BF_WIDTH(MAX_IRQ
); i
++)
1118 qemu_get_be32s(f
, &q
->queue
[i
]);
1120 qemu_get_sbe32s(f
, &q
->next
);
1121 qemu_get_sbe32s(f
, &q
->priority
);
1124 static int openpic_load(QEMUFile
* f
, void *opaque
, int version_id
)
1126 openpic_t
*opp
= (openpic_t
*)opaque
;
1129 if (version_id
!= 1)
1132 qemu_get_be32s(f
, &opp
->frep
);
1133 qemu_get_be32s(f
, &opp
->glbc
);
1134 qemu_get_be32s(f
, &opp
->micr
);
1135 qemu_get_be32s(f
, &opp
->veni
);
1136 qemu_get_be32s(f
, &opp
->pint
);
1137 qemu_get_be32s(f
, &opp
->spve
);
1138 qemu_get_be32s(f
, &opp
->tifr
);
1140 for (i
= 0; i
< opp
->max_irq
; i
++) {
1141 qemu_get_be32s(f
, &opp
->src
[i
].ipvp
);
1142 qemu_get_be32s(f
, &opp
->src
[i
].ide
);
1143 qemu_get_sbe32s(f
, &opp
->src
[i
].type
);
1144 qemu_get_sbe32s(f
, &opp
->src
[i
].last_cpu
);
1145 qemu_get_sbe32s(f
, &opp
->src
[i
].pending
);
1148 qemu_get_sbe32s(f
, &opp
->nb_cpus
);
1150 for (i
= 0; i
< opp
->nb_cpus
; i
++) {
1151 qemu_get_be32s(f
, &opp
->dst
[i
].tfrr
);
1152 qemu_get_be32s(f
, &opp
->dst
[i
].pctp
);
1153 qemu_get_be32s(f
, &opp
->dst
[i
].pcsr
);
1154 openpic_load_IRQ_queue(f
, &opp
->dst
[i
].raised
);
1155 openpic_load_IRQ_queue(f
, &opp
->dst
[i
].servicing
);
1158 for (i
= 0; i
< MAX_TMR
; i
++) {
1159 qemu_get_be32s(f
, &opp
->timers
[i
].ticc
);
1160 qemu_get_be32s(f
, &opp
->timers
[i
].tibc
);
1164 qemu_get_be32s(f
, &opp
->dar
);
1166 for (i
= 0; i
< MAX_DBL
; i
++) {
1167 qemu_get_be32s(f
, &opp
->doorbells
[i
].dmr
);
1172 for (i
= 0; i
< MAX_MAILBOXES
; i
++) {
1173 qemu_get_be32s(f
, &opp
->mailboxes
[i
].mbr
);
1177 return pci_device_load(&opp
->pci_dev
, f
);
1180 static void openpic_irq_raise(openpic_t
*opp
, int n_CPU
, IRQ_src_t
*src
)
1182 qemu_irq_raise(opp
->dst
[n_CPU
].irqs
[OPENPIC_OUTPUT_INT
]);
1185 qemu_irq
*openpic_init (PCIBus
*bus
, MemoryRegion
**pmem
, int nb_cpus
,
1186 qemu_irq
**irqs
, qemu_irq irq_out
)
1192 /* XXX: for now, only one CPU is supported */
1196 opp
= (openpic_t
*)pci_register_device(bus
, "OpenPIC", sizeof(openpic_t
),
1198 pci_conf
= opp
->pci_dev
.config
;
1199 pci_config_set_vendor_id(pci_conf
, PCI_VENDOR_ID_IBM
);
1200 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_IBM_OPENPIC2
);
1201 pci_config_set_class(pci_conf
, PCI_CLASS_SYSTEM_OTHER
); // FIXME?
1202 pci_conf
[0x3d] = 0x00; // no interrupt pin
1204 memory_region_init_io(&opp
->mem
, &openpic_ops
, opp
, "openpic", 0x40000);
1205 #if 0 // Don't implement ISU for now
1206 opp_io_memory
= cpu_register_io_memory(openpic_src_read
,
1207 openpic_src_write
, NULL
1208 DEVICE_NATIVE_ENDIAN
);
1209 cpu_register_physical_memory(isu_base
, 0x20 * (EXT_IRQ
+ 2),
1213 /* Register I/O spaces */
1214 pci_register_bar(&opp
->pci_dev
, 0,
1215 PCI_BASE_ADDRESS_SPACE_MEMORY
, &opp
->mem
);
1217 opp
= g_malloc0(sizeof(openpic_t
));
1218 memory_region_init_io(&opp
->mem
, &openpic_ops
, opp
, "openpic", 0x40000);
1221 // isu_base &= 0xFFFC0000;
1222 opp
->nb_cpus
= nb_cpus
;
1223 opp
->max_irq
= OPENPIC_MAX_IRQ
;
1224 opp
->irq_ipi0
= OPENPIC_IRQ_IPI0
;
1225 opp
->irq_tim0
= OPENPIC_IRQ_TIM0
;
1227 for (i
= 0; i
< OPENPIC_EXT_IRQ
; i
++) {
1228 opp
->src
[i
].type
= IRQ_EXTERNAL
;
1230 for (; i
< OPENPIC_IRQ_TIM0
; i
++) {
1231 opp
->src
[i
].type
= IRQ_SPECIAL
;
1234 m
= OPENPIC_IRQ_IPI0
;
1236 m
= OPENPIC_IRQ_DBL0
;
1238 for (; i
< m
; i
++) {
1239 opp
->src
[i
].type
= IRQ_TIMER
;
1241 for (; i
< OPENPIC_MAX_IRQ
; i
++) {
1242 opp
->src
[i
].type
= IRQ_INTERNAL
;
1244 for (i
= 0; i
< nb_cpus
; i
++)
1245 opp
->dst
[i
].irqs
= irqs
[i
];
1246 opp
->irq_out
= irq_out
;
1248 register_savevm(&opp
->pci_dev
.qdev
, "openpic", 0, 2,
1249 openpic_save
, openpic_load
, opp
);
1250 qemu_register_reset(openpic_reset
, opp
);
1252 opp
->irq_raise
= openpic_irq_raise
;
1253 opp
->reset
= openpic_reset
;
1258 return qemu_allocate_irqs(openpic_set_irq
, opp
, opp
->max_irq
);
1261 static void mpic_irq_raise(openpic_t
*mpp
, int n_CPU
, IRQ_src_t
*src
)
1263 int n_ci
= IDR_CI0
- n_CPU
;
1265 if(test_bit(&src
->ide
, n_ci
)) {
1266 qemu_irq_raise(mpp
->dst
[n_CPU
].irqs
[OPENPIC_OUTPUT_CINT
]);
1269 qemu_irq_raise(mpp
->dst
[n_CPU
].irqs
[OPENPIC_OUTPUT_INT
]);
1273 static void mpic_reset (void *opaque
)
1275 openpic_t
*mpp
= (openpic_t
*)opaque
;
1278 mpp
->glbc
= 0x80000000;
1279 /* Initialise controller registers */
1280 mpp
->frep
= 0x004f0002 | ((mpp
->nb_cpus
- 1) << 8);
1282 mpp
->pint
= 0x00000000;
1283 mpp
->spve
= 0x0000FFFF;
1284 /* Initialise IRQ sources */
1285 for (i
= 0; i
< mpp
->max_irq
; i
++) {
1286 mpp
->src
[i
].ipvp
= 0x80800000;
1287 mpp
->src
[i
].ide
= 0x00000001;
1289 /* Set IDE for IPIs to 0 so we don't get spurious interrupts */
1290 for (i
= mpp
->irq_ipi0
; i
< (mpp
->irq_ipi0
+ MAX_IPI
); i
++) {
1291 mpp
->src
[i
].ide
= 0;
1293 /* Initialise IRQ destinations */
1294 for (i
= 0; i
< MAX_CPU
; i
++) {
1295 mpp
->dst
[i
].pctp
= 0x0000000F;
1296 mpp
->dst
[i
].tfrr
= 0x00000000;
1297 memset(&mpp
->dst
[i
].raised
, 0, sizeof(IRQ_queue_t
));
1298 mpp
->dst
[i
].raised
.next
= -1;
1299 memset(&mpp
->dst
[i
].servicing
, 0, sizeof(IRQ_queue_t
));
1300 mpp
->dst
[i
].servicing
.next
= -1;
1302 /* Initialise timers */
1303 for (i
= 0; i
< MAX_TMR
; i
++) {
1304 mpp
->timers
[i
].ticc
= 0x00000000;
1305 mpp
->timers
[i
].tibc
= 0x80000000;
1307 /* Go out of RESET state */
1308 mpp
->glbc
= 0x00000000;
1311 static void mpic_timer_write (void *opaque
, target_phys_addr_t addr
, uint32_t val
)
1313 openpic_t
*mpp
= opaque
;
1316 DPRINTF("%s: addr " TARGET_FMT_plx
" <= %08x\n", __func__
, addr
, val
);
1321 idx
= (addr
>> 6) & 0x3;
1322 switch (addr
& 0x30) {
1323 case 0x00: /* gtccr */
1325 case 0x10: /* gtbcr */
1326 if ((mpp
->timers
[idx
].ticc
& 0x80000000) != 0 &&
1327 (val
& 0x80000000) == 0 &&
1328 (mpp
->timers
[idx
].tibc
& 0x80000000) != 0)
1329 mpp
->timers
[idx
].ticc
&= ~0x80000000;
1330 mpp
->timers
[idx
].tibc
= val
;
1332 case 0x20: /* GTIVPR */
1333 write_IRQreg(mpp
, MPIC_TMR_IRQ
+ idx
, IRQ_IPVP
, val
);
1335 case 0x30: /* GTIDR & TFRR */
1336 if ((addr
& 0xF0) == 0xF0)
1337 mpp
->dst
[cpu
].tfrr
= val
;
1339 write_IRQreg(mpp
, MPIC_TMR_IRQ
+ idx
, IRQ_IDE
, val
);
1344 static uint32_t mpic_timer_read (void *opaque
, target_phys_addr_t addr
)
1346 openpic_t
*mpp
= opaque
;
1350 DPRINTF("%s: addr " TARGET_FMT_plx
"\n", __func__
, addr
);
1351 retval
= 0xFFFFFFFF;
1356 idx
= (addr
>> 6) & 0x3;
1357 switch (addr
& 0x30) {
1358 case 0x00: /* gtccr */
1359 retval
= mpp
->timers
[idx
].ticc
;
1361 case 0x10: /* gtbcr */
1362 retval
= mpp
->timers
[idx
].tibc
;
1364 case 0x20: /* TIPV */
1365 retval
= read_IRQreg_ipvp(mpp
, MPIC_TMR_IRQ
+ idx
);
1367 case 0x30: /* TIDR */
1368 if ((addr
&0xF0) == 0XF0)
1369 retval
= mpp
->dst
[cpu
].tfrr
;
1371 retval
= read_IRQreg_ide(mpp
, MPIC_TMR_IRQ
+ idx
);
1374 DPRINTF("%s: => %08x\n", __func__
, retval
);
1379 static void mpic_src_ext_write (void *opaque
, target_phys_addr_t addr
,
1382 openpic_t
*mpp
= opaque
;
1383 int idx
= MPIC_EXT_IRQ
;
1385 DPRINTF("%s: addr " TARGET_FMT_plx
" <= %08x\n", __func__
, addr
, val
);
1389 addr
-= MPIC_EXT_REG_START
& (OPENPIC_PAGE_SIZE
- 1);
1390 if (addr
< MPIC_EXT_REG_SIZE
) {
1391 idx
+= (addr
& 0xFFF0) >> 5;
1393 /* EXDE / IFEDE / IEEDE */
1394 write_IRQreg(mpp
, idx
, IRQ_IDE
, val
);
1396 /* EXVP / IFEVP / IEEVP */
1397 write_IRQreg(mpp
, idx
, IRQ_IPVP
, val
);
1402 static uint32_t mpic_src_ext_read (void *opaque
, target_phys_addr_t addr
)
1404 openpic_t
*mpp
= opaque
;
1406 int idx
= MPIC_EXT_IRQ
;
1408 DPRINTF("%s: addr " TARGET_FMT_plx
"\n", __func__
, addr
);
1409 retval
= 0xFFFFFFFF;
1413 addr
-= MPIC_EXT_REG_START
& (OPENPIC_PAGE_SIZE
- 1);
1414 if (addr
< MPIC_EXT_REG_SIZE
) {
1415 idx
+= (addr
& 0xFFF0) >> 5;
1417 /* EXDE / IFEDE / IEEDE */
1418 retval
= read_IRQreg_ide(mpp
, idx
);
1420 /* EXVP / IFEVP / IEEVP */
1421 retval
= read_IRQreg_ipvp(mpp
, idx
);
1423 DPRINTF("%s: => %08x\n", __func__
, retval
);
1429 static void mpic_src_int_write (void *opaque
, target_phys_addr_t addr
,
1432 openpic_t
*mpp
= opaque
;
1433 int idx
= MPIC_INT_IRQ
;
1435 DPRINTF("%s: addr " TARGET_FMT_plx
" <= %08x\n", __func__
, addr
, val
);
1439 addr
-= MPIC_INT_REG_START
& (OPENPIC_PAGE_SIZE
- 1);
1440 if (addr
< MPIC_INT_REG_SIZE
) {
1441 idx
+= (addr
& 0xFFF0) >> 5;
1443 /* EXDE / IFEDE / IEEDE */
1444 write_IRQreg(mpp
, idx
, IRQ_IDE
, val
);
1446 /* EXVP / IFEVP / IEEVP */
1447 write_IRQreg(mpp
, idx
, IRQ_IPVP
, val
);
1452 static uint32_t mpic_src_int_read (void *opaque
, target_phys_addr_t addr
)
1454 openpic_t
*mpp
= opaque
;
1456 int idx
= MPIC_INT_IRQ
;
1458 DPRINTF("%s: addr " TARGET_FMT_plx
"\n", __func__
, addr
);
1459 retval
= 0xFFFFFFFF;
1463 addr
-= MPIC_INT_REG_START
& (OPENPIC_PAGE_SIZE
- 1);
1464 if (addr
< MPIC_INT_REG_SIZE
) {
1465 idx
+= (addr
& 0xFFF0) >> 5;
1467 /* EXDE / IFEDE / IEEDE */
1468 retval
= read_IRQreg_ide(mpp
, idx
);
1470 /* EXVP / IFEVP / IEEVP */
1471 retval
= read_IRQreg_ipvp(mpp
, idx
);
1473 DPRINTF("%s: => %08x\n", __func__
, retval
);
1479 static void mpic_src_msg_write (void *opaque
, target_phys_addr_t addr
,
1482 openpic_t
*mpp
= opaque
;
1483 int idx
= MPIC_MSG_IRQ
;
1485 DPRINTF("%s: addr " TARGET_FMT_plx
" <= %08x\n", __func__
, addr
, val
);
1489 addr
-= MPIC_MSG_REG_START
& (OPENPIC_PAGE_SIZE
- 1);
1490 if (addr
< MPIC_MSG_REG_SIZE
) {
1491 idx
+= (addr
& 0xFFF0) >> 5;
1493 /* EXDE / IFEDE / IEEDE */
1494 write_IRQreg(mpp
, idx
, IRQ_IDE
, val
);
1496 /* EXVP / IFEVP / IEEVP */
1497 write_IRQreg(mpp
, idx
, IRQ_IPVP
, val
);
1502 static uint32_t mpic_src_msg_read (void *opaque
, target_phys_addr_t addr
)
1504 openpic_t
*mpp
= opaque
;
1506 int idx
= MPIC_MSG_IRQ
;
1508 DPRINTF("%s: addr " TARGET_FMT_plx
"\n", __func__
, addr
);
1509 retval
= 0xFFFFFFFF;
1513 addr
-= MPIC_MSG_REG_START
& (OPENPIC_PAGE_SIZE
- 1);
1514 if (addr
< MPIC_MSG_REG_SIZE
) {
1515 idx
+= (addr
& 0xFFF0) >> 5;
1517 /* EXDE / IFEDE / IEEDE */
1518 retval
= read_IRQreg_ide(mpp
, idx
);
1520 /* EXVP / IFEVP / IEEVP */
1521 retval
= read_IRQreg_ipvp(mpp
, idx
);
1523 DPRINTF("%s: => %08x\n", __func__
, retval
);
1529 static void mpic_src_msi_write (void *opaque
, target_phys_addr_t addr
,
1532 openpic_t
*mpp
= opaque
;
1533 int idx
= MPIC_MSI_IRQ
;
1535 DPRINTF("%s: addr " TARGET_FMT_plx
" <= %08x\n", __func__
, addr
, val
);
1539 addr
-= MPIC_MSI_REG_START
& (OPENPIC_PAGE_SIZE
- 1);
1540 if (addr
< MPIC_MSI_REG_SIZE
) {
1541 idx
+= (addr
& 0xFFF0) >> 5;
1543 /* EXDE / IFEDE / IEEDE */
1544 write_IRQreg(mpp
, idx
, IRQ_IDE
, val
);
1546 /* EXVP / IFEVP / IEEVP */
1547 write_IRQreg(mpp
, idx
, IRQ_IPVP
, val
);
1551 static uint32_t mpic_src_msi_read (void *opaque
, target_phys_addr_t addr
)
1553 openpic_t
*mpp
= opaque
;
1555 int idx
= MPIC_MSI_IRQ
;
1557 DPRINTF("%s: addr " TARGET_FMT_plx
"\n", __func__
, addr
);
1558 retval
= 0xFFFFFFFF;
1562 addr
-= MPIC_MSI_REG_START
& (OPENPIC_PAGE_SIZE
- 1);
1563 if (addr
< MPIC_MSI_REG_SIZE
) {
1564 idx
+= (addr
& 0xFFF0) >> 5;
1566 /* EXDE / IFEDE / IEEDE */
1567 retval
= read_IRQreg_ide(mpp
, idx
);
1569 /* EXVP / IFEVP / IEEVP */
1570 retval
= read_IRQreg_ipvp(mpp
, idx
);
1572 DPRINTF("%s: => %08x\n", __func__
, retval
);
1578 static CPUWriteMemoryFunc
* const mpic_glb_write
[] = {
1579 &openpic_buggy_write
,
1580 &openpic_buggy_write
,
1584 static CPUReadMemoryFunc
* const mpic_glb_read
[] = {
1585 &openpic_buggy_read
,
1586 &openpic_buggy_read
,
1590 static CPUWriteMemoryFunc
* const mpic_tmr_write
[] = {
1591 &openpic_buggy_write
,
1592 &openpic_buggy_write
,
1596 static CPUReadMemoryFunc
* const mpic_tmr_read
[] = {
1597 &openpic_buggy_read
,
1598 &openpic_buggy_read
,
1602 static CPUWriteMemoryFunc
* const mpic_cpu_write
[] = {
1603 &openpic_buggy_write
,
1604 &openpic_buggy_write
,
1608 static CPUReadMemoryFunc
* const mpic_cpu_read
[] = {
1609 &openpic_buggy_read
,
1610 &openpic_buggy_read
,
1614 static CPUWriteMemoryFunc
* const mpic_ext_write
[] = {
1615 &openpic_buggy_write
,
1616 &openpic_buggy_write
,
1617 &mpic_src_ext_write
,
1620 static CPUReadMemoryFunc
* const mpic_ext_read
[] = {
1621 &openpic_buggy_read
,
1622 &openpic_buggy_read
,
1626 static CPUWriteMemoryFunc
* const mpic_int_write
[] = {
1627 &openpic_buggy_write
,
1628 &openpic_buggy_write
,
1629 &mpic_src_int_write
,
1632 static CPUReadMemoryFunc
* const mpic_int_read
[] = {
1633 &openpic_buggy_read
,
1634 &openpic_buggy_read
,
1638 static CPUWriteMemoryFunc
* const mpic_msg_write
[] = {
1639 &openpic_buggy_write
,
1640 &openpic_buggy_write
,
1641 &mpic_src_msg_write
,
1644 static CPUReadMemoryFunc
* const mpic_msg_read
[] = {
1645 &openpic_buggy_read
,
1646 &openpic_buggy_read
,
1649 static CPUWriteMemoryFunc
* const mpic_msi_write
[] = {
1650 &openpic_buggy_write
,
1651 &openpic_buggy_write
,
1652 &mpic_src_msi_write
,
1655 static CPUReadMemoryFunc
* const mpic_msi_read
[] = {
1656 &openpic_buggy_read
,
1657 &openpic_buggy_read
,
1661 qemu_irq
*mpic_init (target_phys_addr_t base
, int nb_cpus
,
1662 qemu_irq
**irqs
, qemu_irq irq_out
)
1667 CPUReadMemoryFunc
* const *read
;
1668 CPUWriteMemoryFunc
* const *write
;
1669 target_phys_addr_t start_addr
;
1672 {mpic_glb_read
, mpic_glb_write
, MPIC_GLB_REG_START
, MPIC_GLB_REG_SIZE
},
1673 {mpic_tmr_read
, mpic_tmr_write
, MPIC_TMR_REG_START
, MPIC_TMR_REG_SIZE
},
1674 {mpic_ext_read
, mpic_ext_write
, MPIC_EXT_REG_START
, MPIC_EXT_REG_SIZE
},
1675 {mpic_int_read
, mpic_int_write
, MPIC_INT_REG_START
, MPIC_INT_REG_SIZE
},
1676 {mpic_msg_read
, mpic_msg_write
, MPIC_MSG_REG_START
, MPIC_MSG_REG_SIZE
},
1677 {mpic_msi_read
, mpic_msi_write
, MPIC_MSI_REG_START
, MPIC_MSI_REG_SIZE
},
1678 {mpic_cpu_read
, mpic_cpu_write
, MPIC_CPU_REG_START
, MPIC_CPU_REG_SIZE
},
1681 mpp
= g_malloc0(sizeof(openpic_t
));
1683 for (i
= 0; i
< sizeof(list
)/sizeof(list
[0]); i
++) {
1686 mem_index
= cpu_register_io_memory(list
[i
].read
, list
[i
].write
, mpp
,
1688 if (mem_index
< 0) {
1691 cpu_register_physical_memory(base
+ list
[i
].start_addr
,
1692 list
[i
].size
, mem_index
);
1695 mpp
->nb_cpus
= nb_cpus
;
1696 mpp
->max_irq
= MPIC_MAX_IRQ
;
1697 mpp
->irq_ipi0
= MPIC_IPI_IRQ
;
1698 mpp
->irq_tim0
= MPIC_TMR_IRQ
;
1700 for (i
= 0; i
< nb_cpus
; i
++)
1701 mpp
->dst
[i
].irqs
= irqs
[i
];
1702 mpp
->irq_out
= irq_out
;
1704 mpp
->irq_raise
= mpic_irq_raise
;
1705 mpp
->reset
= mpic_reset
;
1707 register_savevm(NULL
, "mpic", 0, 2, openpic_save
, openpic_load
, mpp
);
1708 qemu_register_reset(mpic_reset
, mpp
);
1710 return qemu_allocate_irqs(openpic_set_irq
, mpp
, mpp
->max_irq
);