hw/openrisc/openrisc_sim.c

   1 /*
   2  * OpenRISC simulator for use as an IIS.
   3  *
   4  * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
   5  *                         Feng Gao <gf91597@gmail.com>
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qapi/error.h"
  23 #include "hw/hw.h"
  24 #include "hw/boards.h"
  25 #include "elf.h"
  26 #include "hw/char/serial.h"
  27 #include "net/net.h"
  28 #include "hw/loader.h"
  29 #include "exec/address-spaces.h"
  30 #include "sysemu/sysemu.h"
  31 #include "hw/sysbus.h"
  32 #include "sysemu/qtest.h"
  33
  34 #define KERNEL_LOAD_ADDR 0x100
  35
  36 static void main_cpu_reset(void *opaque)
  37 {
  38     OpenRISCCPU *cpu = opaque;
  39
  40     cpu_reset(CPU(cpu));
  41 }
  42
  43 static void openrisc_sim_net_init(MemoryRegion *address_space,
  44                                   hwaddr base,
  45                                   hwaddr descriptors,
  46                                   qemu_irq irq, NICInfo *nd)
  47 {
  48     DeviceState *dev;
  49     SysBusDevice *s;
  50
  51     dev = qdev_create(NULL, "open_eth");
  52     qdev_set_nic_properties(dev, nd);
  53     qdev_init_nofail(dev);
  54
  55     s = SYS_BUS_DEVICE(dev);
  56     sysbus_connect_irq(s, 0, irq);
  57     memory_region_add_subregion(address_space, base,
  58                                 sysbus_mmio_get_region(s, 0));
  59     memory_region_add_subregion(address_space, descriptors,
  60                                 sysbus_mmio_get_region(s, 1));
  61 }
  62
  63 static void cpu_openrisc_load_kernel(ram_addr_t ram_size,
  64                                      const char *kernel_filename,
  65                                      OpenRISCCPU *cpu)
  66 {
  67     long kernel_size;
  68     uint64_t elf_entry;
  69     hwaddr entry;
  70
  71     if (kernel_filename && !qtest_enabled()) {
  72         kernel_size = load_elf(kernel_filename, NULL, NULL,
  73                                &elf_entry, NULL, NULL, 1, EM_OPENRISC,
  74                                1, 0);
  75         entry = elf_entry;
  76         if (kernel_size < 0) {
  77             kernel_size = load_uimage(kernel_filename,
  78                                       &entry, NULL, NULL, NULL, NULL);
  79         }
  80         if (kernel_size < 0) {
  81             kernel_size = load_image_targphys(kernel_filename,
  82                                               KERNEL_LOAD_ADDR,
  83                                               ram_size - KERNEL_LOAD_ADDR);
  84             entry = KERNEL_LOAD_ADDR;
  85         }
  86
  87         if (kernel_size < 0) {
  88             fprintf(stderr, "QEMU: couldn't load the kernel '%s'\n",
  89                     kernel_filename);
  90             exit(1);
  91         }
  92         cpu->env.pc = entry;
  93     }
  94 }
  95
  96 static void openrisc_sim_init(MachineState *machine)
  97 {
  98     ram_addr_t ram_size = machine->ram_size;
  99     const char *cpu_model = machine->cpu_model;
 100     const char *kernel_filename = machine->kernel_filename;
 101     OpenRISCCPU *cpu = NULL;
 102     MemoryRegion *ram;
 103     int n;
 104
 105     if (!cpu_model) {
 106         cpu_model = "or1200";
 107     }
 108
 109     for (n = 0; n < smp_cpus; n++) {
 110         cpu = cpu_openrisc_init(cpu_model);
 111         if (cpu == NULL) {
 112             fprintf(stderr, "Unable to find CPU definition!\n");
 113             exit(1);
 114         }
 115         qemu_register_reset(main_cpu_reset, cpu);
 116         main_cpu_reset(cpu);
 117     }
 118
 119     ram = g_malloc(sizeof(*ram));
 120     memory_region_init_ram(ram, NULL, "openrisc.ram", ram_size, &error_fatal);
 121     vmstate_register_ram_global(ram);
 122     memory_region_add_subregion(get_system_memory(), 0, ram);
 123
 124     cpu_openrisc_pic_init(cpu);
 125     cpu_openrisc_clock_init(cpu);
 126
 127     serial_mm_init(get_system_memory(), 0x90000000, 0, cpu->env.irq[2],
 128                    115200, serial_hds[0], DEVICE_NATIVE_ENDIAN);
 129
 130     if (nd_table[0].used) {
 131         openrisc_sim_net_init(get_system_memory(), 0x92000000,
 132                               0x92000400, cpu->env.irq[4], nd_table);
 133     }
 134
 135     cpu_openrisc_load_kernel(ram_size, kernel_filename, cpu);
 136 }
 137
 138 static void openrisc_sim_machine_init(MachineClass *mc)
 139 {
 140     mc->desc = "or32 simulation";
 141     mc->init = openrisc_sim_init;
 142     mc->max_cpus = 1;
 143     mc->is_default = 1;
 144 }
 145
 146 DEFINE_MACHINE("or32-sim", openrisc_sim_machine_init)