hw/openrisc/virt.c

   1 /*
   2  * SPDX-License-Identifier: GPL-2.0-or-later
   3  *
   4  * OpenRISC QEMU virtual machine.
   5  *
   6  * (c) 2022 Stafford Horne <shorne@gmail.com>
   7  */
   8
   9 #include "qemu/osdep.h"
  10 #include "qemu/error-report.h"
  11 #include "qemu/guest-random.h"
  12 #include "qapi/error.h"
  13 #include "cpu.h"
  14 #include "exec/address-spaces.h"
  15 #include "hw/irq.h"
  16 #include "hw/boards.h"
  17 #include "hw/char/serial.h"
  18 #include "hw/core/split-irq.h"
  19 #include "hw/openrisc/boot.h"
  20 #include "hw/misc/sifive_test.h"
  21 #include "hw/pci/pci.h"
  22 #include "hw/pci-host/gpex.h"
  23 #include "hw/qdev-properties.h"
  24 #include "hw/rtc/goldfish_rtc.h"
  25 #include "hw/sysbus.h"
  26 #include "hw/virtio/virtio-mmio.h"
  27 #include "sysemu/device_tree.h"
  28 #include "sysemu/sysemu.h"
  29 #include "sysemu/qtest.h"
  30 #include "sysemu/reset.h"
  31
  32 #include <libfdt.h>
  33
  34 #define VIRT_CPUS_MAX 4
  35 #define VIRT_CLK_MHZ 20000000
  36
  37 #define TYPE_VIRT_MACHINE MACHINE_TYPE_NAME("virt")
  38 #define VIRT_MACHINE(obj) \
  39     OBJECT_CHECK(OR1KVirtState, (obj), TYPE_VIRT_MACHINE)
  40
  41 typedef struct OR1KVirtState {
  42     /*< private >*/
  43     MachineState parent_obj;
  44
  45     /*< public >*/
  46     void *fdt;
  47     int fdt_size;
  48
  49 } OR1KVirtState;
  50
  51 enum {
  52     VIRT_DRAM,
  53     VIRT_ECAM,
  54     VIRT_MMIO,
  55     VIRT_PIO,
  56     VIRT_TEST,
  57     VIRT_RTC,
  58     VIRT_VIRTIO,
  59     VIRT_UART,
  60     VIRT_OMPIC,
  61 };
  62
  63 enum {
  64     VIRT_OMPIC_IRQ = 1,
  65     VIRT_UART_IRQ = 2,
  66     VIRT_RTC_IRQ = 3,
  67     VIRT_VIRTIO_IRQ = 4, /* to 12 */
  68     VIRTIO_COUNT = 8,
  69     VIRT_PCI_IRQ_BASE = 13, /* to 17 */
  70 };
  71
  72 static const struct MemmapEntry {
  73     hwaddr base;
  74     hwaddr size;
  75 } virt_memmap[] = {
  76     [VIRT_DRAM] =      { 0x00000000,          0 },
  77     [VIRT_UART] =      { 0x90000000,      0x100 },
  78     [VIRT_TEST] =      { 0x96000000,        0x8 },
  79     [VIRT_RTC] =       { 0x96005000,     0x1000 },
  80     [VIRT_VIRTIO] =    { 0x97000000,     0x1000 },
  81     [VIRT_OMPIC] =     { 0x98000000, VIRT_CPUS_MAX * 8 },
  82     [VIRT_ECAM] =      { 0x9e000000,  0x1000000 },
  83     [VIRT_PIO] =       { 0x9f000000,  0x1000000 },
  84     [VIRT_MMIO] =      { 0xa0000000, 0x10000000 },
  85 };
  86
  87 static struct openrisc_boot_info {
  88     uint32_t bootstrap_pc;
  89     uint32_t fdt_addr;
  90 } boot_info;
  91
  92 static void main_cpu_reset(void *opaque)
  93 {
  94     OpenRISCCPU *cpu = opaque;
  95     CPUState *cs = CPU(cpu);
  96
  97     cpu_reset(CPU(cpu));
  98
  99     cpu_set_pc(cs, boot_info.bootstrap_pc);
 100     cpu_set_gpr(&cpu->env, 3, boot_info.fdt_addr);
 101 }
 102
 103 static qemu_irq get_cpu_irq(OpenRISCCPU *cpus[], int cpunum, int irq_pin)
 104 {
 105     return qdev_get_gpio_in_named(DEVICE(cpus[cpunum]), "IRQ", irq_pin);
 106 }
 107
 108 static qemu_irq get_per_cpu_irq(OpenRISCCPU *cpus[], int num_cpus, int irq_pin)
 109 {
 110     int i;
 111
 112     if (num_cpus > 1) {
 113         DeviceState *splitter = qdev_new(TYPE_SPLIT_IRQ);
 114         qdev_prop_set_uint32(splitter, "num-lines", num_cpus);
 115         qdev_realize_and_unref(splitter, NULL, &error_fatal);
 116         for (i = 0; i < num_cpus; i++) {
 117             qdev_connect_gpio_out(splitter, i, get_cpu_irq(cpus, i, irq_pin));
 118         }
 119         return qdev_get_gpio_in(splitter, 0);
 120     } else {
 121         return get_cpu_irq(cpus, 0, irq_pin);
 122     }
 123 }
 124
 125 static void openrisc_create_fdt(OR1KVirtState *state,
 126                                 const struct MemmapEntry *memmap,
 127                                 int num_cpus, uint64_t mem_size,
 128                                 const char *cmdline,
 129                                 int32_t *pic_phandle)
 130 {
 131     void *fdt;
 132     int cpu;
 133     char *nodename;
 134     uint8_t rng_seed[32];
 135
 136     fdt = state->fdt = create_device_tree(&state->fdt_size);
 137     if (!fdt) {
 138         error_report("create_device_tree() failed");
 139         exit(1);
 140     }
 141
 142     qemu_fdt_setprop_string(fdt, "/", "compatible", "opencores,or1ksim");
 143     qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x1);
 144     qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x1);
 145
 146     qemu_fdt_add_subnode(fdt, "/soc");
 147     qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
 148     qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
 149     qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x1);
 150     qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x1);
 151
 152     nodename = g_strdup_printf("/memory@%" HWADDR_PRIx,
 153                                memmap[VIRT_DRAM].base);
 154     qemu_fdt_add_subnode(fdt, nodename);
 155     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 156                            memmap[VIRT_DRAM].base, mem_size);
 157     qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
 158     g_free(nodename);
 159
 160     qemu_fdt_add_subnode(fdt, "/cpus");
 161     qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
 162     qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
 163
 164     for (cpu = 0; cpu < num_cpus; cpu++) {
 165         nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
 166         qemu_fdt_add_subnode(fdt, nodename);
 167         qemu_fdt_setprop_string(fdt, nodename, "compatible",
 168                                 "opencores,or1200-rtlsvn481");
 169         qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
 170         qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
 171                               VIRT_CLK_MHZ);
 172         g_free(nodename);
 173     }
 174
 175     nodename = (char *)"/pic";
 176     qemu_fdt_add_subnode(fdt, nodename);
 177     *pic_phandle = qemu_fdt_alloc_phandle(fdt);
 178     qemu_fdt_setprop_string(fdt, nodename, "compatible",
 179                             "opencores,or1k-pic-level");
 180     qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
 181     qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
 182     qemu_fdt_setprop_cell(fdt, nodename, "phandle", *pic_phandle);
 183
 184     qemu_fdt_setprop_cell(fdt, "/", "interrupt-parent", *pic_phandle);
 185
 186     qemu_fdt_add_subnode(fdt, "/chosen");
 187     if (cmdline) {
 188         qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
 189     }
 190
 191     /* Pass seed to RNG. */
 192     qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed));
 193     qemu_fdt_setprop(fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed));
 194
 195     /* Create aliases node for use by devices. */
 196     qemu_fdt_add_subnode(fdt, "/aliases");
 197 }
 198
 199 static void openrisc_virt_ompic_init(OR1KVirtState *state, hwaddr base,
 200                                     hwaddr size, int num_cpus,
 201                                     OpenRISCCPU *cpus[], int irq_pin)
 202 {
 203     void *fdt = state->fdt;
 204     DeviceState *dev;
 205     SysBusDevice *s;
 206     char *nodename;
 207     int i;
 208
 209     dev = qdev_new("or1k-ompic");
 210     qdev_prop_set_uint32(dev, "num-cpus", num_cpus);
 211
 212     s = SYS_BUS_DEVICE(dev);
 213     sysbus_realize_and_unref(s, &error_fatal);
 214     for (i = 0; i < num_cpus; i++) {
 215         sysbus_connect_irq(s, i, get_cpu_irq(cpus, i, irq_pin));
 216     }
 217     sysbus_mmio_map(s, 0, base);
 218
 219     /* Add device tree node for ompic. */
 220     nodename = g_strdup_printf("/ompic@%" HWADDR_PRIx, base);
 221     qemu_fdt_add_subnode(fdt, nodename);
 222     qemu_fdt_setprop_string(fdt, nodename, "compatible", "openrisc,ompic");
 223     qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size);
 224     qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
 225     qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 0);
 226     qemu_fdt_setprop_cell(fdt, nodename, "interrupts", irq_pin);
 227     g_free(nodename);
 228 }
 229
 230 static void openrisc_virt_serial_init(OR1KVirtState *state, hwaddr base,
 231                                      hwaddr size, int num_cpus,
 232                                      OpenRISCCPU *cpus[], int irq_pin)
 233 {
 234     void *fdt = state->fdt;
 235     char *nodename;
 236     qemu_irq serial_irq = get_per_cpu_irq(cpus, num_cpus, irq_pin);
 237
 238     serial_mm_init(get_system_memory(), base, 0, serial_irq, 115200,
 239                    serial_hd(0), DEVICE_NATIVE_ENDIAN);
 240
 241     /* Add device tree node for serial. */
 242     nodename = g_strdup_printf("/serial@%" HWADDR_PRIx, base);
 243     qemu_fdt_add_subnode(fdt, nodename);
 244     qemu_fdt_setprop_string(fdt, nodename, "compatible", "ns16550a");
 245     qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size);
 246     qemu_fdt_setprop_cell(fdt, nodename, "interrupts", irq_pin);
 247     qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", VIRT_CLK_MHZ);
 248     qemu_fdt_setprop(fdt, nodename, "big-endian", NULL, 0);
 249
 250     /* The /chosen node is created during fdt creation. */
 251     qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
 252     qemu_fdt_setprop_string(fdt, "/aliases", "uart0", nodename);
 253     g_free(nodename);
 254 }
 255
 256 static void openrisc_virt_test_init(OR1KVirtState *state, hwaddr base,
 257                                    hwaddr size)
 258 {
 259     void *fdt = state->fdt;
 260     int test_ph;
 261     char *nodename;
 262
 263     /* SiFive Test MMIO device */
 264     sifive_test_create(base);
 265
 266     /* SiFive Test MMIO Reset device FDT */
 267     nodename = g_strdup_printf("/soc/test@%" HWADDR_PRIx, base);
 268     qemu_fdt_add_subnode(fdt, nodename);
 269     qemu_fdt_setprop_string(fdt, nodename, "compatible", "syscon");
 270     test_ph = qemu_fdt_alloc_phandle(fdt);
 271     qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size);
 272     qemu_fdt_setprop_cell(fdt, nodename, "phandle", test_ph);
 273     qemu_fdt_setprop(fdt, nodename, "big-endian", NULL, 0);
 274     g_free(nodename);
 275
 276     nodename = g_strdup_printf("/soc/reboot");
 277     qemu_fdt_add_subnode(fdt, nodename);
 278     qemu_fdt_setprop_string(fdt, nodename, "compatible", "syscon-reboot");
 279     qemu_fdt_setprop_cell(fdt, nodename, "regmap", test_ph);
 280     qemu_fdt_setprop_cell(fdt, nodename, "offset", 0x0);
 281     qemu_fdt_setprop_cell(fdt, nodename, "value", FINISHER_RESET);
 282     g_free(nodename);
 283
 284     nodename = g_strdup_printf("/soc/poweroff");
 285     qemu_fdt_add_subnode(fdt, nodename);
 286     qemu_fdt_setprop_string(fdt, nodename, "compatible", "syscon-poweroff");
 287     qemu_fdt_setprop_cell(fdt, nodename, "regmap", test_ph);
 288     qemu_fdt_setprop_cell(fdt, nodename, "offset", 0x0);
 289     qemu_fdt_setprop_cell(fdt, nodename, "value", FINISHER_PASS);
 290     g_free(nodename);
 291
 292 }
 293
 294 static void openrisc_virt_rtc_init(OR1KVirtState *state, hwaddr base,
 295                                    hwaddr size, int num_cpus,
 296                                    OpenRISCCPU *cpus[], int irq_pin)
 297 {
 298     void *fdt = state->fdt;
 299     char *nodename;
 300     qemu_irq rtc_irq = get_per_cpu_irq(cpus, num_cpus, irq_pin);
 301
 302     /* Goldfish RTC */
 303     sysbus_create_simple(TYPE_GOLDFISH_RTC, base, rtc_irq);
 304
 305     /* Goldfish RTC FDT */
 306     nodename = g_strdup_printf("/soc/rtc@%" HWADDR_PRIx, base);
 307     qemu_fdt_add_subnode(fdt, nodename);
 308     qemu_fdt_setprop_string(fdt, nodename, "compatible",
 309                             "google,goldfish-rtc");
 310     qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size);
 311     qemu_fdt_setprop_cell(fdt, nodename, "interrupts", irq_pin);
 312     g_free(nodename);
 313
 314 }
 315
 316 static void create_pcie_irq_map(void *fdt, char *nodename, int irq_base,
 317                                 uint32_t irqchip_phandle)
 318 {
 319     int pin, dev;
 320     uint32_t irq_map_stride = 0;
 321     uint32_t full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * 6] = {};
 322     uint32_t *irq_map = full_irq_map;
 323
 324     /*
 325      * This code creates a standard swizzle of interrupts such that
 326      * each device's first interrupt is based on it's PCI_SLOT number.
 327      * (See pci_swizzle_map_irq_fn())
 328      *
 329      * We only need one entry per interrupt in the table (not one per
 330      * possible slot) seeing the interrupt-map-mask will allow the table
 331      * to wrap to any number of devices.
 332      */
 333     for (dev = 0; dev < GPEX_NUM_IRQS; dev++) {
 334         int devfn = dev << 3;
 335
 336         for (pin = 0; pin < GPEX_NUM_IRQS; pin++) {
 337             int irq_nr = irq_base + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS);
 338             int i = 0;
 339
 340             /* Fill PCI address cells */
 341             irq_map[i++] = cpu_to_be32(devfn << 8);
 342             irq_map[i++] = 0;
 343             irq_map[i++] = 0;
 344
 345             /* Fill PCI Interrupt cells */
 346             irq_map[i++] = cpu_to_be32(pin + 1);
 347
 348             /* Fill interrupt controller phandle and cells */
 349             irq_map[i++] = cpu_to_be32(irqchip_phandle);
 350             irq_map[i++] = cpu_to_be32(irq_nr);
 351
 352             if (!irq_map_stride) {
 353                 irq_map_stride = i;
 354             }
 355             irq_map += irq_map_stride;
 356         }
 357     }
 358
 359     qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map,
 360                      GPEX_NUM_IRQS * GPEX_NUM_IRQS *
 361                      irq_map_stride * sizeof(uint32_t));
 362
 363     qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask",
 364                            0x1800, 0, 0, 0x7);
 365 }
 366
 367 static void openrisc_virt_pcie_init(OR1KVirtState *state,
 368                                     hwaddr ecam_base, hwaddr ecam_size,
 369                                     hwaddr pio_base, hwaddr pio_size,
 370                                     hwaddr mmio_base, hwaddr mmio_size,
 371                                     int num_cpus, OpenRISCCPU *cpus[],
 372                                     int irq_base, int32_t pic_phandle)
 373 {
 374     void *fdt = state->fdt;
 375     char *nodename;
 376     MemoryRegion *alias;
 377     MemoryRegion *reg;
 378     DeviceState *dev;
 379     qemu_irq pcie_irq;
 380     int i;
 381
 382     dev = qdev_new(TYPE_GPEX_HOST);
 383     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 384
 385     /* Map ECAM space. */
 386     alias = g_new0(MemoryRegion, 1);
 387     reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
 388     memory_region_init_alias(alias, OBJECT(dev), "pcie-ecam",
 389                              reg, 0, ecam_size);
 390     memory_region_add_subregion(get_system_memory(), ecam_base, alias);
 391
 392     /*
 393      * Map the MMIO window into system address space so as to expose
 394      * the section of PCI MMIO space which starts at the same base address
 395      * (ie 1:1 mapping for that part of PCI MMIO space visible through
 396      * the window).
 397      */
 398     alias = g_new0(MemoryRegion, 1);
 399     reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
 400     memory_region_init_alias(alias, OBJECT(dev), "pcie-mmio",
 401                              reg, mmio_base, mmio_size);
 402     memory_region_add_subregion(get_system_memory(), mmio_base, alias);
 403
 404     /* Map IO port space. */
 405     alias = g_new0(MemoryRegion, 1);
 406     reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 2);
 407     memory_region_init_alias(alias, OBJECT(dev), "pcie-pio",
 408                              reg, 0, pio_size);
 409     memory_region_add_subregion(get_system_memory(), pio_base, alias);
 410
 411     /* Connect IRQ lines. */
 412     for (i = 0; i < GPEX_NUM_IRQS; i++) {
 413         pcie_irq = get_per_cpu_irq(cpus, num_cpus, irq_base + i);
 414
 415         sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pcie_irq);
 416         gpex_set_irq_num(GPEX_HOST(dev), i, irq_base + i);
 417     }
 418
 419     nodename = g_strdup_printf("/soc/pci@%" HWADDR_PRIx, ecam_base);
 420     qemu_fdt_add_subnode(fdt, nodename);
 421     qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
 422     qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 3);
 423     qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 2);
 424     qemu_fdt_setprop_string(fdt, nodename, "compatible",
 425                             "pci-host-ecam-generic");
 426     qemu_fdt_setprop_string(fdt, nodename, "device_type", "pci");
 427     qemu_fdt_setprop_cell(fdt, nodename, "linux,pci-domain", 0);
 428     qemu_fdt_setprop_cells(fdt, nodename, "bus-range", 0,
 429                            ecam_size / PCIE_MMCFG_SIZE_MIN - 1);
 430     qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0);
 431     qemu_fdt_setprop_cells(fdt, nodename, "reg", ecam_base, ecam_size);
 432     /* pci-address(3) cpu-address(1) pci-size(2) */
 433     qemu_fdt_setprop_cells(fdt, nodename, "ranges",
 434                            FDT_PCI_RANGE_IOPORT, 0, 0,
 435                            pio_base, 0, pio_size,
 436                            FDT_PCI_RANGE_MMIO, 0, mmio_base,
 437                            mmio_base, 0, mmio_size);
 438
 439     create_pcie_irq_map(fdt, nodename, irq_base, pic_phandle);
 440     g_free(nodename);
 441 }
 442
 443 static void openrisc_virt_virtio_init(OR1KVirtState *state, hwaddr base,
 444                                       hwaddr size, int num_cpus,
 445                                       OpenRISCCPU *cpus[], int irq_pin)
 446 {
 447     void *fdt = state->fdt;
 448     char *nodename;
 449     DeviceState *dev;
 450     SysBusDevice *sysbus;
 451     qemu_irq virtio_irq = get_per_cpu_irq(cpus, num_cpus, irq_pin);
 452
 453     /* VirtIO MMIO devices */
 454     dev = qdev_new(TYPE_VIRTIO_MMIO);
 455     qdev_prop_set_bit(dev, "force-legacy", false);
 456     sysbus = SYS_BUS_DEVICE(dev);
 457     sysbus_realize_and_unref(sysbus, &error_fatal);
 458     sysbus_connect_irq(sysbus, 0, virtio_irq);
 459     sysbus_mmio_map(sysbus, 0, base);
 460
 461     /* VirtIO MMIO devices FDT */
 462     nodename = g_strdup_printf("/soc/virtio_mmio@%" HWADDR_PRIx, base);
 463     qemu_fdt_add_subnode(fdt, nodename);
 464     qemu_fdt_setprop_string(fdt, nodename, "compatible", "virtio,mmio");
 465     qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size);
 466     qemu_fdt_setprop_cell(fdt, nodename, "interrupts", irq_pin);
 467     g_free(nodename);
 468 }
 469
 470 static void openrisc_virt_init(MachineState *machine)
 471 {
 472     ram_addr_t ram_size = machine->ram_size;
 473     const char *kernel_filename = machine->kernel_filename;
 474     OpenRISCCPU *cpus[VIRT_CPUS_MAX] = {};
 475     OR1KVirtState *state = VIRT_MACHINE(machine);
 476     MemoryRegion *ram;
 477     hwaddr load_addr;
 478     int n;
 479     unsigned int smp_cpus = machine->smp.cpus;
 480     int32_t pic_phandle;
 481
 482     assert(smp_cpus >= 1 && smp_cpus <= VIRT_CPUS_MAX);
 483     for (n = 0; n < smp_cpus; n++) {
 484         cpus[n] = OPENRISC_CPU(cpu_create(machine->cpu_type));
 485         if (cpus[n] == NULL) {
 486             fprintf(stderr, "Unable to find CPU definition!\n");
 487             exit(1);
 488         }
 489
 490         cpu_openrisc_clock_init(cpus[n]);
 491
 492         qemu_register_reset(main_cpu_reset, cpus[n]);
 493     }
 494
 495     ram = g_malloc(sizeof(*ram));
 496     memory_region_init_ram(ram, NULL, "openrisc.ram", ram_size, &error_fatal);
 497     memory_region_add_subregion(get_system_memory(), 0, ram);
 498
 499     openrisc_create_fdt(state, virt_memmap, smp_cpus, machine->ram_size,
 500                         machine->kernel_cmdline, &pic_phandle);
 501
 502     if (smp_cpus > 1) {
 503         openrisc_virt_ompic_init(state, virt_memmap[VIRT_OMPIC].base,
 504                                  virt_memmap[VIRT_OMPIC].size,
 505                                  smp_cpus, cpus, VIRT_OMPIC_IRQ);
 506     }
 507
 508     openrisc_virt_serial_init(state, virt_memmap[VIRT_UART].base,
 509                               virt_memmap[VIRT_UART].size,
 510                               smp_cpus, cpus, VIRT_UART_IRQ);
 511
 512     openrisc_virt_test_init(state, virt_memmap[VIRT_TEST].base,
 513                             virt_memmap[VIRT_TEST].size);
 514
 515     openrisc_virt_rtc_init(state, virt_memmap[VIRT_RTC].base,
 516                            virt_memmap[VIRT_RTC].size, smp_cpus, cpus,
 517                            VIRT_RTC_IRQ);
 518
 519     openrisc_virt_pcie_init(state, virt_memmap[VIRT_ECAM].base,
 520                             virt_memmap[VIRT_ECAM].size,
 521                             virt_memmap[VIRT_PIO].base,
 522                             virt_memmap[VIRT_PIO].size,
 523                             virt_memmap[VIRT_MMIO].base,
 524                             virt_memmap[VIRT_MMIO].size,
 525                             smp_cpus, cpus,
 526                             VIRT_PCI_IRQ_BASE, pic_phandle);
 527
 528     for (n = 0; n < VIRTIO_COUNT; n++) {
 529         openrisc_virt_virtio_init(state, virt_memmap[VIRT_VIRTIO].base
 530                                          + n * virt_memmap[VIRT_VIRTIO].size,
 531                                   virt_memmap[VIRT_VIRTIO].size,
 532                                   smp_cpus, cpus, VIRT_VIRTIO_IRQ + n);
 533     }
 534
 535     load_addr = openrisc_load_kernel(ram_size, kernel_filename,
 536                                      &boot_info.bootstrap_pc);
 537     if (load_addr > 0) {
 538         if (machine->initrd_filename) {
 539             load_addr = openrisc_load_initrd(state->fdt,
 540                                              machine->initrd_filename,
 541                                              load_addr, machine->ram_size);
 542         }
 543         boot_info.fdt_addr = openrisc_load_fdt(state->fdt, load_addr,
 544                                                machine->ram_size);
 545     }
 546 }
 547
 548 static void openrisc_virt_machine_init(ObjectClass *oc, void *data)
 549 {
 550     MachineClass *mc = MACHINE_CLASS(oc);
 551
 552     mc->desc = "or1k virtual machine";
 553     mc->init = openrisc_virt_init;
 554     mc->max_cpus = VIRT_CPUS_MAX;
 555     mc->is_default = false;
 556     mc->default_cpu_type = OPENRISC_CPU_TYPE_NAME("or1200");
 557 }
 558
 559 static const TypeInfo or1ksim_machine_typeinfo = {
 560     .name       = TYPE_VIRT_MACHINE,
 561     .parent     = TYPE_MACHINE,
 562     .class_init = openrisc_virt_machine_init,
 563     .instance_size = sizeof(OR1KVirtState),
 564 };
 565
 566 static void or1ksim_machine_init_register_types(void)
 567 {
 568     type_register_static(&or1ksim_machine_typeinfo);
 569 }
 570
 571 type_init(or1ksim_machine_init_register_types)