2 * QEMU Parallel PORT emulation
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 * Copyright (c) 2007 Marko Kohtala
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 //#define DEBUG_PARALLEL
30 #define pdebug(fmt, arg...) printf("pp: " fmt, ##arg)
32 #define pdebug(fmt, arg...) ((void)0)
35 #define PARA_REG_DATA 0
36 #define PARA_REG_STS 1
37 #define PARA_REG_CTR 2
38 #define PARA_REG_EPP_ADDR 3
39 #define PARA_REG_EPP_DATA 4
42 * These are the definitions for the Printer Status Register
44 #define PARA_STS_BUSY 0x80 /* Busy complement */
45 #define PARA_STS_ACK 0x40 /* Acknowledge */
46 #define PARA_STS_PAPER 0x20 /* Out of paper */
47 #define PARA_STS_ONLINE 0x10 /* Online */
48 #define PARA_STS_ERROR 0x08 /* Error complement */
49 #define PARA_STS_TMOUT 0x01 /* EPP timeout */
52 * These are the definitions for the Printer Control Register
54 #define PARA_CTR_DIR 0x20 /* Direction (1=read, 0=write) */
55 #define PARA_CTR_INTEN 0x10 /* IRQ Enable */
56 #define PARA_CTR_SELECT 0x08 /* Select In complement */
57 #define PARA_CTR_INIT 0x04 /* Initialize Printer complement */
58 #define PARA_CTR_AUTOLF 0x02 /* Auto linefeed complement */
59 #define PARA_CTR_STROBE 0x01 /* Strobe complement */
61 #define PARA_CTR_SIGNAL (PARA_CTR_SELECT|PARA_CTR_INIT|PARA_CTR_AUTOLF|PARA_CTR_STROBE)
63 struct ParallelState
{
73 uint32_t last_read_offset
; /* For debugging */
76 static void parallel_update_irq(ParallelState
*s
)
79 pic_set_irq(s
->irq
, 1);
81 pic_set_irq(s
->irq
, 0);
85 parallel_ioport_write_sw(void *opaque
, uint32_t addr
, uint32_t val
)
87 ParallelState
*s
= opaque
;
89 pdebug("write addr=0x%02x val=0x%02x\n", addr
, val
);
95 parallel_update_irq(s
);
98 if ((val
& PARA_CTR_INIT
) == 0 ) {
99 s
->status
= PARA_STS_BUSY
;
100 s
->status
|= PARA_STS_ACK
;
101 s
->status
|= PARA_STS_ONLINE
;
102 s
->status
|= PARA_STS_ERROR
;
104 else if (val
& PARA_CTR_SELECT
) {
105 if (val
& PARA_CTR_STROBE
) {
106 s
->status
&= ~PARA_STS_BUSY
;
107 if ((s
->control
& PARA_CTR_STROBE
) == 0)
108 qemu_chr_write(s
->chr
, &s
->dataw
, 1);
110 if (s
->control
& PARA_CTR_INTEN
) {
115 parallel_update_irq(s
);
121 static void parallel_ioport_write_hw(void *opaque
, uint32_t addr
, uint32_t val
)
123 ParallelState
*s
= opaque
;
126 /* Sometimes programs do several writes for timing purposes on old
127 HW. Take care not to waste time on writes that do nothing. */
129 s
->last_read_offset
= ~0U;
136 pdebug("wd%02x\n", val
);
137 qemu_chr_ioctl(s
->chr
, CHR_IOCTL_PP_WRITE_DATA
, &parm
);
141 pdebug("ws%02x\n", val
);
142 if (val
& PARA_STS_TMOUT
)
147 if (s
->control
== val
)
149 pdebug("wc%02x\n", val
);
150 qemu_chr_ioctl(s
->chr
, CHR_IOCTL_PP_WRITE_CONTROL
, &parm
);
153 case PARA_REG_EPP_ADDR
:
154 if ((s
->control
& (PARA_CTR_DIR
|PARA_CTR_SIGNAL
)) != PARA_CTR_INIT
)
155 /* Controls not correct for EPP address cycle, so do nothing */
156 pdebug("wa%02x s\n", val
);
158 struct ParallelIOArg ioarg
= { .buffer
= &parm
, .count
= 1 };
159 if (qemu_chr_ioctl(s
->chr
, CHR_IOCTL_PP_EPP_WRITE_ADDR
, &ioarg
)) {
161 pdebug("wa%02x t\n", val
);
164 pdebug("wa%02x\n", val
);
167 case PARA_REG_EPP_DATA
:
168 if ((s
->control
& (PARA_CTR_DIR
|PARA_CTR_SIGNAL
)) != PARA_CTR_INIT
)
169 /* Controls not correct for EPP data cycle, so do nothing */
170 pdebug("we%02x s\n", val
);
172 struct ParallelIOArg ioarg
= { .buffer
= &parm
, .count
= 1 };
173 if (qemu_chr_ioctl(s
->chr
, CHR_IOCTL_PP_EPP_WRITE
, &ioarg
)) {
175 pdebug("we%02x t\n", val
);
178 pdebug("we%02x\n", val
);
185 parallel_ioport_eppdata_write_hw2(void *opaque
, uint32_t addr
, uint32_t val
)
187 ParallelState
*s
= opaque
;
188 uint16_t eppdata
= cpu_to_le16(val
);
190 struct ParallelIOArg ioarg
= {
191 .buffer
= &eppdata
, .count
= sizeof(eppdata
)
193 if ((s
->control
& (PARA_CTR_DIR
|PARA_CTR_SIGNAL
)) != PARA_CTR_INIT
) {
194 /* Controls not correct for EPP data cycle, so do nothing */
195 pdebug("we%04x s\n", val
);
198 err
= qemu_chr_ioctl(s
->chr
, CHR_IOCTL_PP_EPP_WRITE
, &ioarg
);
201 pdebug("we%04x t\n", val
);
204 pdebug("we%04x\n", val
);
208 parallel_ioport_eppdata_write_hw4(void *opaque
, uint32_t addr
, uint32_t val
)
210 ParallelState
*s
= opaque
;
211 uint32_t eppdata
= cpu_to_le32(val
);
213 struct ParallelIOArg ioarg
= {
214 .buffer
= &eppdata
, .count
= sizeof(eppdata
)
216 if ((s
->control
& (PARA_CTR_DIR
|PARA_CTR_SIGNAL
)) != PARA_CTR_INIT
) {
217 /* Controls not correct for EPP data cycle, so do nothing */
218 pdebug("we%08x s\n", val
);
221 err
= qemu_chr_ioctl(s
->chr
, CHR_IOCTL_PP_EPP_WRITE
, &ioarg
);
224 pdebug("we%08x t\n", val
);
227 pdebug("we%08x\n", val
);
230 static uint32_t parallel_ioport_read_sw(void *opaque
, uint32_t addr
)
232 ParallelState
*s
= opaque
;
238 if (s
->control
& PARA_CTR_DIR
)
246 if ((s
->status
& PARA_STS_BUSY
) == 0 && (s
->control
& PARA_CTR_STROBE
) == 0) {
247 /* XXX Fixme: wait 5 microseconds */
248 if (s
->status
& PARA_STS_ACK
)
249 s
->status
&= ~PARA_STS_ACK
;
251 /* XXX Fixme: wait 5 microseconds */
252 s
->status
|= PARA_STS_ACK
;
253 s
->status
|= PARA_STS_BUSY
;
256 parallel_update_irq(s
);
262 pdebug("read addr=0x%02x val=0x%02x\n", addr
, ret
);
266 static uint32_t parallel_ioport_read_hw(void *opaque
, uint32_t addr
)
268 ParallelState
*s
= opaque
;
273 qemu_chr_ioctl(s
->chr
, CHR_IOCTL_PP_READ_DATA
, &ret
);
274 if (s
->last_read_offset
!= addr
|| s
->datar
!= ret
)
275 pdebug("rd%02x\n", ret
);
279 qemu_chr_ioctl(s
->chr
, CHR_IOCTL_PP_READ_STATUS
, &ret
);
280 ret
&= ~PARA_STS_TMOUT
;
282 ret
|= PARA_STS_TMOUT
;
283 if (s
->last_read_offset
!= addr
|| s
->status
!= ret
)
284 pdebug("rs%02x\n", ret
);
288 /* s->control has some bits fixed to 1. It is zero only when
289 it has not been yet written to. */
290 if (s
->control
== 0) {
291 qemu_chr_ioctl(s
->chr
, CHR_IOCTL_PP_READ_CONTROL
, &ret
);
292 if (s
->last_read_offset
!= addr
)
293 pdebug("rc%02x\n", ret
);
298 if (s
->last_read_offset
!= addr
)
299 pdebug("rc%02x\n", ret
);
302 case PARA_REG_EPP_ADDR
:
303 if ((s
->control
& (PARA_CTR_DIR
|PARA_CTR_SIGNAL
)) != (PARA_CTR_DIR
|PARA_CTR_INIT
))
304 /* Controls not correct for EPP addr cycle, so do nothing */
305 pdebug("ra%02x s\n", ret
);
307 struct ParallelIOArg ioarg
= { .buffer
= &ret
, .count
= 1 };
308 if (qemu_chr_ioctl(s
->chr
, CHR_IOCTL_PP_EPP_READ_ADDR
, &ioarg
)) {
310 pdebug("ra%02x t\n", ret
);
313 pdebug("ra%02x\n", ret
);
316 case PARA_REG_EPP_DATA
:
317 if ((s
->control
& (PARA_CTR_DIR
|PARA_CTR_SIGNAL
)) != (PARA_CTR_DIR
|PARA_CTR_INIT
))
318 /* Controls not correct for EPP data cycle, so do nothing */
319 pdebug("re%02x s\n", ret
);
321 struct ParallelIOArg ioarg
= { .buffer
= &ret
, .count
= 1 };
322 if (qemu_chr_ioctl(s
->chr
, CHR_IOCTL_PP_EPP_READ
, &ioarg
)) {
324 pdebug("re%02x t\n", ret
);
327 pdebug("re%02x\n", ret
);
331 s
->last_read_offset
= addr
;
336 parallel_ioport_eppdata_read_hw2(void *opaque
, uint32_t addr
)
338 ParallelState
*s
= opaque
;
340 uint16_t eppdata
= ~0;
342 struct ParallelIOArg ioarg
= {
343 .buffer
= &eppdata
, .count
= sizeof(eppdata
)
345 if ((s
->control
& (PARA_CTR_DIR
|PARA_CTR_SIGNAL
)) != (PARA_CTR_DIR
|PARA_CTR_INIT
)) {
346 /* Controls not correct for EPP data cycle, so do nothing */
347 pdebug("re%04x s\n", eppdata
);
350 err
= qemu_chr_ioctl(s
->chr
, CHR_IOCTL_PP_EPP_READ
, &ioarg
);
351 ret
= le16_to_cpu(eppdata
);
355 pdebug("re%04x t\n", ret
);
358 pdebug("re%04x\n", ret
);
363 parallel_ioport_eppdata_read_hw4(void *opaque
, uint32_t addr
)
365 ParallelState
*s
= opaque
;
367 uint32_t eppdata
= ~0U;
369 struct ParallelIOArg ioarg
= {
370 .buffer
= &eppdata
, .count
= sizeof(eppdata
)
372 if ((s
->control
& (PARA_CTR_DIR
|PARA_CTR_SIGNAL
)) != (PARA_CTR_DIR
|PARA_CTR_INIT
)) {
373 /* Controls not correct for EPP data cycle, so do nothing */
374 pdebug("re%08x s\n", eppdata
);
377 err
= qemu_chr_ioctl(s
->chr
, CHR_IOCTL_PP_EPP_READ
, &ioarg
);
378 ret
= le32_to_cpu(eppdata
);
382 pdebug("re%08x t\n", ret
);
385 pdebug("re%08x\n", ret
);
389 static void parallel_ioport_ecp_write(void *opaque
, uint32_t addr
, uint32_t val
)
392 pdebug("wecp%d=%02x\n", addr
, val
);
395 static uint32_t parallel_ioport_ecp_read(void *opaque
, uint32_t addr
)
399 pdebug("recp%d:%02x\n", addr
, ret
);
403 /* If fd is zero, it means that the parallel device uses the console */
404 ParallelState
*parallel_init(int base
, int irq
, CharDriverState
*chr
)
409 s
= qemu_mallocz(sizeof(ParallelState
));
414 s
->status
= PARA_STS_BUSY
;
415 s
->status
|= PARA_STS_ACK
;
416 s
->status
|= PARA_STS_ONLINE
;
417 s
->status
|= PARA_STS_ERROR
;
418 s
->control
= PARA_CTR_SELECT
;
419 s
->control
|= PARA_CTR_INIT
;
425 s
->last_read_offset
= ~0U;
427 if (qemu_chr_ioctl(chr
, CHR_IOCTL_PP_READ_STATUS
, &dummy
) == 0) {
433 register_ioport_write(base
, 8, 1, parallel_ioport_write_hw
, s
);
434 register_ioport_read(base
, 8, 1, parallel_ioport_read_hw
, s
);
435 register_ioport_write(base
+4, 1, 2, parallel_ioport_eppdata_write_hw2
, s
);
436 register_ioport_read(base
+4, 1, 2, parallel_ioport_eppdata_read_hw2
, s
);
437 register_ioport_write(base
+4, 1, 4, parallel_ioport_eppdata_write_hw4
, s
);
438 register_ioport_read(base
+4, 1, 4, parallel_ioport_eppdata_read_hw4
, s
);
439 register_ioport_write(base
+0x400, 8, 1, parallel_ioport_ecp_write
, s
);
440 register_ioport_read(base
+0x400, 8, 1, parallel_ioport_ecp_read
, s
);
443 register_ioport_write(base
, 8, 1, parallel_ioport_write_sw
, s
);
444 register_ioport_read(base
, 8, 1, parallel_ioport_read_sw
, s
);