hw/pc.c

   1 /*
   2  * QEMU PC System Emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pc.h"
  26 #include "apic.h"
  27 #include "fdc.h"
  28 #include "ide.h"
  29 #include "pci.h"
  30 #include "vmware_vga.h"
  31 #include "monitor.h"
  32 #include "fw_cfg.h"
  33 #include "hpet_emul.h"
  34 #include "smbios.h"
  35 #include "loader.h"
  36 #include "elf.h"
  37 #include "multiboot.h"
  38 #include "mc146818rtc.h"
  39 #include "msi.h"
  40 #include "sysbus.h"
  41 #include "sysemu.h"
  42 #include "kvm.h"
  43 #include "blockdev.h"
  44 #include "ui/qemu-spice.h"
  45 #include "memory.h"
  46 #include "exec-memory.h"
  47
  48 /* output Bochs bios info messages */
  49 //#define DEBUG_BIOS
  50
  51 /* debug PC/ISA interrupts */
  52 //#define DEBUG_IRQ
  53
  54 #ifdef DEBUG_IRQ
  55 #define DPRINTF(fmt, ...)                                       \
  56     do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
  57 #else
  58 #define DPRINTF(fmt, ...)
  59 #endif
  60
  61 #define BIOS_FILENAME "bios.bin"
  62
  63 #define PC_MAX_BIOS_SIZE (4 * 1024 * 1024)
  64
  65 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables.  */
  66 #define ACPI_DATA_SIZE       0x10000
  67 #define BIOS_CFG_IOPORT 0x510
  68 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
  69 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
  70 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
  71 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
  72 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
  73
  74 #define MSI_ADDR_BASE 0xfee00000
  75
  76 #define E820_NR_ENTRIES         16
  77
  78 struct e820_entry {
  79     uint64_t address;
  80     uint64_t length;
  81     uint32_t type;
  82 } QEMU_PACKED __attribute((__aligned__(4)));
  83
  84 struct e820_table {
  85     uint32_t count;
  86     struct e820_entry entry[E820_NR_ENTRIES];
  87 } QEMU_PACKED __attribute((__aligned__(4)));
  88
  89 static struct e820_table e820_table;
  90 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
  91
  92 void gsi_handler(void *opaque, int n, int level)
  93 {
  94     GSIState *s = opaque;
  95
  96     DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n);
  97     if (n < ISA_NUM_IRQS) {
  98         qemu_set_irq(s->i8259_irq[n], level);
  99     }
 100     qemu_set_irq(s->ioapic_irq[n], level);
 101 }
 102
 103 static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
 104 {
 105 }
 106
 107 /* MSDOS compatibility mode FPU exception support */
 108 static qemu_irq ferr_irq;
 109
 110 void pc_register_ferr_irq(qemu_irq irq)
 111 {
 112     ferr_irq = irq;
 113 }
 114
 115 /* XXX: add IGNNE support */
 116 void cpu_set_ferr(CPUX86State *s)
 117 {
 118     qemu_irq_raise(ferr_irq);
 119 }
 120
 121 static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data)
 122 {
 123     qemu_irq_lower(ferr_irq);
 124 }
 125
 126 /* TSC handling */
 127 uint64_t cpu_get_tsc(CPUX86State *env)
 128 {
 129     return cpu_get_ticks();
 130 }
 131
 132 /* SMM support */
 133
 134 static cpu_set_smm_t smm_set;
 135 static void *smm_arg;
 136
 137 void cpu_smm_register(cpu_set_smm_t callback, void *arg)
 138 {
 139     assert(smm_set == NULL);
 140     assert(smm_arg == NULL);
 141     smm_set = callback;
 142     smm_arg = arg;
 143 }
 144
 145 void cpu_smm_update(CPUState *env)
 146 {
 147     if (smm_set && smm_arg && env == first_cpu)
 148         smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg);
 149 }
 150
 151
 152 /* IRQ handling */
 153 int cpu_get_pic_interrupt(CPUState *env)
 154 {
 155     int intno;
 156
 157     intno = apic_get_interrupt(env->apic_state);
 158     if (intno >= 0) {
 159         return intno;
 160     }
 161     /* read the irq from the PIC */
 162     if (!apic_accept_pic_intr(env->apic_state)) {
 163         return -1;
 164     }
 165
 166     intno = pic_read_irq(isa_pic);
 167     return intno;
 168 }
 169
 170 static void pic_irq_request(void *opaque, int irq, int level)
 171 {
 172     CPUState *env = first_cpu;
 173
 174     DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
 175     if (env->apic_state) {
 176         while (env) {
 177             if (apic_accept_pic_intr(env->apic_state)) {
 178                 apic_deliver_pic_intr(env->apic_state, level);
 179             }
 180             env = env->next_cpu;
 181         }
 182     } else {
 183         if (level)
 184             cpu_interrupt(env, CPU_INTERRUPT_HARD);
 185         else
 186             cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 187     }
 188 }
 189
 190 /* PC cmos mappings */
 191
 192 #define REG_EQUIPMENT_BYTE          0x14
 193
 194 static int cmos_get_fd_drive_type(FDriveType fd0)
 195 {
 196     int val;
 197
 198     switch (fd0) {
 199     case FDRIVE_DRV_144:
 200         /* 1.44 Mb 3"5 drive */
 201         val = 4;
 202         break;
 203     case FDRIVE_DRV_288:
 204         /* 2.88 Mb 3"5 drive */
 205         val = 5;
 206         break;
 207     case FDRIVE_DRV_120:
 208         /* 1.2 Mb 5"5 drive */
 209         val = 2;
 210         break;
 211     case FDRIVE_DRV_NONE:
 212     default:
 213         val = 0;
 214         break;
 215     }
 216     return val;
 217 }
 218
 219 static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd,
 220                          ISADevice *s)
 221 {
 222     int cylinders, heads, sectors;
 223     bdrv_get_geometry_hint(hd, &cylinders, &heads, &sectors);
 224     rtc_set_memory(s, type_ofs, 47);
 225     rtc_set_memory(s, info_ofs, cylinders);
 226     rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
 227     rtc_set_memory(s, info_ofs + 2, heads);
 228     rtc_set_memory(s, info_ofs + 3, 0xff);
 229     rtc_set_memory(s, info_ofs + 4, 0xff);
 230     rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
 231     rtc_set_memory(s, info_ofs + 6, cylinders);
 232     rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
 233     rtc_set_memory(s, info_ofs + 8, sectors);
 234 }
 235
 236 /* convert boot_device letter to something recognizable by the bios */
 237 static int boot_device2nibble(char boot_device)
 238 {
 239     switch(boot_device) {
 240     case 'a':
 241     case 'b':
 242         return 0x01; /* floppy boot */
 243     case 'c':
 244         return 0x02; /* hard drive boot */
 245     case 'd':
 246         return 0x03; /* CD-ROM boot */
 247     case 'n':
 248         return 0x04; /* Network boot */
 249     }
 250     return 0;
 251 }
 252
 253 static int set_boot_dev(ISADevice *s, const char *boot_device, int fd_bootchk)
 254 {
 255 #define PC_MAX_BOOT_DEVICES 3
 256     int nbds, bds[3] = { 0, };
 257     int i;
 258
 259     nbds = strlen(boot_device);
 260     if (nbds > PC_MAX_BOOT_DEVICES) {
 261         error_report("Too many boot devices for PC");
 262         return(1);
 263     }
 264     for (i = 0; i < nbds; i++) {
 265         bds[i] = boot_device2nibble(boot_device[i]);
 266         if (bds[i] == 0) {
 267             error_report("Invalid boot device for PC: '%c'",
 268                          boot_device[i]);
 269             return(1);
 270         }
 271     }
 272     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
 273     rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
 274     return(0);
 275 }
 276
 277 static int pc_boot_set(void *opaque, const char *boot_device)
 278 {
 279     return set_boot_dev(opaque, boot_device, 0);
 280 }
 281
 282 typedef struct pc_cmos_init_late_arg {
 283     ISADevice *rtc_state;
 284     BusState *idebus0, *idebus1;
 285 } pc_cmos_init_late_arg;
 286
 287 static void pc_cmos_init_late(void *opaque)
 288 {
 289     pc_cmos_init_late_arg *arg = opaque;
 290     ISADevice *s = arg->rtc_state;
 291     int val;
 292     BlockDriverState *hd_table[4];
 293     int i;
 294
 295     ide_get_bs(hd_table, arg->idebus0);
 296     ide_get_bs(hd_table + 2, arg->idebus1);
 297
 298     rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0));
 299     if (hd_table[0])
 300         cmos_init_hd(0x19, 0x1b, hd_table[0], s);
 301     if (hd_table[1])
 302         cmos_init_hd(0x1a, 0x24, hd_table[1], s);
 303
 304     val = 0;
 305     for (i = 0; i < 4; i++) {
 306         if (hd_table[i]) {
 307             int cylinders, heads, sectors, translation;
 308             /* NOTE: bdrv_get_geometry_hint() returns the physical
 309                 geometry.  It is always such that: 1 <= sects <= 63, 1
 310                 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
 311                 geometry can be different if a translation is done. */
 312             translation = bdrv_get_translation_hint(hd_table[i]);
 313             if (translation == BIOS_ATA_TRANSLATION_AUTO) {
 314                 bdrv_get_geometry_hint(hd_table[i], &cylinders, &heads, &sectors);
 315                 if (cylinders <= 1024 && heads <= 16 && sectors <= 63) {
 316                     /* No translation. */
 317                     translation = 0;
 318                 } else {
 319                     /* LBA translation. */
 320                     translation = 1;
 321                 }
 322             } else {
 323                 translation--;
 324             }
 325             val |= translation << (i * 2);
 326         }
 327     }
 328     rtc_set_memory(s, 0x39, val);
 329
 330     qemu_unregister_reset(pc_cmos_init_late, opaque);
 331 }
 332
 333 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
 334                   const char *boot_device,
 335                   ISADevice *floppy, BusState *idebus0, BusState *idebus1,
 336                   ISADevice *s)
 337 {
 338     int val, nb, nb_heads, max_track, last_sect, i;
 339     FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE };
 340     BlockDriverState *fd[MAX_FD];
 341     static pc_cmos_init_late_arg arg;
 342
 343     /* various important CMOS locations needed by PC/Bochs bios */
 344
 345     /* memory size */
 346     val = 640; /* base memory in K */
 347     rtc_set_memory(s, 0x15, val);
 348     rtc_set_memory(s, 0x16, val >> 8);
 349
 350     val = (ram_size / 1024) - 1024;
 351     if (val > 65535)
 352         val = 65535;
 353     rtc_set_memory(s, 0x17, val);
 354     rtc_set_memory(s, 0x18, val >> 8);
 355     rtc_set_memory(s, 0x30, val);
 356     rtc_set_memory(s, 0x31, val >> 8);
 357
 358     if (above_4g_mem_size) {
 359         rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16);
 360         rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24);
 361         rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32);
 362     }
 363
 364     if (ram_size > (16 * 1024 * 1024))
 365         val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
 366     else
 367         val = 0;
 368     if (val > 65535)
 369         val = 65535;
 370     rtc_set_memory(s, 0x34, val);
 371     rtc_set_memory(s, 0x35, val >> 8);
 372
 373     /* set the number of CPU */
 374     rtc_set_memory(s, 0x5f, smp_cpus - 1);
 375
 376     /* set boot devices, and disable floppy signature check if requested */
 377     if (set_boot_dev(s, boot_device, fd_bootchk)) {
 378         exit(1);
 379     }
 380
 381     /* floppy type */
 382     if (floppy) {
 383         fdc_get_bs(fd, floppy);
 384         for (i = 0; i < 2; i++) {
 385             if (fd[i] && bdrv_is_inserted(fd[i])) {
 386                 bdrv_get_floppy_geometry_hint(fd[i], &nb_heads, &max_track,
 387                                               &last_sect, FDRIVE_DRV_NONE,
 388                                               &fd_type[i]);
 389             }
 390         }
 391     }
 392     val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
 393         cmos_get_fd_drive_type(fd_type[1]);
 394     rtc_set_memory(s, 0x10, val);
 395
 396     val = 0;
 397     nb = 0;
 398     if (fd_type[0] < FDRIVE_DRV_NONE) {
 399         nb++;
 400     }
 401     if (fd_type[1] < FDRIVE_DRV_NONE) {
 402         nb++;
 403     }
 404     switch (nb) {
 405     case 0:
 406         break;
 407     case 1:
 408         val |= 0x01; /* 1 drive, ready for boot */
 409         break;
 410     case 2:
 411         val |= 0x41; /* 2 drives, ready for boot */
 412         break;
 413     }
 414     val |= 0x02; /* FPU is there */
 415     val |= 0x04; /* PS/2 mouse installed */
 416     rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
 417
 418     /* hard drives */
 419     arg.rtc_state = s;
 420     arg.idebus0 = idebus0;
 421     arg.idebus1 = idebus1;
 422     qemu_register_reset(pc_cmos_init_late, &arg);
 423 }
 424
 425 /* port 92 stuff: could be split off */
 426 typedef struct Port92State {
 427     ISADevice dev;
 428     MemoryRegion io;
 429     uint8_t outport;
 430     qemu_irq *a20_out;
 431 } Port92State;
 432
 433 static void port92_write(void *opaque, uint32_t addr, uint32_t val)
 434 {
 435     Port92State *s = opaque;
 436
 437     DPRINTF("port92: write 0x%02x\n", val);
 438     s->outport = val;
 439     qemu_set_irq(*s->a20_out, (val >> 1) & 1);
 440     if (val & 1) {
 441         qemu_system_reset_request();
 442     }
 443 }
 444
 445 static uint32_t port92_read(void *opaque, uint32_t addr)
 446 {
 447     Port92State *s = opaque;
 448     uint32_t ret;
 449
 450     ret = s->outport;
 451     DPRINTF("port92: read 0x%02x\n", ret);
 452     return ret;
 453 }
 454
 455 static void port92_init(ISADevice *dev, qemu_irq *a20_out)
 456 {
 457     Port92State *s = DO_UPCAST(Port92State, dev, dev);
 458
 459     s->a20_out = a20_out;
 460 }
 461
 462 static const VMStateDescription vmstate_port92_isa = {
 463     .name = "port92",
 464     .version_id = 1,
 465     .minimum_version_id = 1,
 466     .minimum_version_id_old = 1,
 467     .fields      = (VMStateField []) {
 468         VMSTATE_UINT8(outport, Port92State),
 469         VMSTATE_END_OF_LIST()
 470     }
 471 };
 472
 473 static void port92_reset(DeviceState *d)
 474 {
 475     Port92State *s = container_of(d, Port92State, dev.qdev);
 476
 477     s->outport &= ~1;
 478 }
 479
 480 static const MemoryRegionPortio port92_portio[] = {
 481     { 0, 1, 1, .read = port92_read, .write = port92_write },
 482     PORTIO_END_OF_LIST(),
 483 };
 484
 485 static const MemoryRegionOps port92_ops = {
 486     .old_portio = port92_portio
 487 };
 488
 489 static int port92_initfn(ISADevice *dev)
 490 {
 491     Port92State *s = DO_UPCAST(Port92State, dev, dev);
 492
 493     memory_region_init_io(&s->io, &port92_ops, s, "port92", 1);
 494     isa_register_ioport(dev, &s->io, 0x92);
 495
 496     s->outport = 0;
 497     return 0;
 498 }
 499
 500 static void port92_class_initfn(ObjectClass *klass, void *data)
 501 {
 502     DeviceClass *dc = DEVICE_CLASS(klass);
 503     ISADeviceClass *ic = ISA_DEVICE_CLASS(klass);
 504     ic->init = port92_initfn;
 505     dc->no_user = 1;
 506     dc->reset = port92_reset;
 507     dc->vmsd = &vmstate_port92_isa;
 508 }
 509
 510 static TypeInfo port92_info = {
 511     .name          = "port92",
 512     .parent        = TYPE_ISA_DEVICE,
 513     .instance_size = sizeof(Port92State),
 514     .class_init    = port92_class_initfn,
 515 };
 516
 517 static void port92_register(void)
 518 {
 519     type_register_static(&port92_info);
 520 }
 521 device_init(port92_register)
 522
 523 static void handle_a20_line_change(void *opaque, int irq, int level)
 524 {
 525     CPUState *cpu = opaque;
 526
 527     /* XXX: send to all CPUs ? */
 528     /* XXX: add logic to handle multiple A20 line sources */
 529     cpu_x86_set_a20(cpu, level);
 530 }
 531
 532 /***********************************************************/
 533 /* Bochs BIOS debug ports */
 534
 535 static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
 536 {
 537     static const char shutdown_str[8] = "Shutdown";
 538     static int shutdown_index = 0;
 539
 540     switch(addr) {
 541         /* Bochs BIOS messages */
 542     case 0x400:
 543     case 0x401:
 544         /* used to be panic, now unused */
 545         break;
 546     case 0x402:
 547     case 0x403:
 548 #ifdef DEBUG_BIOS
 549         fprintf(stderr, "%c", val);
 550 #endif
 551         break;
 552     case 0x8900:
 553         /* same as Bochs power off */
 554         if (val == shutdown_str[shutdown_index]) {
 555             shutdown_index++;
 556             if (shutdown_index == 8) {
 557                 shutdown_index = 0;
 558                 qemu_system_shutdown_request();
 559             }
 560         } else {
 561             shutdown_index = 0;
 562         }
 563         break;
 564
 565         /* LGPL'ed VGA BIOS messages */
 566     case 0x501:
 567     case 0x502:
 568         exit((val << 1) | 1);
 569     case 0x500:
 570     case 0x503:
 571 #ifdef DEBUG_BIOS
 572         fprintf(stderr, "%c", val);
 573 #endif
 574         break;
 575     }
 576 }
 577
 578 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
 579 {
 580     int index = le32_to_cpu(e820_table.count);
 581     struct e820_entry *entry;
 582
 583     if (index >= E820_NR_ENTRIES)
 584         return -EBUSY;
 585     entry = &e820_table.entry[index++];
 586
 587     entry->address = cpu_to_le64(address);
 588     entry->length = cpu_to_le64(length);
 589     entry->type = cpu_to_le32(type);
 590
 591     e820_table.count = cpu_to_le32(index);
 592     return index;
 593 }
 594
 595 static void *bochs_bios_init(void)
 596 {
 597     void *fw_cfg;
 598     uint8_t *smbios_table;
 599     size_t smbios_len;
 600     uint64_t *numa_fw_cfg;
 601     int i, j;
 602
 603     register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL);
 604     register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL);
 605     register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL);
 606     register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL);
 607     register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL);
 608
 609     register_ioport_write(0x501, 1, 1, bochs_bios_write, NULL);
 610     register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL);
 611     register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL);
 612     register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL);
 613     register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL);
 614
 615     fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
 616
 617     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 618     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 619     fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables,
 620                      acpi_tables_len);
 621     fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
 622
 623     smbios_table = smbios_get_table(&smbios_len);
 624     if (smbios_table)
 625         fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
 626                          smbios_table, smbios_len);
 627     fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, (uint8_t *)&e820_table,
 628                      sizeof(struct e820_table));
 629
 630     fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, (uint8_t *)&hpet_cfg,
 631                      sizeof(struct hpet_fw_config));
 632     /* allocate memory for the NUMA channel: one (64bit) word for the number
 633      * of nodes, one word for each VCPU->node and one word for each node to
 634      * hold the amount of memory.
 635      */
 636     numa_fw_cfg = g_malloc0((1 + max_cpus + nb_numa_nodes) * 8);
 637     numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
 638     for (i = 0; i < max_cpus; i++) {
 639         for (j = 0; j < nb_numa_nodes; j++) {
 640             if (node_cpumask[j] & (1 << i)) {
 641                 numa_fw_cfg[i + 1] = cpu_to_le64(j);
 642                 break;
 643             }
 644         }
 645     }
 646     for (i = 0; i < nb_numa_nodes; i++) {
 647         numa_fw_cfg[max_cpus + 1 + i] = cpu_to_le64(node_mem[i]);
 648     }
 649     fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg,
 650                      (1 + max_cpus + nb_numa_nodes) * 8);
 651
 652     return fw_cfg;
 653 }
 654
 655 static long get_file_size(FILE *f)
 656 {
 657     long where, size;
 658
 659     /* XXX: on Unix systems, using fstat() probably makes more sense */
 660
 661     where = ftell(f);
 662     fseek(f, 0, SEEK_END);
 663     size = ftell(f);
 664     fseek(f, where, SEEK_SET);
 665
 666     return size;
 667 }
 668
 669 static void load_linux(void *fw_cfg,
 670                        const char *kernel_filename,
 671                        const char *initrd_filename,
 672                        const char *kernel_cmdline,
 673                        target_phys_addr_t max_ram_size)
 674 {
 675     uint16_t protocol;
 676     int setup_size, kernel_size, initrd_size = 0, cmdline_size;
 677     uint32_t initrd_max;
 678     uint8_t header[8192], *setup, *kernel, *initrd_data;
 679     target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
 680     FILE *f;
 681     char *vmode;
 682
 683     /* Align to 16 bytes as a paranoia measure */
 684     cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
 685
 686     /* load the kernel header */
 687     f = fopen(kernel_filename, "rb");
 688     if (!f || !(kernel_size = get_file_size(f)) ||
 689         fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
 690         MIN(ARRAY_SIZE(header), kernel_size)) {
 691         fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
 692                 kernel_filename, strerror(errno));
 693         exit(1);
 694     }
 695
 696     /* kernel protocol version */
 697 #if 0
 698     fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
 699 #endif
 700     if (ldl_p(header+0x202) == 0x53726448)
 701         protocol = lduw_p(header+0x206);
 702     else {
 703         /* This looks like a multiboot kernel. If it is, let's stop
 704            treating it like a Linux kernel. */
 705         if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
 706                            kernel_cmdline, kernel_size, header))
 707             return;
 708         protocol = 0;
 709     }
 710
 711     if (protocol < 0x200 || !(header[0x211] & 0x01)) {
 712         /* Low kernel */
 713         real_addr    = 0x90000;
 714         cmdline_addr = 0x9a000 - cmdline_size;
 715         prot_addr    = 0x10000;
 716     } else if (protocol < 0x202) {
 717         /* High but ancient kernel */
 718         real_addr    = 0x90000;
 719         cmdline_addr = 0x9a000 - cmdline_size;
 720         prot_addr    = 0x100000;
 721     } else {
 722         /* High and recent kernel */
 723         real_addr    = 0x10000;
 724         cmdline_addr = 0x20000;
 725         prot_addr    = 0x100000;
 726     }
 727
 728 #if 0
 729     fprintf(stderr,
 730             "qemu: real_addr     = 0x" TARGET_FMT_plx "\n"
 731             "qemu: cmdline_addr  = 0x" TARGET_FMT_plx "\n"
 732             "qemu: prot_addr     = 0x" TARGET_FMT_plx "\n",
 733             real_addr,
 734             cmdline_addr,
 735             prot_addr);
 736 #endif
 737
 738     /* highest address for loading the initrd */
 739     if (protocol >= 0x203)
 740         initrd_max = ldl_p(header+0x22c);
 741     else
 742         initrd_max = 0x37ffffff;
 743
 744     if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
 745         initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
 746
 747     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
 748     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
 749     fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
 750                      (uint8_t*)strdup(kernel_cmdline),
 751                      strlen(kernel_cmdline)+1);
 752
 753     if (protocol >= 0x202) {
 754         stl_p(header+0x228, cmdline_addr);
 755     } else {
 756         stw_p(header+0x20, 0xA33F);
 757         stw_p(header+0x22, cmdline_addr-real_addr);
 758     }
 759
 760     /* handle vga= parameter */
 761     vmode = strstr(kernel_cmdline, "vga=");
 762     if (vmode) {
 763         unsigned int video_mode;
 764         /* skip "vga=" */
 765         vmode += 4;
 766         if (!strncmp(vmode, "normal", 6)) {
 767             video_mode = 0xffff;
 768         } else if (!strncmp(vmode, "ext", 3)) {
 769             video_mode = 0xfffe;
 770         } else if (!strncmp(vmode, "ask", 3)) {
 771             video_mode = 0xfffd;
 772         } else {
 773             video_mode = strtol(vmode, NULL, 0);
 774         }
 775         stw_p(header+0x1fa, video_mode);
 776     }
 777
 778     /* loader type */
 779     /* High nybble = B reserved for Qemu; low nybble is revision number.
 780        If this code is substantially changed, you may want to consider
 781        incrementing the revision. */
 782     if (protocol >= 0x200)
 783         header[0x210] = 0xB0;
 784
 785     /* heap */
 786     if (protocol >= 0x201) {
 787         header[0x211] |= 0x80;  /* CAN_USE_HEAP */
 788         stw_p(header+0x224, cmdline_addr-real_addr-0x200);
 789     }
 790
 791     /* load initrd */
 792     if (initrd_filename) {
 793         if (protocol < 0x200) {
 794             fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
 795             exit(1);
 796         }
 797
 798         initrd_size = get_image_size(initrd_filename);
 799         if (initrd_size < 0) {
 800             fprintf(stderr, "qemu: error reading initrd %s\n",
 801                     initrd_filename);
 802             exit(1);
 803         }
 804
 805         initrd_addr = (initrd_max-initrd_size) & ~4095;
 806
 807         initrd_data = g_malloc(initrd_size);
 808         load_image(initrd_filename, initrd_data);
 809
 810         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
 811         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 812         fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
 813
 814         stl_p(header+0x218, initrd_addr);
 815         stl_p(header+0x21c, initrd_size);
 816     }
 817
 818     /* load kernel and setup */
 819     setup_size = header[0x1f1];
 820     if (setup_size == 0)
 821         setup_size = 4;
 822     setup_size = (setup_size+1)*512;
 823     kernel_size -= setup_size;
 824
 825     setup  = g_malloc(setup_size);
 826     kernel = g_malloc(kernel_size);
 827     fseek(f, 0, SEEK_SET);
 828     if (fread(setup, 1, setup_size, f) != setup_size) {
 829         fprintf(stderr, "fread() failed\n");
 830         exit(1);
 831     }
 832     if (fread(kernel, 1, kernel_size, f) != kernel_size) {
 833         fprintf(stderr, "fread() failed\n");
 834         exit(1);
 835     }
 836     fclose(f);
 837     memcpy(setup, header, MIN(sizeof(header), setup_size));
 838
 839     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
 840     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 841     fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
 842
 843     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
 844     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
 845     fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
 846
 847     option_rom[nb_option_roms].name = "linuxboot.bin";
 848     option_rom[nb_option_roms].bootindex = 0;
 849     nb_option_roms++;
 850 }
 851
 852 #define NE2000_NB_MAX 6
 853
 854 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
 855                                               0x280, 0x380 };
 856 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
 857
 858 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 859 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
 860
 861 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
 862 {
 863     static int nb_ne2k = 0;
 864
 865     if (nb_ne2k == NE2000_NB_MAX)
 866         return;
 867     isa_ne2000_init(bus, ne2000_io[nb_ne2k],
 868                     ne2000_irq[nb_ne2k], nd);
 869     nb_ne2k++;
 870 }
 871
 872 int cpu_is_bsp(CPUState *env)
 873 {
 874     /* We hard-wire the BSP to the first CPU. */
 875     return env->cpu_index == 0;
 876 }
 877
 878 DeviceState *cpu_get_current_apic(void)
 879 {
 880     if (cpu_single_env) {
 881         return cpu_single_env->apic_state;
 882     } else {
 883         return NULL;
 884     }
 885 }
 886
 887 static DeviceState *apic_init(void *env, uint8_t apic_id)
 888 {
 889     DeviceState *dev;
 890     static int apic_mapped;
 891
 892     if (kvm_irqchip_in_kernel()) {
 893         dev = qdev_create(NULL, "kvm-apic");
 894     } else {
 895         dev = qdev_create(NULL, "apic");
 896     }
 897     qdev_prop_set_uint8(dev, "id", apic_id);
 898     qdev_prop_set_ptr(dev, "cpu_env", env);
 899     qdev_init_nofail(dev);
 900
 901     /* XXX: mapping more APICs at the same memory location */
 902     if (apic_mapped == 0) {
 903         /* NOTE: the APIC is directly connected to the CPU - it is not
 904            on the global memory bus. */
 905         /* XXX: what if the base changes? */
 906         sysbus_mmio_map(sysbus_from_qdev(dev), 0, MSI_ADDR_BASE);
 907         apic_mapped = 1;
 908     }
 909
 910     /* KVM does not support MSI yet. */
 911     if (!kvm_irqchip_in_kernel()) {
 912         msi_supported = true;
 913     }
 914
 915     return dev;
 916 }
 917
 918 /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
 919    BIOS will read it and start S3 resume at POST Entry */
 920 void pc_cmos_set_s3_resume(void *opaque, int irq, int level)
 921 {
 922     ISADevice *s = opaque;
 923
 924     if (level) {
 925         rtc_set_memory(s, 0xF, 0xFE);
 926     }
 927 }
 928
 929 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
 930 {
 931     CPUState *s = opaque;
 932
 933     if (level) {
 934         cpu_interrupt(s, CPU_INTERRUPT_SMI);
 935     }
 936 }
 937
 938 static void pc_cpu_reset(void *opaque)
 939 {
 940     CPUState *env = opaque;
 941
 942     cpu_reset(env);
 943     env->halted = !cpu_is_bsp(env);
 944 }
 945
 946 static CPUState *pc_new_cpu(const char *cpu_model)
 947 {
 948     CPUState *env;
 949
 950     env = cpu_init(cpu_model);
 951     if (!env) {
 952         fprintf(stderr, "Unable to find x86 CPU definition\n");
 953         exit(1);
 954     }
 955     if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) {
 956         env->apic_state = apic_init(env, env->cpuid_apic_id);
 957     }
 958     qemu_register_reset(pc_cpu_reset, env);
 959     pc_cpu_reset(env);
 960     return env;
 961 }
 962
 963 void pc_cpus_init(const char *cpu_model)
 964 {
 965     int i;
 966
 967     /* init CPUs */
 968     if (cpu_model == NULL) {
 969 #ifdef TARGET_X86_64
 970         cpu_model = "qemu64";
 971 #else
 972         cpu_model = "qemu32";
 973 #endif
 974     }
 975
 976     for(i = 0; i < smp_cpus; i++) {
 977         pc_new_cpu(cpu_model);
 978     }
 979 }
 980
 981 void pc_memory_init(MemoryRegion *system_memory,
 982                     const char *kernel_filename,
 983                     const char *kernel_cmdline,
 984                     const char *initrd_filename,
 985                     ram_addr_t below_4g_mem_size,
 986                     ram_addr_t above_4g_mem_size,
 987                     MemoryRegion *rom_memory,
 988                     MemoryRegion **ram_memory)
 989 {
 990     char *filename;
 991     int ret, linux_boot, i;
 992     MemoryRegion *ram, *bios, *isa_bios, *option_rom_mr;
 993     MemoryRegion *ram_below_4g, *ram_above_4g;
 994     int bios_size, isa_bios_size;
 995     void *fw_cfg;
 996
 997     linux_boot = (kernel_filename != NULL);
 998
 999     /* Allocate RAM.  We allocate it as a single memory region and use
1000      * aliases to address portions of it, mostly for backwards compatibility
1001      * with older qemus that used qemu_ram_alloc().
1002      */
1003     ram = g_malloc(sizeof(*ram));
1004     memory_region_init_ram(ram, "pc.ram",
1005                            below_4g_mem_size + above_4g_mem_size);
1006     vmstate_register_ram_global(ram);
1007     *ram_memory = ram;
1008     ram_below_4g = g_malloc(sizeof(*ram_below_4g));
1009     memory_region_init_alias(ram_below_4g, "ram-below-4g", ram,
1010                              0, below_4g_mem_size);
1011     memory_region_add_subregion(system_memory, 0, ram_below_4g);
1012     if (above_4g_mem_size > 0) {
1013         ram_above_4g = g_malloc(sizeof(*ram_above_4g));
1014         memory_region_init_alias(ram_above_4g, "ram-above-4g", ram,
1015                                  below_4g_mem_size, above_4g_mem_size);
1016         memory_region_add_subregion(system_memory, 0x100000000ULL,
1017                                     ram_above_4g);
1018     }
1019
1020     /* BIOS load */
1021     if (bios_name == NULL)
1022         bios_name = BIOS_FILENAME;
1023     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1024     if (filename) {
1025         bios_size = get_image_size(filename);
1026     } else {
1027         bios_size = -1;
1028     }
1029     if (bios_size <= 0 ||
1030         (bios_size % 65536) != 0) {
1031         goto bios_error;
1032     }
1033     bios = g_malloc(sizeof(*bios));
1034     memory_region_init_ram(bios, "pc.bios", bios_size);
1035     vmstate_register_ram_global(bios);
1036     memory_region_set_readonly(bios, true);
1037     ret = rom_add_file_fixed(bios_name, (uint32_t)(-bios_size), -1);
1038     if (ret != 0) {
1039     bios_error:
1040         fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name);
1041         exit(1);
1042     }
1043     if (filename) {
1044         g_free(filename);
1045     }
1046     /* map the last 128KB of the BIOS in ISA space */
1047     isa_bios_size = bios_size;
1048     if (isa_bios_size > (128 * 1024))
1049         isa_bios_size = 128 * 1024;
1050     isa_bios = g_malloc(sizeof(*isa_bios));
1051     memory_region_init_alias(isa_bios, "isa-bios", bios,
1052                              bios_size - isa_bios_size, isa_bios_size);
1053     memory_region_add_subregion_overlap(rom_memory,
1054                                         0x100000 - isa_bios_size,
1055                                         isa_bios,
1056                                         1);
1057     memory_region_set_readonly(isa_bios, true);
1058
1059     option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1060     memory_region_init_ram(option_rom_mr, "pc.rom", PC_ROM_SIZE);
1061     vmstate_register_ram_global(option_rom_mr);
1062     memory_region_add_subregion_overlap(rom_memory,
1063                                         PC_ROM_MIN_VGA,
1064                                         option_rom_mr,
1065                                         1);
1066
1067     /* map all the bios at the top of memory */
1068     memory_region_add_subregion(rom_memory,
1069                                 (uint32_t)(-bios_size),
1070                                 bios);
1071
1072     fw_cfg = bochs_bios_init();
1073     rom_set_fw(fw_cfg);
1074
1075     if (linux_boot) {
1076         load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size);
1077     }
1078
1079     for (i = 0; i < nb_option_roms; i++) {
1080         rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1081     }
1082 }
1083
1084 qemu_irq *pc_allocate_cpu_irq(void)
1085 {
1086     return qemu_allocate_irqs(pic_irq_request, NULL, 1);
1087 }
1088
1089 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1090 {
1091     DeviceState *dev = NULL;
1092
1093     if (cirrus_vga_enabled) {
1094         if (pci_bus) {
1095             dev = pci_cirrus_vga_init(pci_bus);
1096         } else {
1097             dev = &isa_create_simple(isa_bus, "isa-cirrus-vga")->qdev;
1098         }
1099     } else if (vmsvga_enabled) {
1100         if (pci_bus) {
1101             dev = pci_vmsvga_init(pci_bus);
1102         } else {
1103             fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
1104         }
1105 #ifdef CONFIG_SPICE
1106     } else if (qxl_enabled) {
1107         if (pci_bus) {
1108             dev = &pci_create_simple(pci_bus, -1, "qxl-vga")->qdev;
1109         } else {
1110             fprintf(stderr, "%s: qxl: no PCI bus\n", __FUNCTION__);
1111         }
1112 #endif
1113     } else if (std_vga_enabled) {
1114         if (pci_bus) {
1115             dev = pci_vga_init(pci_bus);
1116         } else {
1117             dev = isa_vga_init(isa_bus);
1118         }
1119     }
1120
1121     return dev;
1122 }
1123
1124 static void cpu_request_exit(void *opaque, int irq, int level)
1125 {
1126     CPUState *env = cpu_single_env;
1127
1128     if (env && level) {
1129         cpu_exit(env);
1130     }
1131 }
1132
1133 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
1134                           ISADevice **rtc_state,
1135                           ISADevice **floppy,
1136                           bool no_vmport)
1137 {
1138     int i;
1139     DriveInfo *fd[MAX_FD];
1140     qemu_irq rtc_irq = NULL;
1141     qemu_irq *a20_line;
1142     ISADevice *i8042, *port92, *vmmouse, *pit;
1143     qemu_irq *cpu_exit_irq;
1144
1145     register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
1146
1147     register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL);
1148
1149     if (!no_hpet) {
1150         DeviceState *hpet = sysbus_try_create_simple("hpet", HPET_BASE, NULL);
1151
1152         if (hpet) {
1153             for (i = 0; i < GSI_NUM_PINS; i++) {
1154                 sysbus_connect_irq(sysbus_from_qdev(hpet), i, gsi[i]);
1155             }
1156             rtc_irq = qdev_get_gpio_in(hpet, 0);
1157         }
1158     }
1159     *rtc_state = rtc_init(isa_bus, 2000, rtc_irq);
1160
1161     qemu_register_boot_set(pc_boot_set, *rtc_state);
1162
1163     pit = pit_init(isa_bus, 0x40, 0);
1164     pcspk_init(pit);
1165
1166     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
1167         if (serial_hds[i]) {
1168             serial_isa_init(isa_bus, i, serial_hds[i]);
1169         }
1170     }
1171
1172     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
1173         if (parallel_hds[i]) {
1174             parallel_init(isa_bus, i, parallel_hds[i]);
1175         }
1176     }
1177
1178     a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1179     i8042 = isa_create_simple(isa_bus, "i8042");
1180     i8042_setup_a20_line(i8042, &a20_line[0]);
1181     if (!no_vmport) {
1182         vmport_init(isa_bus);
1183         vmmouse = isa_try_create(isa_bus, "vmmouse");
1184     } else {
1185         vmmouse = NULL;
1186     }
1187     if (vmmouse) {
1188         qdev_prop_set_ptr(&vmmouse->qdev, "ps2_mouse", i8042);
1189         qdev_init_nofail(&vmmouse->qdev);
1190     }
1191     port92 = isa_create_simple(isa_bus, "port92");
1192     port92_init(port92, &a20_line[1]);
1193
1194     cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
1195     DMA_init(0, cpu_exit_irq);
1196
1197     for(i = 0; i < MAX_FD; i++) {
1198         fd[i] = drive_get(IF_FLOPPY, 0, i);
1199     }
1200     *floppy = fdctrl_init_isa(isa_bus, fd);
1201 }
1202
1203 void pc_pci_device_init(PCIBus *pci_bus)
1204 {
1205     int max_bus;
1206     int bus;
1207
1208     max_bus = drive_get_max_bus(IF_SCSI);
1209     for (bus = 0; bus <= max_bus; bus++) {
1210         pci_create_simple(pci_bus, -1, "lsi53c895a");
1211     }
1212 }