hw/pc.c

   1 /*
   2  * QEMU PC System Emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pc.h"
  26 #include "apic.h"
  27 #include "fdc.h"
  28 #include "pci.h"
  29 #include "vmware_vga.h"
  30 #include "monitor.h"
  31 #include "fw_cfg.h"
  32 #include "hpet_emul.h"
  33 #include "smbios.h"
  34 #include "loader.h"
  35 #include "elf.h"
  36 #include "multiboot.h"
  37 #include "mc146818rtc.h"
  38
  39 /* output Bochs bios info messages */
  40 //#define DEBUG_BIOS
  41
  42 #define BIOS_FILENAME "bios.bin"
  43
  44 #define PC_MAX_BIOS_SIZE (4 * 1024 * 1024)
  45
  46 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables.  */
  47 #define ACPI_DATA_SIZE       0x10000
  48 #define BIOS_CFG_IOPORT 0x510
  49 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
  50 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
  51 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
  52 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
  53
  54 #define E820_NR_ENTRIES         16
  55
  56 struct e820_entry {
  57     uint64_t address;
  58     uint64_t length;
  59     uint32_t type;
  60 };
  61
  62 struct e820_table {
  63     uint32_t count;
  64     struct e820_entry entry[E820_NR_ENTRIES];
  65 };
  66
  67 static struct e820_table e820_table;
  68
  69 void isa_irq_handler(void *opaque, int n, int level)
  70 {
  71     IsaIrqState *isa = (IsaIrqState *)opaque;
  72
  73     if (n < 16) {
  74         qemu_set_irq(isa->i8259[n], level);
  75     }
  76     if (isa->ioapic)
  77         qemu_set_irq(isa->ioapic[n], level);
  78 };
  79
  80 static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
  81 {
  82 }
  83
  84 /* MSDOS compatibility mode FPU exception support */
  85 static qemu_irq ferr_irq;
  86
  87 void pc_register_ferr_irq(qemu_irq irq)
  88 {
  89     ferr_irq = irq;
  90 }
  91
  92 /* XXX: add IGNNE support */
  93 void cpu_set_ferr(CPUX86State *s)
  94 {
  95     qemu_irq_raise(ferr_irq);
  96 }
  97
  98 static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data)
  99 {
 100     qemu_irq_lower(ferr_irq);
 101 }
 102
 103 /* TSC handling */
 104 uint64_t cpu_get_tsc(CPUX86State *env)
 105 {
 106     return cpu_get_ticks();
 107 }
 108
 109 /* SMM support */
 110
 111 static cpu_set_smm_t smm_set;
 112 static void *smm_arg;
 113
 114 void cpu_smm_register(cpu_set_smm_t callback, void *arg)
 115 {
 116     assert(smm_set == NULL);
 117     assert(smm_arg == NULL);
 118     smm_set = callback;
 119     smm_arg = arg;
 120 }
 121
 122 void cpu_smm_update(CPUState *env)
 123 {
 124     if (smm_set && smm_arg && env == first_cpu)
 125         smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg);
 126 }
 127
 128
 129 /* IRQ handling */
 130 int cpu_get_pic_interrupt(CPUState *env)
 131 {
 132     int intno;
 133
 134     intno = apic_get_interrupt(env);
 135     if (intno >= 0) {
 136         /* set irq request if a PIC irq is still pending */
 137         /* XXX: improve that */
 138         pic_update_irq(isa_pic);
 139         return intno;
 140     }
 141     /* read the irq from the PIC */
 142     if (!apic_accept_pic_intr(env))
 143         return -1;
 144
 145     intno = pic_read_irq(isa_pic);
 146     return intno;
 147 }
 148
 149 static void pic_irq_request(void *opaque, int irq, int level)
 150 {
 151     CPUState *env = first_cpu;
 152
 153     if (env->apic_state) {
 154         while (env) {
 155             if (apic_accept_pic_intr(env))
 156                 apic_deliver_pic_intr(env, level);
 157             env = env->next_cpu;
 158         }
 159     } else {
 160         if (level)
 161             cpu_interrupt(env, CPU_INTERRUPT_HARD);
 162         else
 163             cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 164     }
 165 }
 166
 167 /* PC cmos mappings */
 168
 169 #define REG_EQUIPMENT_BYTE          0x14
 170
 171 static int cmos_get_fd_drive_type(int fd0)
 172 {
 173     int val;
 174
 175     switch (fd0) {
 176     case 0:
 177         /* 1.44 Mb 3"5 drive */
 178         val = 4;
 179         break;
 180     case 1:
 181         /* 2.88 Mb 3"5 drive */
 182         val = 5;
 183         break;
 184     case 2:
 185         /* 1.2 Mb 5"5 drive */
 186         val = 2;
 187         break;
 188     default:
 189         val = 0;
 190         break;
 191     }
 192     return val;
 193 }
 194
 195 static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd,
 196                          ISADevice *s)
 197 {
 198     int cylinders, heads, sectors;
 199     bdrv_get_geometry_hint(hd, &cylinders, &heads, &sectors);
 200     rtc_set_memory(s, type_ofs, 47);
 201     rtc_set_memory(s, info_ofs, cylinders);
 202     rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
 203     rtc_set_memory(s, info_ofs + 2, heads);
 204     rtc_set_memory(s, info_ofs + 3, 0xff);
 205     rtc_set_memory(s, info_ofs + 4, 0xff);
 206     rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
 207     rtc_set_memory(s, info_ofs + 6, cylinders);
 208     rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
 209     rtc_set_memory(s, info_ofs + 8, sectors);
 210 }
 211
 212 /* convert boot_device letter to something recognizable by the bios */
 213 static int boot_device2nibble(char boot_device)
 214 {
 215     switch(boot_device) {
 216     case 'a':
 217     case 'b':
 218         return 0x01; /* floppy boot */
 219     case 'c':
 220         return 0x02; /* hard drive boot */
 221     case 'd':
 222         return 0x03; /* CD-ROM boot */
 223     case 'n':
 224         return 0x04; /* Network boot */
 225     }
 226     return 0;
 227 }
 228
 229 static int set_boot_dev(ISADevice *s, const char *boot_device, int fd_bootchk)
 230 {
 231 #define PC_MAX_BOOT_DEVICES 3
 232     int nbds, bds[3] = { 0, };
 233     int i;
 234
 235     nbds = strlen(boot_device);
 236     if (nbds > PC_MAX_BOOT_DEVICES) {
 237         error_report("Too many boot devices for PC");
 238         return(1);
 239     }
 240     for (i = 0; i < nbds; i++) {
 241         bds[i] = boot_device2nibble(boot_device[i]);
 242         if (bds[i] == 0) {
 243             error_report("Invalid boot device for PC: '%c'",
 244                          boot_device[i]);
 245             return(1);
 246         }
 247     }
 248     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
 249     rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
 250     return(0);
 251 }
 252
 253 static int pc_boot_set(void *opaque, const char *boot_device)
 254 {
 255     return set_boot_dev(opaque, boot_device, 0);
 256 }
 257
 258 /* hd_table must contain 4 block drivers */
 259 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
 260                   const char *boot_device, DriveInfo **hd_table,
 261                   FDCtrl *floppy_controller, ISADevice *s)
 262 {
 263     int val;
 264     int fd0, fd1, nb;
 265     int i;
 266
 267     /* various important CMOS locations needed by PC/Bochs bios */
 268
 269     /* memory size */
 270     val = 640; /* base memory in K */
 271     rtc_set_memory(s, 0x15, val);
 272     rtc_set_memory(s, 0x16, val >> 8);
 273
 274     val = (ram_size / 1024) - 1024;
 275     if (val > 65535)
 276         val = 65535;
 277     rtc_set_memory(s, 0x17, val);
 278     rtc_set_memory(s, 0x18, val >> 8);
 279     rtc_set_memory(s, 0x30, val);
 280     rtc_set_memory(s, 0x31, val >> 8);
 281
 282     if (above_4g_mem_size) {
 283         rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16);
 284         rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24);
 285         rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32);
 286     }
 287
 288     if (ram_size > (16 * 1024 * 1024))
 289         val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
 290     else
 291         val = 0;
 292     if (val > 65535)
 293         val = 65535;
 294     rtc_set_memory(s, 0x34, val);
 295     rtc_set_memory(s, 0x35, val >> 8);
 296
 297     /* set the number of CPU */
 298     rtc_set_memory(s, 0x5f, smp_cpus - 1);
 299
 300     /* set boot devices, and disable floppy signature check if requested */
 301     if (set_boot_dev(s, boot_device, fd_bootchk)) {
 302         exit(1);
 303     }
 304
 305     /* floppy type */
 306
 307     fd0 = fdctrl_get_drive_type(floppy_controller, 0);
 308     fd1 = fdctrl_get_drive_type(floppy_controller, 1);
 309
 310     val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1);
 311     rtc_set_memory(s, 0x10, val);
 312
 313     val = 0;
 314     nb = 0;
 315     if (fd0 < 3)
 316         nb++;
 317     if (fd1 < 3)
 318         nb++;
 319     switch (nb) {
 320     case 0:
 321         break;
 322     case 1:
 323         val |= 0x01; /* 1 drive, ready for boot */
 324         break;
 325     case 2:
 326         val |= 0x41; /* 2 drives, ready for boot */
 327         break;
 328     }
 329     val |= 0x02; /* FPU is there */
 330     val |= 0x04; /* PS/2 mouse installed */
 331     rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
 332
 333     /* hard drives */
 334
 335     rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0));
 336     if (hd_table[0])
 337         cmos_init_hd(0x19, 0x1b, hd_table[0]->bdrv, s);
 338     if (hd_table[1])
 339         cmos_init_hd(0x1a, 0x24, hd_table[1]->bdrv, s);
 340
 341     val = 0;
 342     for (i = 0; i < 4; i++) {
 343         if (hd_table[i]) {
 344             int cylinders, heads, sectors, translation;
 345             /* NOTE: bdrv_get_geometry_hint() returns the physical
 346                 geometry.  It is always such that: 1 <= sects <= 63, 1
 347                 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
 348                 geometry can be different if a translation is done. */
 349             translation = bdrv_get_translation_hint(hd_table[i]->bdrv);
 350             if (translation == BIOS_ATA_TRANSLATION_AUTO) {
 351                 bdrv_get_geometry_hint(hd_table[i]->bdrv, &cylinders, &heads, &sectors);
 352                 if (cylinders <= 1024 && heads <= 16 && sectors <= 63) {
 353                     /* No translation. */
 354                     translation = 0;
 355                 } else {
 356                     /* LBA translation. */
 357                     translation = 1;
 358                 }
 359             } else {
 360                 translation--;
 361             }
 362             val |= translation << (i * 2);
 363         }
 364     }
 365     rtc_set_memory(s, 0x39, val);
 366 }
 367
 368 void ioport_set_a20(int enable)
 369 {
 370     /* XXX: send to all CPUs ? */
 371     cpu_x86_set_a20(first_cpu, enable);
 372 }
 373
 374 int ioport_get_a20(void)
 375 {
 376     return ((first_cpu->a20_mask >> 20) & 1);
 377 }
 378
 379 static void ioport92_write(void *opaque, uint32_t addr, uint32_t val)
 380 {
 381     ioport_set_a20((val >> 1) & 1);
 382     /* XXX: bit 0 is fast reset */
 383 }
 384
 385 static uint32_t ioport92_read(void *opaque, uint32_t addr)
 386 {
 387     return ioport_get_a20() << 1;
 388 }
 389
 390 /***********************************************************/
 391 /* Bochs BIOS debug ports */
 392
 393 static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
 394 {
 395     static const char shutdown_str[8] = "Shutdown";
 396     static int shutdown_index = 0;
 397
 398     switch(addr) {
 399         /* Bochs BIOS messages */
 400     case 0x400:
 401     case 0x401:
 402         fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val);
 403         exit(1);
 404     case 0x402:
 405     case 0x403:
 406 #ifdef DEBUG_BIOS
 407         fprintf(stderr, "%c", val);
 408 #endif
 409         break;
 410     case 0x8900:
 411         /* same as Bochs power off */
 412         if (val == shutdown_str[shutdown_index]) {
 413             shutdown_index++;
 414             if (shutdown_index == 8) {
 415                 shutdown_index = 0;
 416                 qemu_system_shutdown_request();
 417             }
 418         } else {
 419             shutdown_index = 0;
 420         }
 421         break;
 422
 423         /* LGPL'ed VGA BIOS messages */
 424     case 0x501:
 425     case 0x502:
 426         fprintf(stderr, "VGA BIOS panic, line %d\n", val);
 427         exit(1);
 428     case 0x500:
 429     case 0x503:
 430 #ifdef DEBUG_BIOS
 431         fprintf(stderr, "%c", val);
 432 #endif
 433         break;
 434     }
 435 }
 436
 437 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
 438 {
 439     int index = e820_table.count;
 440     struct e820_entry *entry;
 441
 442     if (index >= E820_NR_ENTRIES)
 443         return -EBUSY;
 444     entry = &e820_table.entry[index];
 445
 446     entry->address = address;
 447     entry->length = length;
 448     entry->type = type;
 449
 450     e820_table.count++;
 451     return e820_table.count;
 452 }
 453
 454 static void *bochs_bios_init(void)
 455 {
 456     void *fw_cfg;
 457     uint8_t *smbios_table;
 458     size_t smbios_len;
 459     uint64_t *numa_fw_cfg;
 460     int i, j;
 461
 462     register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL);
 463     register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL);
 464     register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL);
 465     register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL);
 466     register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL);
 467
 468     register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL);
 469     register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL);
 470     register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL);
 471     register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL);
 472
 473     fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
 474
 475     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 476     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 477     fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables,
 478                      acpi_tables_len);
 479     fw_cfg_add_bytes(fw_cfg, FW_CFG_IRQ0_OVERRIDE, &irq0override, 1);
 480
 481     smbios_table = smbios_get_table(&smbios_len);
 482     if (smbios_table)
 483         fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
 484                          smbios_table, smbios_len);
 485     fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, (uint8_t *)&e820_table,
 486                      sizeof(struct e820_table));
 487
 488     /* allocate memory for the NUMA channel: one (64bit) word for the number
 489      * of nodes, one word for each VCPU->node and one word for each node to
 490      * hold the amount of memory.
 491      */
 492     numa_fw_cfg = qemu_mallocz((1 + smp_cpus + nb_numa_nodes) * 8);
 493     numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
 494     for (i = 0; i < smp_cpus; i++) {
 495         for (j = 0; j < nb_numa_nodes; j++) {
 496             if (node_cpumask[j] & (1 << i)) {
 497                 numa_fw_cfg[i + 1] = cpu_to_le64(j);
 498                 break;
 499             }
 500         }
 501     }
 502     for (i = 0; i < nb_numa_nodes; i++) {
 503         numa_fw_cfg[smp_cpus + 1 + i] = cpu_to_le64(node_mem[i]);
 504     }
 505     fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg,
 506                      (1 + smp_cpus + nb_numa_nodes) * 8);
 507
 508     return fw_cfg;
 509 }
 510
 511 static long get_file_size(FILE *f)
 512 {
 513     long where, size;
 514
 515     /* XXX: on Unix systems, using fstat() probably makes more sense */
 516
 517     where = ftell(f);
 518     fseek(f, 0, SEEK_END);
 519     size = ftell(f);
 520     fseek(f, where, SEEK_SET);
 521
 522     return size;
 523 }
 524
 525 static void load_linux(void *fw_cfg,
 526                        const char *kernel_filename,
 527                        const char *initrd_filename,
 528                        const char *kernel_cmdline,
 529                        target_phys_addr_t max_ram_size)
 530 {
 531     uint16_t protocol;
 532     int setup_size, kernel_size, initrd_size = 0, cmdline_size;
 533     uint32_t initrd_max;
 534     uint8_t header[8192], *setup, *kernel, *initrd_data;
 535     target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
 536     FILE *f;
 537     char *vmode;
 538
 539     /* Align to 16 bytes as a paranoia measure */
 540     cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
 541
 542     /* load the kernel header */
 543     f = fopen(kernel_filename, "rb");
 544     if (!f || !(kernel_size = get_file_size(f)) ||
 545         fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
 546         MIN(ARRAY_SIZE(header), kernel_size)) {
 547         fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
 548                 kernel_filename, strerror(errno));
 549         exit(1);
 550     }
 551
 552     /* kernel protocol version */
 553 #if 0
 554     fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
 555 #endif
 556     if (ldl_p(header+0x202) == 0x53726448)
 557         protocol = lduw_p(header+0x206);
 558     else {
 559         /* This looks like a multiboot kernel. If it is, let's stop
 560            treating it like a Linux kernel. */
 561         if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
 562                            kernel_cmdline, kernel_size, header))
 563             return;
 564         protocol = 0;
 565     }
 566
 567     if (protocol < 0x200 || !(header[0x211] & 0x01)) {
 568         /* Low kernel */
 569         real_addr    = 0x90000;
 570         cmdline_addr = 0x9a000 - cmdline_size;
 571         prot_addr    = 0x10000;
 572     } else if (protocol < 0x202) {
 573         /* High but ancient kernel */
 574         real_addr    = 0x90000;
 575         cmdline_addr = 0x9a000 - cmdline_size;
 576         prot_addr    = 0x100000;
 577     } else {
 578         /* High and recent kernel */
 579         real_addr    = 0x10000;
 580         cmdline_addr = 0x20000;
 581         prot_addr    = 0x100000;
 582     }
 583
 584 #if 0
 585     fprintf(stderr,
 586             "qemu: real_addr     = 0x" TARGET_FMT_plx "\n"
 587             "qemu: cmdline_addr  = 0x" TARGET_FMT_plx "\n"
 588             "qemu: prot_addr     = 0x" TARGET_FMT_plx "\n",
 589             real_addr,
 590             cmdline_addr,
 591             prot_addr);
 592 #endif
 593
 594     /* highest address for loading the initrd */
 595     if (protocol >= 0x203)
 596         initrd_max = ldl_p(header+0x22c);
 597     else
 598         initrd_max = 0x37ffffff;
 599
 600     if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
 601         initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
 602
 603     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
 604     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
 605     fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
 606                      (uint8_t*)strdup(kernel_cmdline),
 607                      strlen(kernel_cmdline)+1);
 608
 609     if (protocol >= 0x202) {
 610         stl_p(header+0x228, cmdline_addr);
 611     } else {
 612         stw_p(header+0x20, 0xA33F);
 613         stw_p(header+0x22, cmdline_addr-real_addr);
 614     }
 615
 616     /* handle vga= parameter */
 617     vmode = strstr(kernel_cmdline, "vga=");
 618     if (vmode) {
 619         unsigned int video_mode;
 620         /* skip "vga=" */
 621         vmode += 4;
 622         if (!strncmp(vmode, "normal", 6)) {
 623             video_mode = 0xffff;
 624         } else if (!strncmp(vmode, "ext", 3)) {
 625             video_mode = 0xfffe;
 626         } else if (!strncmp(vmode, "ask", 3)) {
 627             video_mode = 0xfffd;
 628         } else {
 629             video_mode = strtol(vmode, NULL, 0);
 630         }
 631         stw_p(header+0x1fa, video_mode);
 632     }
 633
 634     /* loader type */
 635     /* High nybble = B reserved for Qemu; low nybble is revision number.
 636        If this code is substantially changed, you may want to consider
 637        incrementing the revision. */
 638     if (protocol >= 0x200)
 639         header[0x210] = 0xB0;
 640
 641     /* heap */
 642     if (protocol >= 0x201) {
 643         header[0x211] |= 0x80;  /* CAN_USE_HEAP */
 644         stw_p(header+0x224, cmdline_addr-real_addr-0x200);
 645     }
 646
 647     /* load initrd */
 648     if (initrd_filename) {
 649         if (protocol < 0x200) {
 650             fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
 651             exit(1);
 652         }
 653
 654         initrd_size = get_image_size(initrd_filename);
 655         if (initrd_size < 0) {
 656             fprintf(stderr, "qemu: error reading initrd %s\n",
 657                     initrd_filename);
 658             exit(1);
 659         }
 660
 661         initrd_addr = (initrd_max-initrd_size) & ~4095;
 662
 663         initrd_data = qemu_malloc(initrd_size);
 664         load_image(initrd_filename, initrd_data);
 665
 666         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
 667         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 668         fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
 669
 670         stl_p(header+0x218, initrd_addr);
 671         stl_p(header+0x21c, initrd_size);
 672     }
 673
 674     /* load kernel and setup */
 675     setup_size = header[0x1f1];
 676     if (setup_size == 0)
 677         setup_size = 4;
 678     setup_size = (setup_size+1)*512;
 679     kernel_size -= setup_size;
 680
 681     setup  = qemu_malloc(setup_size);
 682     kernel = qemu_malloc(kernel_size);
 683     fseek(f, 0, SEEK_SET);
 684     if (fread(setup, 1, setup_size, f) != setup_size) {
 685         fprintf(stderr, "fread() failed\n");
 686         exit(1);
 687     }
 688     if (fread(kernel, 1, kernel_size, f) != kernel_size) {
 689         fprintf(stderr, "fread() failed\n");
 690         exit(1);
 691     }
 692     fclose(f);
 693     memcpy(setup, header, MIN(sizeof(header), setup_size));
 694
 695     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
 696     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 697     fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
 698
 699     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
 700     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
 701     fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
 702
 703     option_rom[nb_option_roms] = "linuxboot.bin";
 704     nb_option_roms++;
 705 }
 706
 707 #define NE2000_NB_MAX 6
 708
 709 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
 710                                               0x280, 0x380 };
 711 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
 712
 713 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 714 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
 715
 716 #ifdef HAS_AUDIO
 717 void pc_audio_init (PCIBus *pci_bus, qemu_irq *pic)
 718 {
 719     struct soundhw *c;
 720
 721     for (c = soundhw; c->name; ++c) {
 722         if (c->enabled) {
 723             if (c->isa) {
 724                 c->init.init_isa(pic);
 725             } else {
 726                 if (pci_bus) {
 727                     c->init.init_pci(pci_bus);
 728                 }
 729             }
 730         }
 731     }
 732 }
 733 #endif
 734
 735 void pc_init_ne2k_isa(NICInfo *nd)
 736 {
 737     static int nb_ne2k = 0;
 738
 739     if (nb_ne2k == NE2000_NB_MAX)
 740         return;
 741     isa_ne2000_init(ne2000_io[nb_ne2k],
 742                     ne2000_irq[nb_ne2k], nd);
 743     nb_ne2k++;
 744 }
 745
 746 int cpu_is_bsp(CPUState *env)
 747 {
 748     /* We hard-wire the BSP to the first CPU. */
 749     return env->cpu_index == 0;
 750 }
 751
 752 /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
 753    BIOS will read it and start S3 resume at POST Entry */
 754 void pc_cmos_set_s3_resume(void *opaque, int irq, int level)
 755 {
 756     ISADevice *s = opaque;
 757
 758     if (level) {
 759         rtc_set_memory(s, 0xF, 0xFE);
 760     }
 761 }
 762
 763 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
 764 {
 765     CPUState *s = opaque;
 766
 767     if (level) {
 768         cpu_interrupt(s, CPU_INTERRUPT_SMI);
 769     }
 770 }
 771
 772 static CPUState *pc_new_cpu(const char *cpu_model)
 773 {
 774     CPUState *env;
 775
 776     env = cpu_init(cpu_model);
 777     if (!env) {
 778         fprintf(stderr, "Unable to find x86 CPU definition\n");
 779         exit(1);
 780     }
 781     if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) {
 782         env->cpuid_apic_id = env->cpu_index;
 783         /* APIC reset callback resets cpu */
 784         apic_init(env);
 785     } else {
 786         qemu_register_reset((QEMUResetHandler*)cpu_reset, env);
 787     }
 788     return env;
 789 }
 790
 791 void pc_cpus_init(const char *cpu_model)
 792 {
 793     int i;
 794
 795     /* init CPUs */
 796     if (cpu_model == NULL) {
 797 #ifdef TARGET_X86_64
 798         cpu_model = "qemu64";
 799 #else
 800         cpu_model = "qemu32";
 801 #endif
 802     }
 803
 804     for(i = 0; i < smp_cpus; i++) {
 805         pc_new_cpu(cpu_model);
 806     }
 807 }
 808
 809 void pc_memory_init(ram_addr_t ram_size,
 810                     const char *kernel_filename,
 811                     const char *kernel_cmdline,
 812                     const char *initrd_filename,
 813                     ram_addr_t *below_4g_mem_size_p,
 814                     ram_addr_t *above_4g_mem_size_p)
 815 {
 816     char *filename;
 817     int ret, linux_boot, i;
 818     ram_addr_t ram_addr, bios_offset, option_rom_offset;
 819     ram_addr_t below_4g_mem_size, above_4g_mem_size = 0;
 820     int bios_size, isa_bios_size;
 821     void *fw_cfg;
 822
 823     if (ram_size >= 0xe0000000 ) {
 824         above_4g_mem_size = ram_size - 0xe0000000;
 825         below_4g_mem_size = 0xe0000000;
 826     } else {
 827         below_4g_mem_size = ram_size;
 828     }
 829     *above_4g_mem_size_p = above_4g_mem_size;
 830     *below_4g_mem_size_p = below_4g_mem_size;
 831
 832     linux_boot = (kernel_filename != NULL);
 833
 834     /* allocate RAM */
 835     ram_addr = qemu_ram_alloc(below_4g_mem_size);
 836     cpu_register_physical_memory(0, 0xa0000, ram_addr);
 837     cpu_register_physical_memory(0x100000,
 838                  below_4g_mem_size - 0x100000,
 839                  ram_addr + 0x100000);
 840
 841     /* above 4giga memory allocation */
 842     if (above_4g_mem_size > 0) {
 843 #if TARGET_PHYS_ADDR_BITS == 32
 844         hw_error("To much RAM for 32-bit physical address");
 845 #else
 846         ram_addr = qemu_ram_alloc(above_4g_mem_size);
 847         cpu_register_physical_memory(0x100000000ULL,
 848                                      above_4g_mem_size,
 849                                      ram_addr);
 850 #endif
 851     }
 852
 853
 854     /* BIOS load */
 855     if (bios_name == NULL)
 856         bios_name = BIOS_FILENAME;
 857     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 858     if (filename) {
 859         bios_size = get_image_size(filename);
 860     } else {
 861         bios_size = -1;
 862     }
 863     if (bios_size <= 0 ||
 864         (bios_size % 65536) != 0) {
 865         goto bios_error;
 866     }
 867     bios_offset = qemu_ram_alloc(bios_size);
 868     ret = rom_add_file_fixed(bios_name, (uint32_t)(-bios_size));
 869     if (ret != 0) {
 870     bios_error:
 871         fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name);
 872         exit(1);
 873     }
 874     if (filename) {
 875         qemu_free(filename);
 876     }
 877     /* map the last 128KB of the BIOS in ISA space */
 878     isa_bios_size = bios_size;
 879     if (isa_bios_size > (128 * 1024))
 880         isa_bios_size = 128 * 1024;
 881     cpu_register_physical_memory(0x100000 - isa_bios_size,
 882                                  isa_bios_size,
 883                                  (bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM);
 884
 885     option_rom_offset = qemu_ram_alloc(PC_ROM_SIZE);
 886     cpu_register_physical_memory(PC_ROM_MIN_VGA, PC_ROM_SIZE, option_rom_offset);
 887
 888     /* map all the bios at the top of memory */
 889     cpu_register_physical_memory((uint32_t)(-bios_size),
 890                                  bios_size, bios_offset | IO_MEM_ROM);
 891
 892     fw_cfg = bochs_bios_init();
 893     rom_set_fw(fw_cfg);
 894
 895     if (linux_boot) {
 896         load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size);
 897     }
 898
 899     for (i = 0; i < nb_option_roms; i++) {
 900         rom_add_option(option_rom[i]);
 901     }
 902 }
 903
 904 qemu_irq *pc_allocate_cpu_irq(void)
 905 {
 906     return qemu_allocate_irqs(pic_irq_request, NULL, 1);
 907 }
 908
 909 void pc_vga_init(PCIBus *pci_bus)
 910 {
 911     if (cirrus_vga_enabled) {
 912         if (pci_bus) {
 913             pci_cirrus_vga_init(pci_bus);
 914         } else {
 915             isa_cirrus_vga_init();
 916         }
 917     } else if (vmsvga_enabled) {
 918         if (pci_bus)
 919             pci_vmsvga_init(pci_bus);
 920         else
 921             fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
 922     } else if (std_vga_enabled) {
 923         if (pci_bus) {
 924             pci_vga_init(pci_bus, 0, 0);
 925         } else {
 926             isa_vga_init();
 927         }
 928     }
 929 }
 930
 931 void pc_basic_device_init(qemu_irq *isa_irq,
 932                           FDCtrl **floppy_controller,
 933                           ISADevice **rtc_state)
 934 {
 935     int i;
 936     DriveInfo *fd[MAX_FD];
 937     PITState *pit;
 938
 939     register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
 940
 941     register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL);
 942
 943     *rtc_state = rtc_init(2000);
 944
 945     qemu_register_boot_set(pc_boot_set, *rtc_state);
 946
 947     register_ioport_read(0x92, 1, 1, ioport92_read, NULL);
 948     register_ioport_write(0x92, 1, 1, ioport92_write, NULL);
 949
 950     pit = pit_init(0x40, isa_reserve_irq(0));
 951     pcspk_init(pit);
 952     if (!no_hpet) {
 953         hpet_init(isa_irq);
 954     }
 955
 956     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
 957         if (serial_hds[i]) {
 958             serial_isa_init(i, serial_hds[i]);
 959         }
 960     }
 961
 962     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
 963         if (parallel_hds[i]) {
 964             parallel_init(i, parallel_hds[i]);
 965         }
 966     }
 967
 968     isa_create_simple("i8042");
 969     DMA_init(0);
 970
 971     for(i = 0; i < MAX_FD; i++) {
 972         fd[i] = drive_get(IF_FLOPPY, 0, i);
 973     }
 974     *floppy_controller = fdctrl_init_isa(fd);
 975 }
 976
 977 void pc_pci_device_init(PCIBus *pci_bus)
 978 {
 979     int max_bus;
 980     int bus;
 981
 982     max_bus = drive_get_max_bus(IF_SCSI);
 983     for (bus = 0; bus <= max_bus; bus++) {
 984         pci_create_simple(pci_bus, -1, "lsi53c895a");
 985     }
 986 }