hw/pci/msi.c

   1 /*
   2  * msi.c
   3  *
   4  * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
   5  *                    VA Linux Systems Japan K.K.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "hw/pci/msi.h"
  23 #include "hw/xen/xen.h"
  24 #include "qemu/range.h"
  25
  26 /* PCI_MSI_ADDRESS_LO */
  27 #define PCI_MSI_ADDRESS_LO_MASK         (~0x3)
  28
  29 /* If we get rid of cap allocator, we won't need those. */
  30 #define PCI_MSI_32_SIZEOF       0x0a
  31 #define PCI_MSI_64_SIZEOF       0x0e
  32 #define PCI_MSI_32M_SIZEOF      0x14
  33 #define PCI_MSI_64M_SIZEOF      0x18
  34
  35 #define PCI_MSI_VECTORS_MAX     32
  36
  37 /* Flag for interrupt controller to declare MSI/MSI-X support */
  38 bool msi_supported;
  39
  40 /* If we get rid of cap allocator, we won't need this. */
  41 static inline uint8_t msi_cap_sizeof(uint16_t flags)
  42 {
  43     switch (flags & (PCI_MSI_FLAGS_MASKBIT | PCI_MSI_FLAGS_64BIT)) {
  44     case PCI_MSI_FLAGS_MASKBIT | PCI_MSI_FLAGS_64BIT:
  45         return PCI_MSI_64M_SIZEOF;
  46     case PCI_MSI_FLAGS_64BIT:
  47         return PCI_MSI_64_SIZEOF;
  48     case PCI_MSI_FLAGS_MASKBIT:
  49         return PCI_MSI_32M_SIZEOF;
  50     case 0:
  51         return PCI_MSI_32_SIZEOF;
  52     default:
  53         abort();
  54         break;
  55     }
  56     return 0;
  57 }
  58
  59 //#define MSI_DEBUG
  60
  61 #ifdef MSI_DEBUG
  62 # define MSI_DPRINTF(fmt, ...)                                          \
  63     fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__)
  64 #else
  65 # define MSI_DPRINTF(fmt, ...)  do { } while (0)
  66 #endif
  67 #define MSI_DEV_PRINTF(dev, fmt, ...)                                   \
  68     MSI_DPRINTF("%s:%x " fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__)
  69
  70 static inline unsigned int msi_nr_vectors(uint16_t flags)
  71 {
  72     return 1U <<
  73         ((flags & PCI_MSI_FLAGS_QSIZE) >> ctz32(PCI_MSI_FLAGS_QSIZE));
  74 }
  75
  76 static inline uint8_t msi_flags_off(const PCIDevice* dev)
  77 {
  78     return dev->msi_cap + PCI_MSI_FLAGS;
  79 }
  80
  81 static inline uint8_t msi_address_lo_off(const PCIDevice* dev)
  82 {
  83     return dev->msi_cap + PCI_MSI_ADDRESS_LO;
  84 }
  85
  86 static inline uint8_t msi_address_hi_off(const PCIDevice* dev)
  87 {
  88     return dev->msi_cap + PCI_MSI_ADDRESS_HI;
  89 }
  90
  91 static inline uint8_t msi_data_off(const PCIDevice* dev, bool msi64bit)
  92 {
  93     return dev->msi_cap + (msi64bit ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32);
  94 }
  95
  96 static inline uint8_t msi_mask_off(const PCIDevice* dev, bool msi64bit)
  97 {
  98     return dev->msi_cap + (msi64bit ? PCI_MSI_MASK_64 : PCI_MSI_MASK_32);
  99 }
 100
 101 static inline uint8_t msi_pending_off(const PCIDevice* dev, bool msi64bit)
 102 {
 103     return dev->msi_cap + (msi64bit ? PCI_MSI_PENDING_64 : PCI_MSI_PENDING_32);
 104 }
 105
 106 /*
 107  * Special API for POWER to configure the vectors through
 108  * a side channel. Should never be used by devices.
 109  */
 110 void msi_set_message(PCIDevice *dev, MSIMessage msg)
 111 {
 112     uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
 113     bool msi64bit = flags & PCI_MSI_FLAGS_64BIT;
 114
 115     if (msi64bit) {
 116         pci_set_quad(dev->config + msi_address_lo_off(dev), msg.address);
 117     } else {
 118         pci_set_long(dev->config + msi_address_lo_off(dev), msg.address);
 119     }
 120     pci_set_word(dev->config + msi_data_off(dev, msi64bit), msg.data);
 121 }
 122
 123 MSIMessage msi_get_message(PCIDevice *dev, unsigned int vector)
 124 {
 125     uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
 126     bool msi64bit = flags & PCI_MSI_FLAGS_64BIT;
 127     unsigned int nr_vectors = msi_nr_vectors(flags);
 128     MSIMessage msg;
 129
 130     assert(vector < nr_vectors);
 131
 132     if (msi64bit) {
 133         msg.address = pci_get_quad(dev->config + msi_address_lo_off(dev));
 134     } else {
 135         msg.address = pci_get_long(dev->config + msi_address_lo_off(dev));
 136     }
 137
 138     /* upper bit 31:16 is zero */
 139     msg.data = pci_get_word(dev->config + msi_data_off(dev, msi64bit));
 140     if (nr_vectors > 1) {
 141         msg.data &= ~(nr_vectors - 1);
 142         msg.data |= vector;
 143     }
 144
 145     return msg;
 146 }
 147
 148 bool msi_enabled(const PCIDevice *dev)
 149 {
 150     return msi_present(dev) &&
 151         (pci_get_word(dev->config + msi_flags_off(dev)) &
 152          PCI_MSI_FLAGS_ENABLE);
 153 }
 154
 155 int msi_init(struct PCIDevice *dev, uint8_t offset,
 156              unsigned int nr_vectors, bool msi64bit, bool msi_per_vector_mask)
 157 {
 158     unsigned int vectors_order;
 159     uint16_t flags;
 160     uint8_t cap_size;
 161     int config_offset;
 162
 163     if (!msi_supported) {
 164         return -ENOTSUP;
 165     }
 166
 167     MSI_DEV_PRINTF(dev,
 168                    "init offset: 0x%"PRIx8" vector: %"PRId8
 169                    " 64bit %d mask %d\n",
 170                    offset, nr_vectors, msi64bit, msi_per_vector_mask);
 171
 172     assert(!(nr_vectors & (nr_vectors - 1)));   /* power of 2 */
 173     assert(nr_vectors > 0);
 174     assert(nr_vectors <= PCI_MSI_VECTORS_MAX);
 175     /* the nr of MSI vectors is up to 32 */
 176     vectors_order = ctz32(nr_vectors);
 177
 178     flags = vectors_order << ctz32(PCI_MSI_FLAGS_QMASK);
 179     if (msi64bit) {
 180         flags |= PCI_MSI_FLAGS_64BIT;
 181     }
 182     if (msi_per_vector_mask) {
 183         flags |= PCI_MSI_FLAGS_MASKBIT;
 184     }
 185
 186     cap_size = msi_cap_sizeof(flags);
 187     config_offset = pci_add_capability(dev, PCI_CAP_ID_MSI, offset, cap_size);
 188     if (config_offset < 0) {
 189         return config_offset;
 190     }
 191
 192     dev->msi_cap = config_offset;
 193     dev->cap_present |= QEMU_PCI_CAP_MSI;
 194
 195     pci_set_word(dev->config + msi_flags_off(dev), flags);
 196     pci_set_word(dev->wmask + msi_flags_off(dev),
 197                  PCI_MSI_FLAGS_QSIZE | PCI_MSI_FLAGS_ENABLE);
 198     pci_set_long(dev->wmask + msi_address_lo_off(dev),
 199                  PCI_MSI_ADDRESS_LO_MASK);
 200     if (msi64bit) {
 201         pci_set_long(dev->wmask + msi_address_hi_off(dev), 0xffffffff);
 202     }
 203     pci_set_word(dev->wmask + msi_data_off(dev, msi64bit), 0xffff);
 204
 205     if (msi_per_vector_mask) {
 206         /* Make mask bits 0 to nr_vectors - 1 writable. */
 207         pci_set_long(dev->wmask + msi_mask_off(dev, msi64bit),
 208                      0xffffffff >> (PCI_MSI_VECTORS_MAX - nr_vectors));
 209     }
 210     return config_offset;
 211 }
 212
 213 void msi_uninit(struct PCIDevice *dev)
 214 {
 215     uint16_t flags;
 216     uint8_t cap_size;
 217
 218     if (!msi_present(dev)) {
 219         return;
 220     }
 221     flags = pci_get_word(dev->config + msi_flags_off(dev));
 222     cap_size = msi_cap_sizeof(flags);
 223     pci_del_capability(dev, PCI_CAP_ID_MSI, cap_size);
 224     dev->cap_present &= ~QEMU_PCI_CAP_MSI;
 225
 226     MSI_DEV_PRINTF(dev, "uninit\n");
 227 }
 228
 229 void msi_reset(PCIDevice *dev)
 230 {
 231     uint16_t flags;
 232     bool msi64bit;
 233
 234     if (!msi_present(dev)) {
 235         return;
 236     }
 237
 238     flags = pci_get_word(dev->config + msi_flags_off(dev));
 239     flags &= ~(PCI_MSI_FLAGS_QSIZE | PCI_MSI_FLAGS_ENABLE);
 240     msi64bit = flags & PCI_MSI_FLAGS_64BIT;
 241
 242     pci_set_word(dev->config + msi_flags_off(dev), flags);
 243     pci_set_long(dev->config + msi_address_lo_off(dev), 0);
 244     if (msi64bit) {
 245         pci_set_long(dev->config + msi_address_hi_off(dev), 0);
 246     }
 247     pci_set_word(dev->config + msi_data_off(dev, msi64bit), 0);
 248     if (flags & PCI_MSI_FLAGS_MASKBIT) {
 249         pci_set_long(dev->config + msi_mask_off(dev, msi64bit), 0);
 250         pci_set_long(dev->config + msi_pending_off(dev, msi64bit), 0);
 251     }
 252     MSI_DEV_PRINTF(dev, "reset\n");
 253 }
 254
 255 static bool msi_is_masked(const PCIDevice *dev, unsigned int vector)
 256 {
 257     uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
 258     uint32_t mask, data;
 259     bool msi64bit = flags & PCI_MSI_FLAGS_64BIT;
 260     assert(vector < PCI_MSI_VECTORS_MAX);
 261
 262     if (!(flags & PCI_MSI_FLAGS_MASKBIT)) {
 263         return false;
 264     }
 265
 266     data = pci_get_word(dev->config + msi_data_off(dev, msi64bit));
 267     if (xen_is_pirq_msi(data)) {
 268         return false;
 269     }
 270
 271     mask = pci_get_long(dev->config +
 272                         msi_mask_off(dev, flags & PCI_MSI_FLAGS_64BIT));
 273     return mask & (1U << vector);
 274 }
 275
 276 void msi_notify(PCIDevice *dev, unsigned int vector)
 277 {
 278     uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
 279     bool msi64bit = flags & PCI_MSI_FLAGS_64BIT;
 280     unsigned int nr_vectors = msi_nr_vectors(flags);
 281     MSIMessage msg;
 282
 283     assert(vector < nr_vectors);
 284     if (msi_is_masked(dev, vector)) {
 285         assert(flags & PCI_MSI_FLAGS_MASKBIT);
 286         pci_long_test_and_set_mask(
 287             dev->config + msi_pending_off(dev, msi64bit), 1U << vector);
 288         MSI_DEV_PRINTF(dev, "pending vector 0x%x\n", vector);
 289         return;
 290     }
 291
 292     msg = msi_get_message(dev, vector);
 293
 294     MSI_DEV_PRINTF(dev,
 295                    "notify vector 0x%x"
 296                    " address: 0x%"PRIx64" data: 0x%"PRIx32"\n",
 297                    vector, msg.address, msg.data);
 298     msi_send_message(dev, msg);
 299 }
 300
 301 void msi_send_message(PCIDevice *dev, MSIMessage msg)
 302 {
 303     MemTxAttrs attrs = {};
 304
 305     attrs.requester_id = pci_requester_id(dev);
 306     address_space_stl_le(&dev->bus_master_as, msg.address, msg.data,
 307                          attrs, NULL);
 308 }
 309
 310 /* Normally called by pci_default_write_config(). */
 311 void msi_write_config(PCIDevice *dev, uint32_t addr, uint32_t val, int len)
 312 {
 313     uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
 314     bool msi64bit = flags & PCI_MSI_FLAGS_64BIT;
 315     bool msi_per_vector_mask = flags & PCI_MSI_FLAGS_MASKBIT;
 316     unsigned int nr_vectors;
 317     uint8_t log_num_vecs;
 318     uint8_t log_max_vecs;
 319     unsigned int vector;
 320     uint32_t pending;
 321
 322     if (!msi_present(dev) ||
 323         !ranges_overlap(addr, len, dev->msi_cap, msi_cap_sizeof(flags))) {
 324         return;
 325     }
 326
 327 #ifdef MSI_DEBUG
 328     MSI_DEV_PRINTF(dev, "addr 0x%"PRIx32" val 0x%"PRIx32" len %d\n",
 329                    addr, val, len);
 330     MSI_DEV_PRINTF(dev, "ctrl: 0x%"PRIx16" address: 0x%"PRIx32,
 331                    flags,
 332                    pci_get_long(dev->config + msi_address_lo_off(dev)));
 333     if (msi64bit) {
 334         fprintf(stderr, " address-hi: 0x%"PRIx32,
 335                 pci_get_long(dev->config + msi_address_hi_off(dev)));
 336     }
 337     fprintf(stderr, " data: 0x%"PRIx16,
 338             pci_get_word(dev->config + msi_data_off(dev, msi64bit)));
 339     if (flags & PCI_MSI_FLAGS_MASKBIT) {
 340         fprintf(stderr, " mask 0x%"PRIx32" pending 0x%"PRIx32,
 341                 pci_get_long(dev->config + msi_mask_off(dev, msi64bit)),
 342                 pci_get_long(dev->config + msi_pending_off(dev, msi64bit)));
 343     }
 344     fprintf(stderr, "\n");
 345 #endif
 346
 347     if (!(flags & PCI_MSI_FLAGS_ENABLE)) {
 348         return;
 349     }
 350
 351     /*
 352      * Now MSI is enabled, clear INTx# interrupts.
 353      * the driver is prohibited from writing enable bit to mask
 354      * a service request. But the guest OS could do this.
 355      * So we just discard the interrupts as moderate fallback.
 356      *
 357      * 6.8.3.3. Enabling Operation
 358      *   While enabled for MSI or MSI-X operation, a function is prohibited
 359      *   from using its INTx# pin (if implemented) to request
 360      *   service (MSI, MSI-X, and INTx# are mutually exclusive).
 361      */
 362     pci_device_deassert_intx(dev);
 363
 364     /*
 365      * nr_vectors might be set bigger than capable. So clamp it.
 366      * This is not legal by spec, so we can do anything we like,
 367      * just don't crash the host
 368      */
 369     log_num_vecs =
 370         (flags & PCI_MSI_FLAGS_QSIZE) >> ctz32(PCI_MSI_FLAGS_QSIZE);
 371     log_max_vecs =
 372         (flags & PCI_MSI_FLAGS_QMASK) >> ctz32(PCI_MSI_FLAGS_QMASK);
 373     if (log_num_vecs > log_max_vecs) {
 374         flags &= ~PCI_MSI_FLAGS_QSIZE;
 375         flags |= log_max_vecs << ctz32(PCI_MSI_FLAGS_QSIZE);
 376         pci_set_word(dev->config + msi_flags_off(dev), flags);
 377     }
 378
 379     if (!msi_per_vector_mask) {
 380         /* if per vector masking isn't supported,
 381            there is no pending interrupt. */
 382         return;
 383     }
 384
 385     nr_vectors = msi_nr_vectors(flags);
 386
 387     /* This will discard pending interrupts, if any. */
 388     pending = pci_get_long(dev->config + msi_pending_off(dev, msi64bit));
 389     pending &= 0xffffffff >> (PCI_MSI_VECTORS_MAX - nr_vectors);
 390     pci_set_long(dev->config + msi_pending_off(dev, msi64bit), pending);
 391
 392     /* deliver pending interrupts which are unmasked */
 393     for (vector = 0; vector < nr_vectors; ++vector) {
 394         if (msi_is_masked(dev, vector) || !(pending & (1U << vector))) {
 395             continue;
 396         }
 397
 398         pci_long_test_and_clear_mask(
 399             dev->config + msi_pending_off(dev, msi64bit), 1U << vector);
 400         msi_notify(dev, vector);
 401     }
 402 }
 403
 404 unsigned int msi_nr_vectors_allocated(const PCIDevice *dev)
 405 {
 406     uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
 407     return msi_nr_vectors(flags);
 408 }