4 * Copyright (c) 2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "hw/pci/pci.h"
26 #include "hw/pci/pci_bridge.h"
27 #include "hw/pci/pci_bus.h"
28 #include "hw/pci/pci_host.h"
29 #include "monitor/monitor.h"
31 #include "sysemu/sysemu.h"
32 #include "hw/loader.h"
33 #include "qemu/range.h"
34 #include "qmp-commands.h"
35 #include "hw/pci/msi.h"
36 #include "hw/pci/msix.h"
37 #include "exec/address-spaces.h"
41 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
43 # define PCI_DPRINTF(format, ...) do { } while (0)
46 static void pcibus_dev_print(Monitor
*mon
, DeviceState
*dev
, int indent
);
47 static char *pcibus_get_dev_path(DeviceState
*dev
);
48 static char *pcibus_get_fw_dev_path(DeviceState
*dev
);
49 static int pcibus_reset(BusState
*qbus
);
51 static Property pci_props
[] = {
52 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice
, devfn
, -1),
53 DEFINE_PROP_STRING("romfile", PCIDevice
, romfile
),
54 DEFINE_PROP_UINT32("rombar", PCIDevice
, rom_bar
, 1),
55 DEFINE_PROP_BIT("multifunction", PCIDevice
, cap_present
,
56 QEMU_PCI_CAP_MULTIFUNCTION_BITNR
, false),
57 DEFINE_PROP_BIT("command_serr_enable", PCIDevice
, cap_present
,
58 QEMU_PCI_CAP_SERR_BITNR
, true),
59 DEFINE_PROP_END_OF_LIST()
62 static void pci_bus_class_init(ObjectClass
*klass
, void *data
)
64 BusClass
*k
= BUS_CLASS(klass
);
66 k
->print_dev
= pcibus_dev_print
;
67 k
->get_dev_path
= pcibus_get_dev_path
;
68 k
->get_fw_dev_path
= pcibus_get_fw_dev_path
;
69 k
->reset
= pcibus_reset
;
72 static const TypeInfo pci_bus_info
= {
75 .instance_size
= sizeof(PCIBus
),
76 .class_init
= pci_bus_class_init
,
79 static const TypeInfo pcie_bus_info
= {
80 .name
= TYPE_PCIE_BUS
,
81 .parent
= TYPE_PCI_BUS
,
84 static PCIBus
*pci_find_bus_nr(PCIBus
*bus
, int bus_num
);
85 static void pci_update_mappings(PCIDevice
*d
);
86 static void pci_set_irq(void *opaque
, int irq_num
, int level
);
87 static int pci_add_option_rom(PCIDevice
*pdev
, bool is_default_rom
);
88 static void pci_del_option_rom(PCIDevice
*pdev
);
90 static uint16_t pci_default_sub_vendor_id
= PCI_SUBVENDOR_ID_REDHAT_QUMRANET
;
91 static uint16_t pci_default_sub_device_id
= PCI_SUBDEVICE_ID_QEMU
;
96 QLIST_ENTRY(PCIHostBus
) next
;
98 static QLIST_HEAD(, PCIHostBus
) host_buses
;
100 static const VMStateDescription vmstate_pcibus
= {
103 .minimum_version_id
= 1,
104 .minimum_version_id_old
= 1,
105 .fields
= (VMStateField
[]) {
106 VMSTATE_INT32_EQUAL(nirq
, PCIBus
),
107 VMSTATE_VARRAY_INT32(irq_count
, PCIBus
, nirq
, 0, vmstate_info_int32
, int32_t),
108 VMSTATE_END_OF_LIST()
111 static int pci_bar(PCIDevice
*d
, int reg
)
115 if (reg
!= PCI_ROM_SLOT
)
116 return PCI_BASE_ADDRESS_0
+ reg
* 4;
118 type
= d
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
119 return type
== PCI_HEADER_TYPE_BRIDGE
? PCI_ROM_ADDRESS1
: PCI_ROM_ADDRESS
;
122 static inline int pci_irq_state(PCIDevice
*d
, int irq_num
)
124 return (d
->irq_state
>> irq_num
) & 0x1;
127 static inline void pci_set_irq_state(PCIDevice
*d
, int irq_num
, int level
)
129 d
->irq_state
&= ~(0x1 << irq_num
);
130 d
->irq_state
|= level
<< irq_num
;
133 static void pci_change_irq_level(PCIDevice
*pci_dev
, int irq_num
, int change
)
138 irq_num
= bus
->map_irq(pci_dev
, irq_num
);
141 pci_dev
= bus
->parent_dev
;
143 bus
->irq_count
[irq_num
] += change
;
144 bus
->set_irq(bus
->irq_opaque
, irq_num
, bus
->irq_count
[irq_num
] != 0);
147 int pci_bus_get_irq_level(PCIBus
*bus
, int irq_num
)
149 assert(irq_num
>= 0);
150 assert(irq_num
< bus
->nirq
);
151 return !!bus
->irq_count
[irq_num
];
154 /* Update interrupt status bit in config space on interrupt
156 static void pci_update_irq_status(PCIDevice
*dev
)
158 if (dev
->irq_state
) {
159 dev
->config
[PCI_STATUS
] |= PCI_STATUS_INTERRUPT
;
161 dev
->config
[PCI_STATUS
] &= ~PCI_STATUS_INTERRUPT
;
165 void pci_device_deassert_intx(PCIDevice
*dev
)
168 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
169 qemu_set_irq(dev
->irq
[i
], 0);
174 * This function is called on #RST and FLR.
175 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
177 void pci_device_reset(PCIDevice
*dev
)
181 qdev_reset_all(&dev
->qdev
);
184 pci_update_irq_status(dev
);
185 pci_device_deassert_intx(dev
);
186 /* Clear all writable bits */
187 pci_word_test_and_clear_mask(dev
->config
+ PCI_COMMAND
,
188 pci_get_word(dev
->wmask
+ PCI_COMMAND
) |
189 pci_get_word(dev
->w1cmask
+ PCI_COMMAND
));
190 pci_word_test_and_clear_mask(dev
->config
+ PCI_STATUS
,
191 pci_get_word(dev
->wmask
+ PCI_STATUS
) |
192 pci_get_word(dev
->w1cmask
+ PCI_STATUS
));
193 dev
->config
[PCI_CACHE_LINE_SIZE
] = 0x0;
194 dev
->config
[PCI_INTERRUPT_LINE
] = 0x0;
195 for (r
= 0; r
< PCI_NUM_REGIONS
; ++r
) {
196 PCIIORegion
*region
= &dev
->io_regions
[r
];
201 if (!(region
->type
& PCI_BASE_ADDRESS_SPACE_IO
) &&
202 region
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
203 pci_set_quad(dev
->config
+ pci_bar(dev
, r
), region
->type
);
205 pci_set_long(dev
->config
+ pci_bar(dev
, r
), region
->type
);
208 pci_update_mappings(dev
);
215 * Trigger pci bus reset under a given bus.
216 * To be called on RST# assert.
218 void pci_bus_reset(PCIBus
*bus
)
222 for (i
= 0; i
< bus
->nirq
; i
++) {
223 bus
->irq_count
[i
] = 0;
225 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); ++i
) {
226 if (bus
->devices
[i
]) {
227 pci_device_reset(bus
->devices
[i
]);
232 static int pcibus_reset(BusState
*qbus
)
234 pci_bus_reset(DO_UPCAST(PCIBus
, qbus
, qbus
));
236 /* topology traverse is done by pci_bus_reset().
237 Tell qbus/qdev walker not to traverse the tree */
241 static void pci_host_bus_register(int domain
, PCIBus
*bus
)
243 struct PCIHostBus
*host
;
244 host
= g_malloc0(sizeof(*host
));
245 host
->domain
= domain
;
247 QLIST_INSERT_HEAD(&host_buses
, host
, next
);
250 PCIBus
*pci_find_primary_bus(void)
252 struct PCIHostBus
*host
;
254 QLIST_FOREACH(host
, &host_buses
, next
) {
255 if (host
->domain
== 0) {
263 PCIBus
*pci_device_root_bus(const PCIDevice
*d
)
265 PCIBus
*bus
= d
->bus
;
267 while ((d
= bus
->parent_dev
) != NULL
) {
274 const char *pci_root_bus_path(PCIDevice
*dev
)
276 PCIBus
*rootbus
= pci_device_root_bus(dev
);
277 PCIHostState
*host_bridge
= PCI_HOST_BRIDGE(rootbus
->qbus
.parent
);
278 PCIHostBridgeClass
*hc
= PCI_HOST_BRIDGE_GET_CLASS(host_bridge
);
280 assert(!rootbus
->parent_dev
);
281 assert(host_bridge
->bus
== rootbus
);
283 if (hc
->root_bus_path
) {
284 return (*hc
->root_bus_path
)(host_bridge
, rootbus
);
287 return rootbus
->qbus
.name
;
290 static void pci_bus_init(PCIBus
*bus
, DeviceState
*parent
,
292 MemoryRegion
*address_space_mem
,
293 MemoryRegion
*address_space_io
,
296 assert(PCI_FUNC(devfn_min
) == 0);
297 bus
->devfn_min
= devfn_min
;
298 bus
->address_space_mem
= address_space_mem
;
299 bus
->address_space_io
= address_space_io
;
302 QLIST_INIT(&bus
->child
);
303 pci_host_bus_register(0, bus
); /* for now only pci domain 0 is supported */
305 vmstate_register(NULL
, -1, &vmstate_pcibus
, bus
);
308 bool pci_bus_is_express(PCIBus
*bus
)
310 return object_dynamic_cast(OBJECT(bus
), TYPE_PCIE_BUS
);
313 bool pci_bus_is_root(PCIBus
*bus
)
315 return !bus
->parent_dev
;
318 void pci_bus_new_inplace(PCIBus
*bus
, DeviceState
*parent
,
320 MemoryRegion
*address_space_mem
,
321 MemoryRegion
*address_space_io
,
322 uint8_t devfn_min
, const char *typename
)
324 qbus_create_inplace(bus
, typename
, parent
, name
);
325 pci_bus_init(bus
, parent
, name
, address_space_mem
,
326 address_space_io
, devfn_min
);
329 PCIBus
*pci_bus_new(DeviceState
*parent
, const char *name
,
330 MemoryRegion
*address_space_mem
,
331 MemoryRegion
*address_space_io
,
332 uint8_t devfn_min
, const char *typename
)
336 bus
= PCI_BUS(qbus_create(typename
, parent
, name
));
337 pci_bus_init(bus
, parent
, name
, address_space_mem
,
338 address_space_io
, devfn_min
);
342 void pci_bus_irqs(PCIBus
*bus
, pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
343 void *irq_opaque
, int nirq
)
345 bus
->set_irq
= set_irq
;
346 bus
->map_irq
= map_irq
;
347 bus
->irq_opaque
= irq_opaque
;
349 bus
->irq_count
= g_malloc0(nirq
* sizeof(bus
->irq_count
[0]));
352 void pci_bus_hotplug(PCIBus
*bus
, pci_hotplug_fn hotplug
, DeviceState
*qdev
)
354 bus
->qbus
.allow_hotplug
= 1;
355 bus
->hotplug
= hotplug
;
356 bus
->hotplug_qdev
= qdev
;
359 PCIBus
*pci_register_bus(DeviceState
*parent
, const char *name
,
360 pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
362 MemoryRegion
*address_space_mem
,
363 MemoryRegion
*address_space_io
,
364 uint8_t devfn_min
, int nirq
, const char *typename
)
368 bus
= pci_bus_new(parent
, name
, address_space_mem
,
369 address_space_io
, devfn_min
, typename
);
370 pci_bus_irqs(bus
, set_irq
, map_irq
, irq_opaque
, nirq
);
374 int pci_bus_num(PCIBus
*s
)
376 if (pci_bus_is_root(s
))
377 return 0; /* pci host bridge */
378 return s
->parent_dev
->config
[PCI_SECONDARY_BUS
];
381 static int get_pci_config_device(QEMUFile
*f
, void *pv
, size_t size
)
383 PCIDevice
*s
= container_of(pv
, PCIDevice
, config
);
387 assert(size
== pci_config_size(s
));
388 config
= g_malloc(size
);
390 qemu_get_buffer(f
, config
, size
);
391 for (i
= 0; i
< size
; ++i
) {
392 if ((config
[i
] ^ s
->config
[i
]) &
393 s
->cmask
[i
] & ~s
->wmask
[i
] & ~s
->w1cmask
[i
]) {
398 memcpy(s
->config
, config
, size
);
400 pci_update_mappings(s
);
402 memory_region_set_enabled(&s
->bus_master_enable_region
,
403 pci_get_word(s
->config
+ PCI_COMMAND
)
404 & PCI_COMMAND_MASTER
);
410 /* just put buffer */
411 static void put_pci_config_device(QEMUFile
*f
, void *pv
, size_t size
)
413 const uint8_t **v
= pv
;
414 assert(size
== pci_config_size(container_of(pv
, PCIDevice
, config
)));
415 qemu_put_buffer(f
, *v
, size
);
418 static VMStateInfo vmstate_info_pci_config
= {
419 .name
= "pci config",
420 .get
= get_pci_config_device
,
421 .put
= put_pci_config_device
,
424 static int get_pci_irq_state(QEMUFile
*f
, void *pv
, size_t size
)
426 PCIDevice
*s
= container_of(pv
, PCIDevice
, irq_state
);
427 uint32_t irq_state
[PCI_NUM_PINS
];
429 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
430 irq_state
[i
] = qemu_get_be32(f
);
431 if (irq_state
[i
] != 0x1 && irq_state
[i
] != 0) {
432 fprintf(stderr
, "irq state %d: must be 0 or 1.\n",
438 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
439 pci_set_irq_state(s
, i
, irq_state
[i
]);
445 static void put_pci_irq_state(QEMUFile
*f
, void *pv
, size_t size
)
448 PCIDevice
*s
= container_of(pv
, PCIDevice
, irq_state
);
450 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
451 qemu_put_be32(f
, pci_irq_state(s
, i
));
455 static VMStateInfo vmstate_info_pci_irq_state
= {
456 .name
= "pci irq state",
457 .get
= get_pci_irq_state
,
458 .put
= put_pci_irq_state
,
461 const VMStateDescription vmstate_pci_device
= {
464 .minimum_version_id
= 1,
465 .minimum_version_id_old
= 1,
466 .fields
= (VMStateField
[]) {
467 VMSTATE_INT32_LE(version_id
, PCIDevice
),
468 VMSTATE_BUFFER_UNSAFE_INFO(config
, PCIDevice
, 0,
469 vmstate_info_pci_config
,
470 PCI_CONFIG_SPACE_SIZE
),
471 VMSTATE_BUFFER_UNSAFE_INFO(irq_state
, PCIDevice
, 2,
472 vmstate_info_pci_irq_state
,
473 PCI_NUM_PINS
* sizeof(int32_t)),
474 VMSTATE_END_OF_LIST()
478 const VMStateDescription vmstate_pcie_device
= {
479 .name
= "PCIEDevice",
481 .minimum_version_id
= 1,
482 .minimum_version_id_old
= 1,
483 .fields
= (VMStateField
[]) {
484 VMSTATE_INT32_LE(version_id
, PCIDevice
),
485 VMSTATE_BUFFER_UNSAFE_INFO(config
, PCIDevice
, 0,
486 vmstate_info_pci_config
,
487 PCIE_CONFIG_SPACE_SIZE
),
488 VMSTATE_BUFFER_UNSAFE_INFO(irq_state
, PCIDevice
, 2,
489 vmstate_info_pci_irq_state
,
490 PCI_NUM_PINS
* sizeof(int32_t)),
491 VMSTATE_END_OF_LIST()
495 static inline const VMStateDescription
*pci_get_vmstate(PCIDevice
*s
)
497 return pci_is_express(s
) ? &vmstate_pcie_device
: &vmstate_pci_device
;
500 void pci_device_save(PCIDevice
*s
, QEMUFile
*f
)
502 /* Clear interrupt status bit: it is implicit
503 * in irq_state which we are saving.
504 * This makes us compatible with old devices
505 * which never set or clear this bit. */
506 s
->config
[PCI_STATUS
] &= ~PCI_STATUS_INTERRUPT
;
507 vmstate_save_state(f
, pci_get_vmstate(s
), s
);
508 /* Restore the interrupt status bit. */
509 pci_update_irq_status(s
);
512 int pci_device_load(PCIDevice
*s
, QEMUFile
*f
)
515 ret
= vmstate_load_state(f
, pci_get_vmstate(s
), s
, s
->version_id
);
516 /* Restore the interrupt status bit. */
517 pci_update_irq_status(s
);
521 static void pci_set_default_subsystem_id(PCIDevice
*pci_dev
)
523 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_VENDOR_ID
,
524 pci_default_sub_vendor_id
);
525 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_ID
,
526 pci_default_sub_device_id
);
530 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
531 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
533 int pci_parse_devaddr(const char *addr
, int *domp
, int *busp
,
534 unsigned int *slotp
, unsigned int *funcp
)
539 unsigned long dom
= 0, bus
= 0;
540 unsigned int slot
= 0;
541 unsigned int func
= 0;
544 val
= strtoul(p
, &e
, 16);
550 val
= strtoul(p
, &e
, 16);
557 val
= strtoul(p
, &e
, 16);
570 val
= strtoul(p
, &e
, 16);
577 /* if funcp == NULL func is 0 */
578 if (dom
> 0xffff || bus
> 0xff || slot
> 0x1f || func
> 7)
592 PCIBus
*pci_get_bus_devfn(int *devfnp
, PCIBus
*root
, const char *devaddr
)
597 assert(!root
->parent_dev
);
600 fprintf(stderr
, "No primary PCI bus\n");
606 return pci_find_bus_nr(root
, 0);
609 if (pci_parse_devaddr(devaddr
, &dom
, &bus
, &slot
, NULL
) < 0) {
614 fprintf(stderr
, "No support for non-zero PCI domains\n");
618 *devfnp
= PCI_DEVFN(slot
, 0);
619 return pci_find_bus_nr(root
, bus
);
622 static void pci_init_cmask(PCIDevice
*dev
)
624 pci_set_word(dev
->cmask
+ PCI_VENDOR_ID
, 0xffff);
625 pci_set_word(dev
->cmask
+ PCI_DEVICE_ID
, 0xffff);
626 dev
->cmask
[PCI_STATUS
] = PCI_STATUS_CAP_LIST
;
627 dev
->cmask
[PCI_REVISION_ID
] = 0xff;
628 dev
->cmask
[PCI_CLASS_PROG
] = 0xff;
629 pci_set_word(dev
->cmask
+ PCI_CLASS_DEVICE
, 0xffff);
630 dev
->cmask
[PCI_HEADER_TYPE
] = 0xff;
631 dev
->cmask
[PCI_CAPABILITY_LIST
] = 0xff;
634 static void pci_init_wmask(PCIDevice
*dev
)
636 int config_size
= pci_config_size(dev
);
638 dev
->wmask
[PCI_CACHE_LINE_SIZE
] = 0xff;
639 dev
->wmask
[PCI_INTERRUPT_LINE
] = 0xff;
640 pci_set_word(dev
->wmask
+ PCI_COMMAND
,
641 PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
|
642 PCI_COMMAND_INTX_DISABLE
);
643 if (dev
->cap_present
& QEMU_PCI_CAP_SERR
) {
644 pci_word_test_and_set_mask(dev
->wmask
+ PCI_COMMAND
, PCI_COMMAND_SERR
);
647 memset(dev
->wmask
+ PCI_CONFIG_HEADER_SIZE
, 0xff,
648 config_size
- PCI_CONFIG_HEADER_SIZE
);
651 static void pci_init_w1cmask(PCIDevice
*dev
)
654 * Note: It's okay to set w1cmask even for readonly bits as
655 * long as their value is hardwired to 0.
657 pci_set_word(dev
->w1cmask
+ PCI_STATUS
,
658 PCI_STATUS_PARITY
| PCI_STATUS_SIG_TARGET_ABORT
|
659 PCI_STATUS_REC_TARGET_ABORT
| PCI_STATUS_REC_MASTER_ABORT
|
660 PCI_STATUS_SIG_SYSTEM_ERROR
| PCI_STATUS_DETECTED_PARITY
);
663 static void pci_init_mask_bridge(PCIDevice
*d
)
665 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
666 PCI_SEC_LETENCY_TIMER */
667 memset(d
->wmask
+ PCI_PRIMARY_BUS
, 0xff, 4);
670 d
->wmask
[PCI_IO_BASE
] = PCI_IO_RANGE_MASK
& 0xff;
671 d
->wmask
[PCI_IO_LIMIT
] = PCI_IO_RANGE_MASK
& 0xff;
672 pci_set_word(d
->wmask
+ PCI_MEMORY_BASE
,
673 PCI_MEMORY_RANGE_MASK
& 0xffff);
674 pci_set_word(d
->wmask
+ PCI_MEMORY_LIMIT
,
675 PCI_MEMORY_RANGE_MASK
& 0xffff);
676 pci_set_word(d
->wmask
+ PCI_PREF_MEMORY_BASE
,
677 PCI_PREF_RANGE_MASK
& 0xffff);
678 pci_set_word(d
->wmask
+ PCI_PREF_MEMORY_LIMIT
,
679 PCI_PREF_RANGE_MASK
& 0xffff);
681 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
682 memset(d
->wmask
+ PCI_PREF_BASE_UPPER32
, 0xff, 8);
684 /* Supported memory and i/o types */
685 d
->config
[PCI_IO_BASE
] |= PCI_IO_RANGE_TYPE_16
;
686 d
->config
[PCI_IO_LIMIT
] |= PCI_IO_RANGE_TYPE_16
;
687 pci_word_test_and_set_mask(d
->config
+ PCI_PREF_MEMORY_BASE
,
688 PCI_PREF_RANGE_TYPE_64
);
689 pci_word_test_and_set_mask(d
->config
+ PCI_PREF_MEMORY_LIMIT
,
690 PCI_PREF_RANGE_TYPE_64
);
693 * TODO: Bridges default to 10-bit VGA decoding but we currently only
694 * implement 16-bit decoding (no alias support).
696 pci_set_word(d
->wmask
+ PCI_BRIDGE_CONTROL
,
697 PCI_BRIDGE_CTL_PARITY
|
698 PCI_BRIDGE_CTL_SERR
|
701 PCI_BRIDGE_CTL_VGA_16BIT
|
702 PCI_BRIDGE_CTL_MASTER_ABORT
|
703 PCI_BRIDGE_CTL_BUS_RESET
|
704 PCI_BRIDGE_CTL_FAST_BACK
|
705 PCI_BRIDGE_CTL_DISCARD
|
706 PCI_BRIDGE_CTL_SEC_DISCARD
|
707 PCI_BRIDGE_CTL_DISCARD_SERR
);
708 /* Below does not do anything as we never set this bit, put here for
710 pci_set_word(d
->w1cmask
+ PCI_BRIDGE_CONTROL
,
711 PCI_BRIDGE_CTL_DISCARD_STATUS
);
712 d
->cmask
[PCI_IO_BASE
] |= PCI_IO_RANGE_TYPE_MASK
;
713 d
->cmask
[PCI_IO_LIMIT
] |= PCI_IO_RANGE_TYPE_MASK
;
714 pci_word_test_and_set_mask(d
->cmask
+ PCI_PREF_MEMORY_BASE
,
715 PCI_PREF_RANGE_TYPE_MASK
);
716 pci_word_test_and_set_mask(d
->cmask
+ PCI_PREF_MEMORY_LIMIT
,
717 PCI_PREF_RANGE_TYPE_MASK
);
720 static int pci_init_multifunction(PCIBus
*bus
, PCIDevice
*dev
)
722 uint8_t slot
= PCI_SLOT(dev
->devfn
);
725 if (dev
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
) {
726 dev
->config
[PCI_HEADER_TYPE
] |= PCI_HEADER_TYPE_MULTI_FUNCTION
;
730 * multifunction bit is interpreted in two ways as follows.
731 * - all functions must set the bit to 1.
733 * - function 0 must set the bit, but the rest function (> 0)
734 * is allowed to leave the bit to 0.
735 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
737 * So OS (at least Linux) checks the bit of only function 0,
738 * and doesn't see the bit of function > 0.
740 * The below check allows both interpretation.
742 if (PCI_FUNC(dev
->devfn
)) {
743 PCIDevice
*f0
= bus
->devices
[PCI_DEVFN(slot
, 0)];
744 if (f0
&& !(f0
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
)) {
745 /* function 0 should set multifunction bit */
746 error_report("PCI: single function device can't be populated "
747 "in function %x.%x", slot
, PCI_FUNC(dev
->devfn
));
753 if (dev
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
) {
756 /* function 0 indicates single function, so function > 0 must be NULL */
757 for (func
= 1; func
< PCI_FUNC_MAX
; ++func
) {
758 if (bus
->devices
[PCI_DEVFN(slot
, func
)]) {
759 error_report("PCI: %x.0 indicates single function, "
760 "but %x.%x is already populated.",
768 static void pci_config_alloc(PCIDevice
*pci_dev
)
770 int config_size
= pci_config_size(pci_dev
);
772 pci_dev
->config
= g_malloc0(config_size
);
773 pci_dev
->cmask
= g_malloc0(config_size
);
774 pci_dev
->wmask
= g_malloc0(config_size
);
775 pci_dev
->w1cmask
= g_malloc0(config_size
);
776 pci_dev
->used
= g_malloc0(config_size
);
779 static void pci_config_free(PCIDevice
*pci_dev
)
781 g_free(pci_dev
->config
);
782 g_free(pci_dev
->cmask
);
783 g_free(pci_dev
->wmask
);
784 g_free(pci_dev
->w1cmask
);
785 g_free(pci_dev
->used
);
788 /* -1 for devfn means auto assign */
789 static PCIDevice
*do_pci_register_device(PCIDevice
*pci_dev
, PCIBus
*bus
,
790 const char *name
, int devfn
)
792 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(pci_dev
);
793 PCIConfigReadFunc
*config_read
= pc
->config_read
;
794 PCIConfigWriteFunc
*config_write
= pc
->config_write
;
795 AddressSpace
*dma_as
;
798 for(devfn
= bus
->devfn_min
; devfn
< ARRAY_SIZE(bus
->devices
);
799 devfn
+= PCI_FUNC_MAX
) {
800 if (!bus
->devices
[devfn
])
803 error_report("PCI: no slot/function available for %s, all in use", name
);
806 } else if (bus
->devices
[devfn
]) {
807 error_report("PCI: slot %d function %d not available for %s, in use by %s",
808 PCI_SLOT(devfn
), PCI_FUNC(devfn
), name
, bus
->devices
[devfn
]->name
);
814 dma_as
= bus
->iommu_fn(bus
, bus
->iommu_opaque
, devfn
);
816 /* FIXME: inherit memory region from bus creator */
817 dma_as
= &address_space_memory
;
820 memory_region_init_alias(&pci_dev
->bus_master_enable_region
, "bus master",
821 dma_as
->root
, 0, memory_region_size(dma_as
->root
));
822 memory_region_set_enabled(&pci_dev
->bus_master_enable_region
, false);
823 address_space_init(&pci_dev
->bus_master_as
, &pci_dev
->bus_master_enable_region
,
826 pci_dev
->devfn
= devfn
;
827 pstrcpy(pci_dev
->name
, sizeof(pci_dev
->name
), name
);
828 pci_dev
->irq_state
= 0;
829 pci_config_alloc(pci_dev
);
831 pci_config_set_vendor_id(pci_dev
->config
, pc
->vendor_id
);
832 pci_config_set_device_id(pci_dev
->config
, pc
->device_id
);
833 pci_config_set_revision(pci_dev
->config
, pc
->revision
);
834 pci_config_set_class(pci_dev
->config
, pc
->class_id
);
836 if (!pc
->is_bridge
) {
837 if (pc
->subsystem_vendor_id
|| pc
->subsystem_id
) {
838 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_VENDOR_ID
,
839 pc
->subsystem_vendor_id
);
840 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_ID
,
843 pci_set_default_subsystem_id(pci_dev
);
846 /* subsystem_vendor_id/subsystem_id are only for header type 0 */
847 assert(!pc
->subsystem_vendor_id
);
848 assert(!pc
->subsystem_id
);
850 pci_init_cmask(pci_dev
);
851 pci_init_wmask(pci_dev
);
852 pci_init_w1cmask(pci_dev
);
854 pci_init_mask_bridge(pci_dev
);
856 if (pci_init_multifunction(bus
, pci_dev
)) {
857 pci_config_free(pci_dev
);
862 config_read
= pci_default_read_config
;
864 config_write
= pci_default_write_config
;
865 pci_dev
->config_read
= config_read
;
866 pci_dev
->config_write
= config_write
;
867 bus
->devices
[devfn
] = pci_dev
;
868 pci_dev
->irq
= qemu_allocate_irqs(pci_set_irq
, pci_dev
, PCI_NUM_PINS
);
869 pci_dev
->version_id
= 2; /* Current pci device vmstate version */
873 static void do_pci_unregister_device(PCIDevice
*pci_dev
)
875 qemu_free_irqs(pci_dev
->irq
);
876 pci_dev
->bus
->devices
[pci_dev
->devfn
] = NULL
;
877 pci_config_free(pci_dev
);
879 address_space_destroy(&pci_dev
->bus_master_as
);
880 memory_region_destroy(&pci_dev
->bus_master_enable_region
);
883 static void pci_unregister_io_regions(PCIDevice
*pci_dev
)
888 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
889 r
= &pci_dev
->io_regions
[i
];
890 if (!r
->size
|| r
->addr
== PCI_BAR_UNMAPPED
)
892 memory_region_del_subregion(r
->address_space
, r
->memory
);
895 pci_unregister_vga(pci_dev
);
898 static int pci_unregister_device(DeviceState
*dev
)
900 PCIDevice
*pci_dev
= PCI_DEVICE(dev
);
901 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(pci_dev
);
903 pci_unregister_io_regions(pci_dev
);
904 pci_del_option_rom(pci_dev
);
910 do_pci_unregister_device(pci_dev
);
914 void pci_register_bar(PCIDevice
*pci_dev
, int region_num
,
915 uint8_t type
, MemoryRegion
*memory
)
920 pcibus_t size
= memory_region_size(memory
);
922 assert(region_num
>= 0);
923 assert(region_num
< PCI_NUM_REGIONS
);
924 if (size
& (size
-1)) {
925 fprintf(stderr
, "ERROR: PCI region size must be pow2 "
926 "type=0x%x, size=0x%"FMT_PCIBUS
"\n", type
, size
);
930 r
= &pci_dev
->io_regions
[region_num
];
931 r
->addr
= PCI_BAR_UNMAPPED
;
937 addr
= pci_bar(pci_dev
, region_num
);
938 if (region_num
== PCI_ROM_SLOT
) {
939 /* ROM enable bit is writable */
940 wmask
|= PCI_ROM_ADDRESS_ENABLE
;
942 pci_set_long(pci_dev
->config
+ addr
, type
);
943 if (!(r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) &&
944 r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
945 pci_set_quad(pci_dev
->wmask
+ addr
, wmask
);
946 pci_set_quad(pci_dev
->cmask
+ addr
, ~0ULL);
948 pci_set_long(pci_dev
->wmask
+ addr
, wmask
& 0xffffffff);
949 pci_set_long(pci_dev
->cmask
+ addr
, 0xffffffff);
951 pci_dev
->io_regions
[region_num
].memory
= memory
;
952 pci_dev
->io_regions
[region_num
].address_space
953 = type
& PCI_BASE_ADDRESS_SPACE_IO
954 ? pci_dev
->bus
->address_space_io
955 : pci_dev
->bus
->address_space_mem
;
958 static void pci_update_vga(PCIDevice
*pci_dev
)
962 if (!pci_dev
->has_vga
) {
966 cmd
= pci_get_word(pci_dev
->config
+ PCI_COMMAND
);
968 memory_region_set_enabled(pci_dev
->vga_regions
[QEMU_PCI_VGA_MEM
],
969 cmd
& PCI_COMMAND_MEMORY
);
970 memory_region_set_enabled(pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_LO
],
971 cmd
& PCI_COMMAND_IO
);
972 memory_region_set_enabled(pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_HI
],
973 cmd
& PCI_COMMAND_IO
);
976 void pci_register_vga(PCIDevice
*pci_dev
, MemoryRegion
*mem
,
977 MemoryRegion
*io_lo
, MemoryRegion
*io_hi
)
979 assert(!pci_dev
->has_vga
);
981 assert(memory_region_size(mem
) == QEMU_PCI_VGA_MEM_SIZE
);
982 pci_dev
->vga_regions
[QEMU_PCI_VGA_MEM
] = mem
;
983 memory_region_add_subregion_overlap(pci_dev
->bus
->address_space_mem
,
984 QEMU_PCI_VGA_MEM_BASE
, mem
, 1);
986 assert(memory_region_size(io_lo
) == QEMU_PCI_VGA_IO_LO_SIZE
);
987 pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_LO
] = io_lo
;
988 memory_region_add_subregion_overlap(pci_dev
->bus
->address_space_io
,
989 QEMU_PCI_VGA_IO_LO_BASE
, io_lo
, 1);
991 assert(memory_region_size(io_hi
) == QEMU_PCI_VGA_IO_HI_SIZE
);
992 pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_HI
] = io_hi
;
993 memory_region_add_subregion_overlap(pci_dev
->bus
->address_space_io
,
994 QEMU_PCI_VGA_IO_HI_BASE
, io_hi
, 1);
995 pci_dev
->has_vga
= true;
997 pci_update_vga(pci_dev
);
1000 void pci_unregister_vga(PCIDevice
*pci_dev
)
1002 if (!pci_dev
->has_vga
) {
1006 memory_region_del_subregion(pci_dev
->bus
->address_space_mem
,
1007 pci_dev
->vga_regions
[QEMU_PCI_VGA_MEM
]);
1008 memory_region_del_subregion(pci_dev
->bus
->address_space_io
,
1009 pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_LO
]);
1010 memory_region_del_subregion(pci_dev
->bus
->address_space_io
,
1011 pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_HI
]);
1012 pci_dev
->has_vga
= false;
1015 pcibus_t
pci_get_bar_addr(PCIDevice
*pci_dev
, int region_num
)
1017 return pci_dev
->io_regions
[region_num
].addr
;
1020 static pcibus_t
pci_bar_address(PCIDevice
*d
,
1021 int reg
, uint8_t type
, pcibus_t size
)
1023 pcibus_t new_addr
, last_addr
;
1024 int bar
= pci_bar(d
, reg
);
1025 uint16_t cmd
= pci_get_word(d
->config
+ PCI_COMMAND
);
1027 if (type
& PCI_BASE_ADDRESS_SPACE_IO
) {
1028 if (!(cmd
& PCI_COMMAND_IO
)) {
1029 return PCI_BAR_UNMAPPED
;
1031 new_addr
= pci_get_long(d
->config
+ bar
) & ~(size
- 1);
1032 last_addr
= new_addr
+ size
- 1;
1033 /* NOTE: we have only 64K ioports on PC */
1034 if (last_addr
<= new_addr
|| new_addr
== 0 || last_addr
> UINT16_MAX
) {
1035 return PCI_BAR_UNMAPPED
;
1040 if (!(cmd
& PCI_COMMAND_MEMORY
)) {
1041 return PCI_BAR_UNMAPPED
;
1043 if (type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
1044 new_addr
= pci_get_quad(d
->config
+ bar
);
1046 new_addr
= pci_get_long(d
->config
+ bar
);
1048 /* the ROM slot has a specific enable bit */
1049 if (reg
== PCI_ROM_SLOT
&& !(new_addr
& PCI_ROM_ADDRESS_ENABLE
)) {
1050 return PCI_BAR_UNMAPPED
;
1052 new_addr
&= ~(size
- 1);
1053 last_addr
= new_addr
+ size
- 1;
1054 /* NOTE: we do not support wrapping */
1055 /* XXX: as we cannot support really dynamic
1056 mappings, we handle specific values as invalid
1058 if (last_addr
<= new_addr
|| new_addr
== 0 ||
1059 last_addr
== PCI_BAR_UNMAPPED
) {
1060 return PCI_BAR_UNMAPPED
;
1063 /* Now pcibus_t is 64bit.
1064 * Check if 32 bit BAR wraps around explicitly.
1065 * Without this, PC ide doesn't work well.
1066 * TODO: remove this work around.
1068 if (!(type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) && last_addr
>= UINT32_MAX
) {
1069 return PCI_BAR_UNMAPPED
;
1073 * OS is allowed to set BAR beyond its addressable
1074 * bits. For example, 32 bit OS can set 64bit bar
1075 * to >4G. Check it. TODO: we might need to support
1076 * it in the future for e.g. PAE.
1078 if (last_addr
>= HWADDR_MAX
) {
1079 return PCI_BAR_UNMAPPED
;
1085 static void pci_update_mappings(PCIDevice
*d
)
1091 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1092 r
= &d
->io_regions
[i
];
1094 /* this region isn't registered */
1098 new_addr
= pci_bar_address(d
, i
, r
->type
, r
->size
);
1100 /* This bar isn't changed */
1101 if (new_addr
== r
->addr
)
1104 /* now do the real mapping */
1105 if (r
->addr
!= PCI_BAR_UNMAPPED
) {
1106 memory_region_del_subregion(r
->address_space
, r
->memory
);
1109 if (r
->addr
!= PCI_BAR_UNMAPPED
) {
1110 memory_region_add_subregion_overlap(r
->address_space
,
1111 r
->addr
, r
->memory
, 1);
1118 static inline int pci_irq_disabled(PCIDevice
*d
)
1120 return pci_get_word(d
->config
+ PCI_COMMAND
) & PCI_COMMAND_INTX_DISABLE
;
1123 /* Called after interrupt disabled field update in config space,
1124 * assert/deassert interrupts if necessary.
1125 * Gets original interrupt disable bit value (before update). */
1126 static void pci_update_irq_disabled(PCIDevice
*d
, int was_irq_disabled
)
1128 int i
, disabled
= pci_irq_disabled(d
);
1129 if (disabled
== was_irq_disabled
)
1131 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
1132 int state
= pci_irq_state(d
, i
);
1133 pci_change_irq_level(d
, i
, disabled
? -state
: state
);
1137 uint32_t pci_default_read_config(PCIDevice
*d
,
1138 uint32_t address
, int len
)
1142 memcpy(&val
, d
->config
+ address
, len
);
1143 return le32_to_cpu(val
);
1146 void pci_default_write_config(PCIDevice
*d
, uint32_t addr
, uint32_t val
, int l
)
1148 int i
, was_irq_disabled
= pci_irq_disabled(d
);
1150 for (i
= 0; i
< l
; val
>>= 8, ++i
) {
1151 uint8_t wmask
= d
->wmask
[addr
+ i
];
1152 uint8_t w1cmask
= d
->w1cmask
[addr
+ i
];
1153 assert(!(wmask
& w1cmask
));
1154 d
->config
[addr
+ i
] = (d
->config
[addr
+ i
] & ~wmask
) | (val
& wmask
);
1155 d
->config
[addr
+ i
] &= ~(val
& w1cmask
); /* W1C: Write 1 to Clear */
1157 if (ranges_overlap(addr
, l
, PCI_BASE_ADDRESS_0
, 24) ||
1158 ranges_overlap(addr
, l
, PCI_ROM_ADDRESS
, 4) ||
1159 ranges_overlap(addr
, l
, PCI_ROM_ADDRESS1
, 4) ||
1160 range_covers_byte(addr
, l
, PCI_COMMAND
))
1161 pci_update_mappings(d
);
1163 if (range_covers_byte(addr
, l
, PCI_COMMAND
)) {
1164 pci_update_irq_disabled(d
, was_irq_disabled
);
1165 memory_region_set_enabled(&d
->bus_master_enable_region
,
1166 pci_get_word(d
->config
+ PCI_COMMAND
)
1167 & PCI_COMMAND_MASTER
);
1170 msi_write_config(d
, addr
, val
, l
);
1171 msix_write_config(d
, addr
, val
, l
);
1174 /***********************************************************/
1175 /* generic PCI irq support */
1177 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1178 static void pci_set_irq(void *opaque
, int irq_num
, int level
)
1180 PCIDevice
*pci_dev
= opaque
;
1183 change
= level
- pci_irq_state(pci_dev
, irq_num
);
1187 pci_set_irq_state(pci_dev
, irq_num
, level
);
1188 pci_update_irq_status(pci_dev
);
1189 if (pci_irq_disabled(pci_dev
))
1191 pci_change_irq_level(pci_dev
, irq_num
, change
);
1194 /* Special hooks used by device assignment */
1195 void pci_bus_set_route_irq_fn(PCIBus
*bus
, pci_route_irq_fn route_intx_to_irq
)
1197 assert(pci_bus_is_root(bus
));
1198 bus
->route_intx_to_irq
= route_intx_to_irq
;
1201 PCIINTxRoute
pci_device_route_intx_to_irq(PCIDevice
*dev
, int pin
)
1207 pin
= bus
->map_irq(dev
, pin
);
1208 dev
= bus
->parent_dev
;
1211 if (!bus
->route_intx_to_irq
) {
1212 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)",
1213 object_get_typename(OBJECT(bus
->qbus
.parent
)));
1214 return (PCIINTxRoute
) { PCI_INTX_DISABLED
, -1 };
1217 return bus
->route_intx_to_irq(bus
->irq_opaque
, pin
);
1220 bool pci_intx_route_changed(PCIINTxRoute
*old
, PCIINTxRoute
*new)
1222 return old
->mode
!= new->mode
|| old
->irq
!= new->irq
;
1225 void pci_bus_fire_intx_routing_notifier(PCIBus
*bus
)
1231 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); ++i
) {
1232 dev
= bus
->devices
[i
];
1233 if (dev
&& dev
->intx_routing_notifier
) {
1234 dev
->intx_routing_notifier(dev
);
1238 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
1239 pci_bus_fire_intx_routing_notifier(sec
);
1243 void pci_device_set_intx_routing_notifier(PCIDevice
*dev
,
1244 PCIINTxRoutingNotifier notifier
)
1246 dev
->intx_routing_notifier
= notifier
;
1250 * PCI-to-PCI bridge specification
1251 * 9.1: Interrupt routing. Table 9-1
1253 * the PCI Express Base Specification, Revision 2.1
1254 * 2.2.8.1: INTx interrutp signaling - Rules
1255 * the Implementation Note
1259 * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD
1260 * 0-origin unlike PCI interrupt pin register.
1262 int pci_swizzle_map_irq_fn(PCIDevice
*pci_dev
, int pin
)
1264 return (pin
+ PCI_SLOT(pci_dev
->devfn
)) % PCI_NUM_PINS
;
1267 /***********************************************************/
1268 /* monitor info on PCI */
1273 const char *fw_name
;
1274 uint16_t fw_ign_bits
;
1277 static const pci_class_desc pci_class_descriptions
[] =
1279 { 0x0001, "VGA controller", "display"},
1280 { 0x0100, "SCSI controller", "scsi"},
1281 { 0x0101, "IDE controller", "ide"},
1282 { 0x0102, "Floppy controller", "fdc"},
1283 { 0x0103, "IPI controller", "ipi"},
1284 { 0x0104, "RAID controller", "raid"},
1285 { 0x0106, "SATA controller"},
1286 { 0x0107, "SAS controller"},
1287 { 0x0180, "Storage controller"},
1288 { 0x0200, "Ethernet controller", "ethernet"},
1289 { 0x0201, "Token Ring controller", "token-ring"},
1290 { 0x0202, "FDDI controller", "fddi"},
1291 { 0x0203, "ATM controller", "atm"},
1292 { 0x0280, "Network controller"},
1293 { 0x0300, "VGA controller", "display", 0x00ff},
1294 { 0x0301, "XGA controller"},
1295 { 0x0302, "3D controller"},
1296 { 0x0380, "Display controller"},
1297 { 0x0400, "Video controller", "video"},
1298 { 0x0401, "Audio controller", "sound"},
1300 { 0x0403, "Audio controller", "sound"},
1301 { 0x0480, "Multimedia controller"},
1302 { 0x0500, "RAM controller", "memory"},
1303 { 0x0501, "Flash controller", "flash"},
1304 { 0x0580, "Memory controller"},
1305 { 0x0600, "Host bridge", "host"},
1306 { 0x0601, "ISA bridge", "isa"},
1307 { 0x0602, "EISA bridge", "eisa"},
1308 { 0x0603, "MC bridge", "mca"},
1309 { 0x0604, "PCI bridge", "pci"},
1310 { 0x0605, "PCMCIA bridge", "pcmcia"},
1311 { 0x0606, "NUBUS bridge", "nubus"},
1312 { 0x0607, "CARDBUS bridge", "cardbus"},
1313 { 0x0608, "RACEWAY bridge"},
1314 { 0x0680, "Bridge"},
1315 { 0x0700, "Serial port", "serial"},
1316 { 0x0701, "Parallel port", "parallel"},
1317 { 0x0800, "Interrupt controller", "interrupt-controller"},
1318 { 0x0801, "DMA controller", "dma-controller"},
1319 { 0x0802, "Timer", "timer"},
1320 { 0x0803, "RTC", "rtc"},
1321 { 0x0900, "Keyboard", "keyboard"},
1322 { 0x0901, "Pen", "pen"},
1323 { 0x0902, "Mouse", "mouse"},
1324 { 0x0A00, "Dock station", "dock", 0x00ff},
1325 { 0x0B00, "i386 cpu", "cpu", 0x00ff},
1326 { 0x0c00, "Fireware contorller", "fireware"},
1327 { 0x0c01, "Access bus controller", "access-bus"},
1328 { 0x0c02, "SSA controller", "ssa"},
1329 { 0x0c03, "USB controller", "usb"},
1330 { 0x0c04, "Fibre channel controller", "fibre-channel"},
1335 static void pci_for_each_device_under_bus(PCIBus
*bus
,
1336 void (*fn
)(PCIBus
*b
, PCIDevice
*d
,
1343 for(devfn
= 0; devfn
< ARRAY_SIZE(bus
->devices
); devfn
++) {
1344 d
= bus
->devices
[devfn
];
1351 void pci_for_each_device(PCIBus
*bus
, int bus_num
,
1352 void (*fn
)(PCIBus
*b
, PCIDevice
*d
, void *opaque
),
1355 bus
= pci_find_bus_nr(bus
, bus_num
);
1358 pci_for_each_device_under_bus(bus
, fn
, opaque
);
1362 static const pci_class_desc
*get_class_desc(int class)
1364 const pci_class_desc
*desc
;
1366 desc
= pci_class_descriptions
;
1367 while (desc
->desc
&& class != desc
->class) {
1374 static PciDeviceInfoList
*qmp_query_pci_devices(PCIBus
*bus
, int bus_num
);
1376 static PciMemoryRegionList
*qmp_query_pci_regions(const PCIDevice
*dev
)
1378 PciMemoryRegionList
*head
= NULL
, *cur_item
= NULL
;
1381 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1382 const PCIIORegion
*r
= &dev
->io_regions
[i
];
1383 PciMemoryRegionList
*region
;
1389 region
= g_malloc0(sizeof(*region
));
1390 region
->value
= g_malloc0(sizeof(*region
->value
));
1392 if (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) {
1393 region
->value
->type
= g_strdup("io");
1395 region
->value
->type
= g_strdup("memory");
1396 region
->value
->has_prefetch
= true;
1397 region
->value
->prefetch
= !!(r
->type
& PCI_BASE_ADDRESS_MEM_PREFETCH
);
1398 region
->value
->has_mem_type_64
= true;
1399 region
->value
->mem_type_64
= !!(r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
);
1402 region
->value
->bar
= i
;
1403 region
->value
->address
= r
->addr
;
1404 region
->value
->size
= r
->size
;
1406 /* XXX: waiting for the qapi to support GSList */
1408 head
= cur_item
= region
;
1410 cur_item
->next
= region
;
1418 static PciBridgeInfo
*qmp_query_pci_bridge(PCIDevice
*dev
, PCIBus
*bus
,
1421 PciBridgeInfo
*info
;
1423 info
= g_malloc0(sizeof(*info
));
1425 info
->bus
.number
= dev
->config
[PCI_PRIMARY_BUS
];
1426 info
->bus
.secondary
= dev
->config
[PCI_SECONDARY_BUS
];
1427 info
->bus
.subordinate
= dev
->config
[PCI_SUBORDINATE_BUS
];
1429 info
->bus
.io_range
= g_malloc0(sizeof(*info
->bus
.io_range
));
1430 info
->bus
.io_range
->base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_IO
);
1431 info
->bus
.io_range
->limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_IO
);
1433 info
->bus
.memory_range
= g_malloc0(sizeof(*info
->bus
.memory_range
));
1434 info
->bus
.memory_range
->base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
1435 info
->bus
.memory_range
->limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
1437 info
->bus
.prefetchable_range
= g_malloc0(sizeof(*info
->bus
.prefetchable_range
));
1438 info
->bus
.prefetchable_range
->base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
1439 info
->bus
.prefetchable_range
->limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
1441 if (dev
->config
[PCI_SECONDARY_BUS
] != 0) {
1442 PCIBus
*child_bus
= pci_find_bus_nr(bus
, dev
->config
[PCI_SECONDARY_BUS
]);
1444 info
->has_devices
= true;
1445 info
->devices
= qmp_query_pci_devices(child_bus
, dev
->config
[PCI_SECONDARY_BUS
]);
1452 static PciDeviceInfo
*qmp_query_pci_device(PCIDevice
*dev
, PCIBus
*bus
,
1455 const pci_class_desc
*desc
;
1456 PciDeviceInfo
*info
;
1460 info
= g_malloc0(sizeof(*info
));
1461 info
->bus
= bus_num
;
1462 info
->slot
= PCI_SLOT(dev
->devfn
);
1463 info
->function
= PCI_FUNC(dev
->devfn
);
1465 class = pci_get_word(dev
->config
+ PCI_CLASS_DEVICE
);
1466 info
->class_info
.class = class;
1467 desc
= get_class_desc(class);
1469 info
->class_info
.has_desc
= true;
1470 info
->class_info
.desc
= g_strdup(desc
->desc
);
1473 info
->id
.vendor
= pci_get_word(dev
->config
+ PCI_VENDOR_ID
);
1474 info
->id
.device
= pci_get_word(dev
->config
+ PCI_DEVICE_ID
);
1475 info
->regions
= qmp_query_pci_regions(dev
);
1476 info
->qdev_id
= g_strdup(dev
->qdev
.id
? dev
->qdev
.id
: "");
1478 if (dev
->config
[PCI_INTERRUPT_PIN
] != 0) {
1479 info
->has_irq
= true;
1480 info
->irq
= dev
->config
[PCI_INTERRUPT_LINE
];
1483 type
= dev
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
1484 if (type
== PCI_HEADER_TYPE_BRIDGE
) {
1485 info
->has_pci_bridge
= true;
1486 info
->pci_bridge
= qmp_query_pci_bridge(dev
, bus
, bus_num
);
1492 static PciDeviceInfoList
*qmp_query_pci_devices(PCIBus
*bus
, int bus_num
)
1494 PciDeviceInfoList
*info
, *head
= NULL
, *cur_item
= NULL
;
1498 for (devfn
= 0; devfn
< ARRAY_SIZE(bus
->devices
); devfn
++) {
1499 dev
= bus
->devices
[devfn
];
1501 info
= g_malloc0(sizeof(*info
));
1502 info
->value
= qmp_query_pci_device(dev
, bus
, bus_num
);
1504 /* XXX: waiting for the qapi to support GSList */
1506 head
= cur_item
= info
;
1508 cur_item
->next
= info
;
1517 static PciInfo
*qmp_query_pci_bus(PCIBus
*bus
, int bus_num
)
1519 PciInfo
*info
= NULL
;
1521 bus
= pci_find_bus_nr(bus
, bus_num
);
1523 info
= g_malloc0(sizeof(*info
));
1524 info
->bus
= bus_num
;
1525 info
->devices
= qmp_query_pci_devices(bus
, bus_num
);
1531 PciInfoList
*qmp_query_pci(Error
**errp
)
1533 PciInfoList
*info
, *head
= NULL
, *cur_item
= NULL
;
1534 struct PCIHostBus
*host
;
1536 QLIST_FOREACH(host
, &host_buses
, next
) {
1537 info
= g_malloc0(sizeof(*info
));
1538 info
->value
= qmp_query_pci_bus(host
->bus
, 0);
1540 /* XXX: waiting for the qapi to support GSList */
1542 head
= cur_item
= info
;
1544 cur_item
->next
= info
;
1552 static const char * const pci_nic_models
[] = {
1564 static const char * const pci_nic_names
[] = {
1576 /* Initialize a PCI NIC. */
1577 /* FIXME callers should check for failure, but don't */
1578 PCIDevice
*pci_nic_init(NICInfo
*nd
, PCIBus
*rootbus
,
1579 const char *default_model
,
1580 const char *default_devaddr
)
1582 const char *devaddr
= nd
->devaddr
? nd
->devaddr
: default_devaddr
;
1589 i
= qemu_find_nic_model(nd
, pci_nic_models
, default_model
);
1593 bus
= pci_get_bus_devfn(&devfn
, rootbus
, devaddr
);
1595 error_report("Invalid PCI device address %s for device %s",
1596 devaddr
, pci_nic_names
[i
]);
1600 pci_dev
= pci_create(bus
, devfn
, pci_nic_names
[i
]);
1601 dev
= &pci_dev
->qdev
;
1602 qdev_set_nic_properties(dev
, nd
);
1603 if (qdev_init(dev
) < 0)
1608 PCIDevice
*pci_nic_init_nofail(NICInfo
*nd
, PCIBus
*rootbus
,
1609 const char *default_model
,
1610 const char *default_devaddr
)
1614 if (qemu_show_nic_models(nd
->model
, pci_nic_models
))
1617 res
= pci_nic_init(nd
, rootbus
, default_model
, default_devaddr
);
1623 PCIDevice
*pci_vga_init(PCIBus
*bus
)
1625 switch (vga_interface_type
) {
1627 return pci_create_simple(bus
, -1, "cirrus-vga");
1629 return pci_create_simple(bus
, -1, "qxl-vga");
1631 return pci_create_simple(bus
, -1, "VGA");
1633 return pci_create_simple(bus
, -1, "vmware-svga");
1635 default: /* Other non-PCI types. Checking for unsupported types is already
1641 /* Whether a given bus number is in range of the secondary
1642 * bus of the given bridge device. */
1643 static bool pci_secondary_bus_in_range(PCIDevice
*dev
, int bus_num
)
1645 return !(pci_get_word(dev
->config
+ PCI_BRIDGE_CONTROL
) &
1646 PCI_BRIDGE_CTL_BUS_RESET
) /* Don't walk the bus if it's reset. */ &&
1647 dev
->config
[PCI_SECONDARY_BUS
] < bus_num
&&
1648 bus_num
<= dev
->config
[PCI_SUBORDINATE_BUS
];
1651 static PCIBus
*pci_find_bus_nr(PCIBus
*bus
, int bus_num
)
1659 if (pci_bus_num(bus
) == bus_num
) {
1663 /* Consider all bus numbers in range for the host pci bridge. */
1664 if (!pci_bus_is_root(bus
) &&
1665 !pci_secondary_bus_in_range(bus
->parent_dev
, bus_num
)) {
1670 for (; bus
; bus
= sec
) {
1671 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
1672 assert(!pci_bus_is_root(sec
));
1673 if (sec
->parent_dev
->config
[PCI_SECONDARY_BUS
] == bus_num
) {
1676 if (pci_secondary_bus_in_range(sec
->parent_dev
, bus_num
)) {
1685 PCIDevice
*pci_find_device(PCIBus
*bus
, int bus_num
, uint8_t devfn
)
1687 bus
= pci_find_bus_nr(bus
, bus_num
);
1692 return bus
->devices
[devfn
];
1695 static int pci_qdev_init(DeviceState
*qdev
)
1697 PCIDevice
*pci_dev
= (PCIDevice
*)qdev
;
1698 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(pci_dev
);
1701 bool is_default_rom
;
1703 /* initialize cap_present for pci_is_express() and pci_config_size() */
1704 if (pc
->is_express
) {
1705 pci_dev
->cap_present
|= QEMU_PCI_CAP_EXPRESS
;
1708 bus
= PCI_BUS(qdev_get_parent_bus(qdev
));
1709 pci_dev
= do_pci_register_device(pci_dev
, bus
,
1710 object_get_typename(OBJECT(qdev
)),
1712 if (pci_dev
== NULL
)
1714 if (qdev
->hotplugged
&& pc
->no_hotplug
) {
1715 qerror_report(QERR_DEVICE_NO_HOTPLUG
, object_get_typename(OBJECT(pci_dev
)));
1716 do_pci_unregister_device(pci_dev
);
1720 rc
= pc
->init(pci_dev
);
1722 do_pci_unregister_device(pci_dev
);
1728 is_default_rom
= false;
1729 if (pci_dev
->romfile
== NULL
&& pc
->romfile
!= NULL
) {
1730 pci_dev
->romfile
= g_strdup(pc
->romfile
);
1731 is_default_rom
= true;
1733 pci_add_option_rom(pci_dev
, is_default_rom
);
1736 /* Let buses differentiate between hotplug and when device is
1737 * enabled during qemu machine creation. */
1738 rc
= bus
->hotplug(bus
->hotplug_qdev
, pci_dev
,
1739 qdev
->hotplugged
? PCI_HOTPLUG_ENABLED
:
1740 PCI_COLDPLUG_ENABLED
);
1742 int r
= pci_unregister_device(&pci_dev
->qdev
);
1750 static int pci_unplug_device(DeviceState
*qdev
)
1752 PCIDevice
*dev
= PCI_DEVICE(qdev
);
1753 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(dev
);
1755 if (pc
->no_hotplug
) {
1756 qerror_report(QERR_DEVICE_NO_HOTPLUG
, object_get_typename(OBJECT(dev
)));
1759 return dev
->bus
->hotplug(dev
->bus
->hotplug_qdev
, dev
,
1760 PCI_HOTPLUG_DISABLED
);
1763 PCIDevice
*pci_create_multifunction(PCIBus
*bus
, int devfn
, bool multifunction
,
1768 dev
= qdev_create(&bus
->qbus
, name
);
1769 qdev_prop_set_int32(dev
, "addr", devfn
);
1770 qdev_prop_set_bit(dev
, "multifunction", multifunction
);
1771 return PCI_DEVICE(dev
);
1774 PCIDevice
*pci_create_simple_multifunction(PCIBus
*bus
, int devfn
,
1778 PCIDevice
*dev
= pci_create_multifunction(bus
, devfn
, multifunction
, name
);
1779 qdev_init_nofail(&dev
->qdev
);
1783 PCIDevice
*pci_create(PCIBus
*bus
, int devfn
, const char *name
)
1785 return pci_create_multifunction(bus
, devfn
, false, name
);
1788 PCIDevice
*pci_create_simple(PCIBus
*bus
, int devfn
, const char *name
)
1790 return pci_create_simple_multifunction(bus
, devfn
, false, name
);
1793 static uint8_t pci_find_space(PCIDevice
*pdev
, uint8_t size
)
1795 int offset
= PCI_CONFIG_HEADER_SIZE
;
1797 for (i
= PCI_CONFIG_HEADER_SIZE
; i
< PCI_CONFIG_SPACE_SIZE
; ++i
) {
1800 else if (i
- offset
+ 1 == size
)
1806 static uint8_t pci_find_capability_list(PCIDevice
*pdev
, uint8_t cap_id
,
1811 if (!(pdev
->config
[PCI_STATUS
] & PCI_STATUS_CAP_LIST
))
1814 for (prev
= PCI_CAPABILITY_LIST
; (next
= pdev
->config
[prev
]);
1815 prev
= next
+ PCI_CAP_LIST_NEXT
)
1816 if (pdev
->config
[next
+ PCI_CAP_LIST_ID
] == cap_id
)
1824 static uint8_t pci_find_capability_at_offset(PCIDevice
*pdev
, uint8_t offset
)
1826 uint8_t next
, prev
, found
= 0;
1828 if (!(pdev
->used
[offset
])) {
1832 assert(pdev
->config
[PCI_STATUS
] & PCI_STATUS_CAP_LIST
);
1834 for (prev
= PCI_CAPABILITY_LIST
; (next
= pdev
->config
[prev
]);
1835 prev
= next
+ PCI_CAP_LIST_NEXT
) {
1836 if (next
<= offset
&& next
> found
) {
1843 /* Patch the PCI vendor and device ids in a PCI rom image if necessary.
1844 This is needed for an option rom which is used for more than one device. */
1845 static void pci_patch_ids(PCIDevice
*pdev
, uint8_t *ptr
, int size
)
1849 uint16_t rom_vendor_id
;
1850 uint16_t rom_device_id
;
1852 uint16_t pcir_offset
;
1855 /* Words in rom data are little endian (like in PCI configuration),
1856 so they can be read / written with pci_get_word / pci_set_word. */
1858 /* Only a valid rom will be patched. */
1859 rom_magic
= pci_get_word(ptr
);
1860 if (rom_magic
!= 0xaa55) {
1861 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic
);
1864 pcir_offset
= pci_get_word(ptr
+ 0x18);
1865 if (pcir_offset
+ 8 >= size
|| memcmp(ptr
+ pcir_offset
, "PCIR", 4)) {
1866 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset
);
1870 vendor_id
= pci_get_word(pdev
->config
+ PCI_VENDOR_ID
);
1871 device_id
= pci_get_word(pdev
->config
+ PCI_DEVICE_ID
);
1872 rom_vendor_id
= pci_get_word(ptr
+ pcir_offset
+ 4);
1873 rom_device_id
= pci_get_word(ptr
+ pcir_offset
+ 6);
1875 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev
->romfile
,
1876 vendor_id
, device_id
, rom_vendor_id
, rom_device_id
);
1880 if (vendor_id
!= rom_vendor_id
) {
1881 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */
1882 checksum
+= (uint8_t)rom_vendor_id
+ (uint8_t)(rom_vendor_id
>> 8);
1883 checksum
-= (uint8_t)vendor_id
+ (uint8_t)(vendor_id
>> 8);
1884 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr
[6], checksum
);
1886 pci_set_word(ptr
+ pcir_offset
+ 4, vendor_id
);
1889 if (device_id
!= rom_device_id
) {
1890 /* Patch device id and checksum (at offset 6 for etherboot roms). */
1891 checksum
+= (uint8_t)rom_device_id
+ (uint8_t)(rom_device_id
>> 8);
1892 checksum
-= (uint8_t)device_id
+ (uint8_t)(device_id
>> 8);
1893 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr
[6], checksum
);
1895 pci_set_word(ptr
+ pcir_offset
+ 6, device_id
);
1899 /* Add an option rom for the device */
1900 static int pci_add_option_rom(PCIDevice
*pdev
, bool is_default_rom
)
1906 const VMStateDescription
*vmsd
;
1910 if (strlen(pdev
->romfile
) == 0)
1913 if (!pdev
->rom_bar
) {
1915 * Load rom via fw_cfg instead of creating a rom bar,
1916 * for 0.11 compatibility.
1918 int class = pci_get_word(pdev
->config
+ PCI_CLASS_DEVICE
);
1919 if (class == 0x0300) {
1920 rom_add_vga(pdev
->romfile
);
1922 rom_add_option(pdev
->romfile
, -1);
1927 path
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, pdev
->romfile
);
1929 path
= g_strdup(pdev
->romfile
);
1932 size
= get_image_size(path
);
1934 error_report("%s: failed to find romfile \"%s\"",
1935 __func__
, pdev
->romfile
);
1938 } else if (size
== 0) {
1939 error_report("%s: ignoring empty romfile \"%s\"",
1940 __func__
, pdev
->romfile
);
1944 if (size
& (size
- 1)) {
1945 size
= 1 << qemu_fls(size
);
1948 vmsd
= qdev_get_vmsd(DEVICE(pdev
));
1951 snprintf(name
, sizeof(name
), "%s.rom", vmsd
->name
);
1953 snprintf(name
, sizeof(name
), "%s.rom", object_get_typename(OBJECT(pdev
)));
1955 pdev
->has_rom
= true;
1956 memory_region_init_ram(&pdev
->rom
, name
, size
);
1957 vmstate_register_ram(&pdev
->rom
, &pdev
->qdev
);
1958 ptr
= memory_region_get_ram_ptr(&pdev
->rom
);
1959 load_image(path
, ptr
);
1962 if (is_default_rom
) {
1963 /* Only the default rom images will be patched (if needed). */
1964 pci_patch_ids(pdev
, ptr
, size
);
1967 pci_register_bar(pdev
, PCI_ROM_SLOT
, 0, &pdev
->rom
);
1972 static void pci_del_option_rom(PCIDevice
*pdev
)
1977 vmstate_unregister_ram(&pdev
->rom
, &pdev
->qdev
);
1978 memory_region_destroy(&pdev
->rom
);
1979 pdev
->has_rom
= false;
1984 * Reserve space and add capability to the linked list in pci config space
1987 * Find and reserve space and add capability to the linked list
1988 * in pci config space */
1989 int pci_add_capability(PCIDevice
*pdev
, uint8_t cap_id
,
1990 uint8_t offset
, uint8_t size
)
1993 int i
, overlapping_cap
;
1996 offset
= pci_find_space(pdev
, size
);
2001 /* Verify that capabilities don't overlap. Note: device assignment
2002 * depends on this check to verify that the device is not broken.
2003 * Should never trigger for emulated devices, but it's helpful
2004 * for debugging these. */
2005 for (i
= offset
; i
< offset
+ size
; i
++) {
2006 overlapping_cap
= pci_find_capability_at_offset(pdev
, i
);
2007 if (overlapping_cap
) {
2008 fprintf(stderr
, "ERROR: %s:%02x:%02x.%x "
2009 "Attempt to add PCI capability %x at offset "
2010 "%x overlaps existing capability %x at offset %x\n",
2011 pci_root_bus_path(pdev
), pci_bus_num(pdev
->bus
),
2012 PCI_SLOT(pdev
->devfn
), PCI_FUNC(pdev
->devfn
),
2013 cap_id
, offset
, overlapping_cap
, i
);
2019 config
= pdev
->config
+ offset
;
2020 config
[PCI_CAP_LIST_ID
] = cap_id
;
2021 config
[PCI_CAP_LIST_NEXT
] = pdev
->config
[PCI_CAPABILITY_LIST
];
2022 pdev
->config
[PCI_CAPABILITY_LIST
] = offset
;
2023 pdev
->config
[PCI_STATUS
] |= PCI_STATUS_CAP_LIST
;
2024 memset(pdev
->used
+ offset
, 0xFF, QEMU_ALIGN_UP(size
, 4));
2025 /* Make capability read-only by default */
2026 memset(pdev
->wmask
+ offset
, 0, size
);
2027 /* Check capability by default */
2028 memset(pdev
->cmask
+ offset
, 0xFF, size
);
2032 /* Unlink capability from the pci config space. */
2033 void pci_del_capability(PCIDevice
*pdev
, uint8_t cap_id
, uint8_t size
)
2035 uint8_t prev
, offset
= pci_find_capability_list(pdev
, cap_id
, &prev
);
2038 pdev
->config
[prev
] = pdev
->config
[offset
+ PCI_CAP_LIST_NEXT
];
2039 /* Make capability writable again */
2040 memset(pdev
->wmask
+ offset
, 0xff, size
);
2041 memset(pdev
->w1cmask
+ offset
, 0, size
);
2042 /* Clear cmask as device-specific registers can't be checked */
2043 memset(pdev
->cmask
+ offset
, 0, size
);
2044 memset(pdev
->used
+ offset
, 0, QEMU_ALIGN_UP(size
, 4));
2046 if (!pdev
->config
[PCI_CAPABILITY_LIST
])
2047 pdev
->config
[PCI_STATUS
] &= ~PCI_STATUS_CAP_LIST
;
2050 uint8_t pci_find_capability(PCIDevice
*pdev
, uint8_t cap_id
)
2052 return pci_find_capability_list(pdev
, cap_id
, NULL
);
2055 static void pcibus_dev_print(Monitor
*mon
, DeviceState
*dev
, int indent
)
2057 PCIDevice
*d
= (PCIDevice
*)dev
;
2058 const pci_class_desc
*desc
;
2063 class = pci_get_word(d
->config
+ PCI_CLASS_DEVICE
);
2064 desc
= pci_class_descriptions
;
2065 while (desc
->desc
&& class != desc
->class)
2068 snprintf(ctxt
, sizeof(ctxt
), "%s", desc
->desc
);
2070 snprintf(ctxt
, sizeof(ctxt
), "Class %04x", class);
2073 monitor_printf(mon
, "%*sclass %s, addr %02x:%02x.%x, "
2074 "pci id %04x:%04x (sub %04x:%04x)\n",
2075 indent
, "", ctxt
, pci_bus_num(d
->bus
),
2076 PCI_SLOT(d
->devfn
), PCI_FUNC(d
->devfn
),
2077 pci_get_word(d
->config
+ PCI_VENDOR_ID
),
2078 pci_get_word(d
->config
+ PCI_DEVICE_ID
),
2079 pci_get_word(d
->config
+ PCI_SUBSYSTEM_VENDOR_ID
),
2080 pci_get_word(d
->config
+ PCI_SUBSYSTEM_ID
));
2081 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
2082 r
= &d
->io_regions
[i
];
2085 monitor_printf(mon
, "%*sbar %d: %s at 0x%"FMT_PCIBUS
2086 " [0x%"FMT_PCIBUS
"]\n",
2088 i
, r
->type
& PCI_BASE_ADDRESS_SPACE_IO
? "i/o" : "mem",
2089 r
->addr
, r
->addr
+ r
->size
- 1);
2093 static char *pci_dev_fw_name(DeviceState
*dev
, char *buf
, int len
)
2095 PCIDevice
*d
= (PCIDevice
*)dev
;
2096 const char *name
= NULL
;
2097 const pci_class_desc
*desc
= pci_class_descriptions
;
2098 int class = pci_get_word(d
->config
+ PCI_CLASS_DEVICE
);
2100 while (desc
->desc
&&
2101 (class & ~desc
->fw_ign_bits
) !=
2102 (desc
->class & ~desc
->fw_ign_bits
)) {
2107 name
= desc
->fw_name
;
2111 pstrcpy(buf
, len
, name
);
2113 snprintf(buf
, len
, "pci%04x,%04x",
2114 pci_get_word(d
->config
+ PCI_VENDOR_ID
),
2115 pci_get_word(d
->config
+ PCI_DEVICE_ID
));
2121 static char *pcibus_get_fw_dev_path(DeviceState
*dev
)
2123 PCIDevice
*d
= (PCIDevice
*)dev
;
2124 char path
[50], name
[33];
2127 off
= snprintf(path
, sizeof(path
), "%s@%x",
2128 pci_dev_fw_name(dev
, name
, sizeof name
),
2129 PCI_SLOT(d
->devfn
));
2130 if (PCI_FUNC(d
->devfn
))
2131 snprintf(path
+ off
, sizeof(path
) + off
, ",%x", PCI_FUNC(d
->devfn
));
2132 return g_strdup(path
);
2135 static char *pcibus_get_dev_path(DeviceState
*dev
)
2137 PCIDevice
*d
= container_of(dev
, PCIDevice
, qdev
);
2140 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function.
2141 * 00 is added here to make this format compatible with
2142 * domain:Bus:Slot.Func for systems without nested PCI bridges.
2143 * Slot.Function list specifies the slot and function numbers for all
2144 * devices on the path from root to the specific device. */
2145 const char *root_bus_path
;
2147 char slot
[] = ":SS.F";
2148 int slot_len
= sizeof slot
- 1 /* For '\0' */;
2153 root_bus_path
= pci_root_bus_path(d
);
2154 root_bus_len
= strlen(root_bus_path
);
2156 /* Calculate # of slots on path between device and root. */;
2158 for (t
= d
; t
; t
= t
->bus
->parent_dev
) {
2162 path_len
= root_bus_len
+ slot_len
* slot_depth
;
2164 /* Allocate memory, fill in the terminating null byte. */
2165 path
= g_malloc(path_len
+ 1 /* For '\0' */);
2166 path
[path_len
] = '\0';
2168 memcpy(path
, root_bus_path
, root_bus_len
);
2170 /* Fill in slot numbers. We walk up from device to root, so need to print
2171 * them in the reverse order, last to first. */
2172 p
= path
+ path_len
;
2173 for (t
= d
; t
; t
= t
->bus
->parent_dev
) {
2175 s
= snprintf(slot
, sizeof slot
, ":%02x.%x",
2176 PCI_SLOT(t
->devfn
), PCI_FUNC(t
->devfn
));
2177 assert(s
== slot_len
);
2178 memcpy(p
, slot
, slot_len
);
2184 static int pci_qdev_find_recursive(PCIBus
*bus
,
2185 const char *id
, PCIDevice
**pdev
)
2187 DeviceState
*qdev
= qdev_find_recursive(&bus
->qbus
, id
);
2192 /* roughly check if given qdev is pci device */
2193 if (object_dynamic_cast(OBJECT(qdev
), TYPE_PCI_DEVICE
)) {
2194 *pdev
= PCI_DEVICE(qdev
);
2200 int pci_qdev_find_device(const char *id
, PCIDevice
**pdev
)
2202 struct PCIHostBus
*host
;
2205 QLIST_FOREACH(host
, &host_buses
, next
) {
2206 int tmp
= pci_qdev_find_recursive(host
->bus
, id
, pdev
);
2211 if (tmp
!= -ENODEV
) {
2219 MemoryRegion
*pci_address_space(PCIDevice
*dev
)
2221 return dev
->bus
->address_space_mem
;
2224 MemoryRegion
*pci_address_space_io(PCIDevice
*dev
)
2226 return dev
->bus
->address_space_io
;
2229 static void pci_device_class_init(ObjectClass
*klass
, void *data
)
2231 DeviceClass
*k
= DEVICE_CLASS(klass
);
2232 k
->init
= pci_qdev_init
;
2233 k
->unplug
= pci_unplug_device
;
2234 k
->exit
= pci_unregister_device
;
2235 k
->bus_type
= TYPE_PCI_BUS
;
2236 k
->props
= pci_props
;
2239 void pci_setup_iommu(PCIBus
*bus
, PCIIOMMUFunc fn
, void *opaque
)
2242 bus
->iommu_opaque
= opaque
;
2245 static const TypeInfo pci_device_type_info
= {
2246 .name
= TYPE_PCI_DEVICE
,
2247 .parent
= TYPE_DEVICE
,
2248 .instance_size
= sizeof(PCIDevice
),
2250 .class_size
= sizeof(PCIDeviceClass
),
2251 .class_init
= pci_device_class_init
,
2254 static void pci_register_types(void)
2256 type_register_static(&pci_bus_info
);
2257 type_register_static(&pcie_bus_info
);
2258 type_register_static(&pci_device_type_info
);
2261 type_init(pci_register_types
)