4 * Copyright (c) 2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "qemu-common.h"
28 #include "hw/pci/pci.h"
29 #include "hw/pci/pci_bridge.h"
30 #include "hw/pci/pci_bus.h"
31 #include "hw/pci/pci_host.h"
32 #include "hw/qdev-properties.h"
33 #include "migration/qemu-file-types.h"
34 #include "migration/vmstate.h"
35 #include "monitor/monitor.h"
37 #include "sysemu/numa.h"
38 #include "sysemu/sysemu.h"
39 #include "hw/loader.h"
40 #include "qemu/error-report.h"
41 #include "qemu/range.h"
43 #include "hw/pci/msi.h"
44 #include "hw/pci/msix.h"
45 #include "exec/address-spaces.h"
46 #include "hw/hotplug.h"
47 #include "hw/boards.h"
48 #include "qapi/error.h"
49 #include "qapi/qapi-commands-pci.h"
50 #include "qemu/cutils.h"
54 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
56 # define PCI_DPRINTF(format, ...) do { } while (0)
59 bool pci_available
= true;
61 static void pcibus_dev_print(Monitor
*mon
, DeviceState
*dev
, int indent
);
62 static char *pcibus_get_dev_path(DeviceState
*dev
);
63 static char *pcibus_get_fw_dev_path(DeviceState
*dev
);
64 static void pcibus_reset(BusState
*qbus
);
66 static Property pci_props
[] = {
67 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice
, devfn
, -1),
68 DEFINE_PROP_STRING("romfile", PCIDevice
, romfile
),
69 DEFINE_PROP_UINT32("rombar", PCIDevice
, rom_bar
, 1),
70 DEFINE_PROP_BIT("multifunction", PCIDevice
, cap_present
,
71 QEMU_PCI_CAP_MULTIFUNCTION_BITNR
, false),
72 DEFINE_PROP_BIT("x-pcie-lnksta-dllla", PCIDevice
, cap_present
,
73 QEMU_PCIE_LNKSTA_DLLLA_BITNR
, true),
74 DEFINE_PROP_BIT("x-pcie-extcap-init", PCIDevice
, cap_present
,
75 QEMU_PCIE_EXTCAP_INIT_BITNR
, true),
76 DEFINE_PROP_STRING("failover_pair_id", PCIDevice
,
78 DEFINE_PROP_END_OF_LIST()
81 static const VMStateDescription vmstate_pcibus
= {
84 .minimum_version_id
= 1,
85 .fields
= (VMStateField
[]) {
86 VMSTATE_INT32_EQUAL(nirq
, PCIBus
, NULL
),
87 VMSTATE_VARRAY_INT32(irq_count
, PCIBus
,
88 nirq
, 0, vmstate_info_int32
,
94 static void pci_init_bus_master(PCIDevice
*pci_dev
)
96 AddressSpace
*dma_as
= pci_device_iommu_address_space(pci_dev
);
98 memory_region_init_alias(&pci_dev
->bus_master_enable_region
,
99 OBJECT(pci_dev
), "bus master",
100 dma_as
->root
, 0, memory_region_size(dma_as
->root
));
101 memory_region_set_enabled(&pci_dev
->bus_master_enable_region
, false);
102 memory_region_add_subregion(&pci_dev
->bus_master_container_region
, 0,
103 &pci_dev
->bus_master_enable_region
);
106 static void pcibus_machine_done(Notifier
*notifier
, void *data
)
108 PCIBus
*bus
= container_of(notifier
, PCIBus
, machine_done
);
111 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); ++i
) {
112 if (bus
->devices
[i
]) {
113 pci_init_bus_master(bus
->devices
[i
]);
118 static void pci_bus_realize(BusState
*qbus
, Error
**errp
)
120 PCIBus
*bus
= PCI_BUS(qbus
);
122 bus
->machine_done
.notify
= pcibus_machine_done
;
123 qemu_add_machine_init_done_notifier(&bus
->machine_done
);
125 vmstate_register(NULL
, VMSTATE_INSTANCE_ID_ANY
, &vmstate_pcibus
, bus
);
128 static void pcie_bus_realize(BusState
*qbus
, Error
**errp
)
130 PCIBus
*bus
= PCI_BUS(qbus
);
132 pci_bus_realize(qbus
, errp
);
135 * A PCI-E bus can support extended config space if it's the root
136 * bus, or if the bus/bridge above it does as well
138 if (pci_bus_is_root(bus
)) {
139 bus
->flags
|= PCI_BUS_EXTENDED_CONFIG_SPACE
;
141 PCIBus
*parent_bus
= pci_get_bus(bus
->parent_dev
);
143 if (pci_bus_allows_extended_config_space(parent_bus
)) {
144 bus
->flags
|= PCI_BUS_EXTENDED_CONFIG_SPACE
;
149 static void pci_bus_unrealize(BusState
*qbus
)
151 PCIBus
*bus
= PCI_BUS(qbus
);
153 qemu_remove_machine_init_done_notifier(&bus
->machine_done
);
155 vmstate_unregister(NULL
, &vmstate_pcibus
, bus
);
158 static int pcibus_num(PCIBus
*bus
)
160 if (pci_bus_is_root(bus
)) {
161 return 0; /* pci host bridge */
163 return bus
->parent_dev
->config
[PCI_SECONDARY_BUS
];
166 static uint16_t pcibus_numa_node(PCIBus
*bus
)
168 return NUMA_NODE_UNASSIGNED
;
171 static void pci_bus_class_init(ObjectClass
*klass
, void *data
)
173 BusClass
*k
= BUS_CLASS(klass
);
174 PCIBusClass
*pbc
= PCI_BUS_CLASS(klass
);
176 k
->print_dev
= pcibus_dev_print
;
177 k
->get_dev_path
= pcibus_get_dev_path
;
178 k
->get_fw_dev_path
= pcibus_get_fw_dev_path
;
179 k
->realize
= pci_bus_realize
;
180 k
->unrealize
= pci_bus_unrealize
;
181 k
->reset
= pcibus_reset
;
183 pbc
->bus_num
= pcibus_num
;
184 pbc
->numa_node
= pcibus_numa_node
;
187 static const TypeInfo pci_bus_info
= {
188 .name
= TYPE_PCI_BUS
,
190 .instance_size
= sizeof(PCIBus
),
191 .class_size
= sizeof(PCIBusClass
),
192 .class_init
= pci_bus_class_init
,
195 static const TypeInfo pcie_interface_info
= {
196 .name
= INTERFACE_PCIE_DEVICE
,
197 .parent
= TYPE_INTERFACE
,
200 static const TypeInfo conventional_pci_interface_info
= {
201 .name
= INTERFACE_CONVENTIONAL_PCI_DEVICE
,
202 .parent
= TYPE_INTERFACE
,
205 static void pcie_bus_class_init(ObjectClass
*klass
, void *data
)
207 BusClass
*k
= BUS_CLASS(klass
);
209 k
->realize
= pcie_bus_realize
;
212 static const TypeInfo pcie_bus_info
= {
213 .name
= TYPE_PCIE_BUS
,
214 .parent
= TYPE_PCI_BUS
,
215 .class_init
= pcie_bus_class_init
,
218 static PCIBus
*pci_find_bus_nr(PCIBus
*bus
, int bus_num
);
219 static void pci_update_mappings(PCIDevice
*d
);
220 static void pci_irq_handler(void *opaque
, int irq_num
, int level
);
221 static void pci_add_option_rom(PCIDevice
*pdev
, bool is_default_rom
, Error
**);
222 static void pci_del_option_rom(PCIDevice
*pdev
);
224 static uint16_t pci_default_sub_vendor_id
= PCI_SUBVENDOR_ID_REDHAT_QUMRANET
;
225 static uint16_t pci_default_sub_device_id
= PCI_SUBDEVICE_ID_QEMU
;
227 static QLIST_HEAD(, PCIHostState
) pci_host_bridges
;
229 int pci_bar(PCIDevice
*d
, int reg
)
233 if (reg
!= PCI_ROM_SLOT
)
234 return PCI_BASE_ADDRESS_0
+ reg
* 4;
236 type
= d
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
237 return type
== PCI_HEADER_TYPE_BRIDGE
? PCI_ROM_ADDRESS1
: PCI_ROM_ADDRESS
;
240 static inline int pci_irq_state(PCIDevice
*d
, int irq_num
)
242 return (d
->irq_state
>> irq_num
) & 0x1;
245 static inline void pci_set_irq_state(PCIDevice
*d
, int irq_num
, int level
)
247 d
->irq_state
&= ~(0x1 << irq_num
);
248 d
->irq_state
|= level
<< irq_num
;
251 static void pci_bus_change_irq_level(PCIBus
*bus
, int irq_num
, int change
)
253 bus
->irq_count
[irq_num
] += change
;
254 bus
->set_irq(bus
->irq_opaque
, irq_num
, bus
->irq_count
[irq_num
] != 0);
257 static void pci_change_irq_level(PCIDevice
*pci_dev
, int irq_num
, int change
)
261 bus
= pci_get_bus(pci_dev
);
262 irq_num
= bus
->map_irq(pci_dev
, irq_num
);
265 pci_dev
= bus
->parent_dev
;
267 pci_bus_change_irq_level(bus
, irq_num
, change
);
270 int pci_bus_get_irq_level(PCIBus
*bus
, int irq_num
)
272 assert(irq_num
>= 0);
273 assert(irq_num
< bus
->nirq
);
274 return !!bus
->irq_count
[irq_num
];
277 /* Update interrupt status bit in config space on interrupt
279 static void pci_update_irq_status(PCIDevice
*dev
)
281 if (dev
->irq_state
) {
282 dev
->config
[PCI_STATUS
] |= PCI_STATUS_INTERRUPT
;
284 dev
->config
[PCI_STATUS
] &= ~PCI_STATUS_INTERRUPT
;
288 void pci_device_deassert_intx(PCIDevice
*dev
)
291 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
292 pci_irq_handler(dev
, i
, 0);
296 static void pci_do_device_reset(PCIDevice
*dev
)
300 pci_device_deassert_intx(dev
);
301 assert(dev
->irq_state
== 0);
303 /* Clear all writable bits */
304 pci_word_test_and_clear_mask(dev
->config
+ PCI_COMMAND
,
305 pci_get_word(dev
->wmask
+ PCI_COMMAND
) |
306 pci_get_word(dev
->w1cmask
+ PCI_COMMAND
));
307 pci_word_test_and_clear_mask(dev
->config
+ PCI_STATUS
,
308 pci_get_word(dev
->wmask
+ PCI_STATUS
) |
309 pci_get_word(dev
->w1cmask
+ PCI_STATUS
));
310 /* Some devices make bits of PCI_INTERRUPT_LINE read only */
311 pci_byte_test_and_clear_mask(dev
->config
+ PCI_INTERRUPT_LINE
,
312 pci_get_word(dev
->wmask
+ PCI_INTERRUPT_LINE
) |
313 pci_get_word(dev
->w1cmask
+ PCI_INTERRUPT_LINE
));
314 dev
->config
[PCI_CACHE_LINE_SIZE
] = 0x0;
315 for (r
= 0; r
< PCI_NUM_REGIONS
; ++r
) {
316 PCIIORegion
*region
= &dev
->io_regions
[r
];
321 if (!(region
->type
& PCI_BASE_ADDRESS_SPACE_IO
) &&
322 region
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
323 pci_set_quad(dev
->config
+ pci_bar(dev
, r
), region
->type
);
325 pci_set_long(dev
->config
+ pci_bar(dev
, r
), region
->type
);
328 pci_update_mappings(dev
);
335 * This function is called on #RST and FLR.
336 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
338 void pci_device_reset(PCIDevice
*dev
)
340 qdev_reset_all(&dev
->qdev
);
341 pci_do_device_reset(dev
);
345 * Trigger pci bus reset under a given bus.
346 * Called via qbus_reset_all on RST# assert, after the devices
347 * have been reset qdev_reset_all-ed already.
349 static void pcibus_reset(BusState
*qbus
)
351 PCIBus
*bus
= DO_UPCAST(PCIBus
, qbus
, qbus
);
354 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); ++i
) {
355 if (bus
->devices
[i
]) {
356 pci_do_device_reset(bus
->devices
[i
]);
360 for (i
= 0; i
< bus
->nirq
; i
++) {
361 assert(bus
->irq_count
[i
] == 0);
365 static void pci_host_bus_register(DeviceState
*host
)
367 PCIHostState
*host_bridge
= PCI_HOST_BRIDGE(host
);
369 QLIST_INSERT_HEAD(&pci_host_bridges
, host_bridge
, next
);
372 static void pci_host_bus_unregister(DeviceState
*host
)
374 PCIHostState
*host_bridge
= PCI_HOST_BRIDGE(host
);
376 QLIST_REMOVE(host_bridge
, next
);
379 PCIBus
*pci_device_root_bus(const PCIDevice
*d
)
381 PCIBus
*bus
= pci_get_bus(d
);
383 while (!pci_bus_is_root(bus
)) {
387 bus
= pci_get_bus(d
);
393 const char *pci_root_bus_path(PCIDevice
*dev
)
395 PCIBus
*rootbus
= pci_device_root_bus(dev
);
396 PCIHostState
*host_bridge
= PCI_HOST_BRIDGE(rootbus
->qbus
.parent
);
397 PCIHostBridgeClass
*hc
= PCI_HOST_BRIDGE_GET_CLASS(host_bridge
);
399 assert(host_bridge
->bus
== rootbus
);
401 if (hc
->root_bus_path
) {
402 return (*hc
->root_bus_path
)(host_bridge
, rootbus
);
405 return rootbus
->qbus
.name
;
408 static void pci_root_bus_init(PCIBus
*bus
, DeviceState
*parent
,
409 MemoryRegion
*address_space_mem
,
410 MemoryRegion
*address_space_io
,
413 assert(PCI_FUNC(devfn_min
) == 0);
414 bus
->devfn_min
= devfn_min
;
415 bus
->slot_reserved_mask
= 0x0;
416 bus
->address_space_mem
= address_space_mem
;
417 bus
->address_space_io
= address_space_io
;
418 bus
->flags
|= PCI_BUS_IS_ROOT
;
421 QLIST_INIT(&bus
->child
);
423 pci_host_bus_register(parent
);
426 static void pci_bus_uninit(PCIBus
*bus
)
428 pci_host_bus_unregister(BUS(bus
)->parent
);
431 bool pci_bus_is_express(PCIBus
*bus
)
433 return object_dynamic_cast(OBJECT(bus
), TYPE_PCIE_BUS
);
436 void pci_root_bus_new_inplace(PCIBus
*bus
, size_t bus_size
, DeviceState
*parent
,
438 MemoryRegion
*address_space_mem
,
439 MemoryRegion
*address_space_io
,
440 uint8_t devfn_min
, const char *typename
)
442 qbus_create_inplace(bus
, bus_size
, typename
, parent
, name
);
443 pci_root_bus_init(bus
, parent
, address_space_mem
, address_space_io
,
447 PCIBus
*pci_root_bus_new(DeviceState
*parent
, const char *name
,
448 MemoryRegion
*address_space_mem
,
449 MemoryRegion
*address_space_io
,
450 uint8_t devfn_min
, const char *typename
)
454 bus
= PCI_BUS(qbus_create(typename
, parent
, name
));
455 pci_root_bus_init(bus
, parent
, address_space_mem
, address_space_io
,
460 void pci_root_bus_cleanup(PCIBus
*bus
)
463 /* the caller of the unplug hotplug handler will delete this device */
464 qbus_unrealize(BUS(bus
));
467 void pci_bus_irqs(PCIBus
*bus
, pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
468 void *irq_opaque
, int nirq
)
470 bus
->set_irq
= set_irq
;
471 bus
->map_irq
= map_irq
;
472 bus
->irq_opaque
= irq_opaque
;
474 bus
->irq_count
= g_malloc0(nirq
* sizeof(bus
->irq_count
[0]));
477 void pci_bus_irqs_cleanup(PCIBus
*bus
)
481 bus
->irq_opaque
= NULL
;
483 g_free(bus
->irq_count
);
486 PCIBus
*pci_register_root_bus(DeviceState
*parent
, const char *name
,
487 pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
489 MemoryRegion
*address_space_mem
,
490 MemoryRegion
*address_space_io
,
491 uint8_t devfn_min
, int nirq
,
492 const char *typename
)
496 bus
= pci_root_bus_new(parent
, name
, address_space_mem
,
497 address_space_io
, devfn_min
, typename
);
498 pci_bus_irqs(bus
, set_irq
, map_irq
, irq_opaque
, nirq
);
502 void pci_unregister_root_bus(PCIBus
*bus
)
504 pci_bus_irqs_cleanup(bus
);
505 pci_root_bus_cleanup(bus
);
508 int pci_bus_num(PCIBus
*s
)
510 return PCI_BUS_GET_CLASS(s
)->bus_num(s
);
513 int pci_bus_numa_node(PCIBus
*bus
)
515 return PCI_BUS_GET_CLASS(bus
)->numa_node(bus
);
518 static int get_pci_config_device(QEMUFile
*f
, void *pv
, size_t size
,
519 const VMStateField
*field
)
521 PCIDevice
*s
= container_of(pv
, PCIDevice
, config
);
522 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(s
);
526 assert(size
== pci_config_size(s
));
527 config
= g_malloc(size
);
529 qemu_get_buffer(f
, config
, size
);
530 for (i
= 0; i
< size
; ++i
) {
531 if ((config
[i
] ^ s
->config
[i
]) &
532 s
->cmask
[i
] & ~s
->wmask
[i
] & ~s
->w1cmask
[i
]) {
533 error_report("%s: Bad config data: i=0x%x read: %x device: %x "
534 "cmask: %x wmask: %x w1cmask:%x", __func__
,
535 i
, config
[i
], s
->config
[i
],
536 s
->cmask
[i
], s
->wmask
[i
], s
->w1cmask
[i
]);
541 memcpy(s
->config
, config
, size
);
543 pci_update_mappings(s
);
545 PCIBridge
*b
= PCI_BRIDGE(s
);
546 pci_bridge_update_mappings(b
);
549 memory_region_set_enabled(&s
->bus_master_enable_region
,
550 pci_get_word(s
->config
+ PCI_COMMAND
)
551 & PCI_COMMAND_MASTER
);
557 /* just put buffer */
558 static int put_pci_config_device(QEMUFile
*f
, void *pv
, size_t size
,
559 const VMStateField
*field
, QJSON
*vmdesc
)
561 const uint8_t **v
= pv
;
562 assert(size
== pci_config_size(container_of(pv
, PCIDevice
, config
)));
563 qemu_put_buffer(f
, *v
, size
);
568 static VMStateInfo vmstate_info_pci_config
= {
569 .name
= "pci config",
570 .get
= get_pci_config_device
,
571 .put
= put_pci_config_device
,
574 static int get_pci_irq_state(QEMUFile
*f
, void *pv
, size_t size
,
575 const VMStateField
*field
)
577 PCIDevice
*s
= container_of(pv
, PCIDevice
, irq_state
);
578 uint32_t irq_state
[PCI_NUM_PINS
];
580 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
581 irq_state
[i
] = qemu_get_be32(f
);
582 if (irq_state
[i
] != 0x1 && irq_state
[i
] != 0) {
583 fprintf(stderr
, "irq state %d: must be 0 or 1.\n",
589 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
590 pci_set_irq_state(s
, i
, irq_state
[i
]);
596 static int put_pci_irq_state(QEMUFile
*f
, void *pv
, size_t size
,
597 const VMStateField
*field
, QJSON
*vmdesc
)
600 PCIDevice
*s
= container_of(pv
, PCIDevice
, irq_state
);
602 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
603 qemu_put_be32(f
, pci_irq_state(s
, i
));
609 static VMStateInfo vmstate_info_pci_irq_state
= {
610 .name
= "pci irq state",
611 .get
= get_pci_irq_state
,
612 .put
= put_pci_irq_state
,
615 static bool migrate_is_pcie(void *opaque
, int version_id
)
617 return pci_is_express((PCIDevice
*)opaque
);
620 static bool migrate_is_not_pcie(void *opaque
, int version_id
)
622 return !pci_is_express((PCIDevice
*)opaque
);
625 const VMStateDescription vmstate_pci_device
= {
628 .minimum_version_id
= 1,
629 .fields
= (VMStateField
[]) {
630 VMSTATE_INT32_POSITIVE_LE(version_id
, PCIDevice
),
631 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config
, PCIDevice
,
633 0, vmstate_info_pci_config
,
634 PCI_CONFIG_SPACE_SIZE
),
635 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config
, PCIDevice
,
637 0, vmstate_info_pci_config
,
638 PCIE_CONFIG_SPACE_SIZE
),
639 VMSTATE_BUFFER_UNSAFE_INFO(irq_state
, PCIDevice
, 2,
640 vmstate_info_pci_irq_state
,
641 PCI_NUM_PINS
* sizeof(int32_t)),
642 VMSTATE_END_OF_LIST()
647 void pci_device_save(PCIDevice
*s
, QEMUFile
*f
)
649 /* Clear interrupt status bit: it is implicit
650 * in irq_state which we are saving.
651 * This makes us compatible with old devices
652 * which never set or clear this bit. */
653 s
->config
[PCI_STATUS
] &= ~PCI_STATUS_INTERRUPT
;
654 vmstate_save_state(f
, &vmstate_pci_device
, s
, NULL
);
655 /* Restore the interrupt status bit. */
656 pci_update_irq_status(s
);
659 int pci_device_load(PCIDevice
*s
, QEMUFile
*f
)
662 ret
= vmstate_load_state(f
, &vmstate_pci_device
, s
, s
->version_id
);
663 /* Restore the interrupt status bit. */
664 pci_update_irq_status(s
);
668 static void pci_set_default_subsystem_id(PCIDevice
*pci_dev
)
670 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_VENDOR_ID
,
671 pci_default_sub_vendor_id
);
672 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_ID
,
673 pci_default_sub_device_id
);
677 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
678 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
680 static int pci_parse_devaddr(const char *addr
, int *domp
, int *busp
,
681 unsigned int *slotp
, unsigned int *funcp
)
686 unsigned long dom
= 0, bus
= 0;
687 unsigned int slot
= 0;
688 unsigned int func
= 0;
691 val
= strtoul(p
, &e
, 16);
697 val
= strtoul(p
, &e
, 16);
704 val
= strtoul(p
, &e
, 16);
717 val
= strtoul(p
, &e
, 16);
724 /* if funcp == NULL func is 0 */
725 if (dom
> 0xffff || bus
> 0xff || slot
> 0x1f || func
> 7)
739 static void pci_init_cmask(PCIDevice
*dev
)
741 pci_set_word(dev
->cmask
+ PCI_VENDOR_ID
, 0xffff);
742 pci_set_word(dev
->cmask
+ PCI_DEVICE_ID
, 0xffff);
743 dev
->cmask
[PCI_STATUS
] = PCI_STATUS_CAP_LIST
;
744 dev
->cmask
[PCI_REVISION_ID
] = 0xff;
745 dev
->cmask
[PCI_CLASS_PROG
] = 0xff;
746 pci_set_word(dev
->cmask
+ PCI_CLASS_DEVICE
, 0xffff);
747 dev
->cmask
[PCI_HEADER_TYPE
] = 0xff;
748 dev
->cmask
[PCI_CAPABILITY_LIST
] = 0xff;
751 static void pci_init_wmask(PCIDevice
*dev
)
753 int config_size
= pci_config_size(dev
);
755 dev
->wmask
[PCI_CACHE_LINE_SIZE
] = 0xff;
756 dev
->wmask
[PCI_INTERRUPT_LINE
] = 0xff;
757 pci_set_word(dev
->wmask
+ PCI_COMMAND
,
758 PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
|
759 PCI_COMMAND_INTX_DISABLE
);
760 pci_word_test_and_set_mask(dev
->wmask
+ PCI_COMMAND
, PCI_COMMAND_SERR
);
762 memset(dev
->wmask
+ PCI_CONFIG_HEADER_SIZE
, 0xff,
763 config_size
- PCI_CONFIG_HEADER_SIZE
);
766 static void pci_init_w1cmask(PCIDevice
*dev
)
769 * Note: It's okay to set w1cmask even for readonly bits as
770 * long as their value is hardwired to 0.
772 pci_set_word(dev
->w1cmask
+ PCI_STATUS
,
773 PCI_STATUS_PARITY
| PCI_STATUS_SIG_TARGET_ABORT
|
774 PCI_STATUS_REC_TARGET_ABORT
| PCI_STATUS_REC_MASTER_ABORT
|
775 PCI_STATUS_SIG_SYSTEM_ERROR
| PCI_STATUS_DETECTED_PARITY
);
778 static void pci_init_mask_bridge(PCIDevice
*d
)
780 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
781 PCI_SEC_LETENCY_TIMER */
782 memset(d
->wmask
+ PCI_PRIMARY_BUS
, 0xff, 4);
785 d
->wmask
[PCI_IO_BASE
] = PCI_IO_RANGE_MASK
& 0xff;
786 d
->wmask
[PCI_IO_LIMIT
] = PCI_IO_RANGE_MASK
& 0xff;
787 pci_set_word(d
->wmask
+ PCI_MEMORY_BASE
,
788 PCI_MEMORY_RANGE_MASK
& 0xffff);
789 pci_set_word(d
->wmask
+ PCI_MEMORY_LIMIT
,
790 PCI_MEMORY_RANGE_MASK
& 0xffff);
791 pci_set_word(d
->wmask
+ PCI_PREF_MEMORY_BASE
,
792 PCI_PREF_RANGE_MASK
& 0xffff);
793 pci_set_word(d
->wmask
+ PCI_PREF_MEMORY_LIMIT
,
794 PCI_PREF_RANGE_MASK
& 0xffff);
796 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
797 memset(d
->wmask
+ PCI_PREF_BASE_UPPER32
, 0xff, 8);
799 /* Supported memory and i/o types */
800 d
->config
[PCI_IO_BASE
] |= PCI_IO_RANGE_TYPE_16
;
801 d
->config
[PCI_IO_LIMIT
] |= PCI_IO_RANGE_TYPE_16
;
802 pci_word_test_and_set_mask(d
->config
+ PCI_PREF_MEMORY_BASE
,
803 PCI_PREF_RANGE_TYPE_64
);
804 pci_word_test_and_set_mask(d
->config
+ PCI_PREF_MEMORY_LIMIT
,
805 PCI_PREF_RANGE_TYPE_64
);
808 * TODO: Bridges default to 10-bit VGA decoding but we currently only
809 * implement 16-bit decoding (no alias support).
811 pci_set_word(d
->wmask
+ PCI_BRIDGE_CONTROL
,
812 PCI_BRIDGE_CTL_PARITY
|
813 PCI_BRIDGE_CTL_SERR
|
816 PCI_BRIDGE_CTL_VGA_16BIT
|
817 PCI_BRIDGE_CTL_MASTER_ABORT
|
818 PCI_BRIDGE_CTL_BUS_RESET
|
819 PCI_BRIDGE_CTL_FAST_BACK
|
820 PCI_BRIDGE_CTL_DISCARD
|
821 PCI_BRIDGE_CTL_SEC_DISCARD
|
822 PCI_BRIDGE_CTL_DISCARD_SERR
);
823 /* Below does not do anything as we never set this bit, put here for
825 pci_set_word(d
->w1cmask
+ PCI_BRIDGE_CONTROL
,
826 PCI_BRIDGE_CTL_DISCARD_STATUS
);
827 d
->cmask
[PCI_IO_BASE
] |= PCI_IO_RANGE_TYPE_MASK
;
828 d
->cmask
[PCI_IO_LIMIT
] |= PCI_IO_RANGE_TYPE_MASK
;
829 pci_word_test_and_set_mask(d
->cmask
+ PCI_PREF_MEMORY_BASE
,
830 PCI_PREF_RANGE_TYPE_MASK
);
831 pci_word_test_and_set_mask(d
->cmask
+ PCI_PREF_MEMORY_LIMIT
,
832 PCI_PREF_RANGE_TYPE_MASK
);
835 static void pci_init_multifunction(PCIBus
*bus
, PCIDevice
*dev
, Error
**errp
)
837 uint8_t slot
= PCI_SLOT(dev
->devfn
);
840 if (dev
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
) {
841 dev
->config
[PCI_HEADER_TYPE
] |= PCI_HEADER_TYPE_MULTI_FUNCTION
;
845 * multifunction bit is interpreted in two ways as follows.
846 * - all functions must set the bit to 1.
848 * - function 0 must set the bit, but the rest function (> 0)
849 * is allowed to leave the bit to 0.
850 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
852 * So OS (at least Linux) checks the bit of only function 0,
853 * and doesn't see the bit of function > 0.
855 * The below check allows both interpretation.
857 if (PCI_FUNC(dev
->devfn
)) {
858 PCIDevice
*f0
= bus
->devices
[PCI_DEVFN(slot
, 0)];
859 if (f0
&& !(f0
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
)) {
860 /* function 0 should set multifunction bit */
861 error_setg(errp
, "PCI: single function device can't be populated "
862 "in function %x.%x", slot
, PCI_FUNC(dev
->devfn
));
868 if (dev
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
) {
871 /* function 0 indicates single function, so function > 0 must be NULL */
872 for (func
= 1; func
< PCI_FUNC_MAX
; ++func
) {
873 if (bus
->devices
[PCI_DEVFN(slot
, func
)]) {
874 error_setg(errp
, "PCI: %x.0 indicates single function, "
875 "but %x.%x is already populated.",
882 static void pci_config_alloc(PCIDevice
*pci_dev
)
884 int config_size
= pci_config_size(pci_dev
);
886 pci_dev
->config
= g_malloc0(config_size
);
887 pci_dev
->cmask
= g_malloc0(config_size
);
888 pci_dev
->wmask
= g_malloc0(config_size
);
889 pci_dev
->w1cmask
= g_malloc0(config_size
);
890 pci_dev
->used
= g_malloc0(config_size
);
893 static void pci_config_free(PCIDevice
*pci_dev
)
895 g_free(pci_dev
->config
);
896 g_free(pci_dev
->cmask
);
897 g_free(pci_dev
->wmask
);
898 g_free(pci_dev
->w1cmask
);
899 g_free(pci_dev
->used
);
902 static void do_pci_unregister_device(PCIDevice
*pci_dev
)
904 pci_get_bus(pci_dev
)->devices
[pci_dev
->devfn
] = NULL
;
905 pci_config_free(pci_dev
);
907 if (memory_region_is_mapped(&pci_dev
->bus_master_enable_region
)) {
908 memory_region_del_subregion(&pci_dev
->bus_master_container_region
,
909 &pci_dev
->bus_master_enable_region
);
911 address_space_destroy(&pci_dev
->bus_master_as
);
914 /* Extract PCIReqIDCache into BDF format */
915 static uint16_t pci_req_id_cache_extract(PCIReqIDCache
*cache
)
920 switch (cache
->type
) {
922 result
= pci_get_bdf(cache
->dev
);
924 case PCI_REQ_ID_SECONDARY_BUS
:
925 bus_n
= pci_dev_bus_num(cache
->dev
);
926 result
= PCI_BUILD_BDF(bus_n
, 0);
929 error_report("Invalid PCI requester ID cache type: %d",
938 /* Parse bridges up to the root complex and return requester ID
939 * cache for specific device. For full PCIe topology, the cache
940 * result would be exactly the same as getting BDF of the device.
941 * However, several tricks are required when system mixed up with
942 * legacy PCI devices and PCIe-to-PCI bridges.
944 * Here we cache the proxy device (and type) not requester ID since
945 * bus number might change from time to time.
947 static PCIReqIDCache
pci_req_id_cache_get(PCIDevice
*dev
)
950 PCIReqIDCache cache
= {
952 .type
= PCI_REQ_ID_BDF
,
955 while (!pci_bus_is_root(pci_get_bus(dev
))) {
956 /* We are under PCI/PCIe bridges */
957 parent
= pci_get_bus(dev
)->parent_dev
;
958 if (pci_is_express(parent
)) {
959 if (pcie_cap_get_type(parent
) == PCI_EXP_TYPE_PCI_BRIDGE
) {
960 /* When we pass through PCIe-to-PCI/PCIX bridges, we
961 * override the requester ID using secondary bus
962 * number of parent bridge with zeroed devfn
963 * (pcie-to-pci bridge spec chap 2.3). */
964 cache
.type
= PCI_REQ_ID_SECONDARY_BUS
;
968 /* Legacy PCI, override requester ID with the bridge's
969 * BDF upstream. When the root complex connects to
970 * legacy PCI devices (including buses), it can only
971 * obtain requester ID info from directly attached
972 * devices. If devices are attached under bridges, only
973 * the requester ID of the bridge that is directly
974 * attached to the root complex can be recognized. */
975 cache
.type
= PCI_REQ_ID_BDF
;
984 uint16_t pci_requester_id(PCIDevice
*dev
)
986 return pci_req_id_cache_extract(&dev
->requester_id_cache
);
989 static bool pci_bus_devfn_available(PCIBus
*bus
, int devfn
)
991 return !(bus
->devices
[devfn
]);
994 static bool pci_bus_devfn_reserved(PCIBus
*bus
, int devfn
)
996 return bus
->slot_reserved_mask
& (1UL << PCI_SLOT(devfn
));
999 /* -1 for devfn means auto assign */
1000 static PCIDevice
*do_pci_register_device(PCIDevice
*pci_dev
,
1001 const char *name
, int devfn
,
1004 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(pci_dev
);
1005 PCIConfigReadFunc
*config_read
= pc
->config_read
;
1006 PCIConfigWriteFunc
*config_write
= pc
->config_write
;
1007 Error
*local_err
= NULL
;
1008 DeviceState
*dev
= DEVICE(pci_dev
);
1009 PCIBus
*bus
= pci_get_bus(pci_dev
);
1011 /* Only pci bridges can be attached to extra PCI root buses */
1012 if (pci_bus_is_root(bus
) && bus
->parent_dev
&& !pc
->is_bridge
) {
1014 "PCI: Only PCI/PCIe bridges can be plugged into %s",
1015 bus
->parent_dev
->name
);
1020 for(devfn
= bus
->devfn_min
; devfn
< ARRAY_SIZE(bus
->devices
);
1021 devfn
+= PCI_FUNC_MAX
) {
1022 if (pci_bus_devfn_available(bus
, devfn
) &&
1023 !pci_bus_devfn_reserved(bus
, devfn
)) {
1027 error_setg(errp
, "PCI: no slot/function available for %s, all in use "
1028 "or reserved", name
);
1031 } else if (pci_bus_devfn_reserved(bus
, devfn
)) {
1032 error_setg(errp
, "PCI: slot %d function %d not available for %s,"
1034 PCI_SLOT(devfn
), PCI_FUNC(devfn
), name
);
1036 } else if (!pci_bus_devfn_available(bus
, devfn
)) {
1037 error_setg(errp
, "PCI: slot %d function %d not available for %s,"
1039 PCI_SLOT(devfn
), PCI_FUNC(devfn
), name
,
1040 bus
->devices
[devfn
]->name
);
1042 } else if (dev
->hotplugged
&&
1043 pci_get_function_0(pci_dev
)) {
1044 error_setg(errp
, "PCI: slot %d function 0 already occupied by %s,"
1045 " new func %s cannot be exposed to guest.",
1046 PCI_SLOT(pci_get_function_0(pci_dev
)->devfn
),
1047 pci_get_function_0(pci_dev
)->name
,
1053 pci_dev
->devfn
= devfn
;
1054 pci_dev
->requester_id_cache
= pci_req_id_cache_get(pci_dev
);
1055 pstrcpy(pci_dev
->name
, sizeof(pci_dev
->name
), name
);
1057 memory_region_init(&pci_dev
->bus_master_container_region
, OBJECT(pci_dev
),
1058 "bus master container", UINT64_MAX
);
1059 address_space_init(&pci_dev
->bus_master_as
,
1060 &pci_dev
->bus_master_container_region
, pci_dev
->name
);
1063 pci_init_bus_master(pci_dev
);
1065 pci_dev
->irq_state
= 0;
1066 pci_config_alloc(pci_dev
);
1068 pci_config_set_vendor_id(pci_dev
->config
, pc
->vendor_id
);
1069 pci_config_set_device_id(pci_dev
->config
, pc
->device_id
);
1070 pci_config_set_revision(pci_dev
->config
, pc
->revision
);
1071 pci_config_set_class(pci_dev
->config
, pc
->class_id
);
1073 if (!pc
->is_bridge
) {
1074 if (pc
->subsystem_vendor_id
|| pc
->subsystem_id
) {
1075 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_VENDOR_ID
,
1076 pc
->subsystem_vendor_id
);
1077 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_ID
,
1080 pci_set_default_subsystem_id(pci_dev
);
1083 /* subsystem_vendor_id/subsystem_id are only for header type 0 */
1084 assert(!pc
->subsystem_vendor_id
);
1085 assert(!pc
->subsystem_id
);
1087 pci_init_cmask(pci_dev
);
1088 pci_init_wmask(pci_dev
);
1089 pci_init_w1cmask(pci_dev
);
1090 if (pc
->is_bridge
) {
1091 pci_init_mask_bridge(pci_dev
);
1093 pci_init_multifunction(bus
, pci_dev
, &local_err
);
1095 error_propagate(errp
, local_err
);
1096 do_pci_unregister_device(pci_dev
);
1101 config_read
= pci_default_read_config
;
1103 config_write
= pci_default_write_config
;
1104 pci_dev
->config_read
= config_read
;
1105 pci_dev
->config_write
= config_write
;
1106 bus
->devices
[devfn
] = pci_dev
;
1107 pci_dev
->version_id
= 2; /* Current pci device vmstate version */
1111 static void pci_unregister_io_regions(PCIDevice
*pci_dev
)
1116 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1117 r
= &pci_dev
->io_regions
[i
];
1118 if (!r
->size
|| r
->addr
== PCI_BAR_UNMAPPED
)
1120 memory_region_del_subregion(r
->address_space
, r
->memory
);
1123 pci_unregister_vga(pci_dev
);
1126 static void pci_qdev_unrealize(DeviceState
*dev
)
1128 PCIDevice
*pci_dev
= PCI_DEVICE(dev
);
1129 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(pci_dev
);
1131 pci_unregister_io_regions(pci_dev
);
1132 pci_del_option_rom(pci_dev
);
1138 pci_device_deassert_intx(pci_dev
);
1139 do_pci_unregister_device(pci_dev
);
1142 void pci_register_bar(PCIDevice
*pci_dev
, int region_num
,
1143 uint8_t type
, MemoryRegion
*memory
)
1146 uint32_t addr
; /* offset in pci config space */
1148 pcibus_t size
= memory_region_size(memory
);
1150 assert(region_num
>= 0);
1151 assert(region_num
< PCI_NUM_REGIONS
);
1152 if (size
& (size
-1)) {
1153 error_report("ERROR: PCI region size must be pow2 "
1154 "type=0x%x, size=0x%"FMT_PCIBUS
"", type
, size
);
1158 r
= &pci_dev
->io_regions
[region_num
];
1159 r
->addr
= PCI_BAR_UNMAPPED
;
1163 r
->address_space
= type
& PCI_BASE_ADDRESS_SPACE_IO
1164 ? pci_get_bus(pci_dev
)->address_space_io
1165 : pci_get_bus(pci_dev
)->address_space_mem
;
1167 wmask
= ~(size
- 1);
1168 if (region_num
== PCI_ROM_SLOT
) {
1169 /* ROM enable bit is writable */
1170 wmask
|= PCI_ROM_ADDRESS_ENABLE
;
1173 addr
= pci_bar(pci_dev
, region_num
);
1174 pci_set_long(pci_dev
->config
+ addr
, type
);
1176 if (!(r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) &&
1177 r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
1178 pci_set_quad(pci_dev
->wmask
+ addr
, wmask
);
1179 pci_set_quad(pci_dev
->cmask
+ addr
, ~0ULL);
1181 pci_set_long(pci_dev
->wmask
+ addr
, wmask
& 0xffffffff);
1182 pci_set_long(pci_dev
->cmask
+ addr
, 0xffffffff);
1186 static void pci_update_vga(PCIDevice
*pci_dev
)
1190 if (!pci_dev
->has_vga
) {
1194 cmd
= pci_get_word(pci_dev
->config
+ PCI_COMMAND
);
1196 memory_region_set_enabled(pci_dev
->vga_regions
[QEMU_PCI_VGA_MEM
],
1197 cmd
& PCI_COMMAND_MEMORY
);
1198 memory_region_set_enabled(pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_LO
],
1199 cmd
& PCI_COMMAND_IO
);
1200 memory_region_set_enabled(pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_HI
],
1201 cmd
& PCI_COMMAND_IO
);
1204 void pci_register_vga(PCIDevice
*pci_dev
, MemoryRegion
*mem
,
1205 MemoryRegion
*io_lo
, MemoryRegion
*io_hi
)
1207 PCIBus
*bus
= pci_get_bus(pci_dev
);
1209 assert(!pci_dev
->has_vga
);
1211 assert(memory_region_size(mem
) == QEMU_PCI_VGA_MEM_SIZE
);
1212 pci_dev
->vga_regions
[QEMU_PCI_VGA_MEM
] = mem
;
1213 memory_region_add_subregion_overlap(bus
->address_space_mem
,
1214 QEMU_PCI_VGA_MEM_BASE
, mem
, 1);
1216 assert(memory_region_size(io_lo
) == QEMU_PCI_VGA_IO_LO_SIZE
);
1217 pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_LO
] = io_lo
;
1218 memory_region_add_subregion_overlap(bus
->address_space_io
,
1219 QEMU_PCI_VGA_IO_LO_BASE
, io_lo
, 1);
1221 assert(memory_region_size(io_hi
) == QEMU_PCI_VGA_IO_HI_SIZE
);
1222 pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_HI
] = io_hi
;
1223 memory_region_add_subregion_overlap(bus
->address_space_io
,
1224 QEMU_PCI_VGA_IO_HI_BASE
, io_hi
, 1);
1225 pci_dev
->has_vga
= true;
1227 pci_update_vga(pci_dev
);
1230 void pci_unregister_vga(PCIDevice
*pci_dev
)
1232 PCIBus
*bus
= pci_get_bus(pci_dev
);
1234 if (!pci_dev
->has_vga
) {
1238 memory_region_del_subregion(bus
->address_space_mem
,
1239 pci_dev
->vga_regions
[QEMU_PCI_VGA_MEM
]);
1240 memory_region_del_subregion(bus
->address_space_io
,
1241 pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_LO
]);
1242 memory_region_del_subregion(bus
->address_space_io
,
1243 pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_HI
]);
1244 pci_dev
->has_vga
= false;
1247 pcibus_t
pci_get_bar_addr(PCIDevice
*pci_dev
, int region_num
)
1249 return pci_dev
->io_regions
[region_num
].addr
;
1252 static pcibus_t
pci_bar_address(PCIDevice
*d
,
1253 int reg
, uint8_t type
, pcibus_t size
)
1255 pcibus_t new_addr
, last_addr
;
1256 int bar
= pci_bar(d
, reg
);
1257 uint16_t cmd
= pci_get_word(d
->config
+ PCI_COMMAND
);
1258 Object
*machine
= qdev_get_machine();
1259 ObjectClass
*oc
= object_get_class(machine
);
1260 MachineClass
*mc
= MACHINE_CLASS(oc
);
1261 bool allow_0_address
= mc
->pci_allow_0_address
;
1263 if (type
& PCI_BASE_ADDRESS_SPACE_IO
) {
1264 if (!(cmd
& PCI_COMMAND_IO
)) {
1265 return PCI_BAR_UNMAPPED
;
1267 new_addr
= pci_get_long(d
->config
+ bar
) & ~(size
- 1);
1268 last_addr
= new_addr
+ size
- 1;
1269 /* Check if 32 bit BAR wraps around explicitly.
1270 * TODO: make priorities correct and remove this work around.
1272 if (last_addr
<= new_addr
|| last_addr
>= UINT32_MAX
||
1273 (!allow_0_address
&& new_addr
== 0)) {
1274 return PCI_BAR_UNMAPPED
;
1279 if (!(cmd
& PCI_COMMAND_MEMORY
)) {
1280 return PCI_BAR_UNMAPPED
;
1282 if (type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
1283 new_addr
= pci_get_quad(d
->config
+ bar
);
1285 new_addr
= pci_get_long(d
->config
+ bar
);
1287 /* the ROM slot has a specific enable bit */
1288 if (reg
== PCI_ROM_SLOT
&& !(new_addr
& PCI_ROM_ADDRESS_ENABLE
)) {
1289 return PCI_BAR_UNMAPPED
;
1291 new_addr
&= ~(size
- 1);
1292 last_addr
= new_addr
+ size
- 1;
1293 /* NOTE: we do not support wrapping */
1294 /* XXX: as we cannot support really dynamic
1295 mappings, we handle specific values as invalid
1297 if (last_addr
<= new_addr
|| last_addr
== PCI_BAR_UNMAPPED
||
1298 (!allow_0_address
&& new_addr
== 0)) {
1299 return PCI_BAR_UNMAPPED
;
1302 /* Now pcibus_t is 64bit.
1303 * Check if 32 bit BAR wraps around explicitly.
1304 * Without this, PC ide doesn't work well.
1305 * TODO: remove this work around.
1307 if (!(type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) && last_addr
>= UINT32_MAX
) {
1308 return PCI_BAR_UNMAPPED
;
1312 * OS is allowed to set BAR beyond its addressable
1313 * bits. For example, 32 bit OS can set 64bit bar
1314 * to >4G. Check it. TODO: we might need to support
1315 * it in the future for e.g. PAE.
1317 if (last_addr
>= HWADDR_MAX
) {
1318 return PCI_BAR_UNMAPPED
;
1324 static void pci_update_mappings(PCIDevice
*d
)
1330 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1331 r
= &d
->io_regions
[i
];
1333 /* this region isn't registered */
1337 new_addr
= pci_bar_address(d
, i
, r
->type
, r
->size
);
1339 /* This bar isn't changed */
1340 if (new_addr
== r
->addr
)
1343 /* now do the real mapping */
1344 if (r
->addr
!= PCI_BAR_UNMAPPED
) {
1345 trace_pci_update_mappings_del(d
, pci_dev_bus_num(d
),
1348 i
, r
->addr
, r
->size
);
1349 memory_region_del_subregion(r
->address_space
, r
->memory
);
1352 if (r
->addr
!= PCI_BAR_UNMAPPED
) {
1353 trace_pci_update_mappings_add(d
, pci_dev_bus_num(d
),
1356 i
, r
->addr
, r
->size
);
1357 memory_region_add_subregion_overlap(r
->address_space
,
1358 r
->addr
, r
->memory
, 1);
1365 static inline int pci_irq_disabled(PCIDevice
*d
)
1367 return pci_get_word(d
->config
+ PCI_COMMAND
) & PCI_COMMAND_INTX_DISABLE
;
1370 /* Called after interrupt disabled field update in config space,
1371 * assert/deassert interrupts if necessary.
1372 * Gets original interrupt disable bit value (before update). */
1373 static void pci_update_irq_disabled(PCIDevice
*d
, int was_irq_disabled
)
1375 int i
, disabled
= pci_irq_disabled(d
);
1376 if (disabled
== was_irq_disabled
)
1378 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
1379 int state
= pci_irq_state(d
, i
);
1380 pci_change_irq_level(d
, i
, disabled
? -state
: state
);
1384 uint32_t pci_default_read_config(PCIDevice
*d
,
1385 uint32_t address
, int len
)
1389 assert(address
+ len
<= pci_config_size(d
));
1391 if (pci_is_express_downstream_port(d
) &&
1392 ranges_overlap(address
, len
, d
->exp
.exp_cap
+ PCI_EXP_LNKSTA
, 2)) {
1393 pcie_sync_bridge_lnk(d
);
1395 memcpy(&val
, d
->config
+ address
, len
);
1396 return le32_to_cpu(val
);
1399 void pci_default_write_config(PCIDevice
*d
, uint32_t addr
, uint32_t val_in
, int l
)
1401 int i
, was_irq_disabled
= pci_irq_disabled(d
);
1402 uint32_t val
= val_in
;
1404 assert(addr
+ l
<= pci_config_size(d
));
1406 for (i
= 0; i
< l
; val
>>= 8, ++i
) {
1407 uint8_t wmask
= d
->wmask
[addr
+ i
];
1408 uint8_t w1cmask
= d
->w1cmask
[addr
+ i
];
1409 assert(!(wmask
& w1cmask
));
1410 d
->config
[addr
+ i
] = (d
->config
[addr
+ i
] & ~wmask
) | (val
& wmask
);
1411 d
->config
[addr
+ i
] &= ~(val
& w1cmask
); /* W1C: Write 1 to Clear */
1413 if (ranges_overlap(addr
, l
, PCI_BASE_ADDRESS_0
, 24) ||
1414 ranges_overlap(addr
, l
, PCI_ROM_ADDRESS
, 4) ||
1415 ranges_overlap(addr
, l
, PCI_ROM_ADDRESS1
, 4) ||
1416 range_covers_byte(addr
, l
, PCI_COMMAND
))
1417 pci_update_mappings(d
);
1419 if (range_covers_byte(addr
, l
, PCI_COMMAND
)) {
1420 pci_update_irq_disabled(d
, was_irq_disabled
);
1421 memory_region_set_enabled(&d
->bus_master_enable_region
,
1422 pci_get_word(d
->config
+ PCI_COMMAND
)
1423 & PCI_COMMAND_MASTER
);
1426 msi_write_config(d
, addr
, val_in
, l
);
1427 msix_write_config(d
, addr
, val_in
, l
);
1430 /***********************************************************/
1431 /* generic PCI irq support */
1433 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1434 static void pci_irq_handler(void *opaque
, int irq_num
, int level
)
1436 PCIDevice
*pci_dev
= opaque
;
1439 change
= level
- pci_irq_state(pci_dev
, irq_num
);
1443 pci_set_irq_state(pci_dev
, irq_num
, level
);
1444 pci_update_irq_status(pci_dev
);
1445 if (pci_irq_disabled(pci_dev
))
1447 pci_change_irq_level(pci_dev
, irq_num
, change
);
1450 static inline int pci_intx(PCIDevice
*pci_dev
)
1452 return pci_get_byte(pci_dev
->config
+ PCI_INTERRUPT_PIN
) - 1;
1455 qemu_irq
pci_allocate_irq(PCIDevice
*pci_dev
)
1457 int intx
= pci_intx(pci_dev
);
1459 return qemu_allocate_irq(pci_irq_handler
, pci_dev
, intx
);
1462 void pci_set_irq(PCIDevice
*pci_dev
, int level
)
1464 int intx
= pci_intx(pci_dev
);
1465 pci_irq_handler(pci_dev
, intx
, level
);
1468 /* Special hooks used by device assignment */
1469 void pci_bus_set_route_irq_fn(PCIBus
*bus
, pci_route_irq_fn route_intx_to_irq
)
1471 assert(pci_bus_is_root(bus
));
1472 bus
->route_intx_to_irq
= route_intx_to_irq
;
1475 PCIINTxRoute
pci_device_route_intx_to_irq(PCIDevice
*dev
, int pin
)
1480 bus
= pci_get_bus(dev
);
1481 pin
= bus
->map_irq(dev
, pin
);
1482 dev
= bus
->parent_dev
;
1485 if (!bus
->route_intx_to_irq
) {
1486 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)",
1487 object_get_typename(OBJECT(bus
->qbus
.parent
)));
1488 return (PCIINTxRoute
) { PCI_INTX_DISABLED
, -1 };
1491 return bus
->route_intx_to_irq(bus
->irq_opaque
, pin
);
1494 bool pci_intx_route_changed(PCIINTxRoute
*old
, PCIINTxRoute
*new)
1496 return old
->mode
!= new->mode
|| old
->irq
!= new->irq
;
1499 void pci_bus_fire_intx_routing_notifier(PCIBus
*bus
)
1505 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); ++i
) {
1506 dev
= bus
->devices
[i
];
1507 if (dev
&& dev
->intx_routing_notifier
) {
1508 dev
->intx_routing_notifier(dev
);
1512 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
1513 pci_bus_fire_intx_routing_notifier(sec
);
1517 void pci_device_set_intx_routing_notifier(PCIDevice
*dev
,
1518 PCIINTxRoutingNotifier notifier
)
1520 dev
->intx_routing_notifier
= notifier
;
1524 * PCI-to-PCI bridge specification
1525 * 9.1: Interrupt routing. Table 9-1
1527 * the PCI Express Base Specification, Revision 2.1
1528 * 2.2.8.1: INTx interrutp signaling - Rules
1529 * the Implementation Note
1533 * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD
1534 * 0-origin unlike PCI interrupt pin register.
1536 int pci_swizzle_map_irq_fn(PCIDevice
*pci_dev
, int pin
)
1538 return pci_swizzle(PCI_SLOT(pci_dev
->devfn
), pin
);
1541 /***********************************************************/
1542 /* monitor info on PCI */
1547 const char *fw_name
;
1548 uint16_t fw_ign_bits
;
1551 static const pci_class_desc pci_class_descriptions
[] =
1553 { 0x0001, "VGA controller", "display"},
1554 { 0x0100, "SCSI controller", "scsi"},
1555 { 0x0101, "IDE controller", "ide"},
1556 { 0x0102, "Floppy controller", "fdc"},
1557 { 0x0103, "IPI controller", "ipi"},
1558 { 0x0104, "RAID controller", "raid"},
1559 { 0x0106, "SATA controller"},
1560 { 0x0107, "SAS controller"},
1561 { 0x0180, "Storage controller"},
1562 { 0x0200, "Ethernet controller", "ethernet"},
1563 { 0x0201, "Token Ring controller", "token-ring"},
1564 { 0x0202, "FDDI controller", "fddi"},
1565 { 0x0203, "ATM controller", "atm"},
1566 { 0x0280, "Network controller"},
1567 { 0x0300, "VGA controller", "display", 0x00ff},
1568 { 0x0301, "XGA controller"},
1569 { 0x0302, "3D controller"},
1570 { 0x0380, "Display controller"},
1571 { 0x0400, "Video controller", "video"},
1572 { 0x0401, "Audio controller", "sound"},
1574 { 0x0403, "Audio controller", "sound"},
1575 { 0x0480, "Multimedia controller"},
1576 { 0x0500, "RAM controller", "memory"},
1577 { 0x0501, "Flash controller", "flash"},
1578 { 0x0580, "Memory controller"},
1579 { 0x0600, "Host bridge", "host"},
1580 { 0x0601, "ISA bridge", "isa"},
1581 { 0x0602, "EISA bridge", "eisa"},
1582 { 0x0603, "MC bridge", "mca"},
1583 { 0x0604, "PCI bridge", "pci-bridge"},
1584 { 0x0605, "PCMCIA bridge", "pcmcia"},
1585 { 0x0606, "NUBUS bridge", "nubus"},
1586 { 0x0607, "CARDBUS bridge", "cardbus"},
1587 { 0x0608, "RACEWAY bridge"},
1588 { 0x0680, "Bridge"},
1589 { 0x0700, "Serial port", "serial"},
1590 { 0x0701, "Parallel port", "parallel"},
1591 { 0x0800, "Interrupt controller", "interrupt-controller"},
1592 { 0x0801, "DMA controller", "dma-controller"},
1593 { 0x0802, "Timer", "timer"},
1594 { 0x0803, "RTC", "rtc"},
1595 { 0x0900, "Keyboard", "keyboard"},
1596 { 0x0901, "Pen", "pen"},
1597 { 0x0902, "Mouse", "mouse"},
1598 { 0x0A00, "Dock station", "dock", 0x00ff},
1599 { 0x0B00, "i386 cpu", "cpu", 0x00ff},
1600 { 0x0c00, "Fireware contorller", "fireware"},
1601 { 0x0c01, "Access bus controller", "access-bus"},
1602 { 0x0c02, "SSA controller", "ssa"},
1603 { 0x0c03, "USB controller", "usb"},
1604 { 0x0c04, "Fibre channel controller", "fibre-channel"},
1609 static void pci_for_each_device_under_bus_reverse(PCIBus
*bus
,
1610 void (*fn
)(PCIBus
*b
,
1618 for (devfn
= 0; devfn
< ARRAY_SIZE(bus
->devices
); devfn
++) {
1619 d
= bus
->devices
[ARRAY_SIZE(bus
->devices
) - 1 - devfn
];
1626 void pci_for_each_device_reverse(PCIBus
*bus
, int bus_num
,
1627 void (*fn
)(PCIBus
*b
, PCIDevice
*d
, void *opaque
),
1630 bus
= pci_find_bus_nr(bus
, bus_num
);
1633 pci_for_each_device_under_bus_reverse(bus
, fn
, opaque
);
1637 static void pci_for_each_device_under_bus(PCIBus
*bus
,
1638 void (*fn
)(PCIBus
*b
, PCIDevice
*d
,
1645 for(devfn
= 0; devfn
< ARRAY_SIZE(bus
->devices
); devfn
++) {
1646 d
= bus
->devices
[devfn
];
1653 void pci_for_each_device(PCIBus
*bus
, int bus_num
,
1654 void (*fn
)(PCIBus
*b
, PCIDevice
*d
, void *opaque
),
1657 bus
= pci_find_bus_nr(bus
, bus_num
);
1660 pci_for_each_device_under_bus(bus
, fn
, opaque
);
1664 static const pci_class_desc
*get_class_desc(int class)
1666 const pci_class_desc
*desc
;
1668 desc
= pci_class_descriptions
;
1669 while (desc
->desc
&& class != desc
->class) {
1676 static PciDeviceInfoList
*qmp_query_pci_devices(PCIBus
*bus
, int bus_num
);
1678 static PciMemoryRegionList
*qmp_query_pci_regions(const PCIDevice
*dev
)
1680 PciMemoryRegionList
*head
= NULL
, *cur_item
= NULL
;
1683 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1684 const PCIIORegion
*r
= &dev
->io_regions
[i
];
1685 PciMemoryRegionList
*region
;
1691 region
= g_malloc0(sizeof(*region
));
1692 region
->value
= g_malloc0(sizeof(*region
->value
));
1694 if (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) {
1695 region
->value
->type
= g_strdup("io");
1697 region
->value
->type
= g_strdup("memory");
1698 region
->value
->has_prefetch
= true;
1699 region
->value
->prefetch
= !!(r
->type
& PCI_BASE_ADDRESS_MEM_PREFETCH
);
1700 region
->value
->has_mem_type_64
= true;
1701 region
->value
->mem_type_64
= !!(r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
);
1704 region
->value
->bar
= i
;
1705 region
->value
->address
= r
->addr
;
1706 region
->value
->size
= r
->size
;
1708 /* XXX: waiting for the qapi to support GSList */
1710 head
= cur_item
= region
;
1712 cur_item
->next
= region
;
1720 static PciBridgeInfo
*qmp_query_pci_bridge(PCIDevice
*dev
, PCIBus
*bus
,
1723 PciBridgeInfo
*info
;
1724 PciMemoryRange
*range
;
1726 info
= g_new0(PciBridgeInfo
, 1);
1728 info
->bus
= g_new0(PciBusInfo
, 1);
1729 info
->bus
->number
= dev
->config
[PCI_PRIMARY_BUS
];
1730 info
->bus
->secondary
= dev
->config
[PCI_SECONDARY_BUS
];
1731 info
->bus
->subordinate
= dev
->config
[PCI_SUBORDINATE_BUS
];
1733 range
= info
->bus
->io_range
= g_new0(PciMemoryRange
, 1);
1734 range
->base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_IO
);
1735 range
->limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_IO
);
1737 range
= info
->bus
->memory_range
= g_new0(PciMemoryRange
, 1);
1738 range
->base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
1739 range
->limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
1741 range
= info
->bus
->prefetchable_range
= g_new0(PciMemoryRange
, 1);
1742 range
->base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
1743 range
->limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
1745 if (dev
->config
[PCI_SECONDARY_BUS
] != 0) {
1746 PCIBus
*child_bus
= pci_find_bus_nr(bus
, dev
->config
[PCI_SECONDARY_BUS
]);
1748 info
->has_devices
= true;
1749 info
->devices
= qmp_query_pci_devices(child_bus
, dev
->config
[PCI_SECONDARY_BUS
]);
1756 static PciDeviceInfo
*qmp_query_pci_device(PCIDevice
*dev
, PCIBus
*bus
,
1759 const pci_class_desc
*desc
;
1760 PciDeviceInfo
*info
;
1764 info
= g_new0(PciDeviceInfo
, 1);
1765 info
->bus
= bus_num
;
1766 info
->slot
= PCI_SLOT(dev
->devfn
);
1767 info
->function
= PCI_FUNC(dev
->devfn
);
1769 info
->class_info
= g_new0(PciDeviceClass
, 1);
1770 class = pci_get_word(dev
->config
+ PCI_CLASS_DEVICE
);
1771 info
->class_info
->q_class
= class;
1772 desc
= get_class_desc(class);
1774 info
->class_info
->has_desc
= true;
1775 info
->class_info
->desc
= g_strdup(desc
->desc
);
1778 info
->id
= g_new0(PciDeviceId
, 1);
1779 info
->id
->vendor
= pci_get_word(dev
->config
+ PCI_VENDOR_ID
);
1780 info
->id
->device
= pci_get_word(dev
->config
+ PCI_DEVICE_ID
);
1781 info
->regions
= qmp_query_pci_regions(dev
);
1782 info
->qdev_id
= g_strdup(dev
->qdev
.id
? dev
->qdev
.id
: "");
1784 info
->irq_pin
= dev
->config
[PCI_INTERRUPT_PIN
];
1785 if (dev
->config
[PCI_INTERRUPT_PIN
] != 0) {
1786 info
->has_irq
= true;
1787 info
->irq
= dev
->config
[PCI_INTERRUPT_LINE
];
1790 type
= dev
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
1791 if (type
== PCI_HEADER_TYPE_BRIDGE
) {
1792 info
->has_pci_bridge
= true;
1793 info
->pci_bridge
= qmp_query_pci_bridge(dev
, bus
, bus_num
);
1794 } else if (type
== PCI_HEADER_TYPE_NORMAL
) {
1795 info
->id
->has_subsystem
= info
->id
->has_subsystem_vendor
= true;
1796 info
->id
->subsystem
= pci_get_word(dev
->config
+ PCI_SUBSYSTEM_ID
);
1797 info
->id
->subsystem_vendor
=
1798 pci_get_word(dev
->config
+ PCI_SUBSYSTEM_VENDOR_ID
);
1799 } else if (type
== PCI_HEADER_TYPE_CARDBUS
) {
1800 info
->id
->has_subsystem
= info
->id
->has_subsystem_vendor
= true;
1801 info
->id
->subsystem
= pci_get_word(dev
->config
+ PCI_CB_SUBSYSTEM_ID
);
1802 info
->id
->subsystem_vendor
=
1803 pci_get_word(dev
->config
+ PCI_CB_SUBSYSTEM_VENDOR_ID
);
1809 static PciDeviceInfoList
*qmp_query_pci_devices(PCIBus
*bus
, int bus_num
)
1811 PciDeviceInfoList
*info
, *head
= NULL
, *cur_item
= NULL
;
1815 for (devfn
= 0; devfn
< ARRAY_SIZE(bus
->devices
); devfn
++) {
1816 dev
= bus
->devices
[devfn
];
1818 info
= g_malloc0(sizeof(*info
));
1819 info
->value
= qmp_query_pci_device(dev
, bus
, bus_num
);
1821 /* XXX: waiting for the qapi to support GSList */
1823 head
= cur_item
= info
;
1825 cur_item
->next
= info
;
1834 static PciInfo
*qmp_query_pci_bus(PCIBus
*bus
, int bus_num
)
1836 PciInfo
*info
= NULL
;
1838 bus
= pci_find_bus_nr(bus
, bus_num
);
1840 info
= g_malloc0(sizeof(*info
));
1841 info
->bus
= bus_num
;
1842 info
->devices
= qmp_query_pci_devices(bus
, bus_num
);
1848 PciInfoList
*qmp_query_pci(Error
**errp
)
1850 PciInfoList
*info
, *head
= NULL
, *cur_item
= NULL
;
1851 PCIHostState
*host_bridge
;
1853 QLIST_FOREACH(host_bridge
, &pci_host_bridges
, next
) {
1854 info
= g_malloc0(sizeof(*info
));
1855 info
->value
= qmp_query_pci_bus(host_bridge
->bus
,
1856 pci_bus_num(host_bridge
->bus
));
1858 /* XXX: waiting for the qapi to support GSList */
1860 head
= cur_item
= info
;
1862 cur_item
->next
= info
;
1870 /* Initialize a PCI NIC. */
1871 PCIDevice
*pci_nic_init_nofail(NICInfo
*nd
, PCIBus
*rootbus
,
1872 const char *default_model
,
1873 const char *default_devaddr
)
1875 const char *devaddr
= nd
->devaddr
? nd
->devaddr
: default_devaddr
;
1877 GPtrArray
*pci_nic_models
;
1886 if (nd
->model
&& !strcmp(nd
->model
, "virtio")) {
1888 nd
->model
= g_strdup("virtio-net-pci");
1891 list
= object_class_get_list_sorted(TYPE_PCI_DEVICE
, false);
1892 pci_nic_models
= g_ptr_array_new();
1894 DeviceClass
*dc
= OBJECT_CLASS_CHECK(DeviceClass
, list
->data
,
1897 if (test_bit(DEVICE_CATEGORY_NETWORK
, dc
->categories
) &&
1898 dc
->user_creatable
) {
1899 const char *name
= object_class_get_name(list
->data
);
1901 * A network device might also be something else than a NIC, see
1902 * e.g. the "rocker" device. Thus we have to look for the "netdev"
1903 * property, too. Unfortunately, some devices like virtio-net only
1904 * create this property during instance_init, so we have to create
1905 * a temporary instance here to be able to check it.
1907 Object
*obj
= object_new_with_class(OBJECT_CLASS(dc
));
1908 if (object_property_find(obj
, "netdev")) {
1909 g_ptr_array_add(pci_nic_models
, (gpointer
)name
);
1914 g_slist_free_1(list
);
1917 g_ptr_array_add(pci_nic_models
, NULL
);
1919 if (qemu_show_nic_models(nd
->model
, (const char **)pci_nic_models
->pdata
)) {
1923 i
= qemu_find_nic_model(nd
, (const char **)pci_nic_models
->pdata
,
1930 error_report("No primary PCI bus");
1934 assert(!rootbus
->parent_dev
);
1940 if (pci_parse_devaddr(devaddr
, &dom
, &busnr
, &slot
, NULL
) < 0) {
1941 error_report("Invalid PCI device address %s for device %s",
1942 devaddr
, nd
->model
);
1947 error_report("No support for non-zero PCI domains");
1951 devfn
= PCI_DEVFN(slot
, 0);
1954 bus
= pci_find_bus_nr(rootbus
, busnr
);
1956 error_report("Invalid PCI device address %s for device %s",
1957 devaddr
, nd
->model
);
1961 pci_dev
= pci_new(devfn
, nd
->model
);
1962 dev
= &pci_dev
->qdev
;
1963 qdev_set_nic_properties(dev
, nd
);
1964 pci_realize_and_unref(pci_dev
, bus
, &error_fatal
);
1965 g_ptr_array_free(pci_nic_models
, true);
1969 PCIDevice
*pci_vga_init(PCIBus
*bus
)
1971 switch (vga_interface_type
) {
1973 return pci_create_simple(bus
, -1, "cirrus-vga");
1975 return pci_create_simple(bus
, -1, "qxl-vga");
1977 return pci_create_simple(bus
, -1, "VGA");
1979 return pci_create_simple(bus
, -1, "vmware-svga");
1981 return pci_create_simple(bus
, -1, "virtio-vga");
1983 default: /* Other non-PCI types. Checking for unsupported types is already
1989 /* Whether a given bus number is in range of the secondary
1990 * bus of the given bridge device. */
1991 static bool pci_secondary_bus_in_range(PCIDevice
*dev
, int bus_num
)
1993 return !(pci_get_word(dev
->config
+ PCI_BRIDGE_CONTROL
) &
1994 PCI_BRIDGE_CTL_BUS_RESET
) /* Don't walk the bus if it's reset. */ &&
1995 dev
->config
[PCI_SECONDARY_BUS
] <= bus_num
&&
1996 bus_num
<= dev
->config
[PCI_SUBORDINATE_BUS
];
1999 /* Whether a given bus number is in a range of a root bus */
2000 static bool pci_root_bus_in_range(PCIBus
*bus
, int bus_num
)
2004 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); ++i
) {
2005 PCIDevice
*dev
= bus
->devices
[i
];
2007 if (dev
&& PCI_DEVICE_GET_CLASS(dev
)->is_bridge
) {
2008 if (pci_secondary_bus_in_range(dev
, bus_num
)) {
2017 static PCIBus
*pci_find_bus_nr(PCIBus
*bus
, int bus_num
)
2025 if (pci_bus_num(bus
) == bus_num
) {
2029 /* Consider all bus numbers in range for the host pci bridge. */
2030 if (!pci_bus_is_root(bus
) &&
2031 !pci_secondary_bus_in_range(bus
->parent_dev
, bus_num
)) {
2036 for (; bus
; bus
= sec
) {
2037 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
2038 if (pci_bus_num(sec
) == bus_num
) {
2041 /* PXB buses assumed to be children of bus 0 */
2042 if (pci_bus_is_root(sec
)) {
2043 if (pci_root_bus_in_range(sec
, bus_num
)) {
2047 if (pci_secondary_bus_in_range(sec
->parent_dev
, bus_num
)) {
2057 void pci_for_each_bus_depth_first(PCIBus
*bus
,
2058 void *(*begin
)(PCIBus
*bus
, void *parent_state
),
2059 void (*end
)(PCIBus
*bus
, void *state
),
2070 state
= begin(bus
, parent_state
);
2072 state
= parent_state
;
2075 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
2076 pci_for_each_bus_depth_first(sec
, begin
, end
, state
);
2085 PCIDevice
*pci_find_device(PCIBus
*bus
, int bus_num
, uint8_t devfn
)
2087 bus
= pci_find_bus_nr(bus
, bus_num
);
2092 return bus
->devices
[devfn
];
2095 static void pci_qdev_realize(DeviceState
*qdev
, Error
**errp
)
2097 PCIDevice
*pci_dev
= (PCIDevice
*)qdev
;
2098 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(pci_dev
);
2099 ObjectClass
*klass
= OBJECT_CLASS(pc
);
2100 Error
*local_err
= NULL
;
2101 bool is_default_rom
;
2104 /* initialize cap_present for pci_is_express() and pci_config_size(),
2105 * Note that hybrid PCIs are not set automatically and need to manage
2106 * QEMU_PCI_CAP_EXPRESS manually */
2107 if (object_class_dynamic_cast(klass
, INTERFACE_PCIE_DEVICE
) &&
2108 !object_class_dynamic_cast(klass
, INTERFACE_CONVENTIONAL_PCI_DEVICE
)) {
2109 pci_dev
->cap_present
|= QEMU_PCI_CAP_EXPRESS
;
2112 pci_dev
= do_pci_register_device(pci_dev
,
2113 object_get_typename(OBJECT(qdev
)),
2114 pci_dev
->devfn
, errp
);
2115 if (pci_dev
== NULL
)
2119 pc
->realize(pci_dev
, &local_err
);
2121 error_propagate(errp
, local_err
);
2122 do_pci_unregister_device(pci_dev
);
2127 if (pci_dev
->failover_pair_id
) {
2128 if (!pci_bus_is_express(pci_get_bus(pci_dev
))) {
2129 error_setg(errp
, "failover primary device must be on "
2131 pci_qdev_unrealize(DEVICE(pci_dev
));
2134 class_id
= pci_get_word(pci_dev
->config
+ PCI_CLASS_DEVICE
);
2135 if (class_id
!= PCI_CLASS_NETWORK_ETHERNET
) {
2136 error_setg(errp
, "failover primary device is not an "
2138 pci_qdev_unrealize(DEVICE(pci_dev
));
2141 if (!(pci_dev
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
)
2142 && (PCI_FUNC(pci_dev
->devfn
) == 0)) {
2143 qdev
->allow_unplug_during_migration
= true;
2145 error_setg(errp
, "failover: primary device must be in its own "
2147 pci_qdev_unrealize(DEVICE(pci_dev
));
2150 qdev
->allow_unplug_during_migration
= true;
2154 is_default_rom
= false;
2155 if (pci_dev
->romfile
== NULL
&& pc
->romfile
!= NULL
) {
2156 pci_dev
->romfile
= g_strdup(pc
->romfile
);
2157 is_default_rom
= true;
2160 pci_add_option_rom(pci_dev
, is_default_rom
, &local_err
);
2162 error_propagate(errp
, local_err
);
2163 pci_qdev_unrealize(DEVICE(pci_dev
));
2168 PCIDevice
*pci_new_multifunction(int devfn
, bool multifunction
,
2173 dev
= qdev_new(name
);
2174 qdev_prop_set_int32(dev
, "addr", devfn
);
2175 qdev_prop_set_bit(dev
, "multifunction", multifunction
);
2176 return PCI_DEVICE(dev
);
2179 PCIDevice
*pci_new(int devfn
, const char *name
)
2181 return pci_new_multifunction(devfn
, false, name
);
2184 bool pci_realize_and_unref(PCIDevice
*dev
, PCIBus
*bus
, Error
**errp
)
2186 return qdev_realize_and_unref(&dev
->qdev
, &bus
->qbus
, errp
);
2189 PCIDevice
*pci_create_simple_multifunction(PCIBus
*bus
, int devfn
,
2193 PCIDevice
*dev
= pci_new_multifunction(devfn
, multifunction
, name
);
2194 pci_realize_and_unref(dev
, bus
, &error_fatal
);
2198 PCIDevice
*pci_create_simple(PCIBus
*bus
, int devfn
, const char *name
)
2200 return pci_create_simple_multifunction(bus
, devfn
, false, name
);
2203 static uint8_t pci_find_space(PCIDevice
*pdev
, uint8_t size
)
2205 int offset
= PCI_CONFIG_HEADER_SIZE
;
2207 for (i
= PCI_CONFIG_HEADER_SIZE
; i
< PCI_CONFIG_SPACE_SIZE
; ++i
) {
2210 else if (i
- offset
+ 1 == size
)
2216 static uint8_t pci_find_capability_list(PCIDevice
*pdev
, uint8_t cap_id
,
2221 if (!(pdev
->config
[PCI_STATUS
] & PCI_STATUS_CAP_LIST
))
2224 for (prev
= PCI_CAPABILITY_LIST
; (next
= pdev
->config
[prev
]);
2225 prev
= next
+ PCI_CAP_LIST_NEXT
)
2226 if (pdev
->config
[next
+ PCI_CAP_LIST_ID
] == cap_id
)
2234 static uint8_t pci_find_capability_at_offset(PCIDevice
*pdev
, uint8_t offset
)
2236 uint8_t next
, prev
, found
= 0;
2238 if (!(pdev
->used
[offset
])) {
2242 assert(pdev
->config
[PCI_STATUS
] & PCI_STATUS_CAP_LIST
);
2244 for (prev
= PCI_CAPABILITY_LIST
; (next
= pdev
->config
[prev
]);
2245 prev
= next
+ PCI_CAP_LIST_NEXT
) {
2246 if (next
<= offset
&& next
> found
) {
2253 /* Patch the PCI vendor and device ids in a PCI rom image if necessary.
2254 This is needed for an option rom which is used for more than one device. */
2255 static void pci_patch_ids(PCIDevice
*pdev
, uint8_t *ptr
, int size
)
2259 uint16_t rom_vendor_id
;
2260 uint16_t rom_device_id
;
2262 uint16_t pcir_offset
;
2265 /* Words in rom data are little endian (like in PCI configuration),
2266 so they can be read / written with pci_get_word / pci_set_word. */
2268 /* Only a valid rom will be patched. */
2269 rom_magic
= pci_get_word(ptr
);
2270 if (rom_magic
!= 0xaa55) {
2271 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic
);
2274 pcir_offset
= pci_get_word(ptr
+ 0x18);
2275 if (pcir_offset
+ 8 >= size
|| memcmp(ptr
+ pcir_offset
, "PCIR", 4)) {
2276 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset
);
2280 vendor_id
= pci_get_word(pdev
->config
+ PCI_VENDOR_ID
);
2281 device_id
= pci_get_word(pdev
->config
+ PCI_DEVICE_ID
);
2282 rom_vendor_id
= pci_get_word(ptr
+ pcir_offset
+ 4);
2283 rom_device_id
= pci_get_word(ptr
+ pcir_offset
+ 6);
2285 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev
->romfile
,
2286 vendor_id
, device_id
, rom_vendor_id
, rom_device_id
);
2290 if (vendor_id
!= rom_vendor_id
) {
2291 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */
2292 checksum
+= (uint8_t)rom_vendor_id
+ (uint8_t)(rom_vendor_id
>> 8);
2293 checksum
-= (uint8_t)vendor_id
+ (uint8_t)(vendor_id
>> 8);
2294 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr
[6], checksum
);
2296 pci_set_word(ptr
+ pcir_offset
+ 4, vendor_id
);
2299 if (device_id
!= rom_device_id
) {
2300 /* Patch device id and checksum (at offset 6 for etherboot roms). */
2301 checksum
+= (uint8_t)rom_device_id
+ (uint8_t)(rom_device_id
>> 8);
2302 checksum
-= (uint8_t)device_id
+ (uint8_t)(device_id
>> 8);
2303 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr
[6], checksum
);
2305 pci_set_word(ptr
+ pcir_offset
+ 6, device_id
);
2309 /* Add an option rom for the device */
2310 static void pci_add_option_rom(PCIDevice
*pdev
, bool is_default_rom
,
2317 const VMStateDescription
*vmsd
;
2321 if (strlen(pdev
->romfile
) == 0)
2324 if (!pdev
->rom_bar
) {
2326 * Load rom via fw_cfg instead of creating a rom bar,
2327 * for 0.11 compatibility.
2329 int class = pci_get_word(pdev
->config
+ PCI_CLASS_DEVICE
);
2332 * Hot-plugged devices can't use the option ROM
2333 * if the rom bar is disabled.
2335 if (DEVICE(pdev
)->hotplugged
) {
2336 error_setg(errp
, "Hot-plugged device without ROM bar"
2337 " can't have an option ROM");
2341 if (class == 0x0300) {
2342 rom_add_vga(pdev
->romfile
);
2344 rom_add_option(pdev
->romfile
, -1);
2349 path
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, pdev
->romfile
);
2351 path
= g_strdup(pdev
->romfile
);
2354 size
= get_image_size(path
);
2356 error_setg(errp
, "failed to find romfile \"%s\"", pdev
->romfile
);
2359 } else if (size
== 0) {
2360 error_setg(errp
, "romfile \"%s\" is empty", pdev
->romfile
);
2364 size
= pow2ceil(size
);
2366 vmsd
= qdev_get_vmsd(DEVICE(pdev
));
2369 snprintf(name
, sizeof(name
), "%s.rom", vmsd
->name
);
2371 snprintf(name
, sizeof(name
), "%s.rom", object_get_typename(OBJECT(pdev
)));
2373 pdev
->has_rom
= true;
2374 memory_region_init_rom(&pdev
->rom
, OBJECT(pdev
), name
, size
, &error_fatal
);
2375 ptr
= memory_region_get_ram_ptr(&pdev
->rom
);
2376 if (load_image_size(path
, ptr
, size
) < 0) {
2377 error_setg(errp
, "failed to load romfile \"%s\"", pdev
->romfile
);
2383 if (is_default_rom
) {
2384 /* Only the default rom images will be patched (if needed). */
2385 pci_patch_ids(pdev
, ptr
, size
);
2388 pci_register_bar(pdev
, PCI_ROM_SLOT
, 0, &pdev
->rom
);
2391 static void pci_del_option_rom(PCIDevice
*pdev
)
2396 vmstate_unregister_ram(&pdev
->rom
, &pdev
->qdev
);
2397 pdev
->has_rom
= false;
2401 * On success, pci_add_capability() returns a positive value
2402 * that the offset of the pci capability.
2403 * On failure, it sets an error and returns a negative error
2406 int pci_add_capability(PCIDevice
*pdev
, uint8_t cap_id
,
2407 uint8_t offset
, uint8_t size
,
2411 int i
, overlapping_cap
;
2414 offset
= pci_find_space(pdev
, size
);
2415 /* out of PCI config space is programming error */
2418 /* Verify that capabilities don't overlap. Note: device assignment
2419 * depends on this check to verify that the device is not broken.
2420 * Should never trigger for emulated devices, but it's helpful
2421 * for debugging these. */
2422 for (i
= offset
; i
< offset
+ size
; i
++) {
2423 overlapping_cap
= pci_find_capability_at_offset(pdev
, i
);
2424 if (overlapping_cap
) {
2425 error_setg(errp
, "%s:%02x:%02x.%x "
2426 "Attempt to add PCI capability %x at offset "
2427 "%x overlaps existing capability %x at offset %x",
2428 pci_root_bus_path(pdev
), pci_dev_bus_num(pdev
),
2429 PCI_SLOT(pdev
->devfn
), PCI_FUNC(pdev
->devfn
),
2430 cap_id
, offset
, overlapping_cap
, i
);
2436 config
= pdev
->config
+ offset
;
2437 config
[PCI_CAP_LIST_ID
] = cap_id
;
2438 config
[PCI_CAP_LIST_NEXT
] = pdev
->config
[PCI_CAPABILITY_LIST
];
2439 pdev
->config
[PCI_CAPABILITY_LIST
] = offset
;
2440 pdev
->config
[PCI_STATUS
] |= PCI_STATUS_CAP_LIST
;
2441 memset(pdev
->used
+ offset
, 0xFF, QEMU_ALIGN_UP(size
, 4));
2442 /* Make capability read-only by default */
2443 memset(pdev
->wmask
+ offset
, 0, size
);
2444 /* Check capability by default */
2445 memset(pdev
->cmask
+ offset
, 0xFF, size
);
2449 /* Unlink capability from the pci config space. */
2450 void pci_del_capability(PCIDevice
*pdev
, uint8_t cap_id
, uint8_t size
)
2452 uint8_t prev
, offset
= pci_find_capability_list(pdev
, cap_id
, &prev
);
2455 pdev
->config
[prev
] = pdev
->config
[offset
+ PCI_CAP_LIST_NEXT
];
2456 /* Make capability writable again */
2457 memset(pdev
->wmask
+ offset
, 0xff, size
);
2458 memset(pdev
->w1cmask
+ offset
, 0, size
);
2459 /* Clear cmask as device-specific registers can't be checked */
2460 memset(pdev
->cmask
+ offset
, 0, size
);
2461 memset(pdev
->used
+ offset
, 0, QEMU_ALIGN_UP(size
, 4));
2463 if (!pdev
->config
[PCI_CAPABILITY_LIST
])
2464 pdev
->config
[PCI_STATUS
] &= ~PCI_STATUS_CAP_LIST
;
2467 uint8_t pci_find_capability(PCIDevice
*pdev
, uint8_t cap_id
)
2469 return pci_find_capability_list(pdev
, cap_id
, NULL
);
2472 static void pcibus_dev_print(Monitor
*mon
, DeviceState
*dev
, int indent
)
2474 PCIDevice
*d
= (PCIDevice
*)dev
;
2475 const pci_class_desc
*desc
;
2480 class = pci_get_word(d
->config
+ PCI_CLASS_DEVICE
);
2481 desc
= pci_class_descriptions
;
2482 while (desc
->desc
&& class != desc
->class)
2485 snprintf(ctxt
, sizeof(ctxt
), "%s", desc
->desc
);
2487 snprintf(ctxt
, sizeof(ctxt
), "Class %04x", class);
2490 monitor_printf(mon
, "%*sclass %s, addr %02x:%02x.%x, "
2491 "pci id %04x:%04x (sub %04x:%04x)\n",
2492 indent
, "", ctxt
, pci_dev_bus_num(d
),
2493 PCI_SLOT(d
->devfn
), PCI_FUNC(d
->devfn
),
2494 pci_get_word(d
->config
+ PCI_VENDOR_ID
),
2495 pci_get_word(d
->config
+ PCI_DEVICE_ID
),
2496 pci_get_word(d
->config
+ PCI_SUBSYSTEM_VENDOR_ID
),
2497 pci_get_word(d
->config
+ PCI_SUBSYSTEM_ID
));
2498 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
2499 r
= &d
->io_regions
[i
];
2502 monitor_printf(mon
, "%*sbar %d: %s at 0x%"FMT_PCIBUS
2503 " [0x%"FMT_PCIBUS
"]\n",
2505 i
, r
->type
& PCI_BASE_ADDRESS_SPACE_IO
? "i/o" : "mem",
2506 r
->addr
, r
->addr
+ r
->size
- 1);
2510 static char *pci_dev_fw_name(DeviceState
*dev
, char *buf
, int len
)
2512 PCIDevice
*d
= (PCIDevice
*)dev
;
2513 const char *name
= NULL
;
2514 const pci_class_desc
*desc
= pci_class_descriptions
;
2515 int class = pci_get_word(d
->config
+ PCI_CLASS_DEVICE
);
2517 while (desc
->desc
&&
2518 (class & ~desc
->fw_ign_bits
) !=
2519 (desc
->class & ~desc
->fw_ign_bits
)) {
2524 name
= desc
->fw_name
;
2528 pstrcpy(buf
, len
, name
);
2530 snprintf(buf
, len
, "pci%04x,%04x",
2531 pci_get_word(d
->config
+ PCI_VENDOR_ID
),
2532 pci_get_word(d
->config
+ PCI_DEVICE_ID
));
2538 static char *pcibus_get_fw_dev_path(DeviceState
*dev
)
2540 PCIDevice
*d
= (PCIDevice
*)dev
;
2541 char path
[50], name
[33];
2544 off
= snprintf(path
, sizeof(path
), "%s@%x",
2545 pci_dev_fw_name(dev
, name
, sizeof name
),
2546 PCI_SLOT(d
->devfn
));
2547 if (PCI_FUNC(d
->devfn
))
2548 snprintf(path
+ off
, sizeof(path
) + off
, ",%x", PCI_FUNC(d
->devfn
));
2549 return g_strdup(path
);
2552 static char *pcibus_get_dev_path(DeviceState
*dev
)
2554 PCIDevice
*d
= container_of(dev
, PCIDevice
, qdev
);
2557 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function.
2558 * 00 is added here to make this format compatible with
2559 * domain:Bus:Slot.Func for systems without nested PCI bridges.
2560 * Slot.Function list specifies the slot and function numbers for all
2561 * devices on the path from root to the specific device. */
2562 const char *root_bus_path
;
2564 char slot
[] = ":SS.F";
2565 int slot_len
= sizeof slot
- 1 /* For '\0' */;
2570 root_bus_path
= pci_root_bus_path(d
);
2571 root_bus_len
= strlen(root_bus_path
);
2573 /* Calculate # of slots on path between device and root. */;
2575 for (t
= d
; t
; t
= pci_get_bus(t
)->parent_dev
) {
2579 path_len
= root_bus_len
+ slot_len
* slot_depth
;
2581 /* Allocate memory, fill in the terminating null byte. */
2582 path
= g_malloc(path_len
+ 1 /* For '\0' */);
2583 path
[path_len
] = '\0';
2585 memcpy(path
, root_bus_path
, root_bus_len
);
2587 /* Fill in slot numbers. We walk up from device to root, so need to print
2588 * them in the reverse order, last to first. */
2589 p
= path
+ path_len
;
2590 for (t
= d
; t
; t
= pci_get_bus(t
)->parent_dev
) {
2592 s
= snprintf(slot
, sizeof slot
, ":%02x.%x",
2593 PCI_SLOT(t
->devfn
), PCI_FUNC(t
->devfn
));
2594 assert(s
== slot_len
);
2595 memcpy(p
, slot
, slot_len
);
2601 static int pci_qdev_find_recursive(PCIBus
*bus
,
2602 const char *id
, PCIDevice
**pdev
)
2604 DeviceState
*qdev
= qdev_find_recursive(&bus
->qbus
, id
);
2609 /* roughly check if given qdev is pci device */
2610 if (object_dynamic_cast(OBJECT(qdev
), TYPE_PCI_DEVICE
)) {
2611 *pdev
= PCI_DEVICE(qdev
);
2617 int pci_qdev_find_device(const char *id
, PCIDevice
**pdev
)
2619 PCIHostState
*host_bridge
;
2622 QLIST_FOREACH(host_bridge
, &pci_host_bridges
, next
) {
2623 int tmp
= pci_qdev_find_recursive(host_bridge
->bus
, id
, pdev
);
2628 if (tmp
!= -ENODEV
) {
2636 MemoryRegion
*pci_address_space(PCIDevice
*dev
)
2638 return pci_get_bus(dev
)->address_space_mem
;
2641 MemoryRegion
*pci_address_space_io(PCIDevice
*dev
)
2643 return pci_get_bus(dev
)->address_space_io
;
2646 static void pci_device_class_init(ObjectClass
*klass
, void *data
)
2648 DeviceClass
*k
= DEVICE_CLASS(klass
);
2650 k
->realize
= pci_qdev_realize
;
2651 k
->unrealize
= pci_qdev_unrealize
;
2652 k
->bus_type
= TYPE_PCI_BUS
;
2653 device_class_set_props(k
, pci_props
);
2656 static void pci_device_class_base_init(ObjectClass
*klass
, void *data
)
2658 if (!object_class_is_abstract(klass
)) {
2659 ObjectClass
*conventional
=
2660 object_class_dynamic_cast(klass
, INTERFACE_CONVENTIONAL_PCI_DEVICE
);
2662 object_class_dynamic_cast(klass
, INTERFACE_PCIE_DEVICE
);
2663 assert(conventional
|| pcie
);
2667 AddressSpace
*pci_device_iommu_address_space(PCIDevice
*dev
)
2669 PCIBus
*bus
= pci_get_bus(dev
);
2670 PCIBus
*iommu_bus
= bus
;
2671 uint8_t devfn
= dev
->devfn
;
2673 while (iommu_bus
&& !iommu_bus
->iommu_fn
&& iommu_bus
->parent_dev
) {
2674 PCIBus
*parent_bus
= pci_get_bus(iommu_bus
->parent_dev
);
2677 * The requester ID of the provided device may be aliased, as seen from
2678 * the IOMMU, due to topology limitations. The IOMMU relies on a
2679 * requester ID to provide a unique AddressSpace for devices, but
2680 * conventional PCI buses pre-date such concepts. Instead, the PCIe-
2681 * to-PCI bridge creates and accepts transactions on behalf of down-
2682 * stream devices. When doing so, all downstream devices are masked
2683 * (aliased) behind a single requester ID. The requester ID used
2684 * depends on the format of the bridge devices. Proper PCIe-to-PCI
2685 * bridges, with a PCIe capability indicating such, follow the
2686 * guidelines of chapter 2.3 of the PCIe-to-PCI/X bridge specification,
2687 * where the bridge uses the seconary bus as the bridge portion of the
2688 * requester ID and devfn of 00.0. For other bridges, typically those
2689 * found on the root complex such as the dmi-to-pci-bridge, we follow
2690 * the convention of typical bare-metal hardware, which uses the
2691 * requester ID of the bridge itself. There are device specific
2692 * exceptions to these rules, but these are the defaults that the
2693 * Linux kernel uses when determining DMA aliases itself and believed
2694 * to be true for the bare metal equivalents of the devices emulated
2697 if (!pci_bus_is_express(iommu_bus
)) {
2698 PCIDevice
*parent
= iommu_bus
->parent_dev
;
2700 if (pci_is_express(parent
) &&
2701 pcie_cap_get_type(parent
) == PCI_EXP_TYPE_PCI_BRIDGE
) {
2702 devfn
= PCI_DEVFN(0, 0);
2705 devfn
= parent
->devfn
;
2710 iommu_bus
= parent_bus
;
2712 if (iommu_bus
&& iommu_bus
->iommu_fn
) {
2713 return iommu_bus
->iommu_fn(bus
, iommu_bus
->iommu_opaque
, devfn
);
2715 return &address_space_memory
;
2718 void pci_setup_iommu(PCIBus
*bus
, PCIIOMMUFunc fn
, void *opaque
)
2721 bus
->iommu_opaque
= opaque
;
2724 static void pci_dev_get_w64(PCIBus
*b
, PCIDevice
*dev
, void *opaque
)
2726 Range
*range
= opaque
;
2727 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(dev
);
2728 uint16_t cmd
= pci_get_word(dev
->config
+ PCI_COMMAND
);
2731 if (!(cmd
& PCI_COMMAND_MEMORY
)) {
2735 if (pc
->is_bridge
) {
2736 pcibus_t base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
2737 pcibus_t limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
2739 base
= MAX(base
, 0x1ULL
<< 32);
2741 if (limit
>= base
) {
2743 range_set_bounds(&pref_range
, base
, limit
);
2744 range_extend(range
, &pref_range
);
2747 for (i
= 0; i
< PCI_NUM_REGIONS
; ++i
) {
2748 PCIIORegion
*r
= &dev
->io_regions
[i
];
2753 (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) ||
2754 !(r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
)) {
2758 lob
= pci_bar_address(dev
, i
, r
->type
, r
->size
);
2759 upb
= lob
+ r
->size
- 1;
2760 if (lob
== PCI_BAR_UNMAPPED
) {
2764 lob
= MAX(lob
, 0x1ULL
<< 32);
2767 range_set_bounds(®ion_range
, lob
, upb
);
2768 range_extend(range
, ®ion_range
);
2773 void pci_bus_get_w64_range(PCIBus
*bus
, Range
*range
)
2775 range_make_empty(range
);
2776 pci_for_each_device_under_bus(bus
, pci_dev_get_w64
, range
);
2779 static bool pcie_has_upstream_port(PCIDevice
*dev
)
2781 PCIDevice
*parent_dev
= pci_bridge_get_device(pci_get_bus(dev
));
2783 /* Device associated with an upstream port.
2784 * As there are several types of these, it's easier to check the
2785 * parent device: upstream ports are always connected to
2786 * root or downstream ports.
2788 return parent_dev
&&
2789 pci_is_express(parent_dev
) &&
2790 parent_dev
->exp
.exp_cap
&&
2791 (pcie_cap_get_type(parent_dev
) == PCI_EXP_TYPE_ROOT_PORT
||
2792 pcie_cap_get_type(parent_dev
) == PCI_EXP_TYPE_DOWNSTREAM
);
2795 PCIDevice
*pci_get_function_0(PCIDevice
*pci_dev
)
2797 PCIBus
*bus
= pci_get_bus(pci_dev
);
2799 if(pcie_has_upstream_port(pci_dev
)) {
2800 /* With an upstream PCIe port, we only support 1 device at slot 0 */
2801 return bus
->devices
[0];
2803 /* Other bus types might support multiple devices at slots 0-31 */
2804 return bus
->devices
[PCI_DEVFN(PCI_SLOT(pci_dev
->devfn
), 0)];
2808 MSIMessage
pci_get_msi_message(PCIDevice
*dev
, int vector
)
2811 if (msix_enabled(dev
)) {
2812 msg
= msix_get_message(dev
, vector
);
2813 } else if (msi_enabled(dev
)) {
2814 msg
= msi_get_message(dev
, vector
);
2816 /* Should never happen */
2817 error_report("%s: unknown interrupt type", __func__
);
2823 static const TypeInfo pci_device_type_info
= {
2824 .name
= TYPE_PCI_DEVICE
,
2825 .parent
= TYPE_DEVICE
,
2826 .instance_size
= sizeof(PCIDevice
),
2828 .class_size
= sizeof(PCIDeviceClass
),
2829 .class_init
= pci_device_class_init
,
2830 .class_base_init
= pci_device_class_base_init
,
2833 static void pci_register_types(void)
2835 type_register_static(&pci_bus_info
);
2836 type_register_static(&pcie_bus_info
);
2837 type_register_static(&conventional_pci_interface_info
);
2838 type_register_static(&pcie_interface_info
);
2839 type_register_static(&pci_device_type_info
);
2842 type_init(pci_register_types
)