4 * Copyright (c) 2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "hw/pci/pci.h"
26 #include "hw/pci/pci_bridge.h"
27 #include "hw/pci/pci_bus.h"
28 #include "hw/pci/pci_host.h"
29 #include "monitor/monitor.h"
31 #include "sysemu/sysemu.h"
32 #include "hw/loader.h"
33 #include "qemu/range.h"
34 #include "qmp-commands.h"
36 #include "hw/pci/msi.h"
37 #include "hw/pci/msix.h"
38 #include "exec/address-spaces.h"
39 #include "hw/hotplug.h"
43 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
45 # define PCI_DPRINTF(format, ...) do { } while (0)
48 static void pcibus_dev_print(Monitor
*mon
, DeviceState
*dev
, int indent
);
49 static char *pcibus_get_dev_path(DeviceState
*dev
);
50 static char *pcibus_get_fw_dev_path(DeviceState
*dev
);
51 static void pcibus_reset(BusState
*qbus
);
53 static Property pci_props
[] = {
54 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice
, devfn
, -1),
55 DEFINE_PROP_STRING("romfile", PCIDevice
, romfile
),
56 DEFINE_PROP_UINT32("rombar", PCIDevice
, rom_bar
, 1),
57 DEFINE_PROP_BIT("multifunction", PCIDevice
, cap_present
,
58 QEMU_PCI_CAP_MULTIFUNCTION_BITNR
, false),
59 DEFINE_PROP_BIT("command_serr_enable", PCIDevice
, cap_present
,
60 QEMU_PCI_CAP_SERR_BITNR
, true),
61 DEFINE_PROP_END_OF_LIST()
64 static const VMStateDescription vmstate_pcibus
= {
67 .minimum_version_id
= 1,
68 .fields
= (VMStateField
[]) {
69 VMSTATE_INT32_EQUAL(nirq
, PCIBus
),
70 VMSTATE_VARRAY_INT32(irq_count
, PCIBus
,
71 nirq
, 0, vmstate_info_int32
,
77 static void pci_bus_realize(BusState
*qbus
, Error
**errp
)
79 PCIBus
*bus
= PCI_BUS(qbus
);
81 vmstate_register(NULL
, -1, &vmstate_pcibus
, bus
);
84 static void pci_bus_unrealize(BusState
*qbus
, Error
**errp
)
86 PCIBus
*bus
= PCI_BUS(qbus
);
88 vmstate_unregister(NULL
, &vmstate_pcibus
, bus
);
91 static bool pcibus_is_root(PCIBus
*bus
)
93 return !bus
->parent_dev
;
96 static void pci_bus_class_init(ObjectClass
*klass
, void *data
)
98 BusClass
*k
= BUS_CLASS(klass
);
99 PCIBusClass
*pbc
= PCI_BUS_CLASS(klass
);
101 k
->print_dev
= pcibus_dev_print
;
102 k
->get_dev_path
= pcibus_get_dev_path
;
103 k
->get_fw_dev_path
= pcibus_get_fw_dev_path
;
104 k
->realize
= pci_bus_realize
;
105 k
->unrealize
= pci_bus_unrealize
;
106 k
->reset
= pcibus_reset
;
108 pbc
->is_root
= pcibus_is_root
;
111 static const TypeInfo pci_bus_info
= {
112 .name
= TYPE_PCI_BUS
,
114 .instance_size
= sizeof(PCIBus
),
115 .class_size
= sizeof(PCIBusClass
),
116 .class_init
= pci_bus_class_init
,
119 static const TypeInfo pcie_bus_info
= {
120 .name
= TYPE_PCIE_BUS
,
121 .parent
= TYPE_PCI_BUS
,
124 static PCIBus
*pci_find_bus_nr(PCIBus
*bus
, int bus_num
);
125 static void pci_update_mappings(PCIDevice
*d
);
126 static void pci_irq_handler(void *opaque
, int irq_num
, int level
);
127 static void pci_add_option_rom(PCIDevice
*pdev
, bool is_default_rom
, Error
**);
128 static void pci_del_option_rom(PCIDevice
*pdev
);
130 static uint16_t pci_default_sub_vendor_id
= PCI_SUBVENDOR_ID_REDHAT_QUMRANET
;
131 static uint16_t pci_default_sub_device_id
= PCI_SUBDEVICE_ID_QEMU
;
133 static QLIST_HEAD(, PCIHostState
) pci_host_bridges
;
135 static int pci_bar(PCIDevice
*d
, int reg
)
139 if (reg
!= PCI_ROM_SLOT
)
140 return PCI_BASE_ADDRESS_0
+ reg
* 4;
142 type
= d
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
143 return type
== PCI_HEADER_TYPE_BRIDGE
? PCI_ROM_ADDRESS1
: PCI_ROM_ADDRESS
;
146 static inline int pci_irq_state(PCIDevice
*d
, int irq_num
)
148 return (d
->irq_state
>> irq_num
) & 0x1;
151 static inline void pci_set_irq_state(PCIDevice
*d
, int irq_num
, int level
)
153 d
->irq_state
&= ~(0x1 << irq_num
);
154 d
->irq_state
|= level
<< irq_num
;
157 static void pci_change_irq_level(PCIDevice
*pci_dev
, int irq_num
, int change
)
162 irq_num
= bus
->map_irq(pci_dev
, irq_num
);
165 pci_dev
= bus
->parent_dev
;
167 bus
->irq_count
[irq_num
] += change
;
168 bus
->set_irq(bus
->irq_opaque
, irq_num
, bus
->irq_count
[irq_num
] != 0);
171 int pci_bus_get_irq_level(PCIBus
*bus
, int irq_num
)
173 assert(irq_num
>= 0);
174 assert(irq_num
< bus
->nirq
);
175 return !!bus
->irq_count
[irq_num
];
178 /* Update interrupt status bit in config space on interrupt
180 static void pci_update_irq_status(PCIDevice
*dev
)
182 if (dev
->irq_state
) {
183 dev
->config
[PCI_STATUS
] |= PCI_STATUS_INTERRUPT
;
185 dev
->config
[PCI_STATUS
] &= ~PCI_STATUS_INTERRUPT
;
189 void pci_device_deassert_intx(PCIDevice
*dev
)
192 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
193 pci_irq_handler(dev
, i
, 0);
197 static void pci_do_device_reset(PCIDevice
*dev
)
201 pci_device_deassert_intx(dev
);
202 assert(dev
->irq_state
== 0);
204 /* Clear all writable bits */
205 pci_word_test_and_clear_mask(dev
->config
+ PCI_COMMAND
,
206 pci_get_word(dev
->wmask
+ PCI_COMMAND
) |
207 pci_get_word(dev
->w1cmask
+ PCI_COMMAND
));
208 pci_word_test_and_clear_mask(dev
->config
+ PCI_STATUS
,
209 pci_get_word(dev
->wmask
+ PCI_STATUS
) |
210 pci_get_word(dev
->w1cmask
+ PCI_STATUS
));
211 dev
->config
[PCI_CACHE_LINE_SIZE
] = 0x0;
212 dev
->config
[PCI_INTERRUPT_LINE
] = 0x0;
213 for (r
= 0; r
< PCI_NUM_REGIONS
; ++r
) {
214 PCIIORegion
*region
= &dev
->io_regions
[r
];
219 if (!(region
->type
& PCI_BASE_ADDRESS_SPACE_IO
) &&
220 region
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
221 pci_set_quad(dev
->config
+ pci_bar(dev
, r
), region
->type
);
223 pci_set_long(dev
->config
+ pci_bar(dev
, r
), region
->type
);
226 pci_update_mappings(dev
);
233 * This function is called on #RST and FLR.
234 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
236 void pci_device_reset(PCIDevice
*dev
)
238 qdev_reset_all(&dev
->qdev
);
239 pci_do_device_reset(dev
);
243 * Trigger pci bus reset under a given bus.
244 * Called via qbus_reset_all on RST# assert, after the devices
245 * have been reset qdev_reset_all-ed already.
247 static void pcibus_reset(BusState
*qbus
)
249 PCIBus
*bus
= DO_UPCAST(PCIBus
, qbus
, qbus
);
252 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); ++i
) {
253 if (bus
->devices
[i
]) {
254 pci_do_device_reset(bus
->devices
[i
]);
258 for (i
= 0; i
< bus
->nirq
; i
++) {
259 assert(bus
->irq_count
[i
] == 0);
263 static void pci_host_bus_register(PCIBus
*bus
, DeviceState
*parent
)
265 PCIHostState
*host_bridge
= PCI_HOST_BRIDGE(parent
);
267 QLIST_INSERT_HEAD(&pci_host_bridges
, host_bridge
, next
);
270 PCIBus
*pci_find_primary_bus(void)
272 PCIBus
*primary_bus
= NULL
;
275 QLIST_FOREACH(host
, &pci_host_bridges
, next
) {
277 /* We have multiple root buses, refuse to select a primary */
280 primary_bus
= host
->bus
;
286 PCIBus
*pci_device_root_bus(const PCIDevice
*d
)
288 PCIBus
*bus
= d
->bus
;
290 while (!pci_bus_is_root(bus
)) {
300 const char *pci_root_bus_path(PCIDevice
*dev
)
302 PCIBus
*rootbus
= pci_device_root_bus(dev
);
303 PCIHostState
*host_bridge
= PCI_HOST_BRIDGE(rootbus
->qbus
.parent
);
304 PCIHostBridgeClass
*hc
= PCI_HOST_BRIDGE_GET_CLASS(host_bridge
);
306 assert(host_bridge
->bus
== rootbus
);
308 if (hc
->root_bus_path
) {
309 return (*hc
->root_bus_path
)(host_bridge
, rootbus
);
312 return rootbus
->qbus
.name
;
315 static void pci_bus_init(PCIBus
*bus
, DeviceState
*parent
,
317 MemoryRegion
*address_space_mem
,
318 MemoryRegion
*address_space_io
,
321 assert(PCI_FUNC(devfn_min
) == 0);
322 bus
->devfn_min
= devfn_min
;
323 bus
->address_space_mem
= address_space_mem
;
324 bus
->address_space_io
= address_space_io
;
327 QLIST_INIT(&bus
->child
);
329 pci_host_bus_register(bus
, parent
);
332 bool pci_bus_is_express(PCIBus
*bus
)
334 return object_dynamic_cast(OBJECT(bus
), TYPE_PCIE_BUS
);
337 bool pci_bus_is_root(PCIBus
*bus
)
339 return PCI_BUS_GET_CLASS(bus
)->is_root(bus
);
342 void pci_bus_new_inplace(PCIBus
*bus
, size_t bus_size
, DeviceState
*parent
,
344 MemoryRegion
*address_space_mem
,
345 MemoryRegion
*address_space_io
,
346 uint8_t devfn_min
, const char *typename
)
348 qbus_create_inplace(bus
, bus_size
, typename
, parent
, name
);
349 pci_bus_init(bus
, parent
, name
, address_space_mem
,
350 address_space_io
, devfn_min
);
353 PCIBus
*pci_bus_new(DeviceState
*parent
, const char *name
,
354 MemoryRegion
*address_space_mem
,
355 MemoryRegion
*address_space_io
,
356 uint8_t devfn_min
, const char *typename
)
360 bus
= PCI_BUS(qbus_create(typename
, parent
, name
));
361 pci_bus_init(bus
, parent
, name
, address_space_mem
,
362 address_space_io
, devfn_min
);
366 void pci_bus_irqs(PCIBus
*bus
, pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
367 void *irq_opaque
, int nirq
)
369 bus
->set_irq
= set_irq
;
370 bus
->map_irq
= map_irq
;
371 bus
->irq_opaque
= irq_opaque
;
373 bus
->irq_count
= g_malloc0(nirq
* sizeof(bus
->irq_count
[0]));
376 PCIBus
*pci_register_bus(DeviceState
*parent
, const char *name
,
377 pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
379 MemoryRegion
*address_space_mem
,
380 MemoryRegion
*address_space_io
,
381 uint8_t devfn_min
, int nirq
, const char *typename
)
385 bus
= pci_bus_new(parent
, name
, address_space_mem
,
386 address_space_io
, devfn_min
, typename
);
387 pci_bus_irqs(bus
, set_irq
, map_irq
, irq_opaque
, nirq
);
391 int pci_bus_num(PCIBus
*s
)
393 if (pci_bus_is_root(s
))
394 return 0; /* pci host bridge */
395 return s
->parent_dev
->config
[PCI_SECONDARY_BUS
];
398 static int get_pci_config_device(QEMUFile
*f
, void *pv
, size_t size
)
400 PCIDevice
*s
= container_of(pv
, PCIDevice
, config
);
401 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(s
);
405 assert(size
== pci_config_size(s
));
406 config
= g_malloc(size
);
408 qemu_get_buffer(f
, config
, size
);
409 for (i
= 0; i
< size
; ++i
) {
410 if ((config
[i
] ^ s
->config
[i
]) &
411 s
->cmask
[i
] & ~s
->wmask
[i
] & ~s
->w1cmask
[i
]) {
416 memcpy(s
->config
, config
, size
);
418 pci_update_mappings(s
);
420 PCIBridge
*b
= PCI_BRIDGE(s
);
421 pci_bridge_update_mappings(b
);
424 memory_region_set_enabled(&s
->bus_master_enable_region
,
425 pci_get_word(s
->config
+ PCI_COMMAND
)
426 & PCI_COMMAND_MASTER
);
432 /* just put buffer */
433 static void put_pci_config_device(QEMUFile
*f
, void *pv
, size_t size
)
435 const uint8_t **v
= pv
;
436 assert(size
== pci_config_size(container_of(pv
, PCIDevice
, config
)));
437 qemu_put_buffer(f
, *v
, size
);
440 static VMStateInfo vmstate_info_pci_config
= {
441 .name
= "pci config",
442 .get
= get_pci_config_device
,
443 .put
= put_pci_config_device
,
446 static int get_pci_irq_state(QEMUFile
*f
, void *pv
, size_t size
)
448 PCIDevice
*s
= container_of(pv
, PCIDevice
, irq_state
);
449 uint32_t irq_state
[PCI_NUM_PINS
];
451 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
452 irq_state
[i
] = qemu_get_be32(f
);
453 if (irq_state
[i
] != 0x1 && irq_state
[i
] != 0) {
454 fprintf(stderr
, "irq state %d: must be 0 or 1.\n",
460 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
461 pci_set_irq_state(s
, i
, irq_state
[i
]);
467 static void put_pci_irq_state(QEMUFile
*f
, void *pv
, size_t size
)
470 PCIDevice
*s
= container_of(pv
, PCIDevice
, irq_state
);
472 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
473 qemu_put_be32(f
, pci_irq_state(s
, i
));
477 static VMStateInfo vmstate_info_pci_irq_state
= {
478 .name
= "pci irq state",
479 .get
= get_pci_irq_state
,
480 .put
= put_pci_irq_state
,
483 const VMStateDescription vmstate_pci_device
= {
486 .minimum_version_id
= 1,
487 .fields
= (VMStateField
[]) {
488 VMSTATE_INT32_POSITIVE_LE(version_id
, PCIDevice
),
489 VMSTATE_BUFFER_UNSAFE_INFO(config
, PCIDevice
, 0,
490 vmstate_info_pci_config
,
491 PCI_CONFIG_SPACE_SIZE
),
492 VMSTATE_BUFFER_UNSAFE_INFO(irq_state
, PCIDevice
, 2,
493 vmstate_info_pci_irq_state
,
494 PCI_NUM_PINS
* sizeof(int32_t)),
495 VMSTATE_END_OF_LIST()
499 const VMStateDescription vmstate_pcie_device
= {
500 .name
= "PCIEDevice",
502 .minimum_version_id
= 1,
503 .fields
= (VMStateField
[]) {
504 VMSTATE_INT32_POSITIVE_LE(version_id
, PCIDevice
),
505 VMSTATE_BUFFER_UNSAFE_INFO(config
, PCIDevice
, 0,
506 vmstate_info_pci_config
,
507 PCIE_CONFIG_SPACE_SIZE
),
508 VMSTATE_BUFFER_UNSAFE_INFO(irq_state
, PCIDevice
, 2,
509 vmstate_info_pci_irq_state
,
510 PCI_NUM_PINS
* sizeof(int32_t)),
511 VMSTATE_END_OF_LIST()
515 static inline const VMStateDescription
*pci_get_vmstate(PCIDevice
*s
)
517 return pci_is_express(s
) ? &vmstate_pcie_device
: &vmstate_pci_device
;
520 void pci_device_save(PCIDevice
*s
, QEMUFile
*f
)
522 /* Clear interrupt status bit: it is implicit
523 * in irq_state which we are saving.
524 * This makes us compatible with old devices
525 * which never set or clear this bit. */
526 s
->config
[PCI_STATUS
] &= ~PCI_STATUS_INTERRUPT
;
527 vmstate_save_state(f
, pci_get_vmstate(s
), s
, NULL
);
528 /* Restore the interrupt status bit. */
529 pci_update_irq_status(s
);
532 int pci_device_load(PCIDevice
*s
, QEMUFile
*f
)
535 ret
= vmstate_load_state(f
, pci_get_vmstate(s
), s
, s
->version_id
);
536 /* Restore the interrupt status bit. */
537 pci_update_irq_status(s
);
541 static void pci_set_default_subsystem_id(PCIDevice
*pci_dev
)
543 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_VENDOR_ID
,
544 pci_default_sub_vendor_id
);
545 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_ID
,
546 pci_default_sub_device_id
);
550 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
551 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
553 static int pci_parse_devaddr(const char *addr
, int *domp
, int *busp
,
554 unsigned int *slotp
, unsigned int *funcp
)
559 unsigned long dom
= 0, bus
= 0;
560 unsigned int slot
= 0;
561 unsigned int func
= 0;
564 val
= strtoul(p
, &e
, 16);
570 val
= strtoul(p
, &e
, 16);
577 val
= strtoul(p
, &e
, 16);
590 val
= strtoul(p
, &e
, 16);
597 /* if funcp == NULL func is 0 */
598 if (dom
> 0xffff || bus
> 0xff || slot
> 0x1f || func
> 7)
612 static PCIBus
*pci_get_bus_devfn(int *devfnp
, PCIBus
*root
,
619 fprintf(stderr
, "No primary PCI bus\n");
623 assert(!root
->parent_dev
);
627 return pci_find_bus_nr(root
, 0);
630 if (pci_parse_devaddr(devaddr
, &dom
, &bus
, &slot
, NULL
) < 0) {
635 fprintf(stderr
, "No support for non-zero PCI domains\n");
639 *devfnp
= PCI_DEVFN(slot
, 0);
640 return pci_find_bus_nr(root
, bus
);
643 static void pci_init_cmask(PCIDevice
*dev
)
645 pci_set_word(dev
->cmask
+ PCI_VENDOR_ID
, 0xffff);
646 pci_set_word(dev
->cmask
+ PCI_DEVICE_ID
, 0xffff);
647 dev
->cmask
[PCI_STATUS
] = PCI_STATUS_CAP_LIST
;
648 dev
->cmask
[PCI_REVISION_ID
] = 0xff;
649 dev
->cmask
[PCI_CLASS_PROG
] = 0xff;
650 pci_set_word(dev
->cmask
+ PCI_CLASS_DEVICE
, 0xffff);
651 dev
->cmask
[PCI_HEADER_TYPE
] = 0xff;
652 dev
->cmask
[PCI_CAPABILITY_LIST
] = 0xff;
655 static void pci_init_wmask(PCIDevice
*dev
)
657 int config_size
= pci_config_size(dev
);
659 dev
->wmask
[PCI_CACHE_LINE_SIZE
] = 0xff;
660 dev
->wmask
[PCI_INTERRUPT_LINE
] = 0xff;
661 pci_set_word(dev
->wmask
+ PCI_COMMAND
,
662 PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
|
663 PCI_COMMAND_INTX_DISABLE
);
664 if (dev
->cap_present
& QEMU_PCI_CAP_SERR
) {
665 pci_word_test_and_set_mask(dev
->wmask
+ PCI_COMMAND
, PCI_COMMAND_SERR
);
668 memset(dev
->wmask
+ PCI_CONFIG_HEADER_SIZE
, 0xff,
669 config_size
- PCI_CONFIG_HEADER_SIZE
);
672 static void pci_init_w1cmask(PCIDevice
*dev
)
675 * Note: It's okay to set w1cmask even for readonly bits as
676 * long as their value is hardwired to 0.
678 pci_set_word(dev
->w1cmask
+ PCI_STATUS
,
679 PCI_STATUS_PARITY
| PCI_STATUS_SIG_TARGET_ABORT
|
680 PCI_STATUS_REC_TARGET_ABORT
| PCI_STATUS_REC_MASTER_ABORT
|
681 PCI_STATUS_SIG_SYSTEM_ERROR
| PCI_STATUS_DETECTED_PARITY
);
684 static void pci_init_mask_bridge(PCIDevice
*d
)
686 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
687 PCI_SEC_LETENCY_TIMER */
688 memset(d
->wmask
+ PCI_PRIMARY_BUS
, 0xff, 4);
691 d
->wmask
[PCI_IO_BASE
] = PCI_IO_RANGE_MASK
& 0xff;
692 d
->wmask
[PCI_IO_LIMIT
] = PCI_IO_RANGE_MASK
& 0xff;
693 pci_set_word(d
->wmask
+ PCI_MEMORY_BASE
,
694 PCI_MEMORY_RANGE_MASK
& 0xffff);
695 pci_set_word(d
->wmask
+ PCI_MEMORY_LIMIT
,
696 PCI_MEMORY_RANGE_MASK
& 0xffff);
697 pci_set_word(d
->wmask
+ PCI_PREF_MEMORY_BASE
,
698 PCI_PREF_RANGE_MASK
& 0xffff);
699 pci_set_word(d
->wmask
+ PCI_PREF_MEMORY_LIMIT
,
700 PCI_PREF_RANGE_MASK
& 0xffff);
702 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
703 memset(d
->wmask
+ PCI_PREF_BASE_UPPER32
, 0xff, 8);
705 /* Supported memory and i/o types */
706 d
->config
[PCI_IO_BASE
] |= PCI_IO_RANGE_TYPE_16
;
707 d
->config
[PCI_IO_LIMIT
] |= PCI_IO_RANGE_TYPE_16
;
708 pci_word_test_and_set_mask(d
->config
+ PCI_PREF_MEMORY_BASE
,
709 PCI_PREF_RANGE_TYPE_64
);
710 pci_word_test_and_set_mask(d
->config
+ PCI_PREF_MEMORY_LIMIT
,
711 PCI_PREF_RANGE_TYPE_64
);
714 * TODO: Bridges default to 10-bit VGA decoding but we currently only
715 * implement 16-bit decoding (no alias support).
717 pci_set_word(d
->wmask
+ PCI_BRIDGE_CONTROL
,
718 PCI_BRIDGE_CTL_PARITY
|
719 PCI_BRIDGE_CTL_SERR
|
722 PCI_BRIDGE_CTL_VGA_16BIT
|
723 PCI_BRIDGE_CTL_MASTER_ABORT
|
724 PCI_BRIDGE_CTL_BUS_RESET
|
725 PCI_BRIDGE_CTL_FAST_BACK
|
726 PCI_BRIDGE_CTL_DISCARD
|
727 PCI_BRIDGE_CTL_SEC_DISCARD
|
728 PCI_BRIDGE_CTL_DISCARD_SERR
);
729 /* Below does not do anything as we never set this bit, put here for
731 pci_set_word(d
->w1cmask
+ PCI_BRIDGE_CONTROL
,
732 PCI_BRIDGE_CTL_DISCARD_STATUS
);
733 d
->cmask
[PCI_IO_BASE
] |= PCI_IO_RANGE_TYPE_MASK
;
734 d
->cmask
[PCI_IO_LIMIT
] |= PCI_IO_RANGE_TYPE_MASK
;
735 pci_word_test_and_set_mask(d
->cmask
+ PCI_PREF_MEMORY_BASE
,
736 PCI_PREF_RANGE_TYPE_MASK
);
737 pci_word_test_and_set_mask(d
->cmask
+ PCI_PREF_MEMORY_LIMIT
,
738 PCI_PREF_RANGE_TYPE_MASK
);
741 static void pci_init_multifunction(PCIBus
*bus
, PCIDevice
*dev
, Error
**errp
)
743 uint8_t slot
= PCI_SLOT(dev
->devfn
);
746 if (dev
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
) {
747 dev
->config
[PCI_HEADER_TYPE
] |= PCI_HEADER_TYPE_MULTI_FUNCTION
;
751 * multifunction bit is interpreted in two ways as follows.
752 * - all functions must set the bit to 1.
754 * - function 0 must set the bit, but the rest function (> 0)
755 * is allowed to leave the bit to 0.
756 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
758 * So OS (at least Linux) checks the bit of only function 0,
759 * and doesn't see the bit of function > 0.
761 * The below check allows both interpretation.
763 if (PCI_FUNC(dev
->devfn
)) {
764 PCIDevice
*f0
= bus
->devices
[PCI_DEVFN(slot
, 0)];
765 if (f0
&& !(f0
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
)) {
766 /* function 0 should set multifunction bit */
767 error_setg(errp
, "PCI: single function device can't be populated "
768 "in function %x.%x", slot
, PCI_FUNC(dev
->devfn
));
774 if (dev
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
) {
777 /* function 0 indicates single function, so function > 0 must be NULL */
778 for (func
= 1; func
< PCI_FUNC_MAX
; ++func
) {
779 if (bus
->devices
[PCI_DEVFN(slot
, func
)]) {
780 error_setg(errp
, "PCI: %x.0 indicates single function, "
781 "but %x.%x is already populated.",
788 static void pci_config_alloc(PCIDevice
*pci_dev
)
790 int config_size
= pci_config_size(pci_dev
);
792 pci_dev
->config
= g_malloc0(config_size
);
793 pci_dev
->cmask
= g_malloc0(config_size
);
794 pci_dev
->wmask
= g_malloc0(config_size
);
795 pci_dev
->w1cmask
= g_malloc0(config_size
);
796 pci_dev
->used
= g_malloc0(config_size
);
799 static void pci_config_free(PCIDevice
*pci_dev
)
801 g_free(pci_dev
->config
);
802 g_free(pci_dev
->cmask
);
803 g_free(pci_dev
->wmask
);
804 g_free(pci_dev
->w1cmask
);
805 g_free(pci_dev
->used
);
808 static void do_pci_unregister_device(PCIDevice
*pci_dev
)
810 pci_dev
->bus
->devices
[pci_dev
->devfn
] = NULL
;
811 pci_config_free(pci_dev
);
813 address_space_destroy(&pci_dev
->bus_master_as
);
816 /* -1 for devfn means auto assign */
817 static PCIDevice
*do_pci_register_device(PCIDevice
*pci_dev
, PCIBus
*bus
,
818 const char *name
, int devfn
,
821 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(pci_dev
);
822 PCIConfigReadFunc
*config_read
= pc
->config_read
;
823 PCIConfigWriteFunc
*config_write
= pc
->config_write
;
824 Error
*local_err
= NULL
;
825 AddressSpace
*dma_as
;
828 for(devfn
= bus
->devfn_min
; devfn
< ARRAY_SIZE(bus
->devices
);
829 devfn
+= PCI_FUNC_MAX
) {
830 if (!bus
->devices
[devfn
])
833 error_setg(errp
, "PCI: no slot/function available for %s, all in use",
837 } else if (bus
->devices
[devfn
]) {
838 error_setg(errp
, "PCI: slot %d function %d not available for %s,"
840 PCI_SLOT(devfn
), PCI_FUNC(devfn
), name
,
841 bus
->devices
[devfn
]->name
);
846 pci_dev
->devfn
= devfn
;
847 dma_as
= pci_device_iommu_address_space(pci_dev
);
849 memory_region_init_alias(&pci_dev
->bus_master_enable_region
,
850 OBJECT(pci_dev
), "bus master",
851 dma_as
->root
, 0, memory_region_size(dma_as
->root
));
852 memory_region_set_enabled(&pci_dev
->bus_master_enable_region
, false);
853 address_space_init(&pci_dev
->bus_master_as
, &pci_dev
->bus_master_enable_region
,
856 pstrcpy(pci_dev
->name
, sizeof(pci_dev
->name
), name
);
857 pci_dev
->irq_state
= 0;
858 pci_config_alloc(pci_dev
);
860 pci_config_set_vendor_id(pci_dev
->config
, pc
->vendor_id
);
861 pci_config_set_device_id(pci_dev
->config
, pc
->device_id
);
862 pci_config_set_revision(pci_dev
->config
, pc
->revision
);
863 pci_config_set_class(pci_dev
->config
, pc
->class_id
);
865 if (!pc
->is_bridge
) {
866 if (pc
->subsystem_vendor_id
|| pc
->subsystem_id
) {
867 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_VENDOR_ID
,
868 pc
->subsystem_vendor_id
);
869 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_ID
,
872 pci_set_default_subsystem_id(pci_dev
);
875 /* subsystem_vendor_id/subsystem_id are only for header type 0 */
876 assert(!pc
->subsystem_vendor_id
);
877 assert(!pc
->subsystem_id
);
879 pci_init_cmask(pci_dev
);
880 pci_init_wmask(pci_dev
);
881 pci_init_w1cmask(pci_dev
);
883 pci_init_mask_bridge(pci_dev
);
885 pci_init_multifunction(bus
, pci_dev
, &local_err
);
887 error_propagate(errp
, local_err
);
888 do_pci_unregister_device(pci_dev
);
893 config_read
= pci_default_read_config
;
895 config_write
= pci_default_write_config
;
896 pci_dev
->config_read
= config_read
;
897 pci_dev
->config_write
= config_write
;
898 bus
->devices
[devfn
] = pci_dev
;
899 pci_dev
->version_id
= 2; /* Current pci device vmstate version */
903 static void pci_unregister_io_regions(PCIDevice
*pci_dev
)
908 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
909 r
= &pci_dev
->io_regions
[i
];
910 if (!r
->size
|| r
->addr
== PCI_BAR_UNMAPPED
)
912 memory_region_del_subregion(r
->address_space
, r
->memory
);
915 pci_unregister_vga(pci_dev
);
918 static void pci_qdev_unrealize(DeviceState
*dev
, Error
**errp
)
920 PCIDevice
*pci_dev
= PCI_DEVICE(dev
);
921 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(pci_dev
);
923 pci_unregister_io_regions(pci_dev
);
924 pci_del_option_rom(pci_dev
);
930 do_pci_unregister_device(pci_dev
);
933 void pci_register_bar(PCIDevice
*pci_dev
, int region_num
,
934 uint8_t type
, MemoryRegion
*memory
)
939 pcibus_t size
= memory_region_size(memory
);
941 assert(region_num
>= 0);
942 assert(region_num
< PCI_NUM_REGIONS
);
943 if (size
& (size
-1)) {
944 fprintf(stderr
, "ERROR: PCI region size must be pow2 "
945 "type=0x%x, size=0x%"FMT_PCIBUS
"\n", type
, size
);
949 r
= &pci_dev
->io_regions
[region_num
];
950 r
->addr
= PCI_BAR_UNMAPPED
;
956 addr
= pci_bar(pci_dev
, region_num
);
957 if (region_num
== PCI_ROM_SLOT
) {
958 /* ROM enable bit is writable */
959 wmask
|= PCI_ROM_ADDRESS_ENABLE
;
961 pci_set_long(pci_dev
->config
+ addr
, type
);
962 if (!(r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) &&
963 r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
964 pci_set_quad(pci_dev
->wmask
+ addr
, wmask
);
965 pci_set_quad(pci_dev
->cmask
+ addr
, ~0ULL);
967 pci_set_long(pci_dev
->wmask
+ addr
, wmask
& 0xffffffff);
968 pci_set_long(pci_dev
->cmask
+ addr
, 0xffffffff);
970 pci_dev
->io_regions
[region_num
].memory
= memory
;
971 pci_dev
->io_regions
[region_num
].address_space
972 = type
& PCI_BASE_ADDRESS_SPACE_IO
973 ? pci_dev
->bus
->address_space_io
974 : pci_dev
->bus
->address_space_mem
;
977 static void pci_update_vga(PCIDevice
*pci_dev
)
981 if (!pci_dev
->has_vga
) {
985 cmd
= pci_get_word(pci_dev
->config
+ PCI_COMMAND
);
987 memory_region_set_enabled(pci_dev
->vga_regions
[QEMU_PCI_VGA_MEM
],
988 cmd
& PCI_COMMAND_MEMORY
);
989 memory_region_set_enabled(pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_LO
],
990 cmd
& PCI_COMMAND_IO
);
991 memory_region_set_enabled(pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_HI
],
992 cmd
& PCI_COMMAND_IO
);
995 void pci_register_vga(PCIDevice
*pci_dev
, MemoryRegion
*mem
,
996 MemoryRegion
*io_lo
, MemoryRegion
*io_hi
)
998 assert(!pci_dev
->has_vga
);
1000 assert(memory_region_size(mem
) == QEMU_PCI_VGA_MEM_SIZE
);
1001 pci_dev
->vga_regions
[QEMU_PCI_VGA_MEM
] = mem
;
1002 memory_region_add_subregion_overlap(pci_dev
->bus
->address_space_mem
,
1003 QEMU_PCI_VGA_MEM_BASE
, mem
, 1);
1005 assert(memory_region_size(io_lo
) == QEMU_PCI_VGA_IO_LO_SIZE
);
1006 pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_LO
] = io_lo
;
1007 memory_region_add_subregion_overlap(pci_dev
->bus
->address_space_io
,
1008 QEMU_PCI_VGA_IO_LO_BASE
, io_lo
, 1);
1010 assert(memory_region_size(io_hi
) == QEMU_PCI_VGA_IO_HI_SIZE
);
1011 pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_HI
] = io_hi
;
1012 memory_region_add_subregion_overlap(pci_dev
->bus
->address_space_io
,
1013 QEMU_PCI_VGA_IO_HI_BASE
, io_hi
, 1);
1014 pci_dev
->has_vga
= true;
1016 pci_update_vga(pci_dev
);
1019 void pci_unregister_vga(PCIDevice
*pci_dev
)
1021 if (!pci_dev
->has_vga
) {
1025 memory_region_del_subregion(pci_dev
->bus
->address_space_mem
,
1026 pci_dev
->vga_regions
[QEMU_PCI_VGA_MEM
]);
1027 memory_region_del_subregion(pci_dev
->bus
->address_space_io
,
1028 pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_LO
]);
1029 memory_region_del_subregion(pci_dev
->bus
->address_space_io
,
1030 pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_HI
]);
1031 pci_dev
->has_vga
= false;
1034 pcibus_t
pci_get_bar_addr(PCIDevice
*pci_dev
, int region_num
)
1036 return pci_dev
->io_regions
[region_num
].addr
;
1039 static pcibus_t
pci_bar_address(PCIDevice
*d
,
1040 int reg
, uint8_t type
, pcibus_t size
)
1042 pcibus_t new_addr
, last_addr
;
1043 int bar
= pci_bar(d
, reg
);
1044 uint16_t cmd
= pci_get_word(d
->config
+ PCI_COMMAND
);
1046 if (type
& PCI_BASE_ADDRESS_SPACE_IO
) {
1047 if (!(cmd
& PCI_COMMAND_IO
)) {
1048 return PCI_BAR_UNMAPPED
;
1050 new_addr
= pci_get_long(d
->config
+ bar
) & ~(size
- 1);
1051 last_addr
= new_addr
+ size
- 1;
1052 /* Check if 32 bit BAR wraps around explicitly.
1053 * TODO: make priorities correct and remove this work around.
1055 if (last_addr
<= new_addr
|| new_addr
== 0 || last_addr
>= UINT32_MAX
) {
1056 return PCI_BAR_UNMAPPED
;
1061 if (!(cmd
& PCI_COMMAND_MEMORY
)) {
1062 return PCI_BAR_UNMAPPED
;
1064 if (type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
1065 new_addr
= pci_get_quad(d
->config
+ bar
);
1067 new_addr
= pci_get_long(d
->config
+ bar
);
1069 /* the ROM slot has a specific enable bit */
1070 if (reg
== PCI_ROM_SLOT
&& !(new_addr
& PCI_ROM_ADDRESS_ENABLE
)) {
1071 return PCI_BAR_UNMAPPED
;
1073 new_addr
&= ~(size
- 1);
1074 last_addr
= new_addr
+ size
- 1;
1075 /* NOTE: we do not support wrapping */
1076 /* XXX: as we cannot support really dynamic
1077 mappings, we handle specific values as invalid
1079 if (last_addr
<= new_addr
|| new_addr
== 0 ||
1080 last_addr
== PCI_BAR_UNMAPPED
) {
1081 return PCI_BAR_UNMAPPED
;
1084 /* Now pcibus_t is 64bit.
1085 * Check if 32 bit BAR wraps around explicitly.
1086 * Without this, PC ide doesn't work well.
1087 * TODO: remove this work around.
1089 if (!(type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) && last_addr
>= UINT32_MAX
) {
1090 return PCI_BAR_UNMAPPED
;
1094 * OS is allowed to set BAR beyond its addressable
1095 * bits. For example, 32 bit OS can set 64bit bar
1096 * to >4G. Check it. TODO: we might need to support
1097 * it in the future for e.g. PAE.
1099 if (last_addr
>= HWADDR_MAX
) {
1100 return PCI_BAR_UNMAPPED
;
1106 static void pci_update_mappings(PCIDevice
*d
)
1112 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1113 r
= &d
->io_regions
[i
];
1115 /* this region isn't registered */
1119 new_addr
= pci_bar_address(d
, i
, r
->type
, r
->size
);
1121 /* This bar isn't changed */
1122 if (new_addr
== r
->addr
)
1125 /* now do the real mapping */
1126 if (r
->addr
!= PCI_BAR_UNMAPPED
) {
1127 trace_pci_update_mappings_del(d
, pci_bus_num(d
->bus
),
1130 i
, r
->addr
, r
->size
);
1131 memory_region_del_subregion(r
->address_space
, r
->memory
);
1134 if (r
->addr
!= PCI_BAR_UNMAPPED
) {
1135 trace_pci_update_mappings_add(d
, pci_bus_num(d
->bus
),
1138 i
, r
->addr
, r
->size
);
1139 memory_region_add_subregion_overlap(r
->address_space
,
1140 r
->addr
, r
->memory
, 1);
1147 static inline int pci_irq_disabled(PCIDevice
*d
)
1149 return pci_get_word(d
->config
+ PCI_COMMAND
) & PCI_COMMAND_INTX_DISABLE
;
1152 /* Called after interrupt disabled field update in config space,
1153 * assert/deassert interrupts if necessary.
1154 * Gets original interrupt disable bit value (before update). */
1155 static void pci_update_irq_disabled(PCIDevice
*d
, int was_irq_disabled
)
1157 int i
, disabled
= pci_irq_disabled(d
);
1158 if (disabled
== was_irq_disabled
)
1160 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
1161 int state
= pci_irq_state(d
, i
);
1162 pci_change_irq_level(d
, i
, disabled
? -state
: state
);
1166 uint32_t pci_default_read_config(PCIDevice
*d
,
1167 uint32_t address
, int len
)
1171 memcpy(&val
, d
->config
+ address
, len
);
1172 return le32_to_cpu(val
);
1175 void pci_default_write_config(PCIDevice
*d
, uint32_t addr
, uint32_t val_in
, int l
)
1177 int i
, was_irq_disabled
= pci_irq_disabled(d
);
1178 uint32_t val
= val_in
;
1180 for (i
= 0; i
< l
; val
>>= 8, ++i
) {
1181 uint8_t wmask
= d
->wmask
[addr
+ i
];
1182 uint8_t w1cmask
= d
->w1cmask
[addr
+ i
];
1183 assert(!(wmask
& w1cmask
));
1184 d
->config
[addr
+ i
] = (d
->config
[addr
+ i
] & ~wmask
) | (val
& wmask
);
1185 d
->config
[addr
+ i
] &= ~(val
& w1cmask
); /* W1C: Write 1 to Clear */
1187 if (ranges_overlap(addr
, l
, PCI_BASE_ADDRESS_0
, 24) ||
1188 ranges_overlap(addr
, l
, PCI_ROM_ADDRESS
, 4) ||
1189 ranges_overlap(addr
, l
, PCI_ROM_ADDRESS1
, 4) ||
1190 range_covers_byte(addr
, l
, PCI_COMMAND
))
1191 pci_update_mappings(d
);
1193 if (range_covers_byte(addr
, l
, PCI_COMMAND
)) {
1194 pci_update_irq_disabled(d
, was_irq_disabled
);
1195 memory_region_set_enabled(&d
->bus_master_enable_region
,
1196 pci_get_word(d
->config
+ PCI_COMMAND
)
1197 & PCI_COMMAND_MASTER
);
1200 msi_write_config(d
, addr
, val_in
, l
);
1201 msix_write_config(d
, addr
, val_in
, l
);
1204 /***********************************************************/
1205 /* generic PCI irq support */
1207 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1208 static void pci_irq_handler(void *opaque
, int irq_num
, int level
)
1210 PCIDevice
*pci_dev
= opaque
;
1213 change
= level
- pci_irq_state(pci_dev
, irq_num
);
1217 pci_set_irq_state(pci_dev
, irq_num
, level
);
1218 pci_update_irq_status(pci_dev
);
1219 if (pci_irq_disabled(pci_dev
))
1221 pci_change_irq_level(pci_dev
, irq_num
, change
);
1224 static inline int pci_intx(PCIDevice
*pci_dev
)
1226 return pci_get_byte(pci_dev
->config
+ PCI_INTERRUPT_PIN
) - 1;
1229 qemu_irq
pci_allocate_irq(PCIDevice
*pci_dev
)
1231 int intx
= pci_intx(pci_dev
);
1233 return qemu_allocate_irq(pci_irq_handler
, pci_dev
, intx
);
1236 void pci_set_irq(PCIDevice
*pci_dev
, int level
)
1238 int intx
= pci_intx(pci_dev
);
1239 pci_irq_handler(pci_dev
, intx
, level
);
1242 /* Special hooks used by device assignment */
1243 void pci_bus_set_route_irq_fn(PCIBus
*bus
, pci_route_irq_fn route_intx_to_irq
)
1245 assert(pci_bus_is_root(bus
));
1246 bus
->route_intx_to_irq
= route_intx_to_irq
;
1249 PCIINTxRoute
pci_device_route_intx_to_irq(PCIDevice
*dev
, int pin
)
1255 pin
= bus
->map_irq(dev
, pin
);
1256 dev
= bus
->parent_dev
;
1259 if (!bus
->route_intx_to_irq
) {
1260 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)",
1261 object_get_typename(OBJECT(bus
->qbus
.parent
)));
1262 return (PCIINTxRoute
) { PCI_INTX_DISABLED
, -1 };
1265 return bus
->route_intx_to_irq(bus
->irq_opaque
, pin
);
1268 bool pci_intx_route_changed(PCIINTxRoute
*old
, PCIINTxRoute
*new)
1270 return old
->mode
!= new->mode
|| old
->irq
!= new->irq
;
1273 void pci_bus_fire_intx_routing_notifier(PCIBus
*bus
)
1279 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); ++i
) {
1280 dev
= bus
->devices
[i
];
1281 if (dev
&& dev
->intx_routing_notifier
) {
1282 dev
->intx_routing_notifier(dev
);
1286 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
1287 pci_bus_fire_intx_routing_notifier(sec
);
1291 void pci_device_set_intx_routing_notifier(PCIDevice
*dev
,
1292 PCIINTxRoutingNotifier notifier
)
1294 dev
->intx_routing_notifier
= notifier
;
1298 * PCI-to-PCI bridge specification
1299 * 9.1: Interrupt routing. Table 9-1
1301 * the PCI Express Base Specification, Revision 2.1
1302 * 2.2.8.1: INTx interrutp signaling - Rules
1303 * the Implementation Note
1307 * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD
1308 * 0-origin unlike PCI interrupt pin register.
1310 int pci_swizzle_map_irq_fn(PCIDevice
*pci_dev
, int pin
)
1312 return (pin
+ PCI_SLOT(pci_dev
->devfn
)) % PCI_NUM_PINS
;
1315 /***********************************************************/
1316 /* monitor info on PCI */
1321 const char *fw_name
;
1322 uint16_t fw_ign_bits
;
1325 static const pci_class_desc pci_class_descriptions
[] =
1327 { 0x0001, "VGA controller", "display"},
1328 { 0x0100, "SCSI controller", "scsi"},
1329 { 0x0101, "IDE controller", "ide"},
1330 { 0x0102, "Floppy controller", "fdc"},
1331 { 0x0103, "IPI controller", "ipi"},
1332 { 0x0104, "RAID controller", "raid"},
1333 { 0x0106, "SATA controller"},
1334 { 0x0107, "SAS controller"},
1335 { 0x0180, "Storage controller"},
1336 { 0x0200, "Ethernet controller", "ethernet"},
1337 { 0x0201, "Token Ring controller", "token-ring"},
1338 { 0x0202, "FDDI controller", "fddi"},
1339 { 0x0203, "ATM controller", "atm"},
1340 { 0x0280, "Network controller"},
1341 { 0x0300, "VGA controller", "display", 0x00ff},
1342 { 0x0301, "XGA controller"},
1343 { 0x0302, "3D controller"},
1344 { 0x0380, "Display controller"},
1345 { 0x0400, "Video controller", "video"},
1346 { 0x0401, "Audio controller", "sound"},
1348 { 0x0403, "Audio controller", "sound"},
1349 { 0x0480, "Multimedia controller"},
1350 { 0x0500, "RAM controller", "memory"},
1351 { 0x0501, "Flash controller", "flash"},
1352 { 0x0580, "Memory controller"},
1353 { 0x0600, "Host bridge", "host"},
1354 { 0x0601, "ISA bridge", "isa"},
1355 { 0x0602, "EISA bridge", "eisa"},
1356 { 0x0603, "MC bridge", "mca"},
1357 { 0x0604, "PCI bridge", "pci-bridge"},
1358 { 0x0605, "PCMCIA bridge", "pcmcia"},
1359 { 0x0606, "NUBUS bridge", "nubus"},
1360 { 0x0607, "CARDBUS bridge", "cardbus"},
1361 { 0x0608, "RACEWAY bridge"},
1362 { 0x0680, "Bridge"},
1363 { 0x0700, "Serial port", "serial"},
1364 { 0x0701, "Parallel port", "parallel"},
1365 { 0x0800, "Interrupt controller", "interrupt-controller"},
1366 { 0x0801, "DMA controller", "dma-controller"},
1367 { 0x0802, "Timer", "timer"},
1368 { 0x0803, "RTC", "rtc"},
1369 { 0x0900, "Keyboard", "keyboard"},
1370 { 0x0901, "Pen", "pen"},
1371 { 0x0902, "Mouse", "mouse"},
1372 { 0x0A00, "Dock station", "dock", 0x00ff},
1373 { 0x0B00, "i386 cpu", "cpu", 0x00ff},
1374 { 0x0c00, "Fireware contorller", "fireware"},
1375 { 0x0c01, "Access bus controller", "access-bus"},
1376 { 0x0c02, "SSA controller", "ssa"},
1377 { 0x0c03, "USB controller", "usb"},
1378 { 0x0c04, "Fibre channel controller", "fibre-channel"},
1383 static void pci_for_each_device_under_bus(PCIBus
*bus
,
1384 void (*fn
)(PCIBus
*b
, PCIDevice
*d
,
1391 for(devfn
= 0; devfn
< ARRAY_SIZE(bus
->devices
); devfn
++) {
1392 d
= bus
->devices
[devfn
];
1399 void pci_for_each_device(PCIBus
*bus
, int bus_num
,
1400 void (*fn
)(PCIBus
*b
, PCIDevice
*d
, void *opaque
),
1403 bus
= pci_find_bus_nr(bus
, bus_num
);
1406 pci_for_each_device_under_bus(bus
, fn
, opaque
);
1410 static const pci_class_desc
*get_class_desc(int class)
1412 const pci_class_desc
*desc
;
1414 desc
= pci_class_descriptions
;
1415 while (desc
->desc
&& class != desc
->class) {
1422 static PciDeviceInfoList
*qmp_query_pci_devices(PCIBus
*bus
, int bus_num
);
1424 static PciMemoryRegionList
*qmp_query_pci_regions(const PCIDevice
*dev
)
1426 PciMemoryRegionList
*head
= NULL
, *cur_item
= NULL
;
1429 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1430 const PCIIORegion
*r
= &dev
->io_regions
[i
];
1431 PciMemoryRegionList
*region
;
1437 region
= g_malloc0(sizeof(*region
));
1438 region
->value
= g_malloc0(sizeof(*region
->value
));
1440 if (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) {
1441 region
->value
->type
= g_strdup("io");
1443 region
->value
->type
= g_strdup("memory");
1444 region
->value
->has_prefetch
= true;
1445 region
->value
->prefetch
= !!(r
->type
& PCI_BASE_ADDRESS_MEM_PREFETCH
);
1446 region
->value
->has_mem_type_64
= true;
1447 region
->value
->mem_type_64
= !!(r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
);
1450 region
->value
->bar
= i
;
1451 region
->value
->address
= r
->addr
;
1452 region
->value
->size
= r
->size
;
1454 /* XXX: waiting for the qapi to support GSList */
1456 head
= cur_item
= region
;
1458 cur_item
->next
= region
;
1466 static PciBridgeInfo
*qmp_query_pci_bridge(PCIDevice
*dev
, PCIBus
*bus
,
1469 PciBridgeInfo
*info
;
1470 PciMemoryRange
*range
;
1472 info
= g_new0(PciBridgeInfo
, 1);
1474 info
->bus
= g_new0(PciBusInfo
, 1);
1475 info
->bus
->number
= dev
->config
[PCI_PRIMARY_BUS
];
1476 info
->bus
->secondary
= dev
->config
[PCI_SECONDARY_BUS
];
1477 info
->bus
->subordinate
= dev
->config
[PCI_SUBORDINATE_BUS
];
1479 range
= info
->bus
->io_range
= g_new0(PciMemoryRange
, 1);
1480 range
->base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_IO
);
1481 range
->limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_IO
);
1483 range
= info
->bus
->memory_range
= g_new0(PciMemoryRange
, 1);
1484 range
->base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
1485 range
->limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
1487 range
= info
->bus
->prefetchable_range
= g_new0(PciMemoryRange
, 1);
1488 range
->base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
1489 range
->limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
1491 if (dev
->config
[PCI_SECONDARY_BUS
] != 0) {
1492 PCIBus
*child_bus
= pci_find_bus_nr(bus
, dev
->config
[PCI_SECONDARY_BUS
]);
1494 info
->has_devices
= true;
1495 info
->devices
= qmp_query_pci_devices(child_bus
, dev
->config
[PCI_SECONDARY_BUS
]);
1502 static PciDeviceInfo
*qmp_query_pci_device(PCIDevice
*dev
, PCIBus
*bus
,
1505 const pci_class_desc
*desc
;
1506 PciDeviceInfo
*info
;
1510 info
= g_new0(PciDeviceInfo
, 1);
1511 info
->bus
= bus_num
;
1512 info
->slot
= PCI_SLOT(dev
->devfn
);
1513 info
->function
= PCI_FUNC(dev
->devfn
);
1515 info
->class_info
= g_new0(PciDeviceClass
, 1);
1516 class = pci_get_word(dev
->config
+ PCI_CLASS_DEVICE
);
1517 info
->class_info
->q_class
= class;
1518 desc
= get_class_desc(class);
1520 info
->class_info
->has_desc
= true;
1521 info
->class_info
->desc
= g_strdup(desc
->desc
);
1524 info
->id
= g_new0(PciDeviceId
, 1);
1525 info
->id
->vendor
= pci_get_word(dev
->config
+ PCI_VENDOR_ID
);
1526 info
->id
->device
= pci_get_word(dev
->config
+ PCI_DEVICE_ID
);
1527 info
->regions
= qmp_query_pci_regions(dev
);
1528 info
->qdev_id
= g_strdup(dev
->qdev
.id
? dev
->qdev
.id
: "");
1530 if (dev
->config
[PCI_INTERRUPT_PIN
] != 0) {
1531 info
->has_irq
= true;
1532 info
->irq
= dev
->config
[PCI_INTERRUPT_LINE
];
1535 type
= dev
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
1536 if (type
== PCI_HEADER_TYPE_BRIDGE
) {
1537 info
->has_pci_bridge
= true;
1538 info
->pci_bridge
= qmp_query_pci_bridge(dev
, bus
, bus_num
);
1544 static PciDeviceInfoList
*qmp_query_pci_devices(PCIBus
*bus
, int bus_num
)
1546 PciDeviceInfoList
*info
, *head
= NULL
, *cur_item
= NULL
;
1550 for (devfn
= 0; devfn
< ARRAY_SIZE(bus
->devices
); devfn
++) {
1551 dev
= bus
->devices
[devfn
];
1553 info
= g_malloc0(sizeof(*info
));
1554 info
->value
= qmp_query_pci_device(dev
, bus
, bus_num
);
1556 /* XXX: waiting for the qapi to support GSList */
1558 head
= cur_item
= info
;
1560 cur_item
->next
= info
;
1569 static PciInfo
*qmp_query_pci_bus(PCIBus
*bus
, int bus_num
)
1571 PciInfo
*info
= NULL
;
1573 bus
= pci_find_bus_nr(bus
, bus_num
);
1575 info
= g_malloc0(sizeof(*info
));
1576 info
->bus
= bus_num
;
1577 info
->devices
= qmp_query_pci_devices(bus
, bus_num
);
1583 PciInfoList
*qmp_query_pci(Error
**errp
)
1585 PciInfoList
*info
, *head
= NULL
, *cur_item
= NULL
;
1586 PCIHostState
*host_bridge
;
1588 QLIST_FOREACH(host_bridge
, &pci_host_bridges
, next
) {
1589 info
= g_malloc0(sizeof(*info
));
1590 info
->value
= qmp_query_pci_bus(host_bridge
->bus
, 0);
1592 /* XXX: waiting for the qapi to support GSList */
1594 head
= cur_item
= info
;
1596 cur_item
->next
= info
;
1604 static const char * const pci_nic_models
[] = {
1616 static const char * const pci_nic_names
[] = {
1628 /* Initialize a PCI NIC. */
1629 PCIDevice
*pci_nic_init_nofail(NICInfo
*nd
, PCIBus
*rootbus
,
1630 const char *default_model
,
1631 const char *default_devaddr
)
1633 const char *devaddr
= nd
->devaddr
? nd
->devaddr
: default_devaddr
;
1641 if (qemu_show_nic_models(nd
->model
, pci_nic_models
)) {
1645 i
= qemu_find_nic_model(nd
, pci_nic_models
, default_model
);
1650 bus
= pci_get_bus_devfn(&devfn
, rootbus
, devaddr
);
1652 error_report("Invalid PCI device address %s for device %s",
1653 devaddr
, pci_nic_names
[i
]);
1657 pci_dev
= pci_create(bus
, devfn
, pci_nic_names
[i
]);
1658 dev
= &pci_dev
->qdev
;
1659 qdev_set_nic_properties(dev
, nd
);
1661 object_property_set_bool(OBJECT(dev
), true, "realized", &err
);
1663 error_report_err(err
);
1664 object_unparent(OBJECT(dev
));
1671 PCIDevice
*pci_vga_init(PCIBus
*bus
)
1673 switch (vga_interface_type
) {
1675 return pci_create_simple(bus
, -1, "cirrus-vga");
1677 return pci_create_simple(bus
, -1, "qxl-vga");
1679 return pci_create_simple(bus
, -1, "VGA");
1681 return pci_create_simple(bus
, -1, "vmware-svga");
1683 default: /* Other non-PCI types. Checking for unsupported types is already
1689 /* Whether a given bus number is in range of the secondary
1690 * bus of the given bridge device. */
1691 static bool pci_secondary_bus_in_range(PCIDevice
*dev
, int bus_num
)
1693 return !(pci_get_word(dev
->config
+ PCI_BRIDGE_CONTROL
) &
1694 PCI_BRIDGE_CTL_BUS_RESET
) /* Don't walk the bus if it's reset. */ &&
1695 dev
->config
[PCI_SECONDARY_BUS
] < bus_num
&&
1696 bus_num
<= dev
->config
[PCI_SUBORDINATE_BUS
];
1699 static PCIBus
*pci_find_bus_nr(PCIBus
*bus
, int bus_num
)
1707 if (pci_bus_num(bus
) == bus_num
) {
1711 /* Consider all bus numbers in range for the host pci bridge. */
1712 if (!pci_bus_is_root(bus
) &&
1713 !pci_secondary_bus_in_range(bus
->parent_dev
, bus_num
)) {
1718 for (; bus
; bus
= sec
) {
1719 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
1720 assert(!pci_bus_is_root(sec
));
1721 if (sec
->parent_dev
->config
[PCI_SECONDARY_BUS
] == bus_num
) {
1724 if (pci_secondary_bus_in_range(sec
->parent_dev
, bus_num
)) {
1733 void pci_for_each_bus_depth_first(PCIBus
*bus
,
1734 void *(*begin
)(PCIBus
*bus
, void *parent_state
),
1735 void (*end
)(PCIBus
*bus
, void *state
),
1746 state
= begin(bus
, parent_state
);
1748 state
= parent_state
;
1751 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
1752 pci_for_each_bus_depth_first(sec
, begin
, end
, state
);
1761 PCIDevice
*pci_find_device(PCIBus
*bus
, int bus_num
, uint8_t devfn
)
1763 bus
= pci_find_bus_nr(bus
, bus_num
);
1768 return bus
->devices
[devfn
];
1771 static void pci_qdev_realize(DeviceState
*qdev
, Error
**errp
)
1773 PCIDevice
*pci_dev
= (PCIDevice
*)qdev
;
1774 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(pci_dev
);
1775 Error
*local_err
= NULL
;
1777 bool is_default_rom
;
1779 /* initialize cap_present for pci_is_express() and pci_config_size() */
1780 if (pc
->is_express
) {
1781 pci_dev
->cap_present
|= QEMU_PCI_CAP_EXPRESS
;
1784 bus
= PCI_BUS(qdev_get_parent_bus(qdev
));
1785 pci_dev
= do_pci_register_device(pci_dev
, bus
,
1786 object_get_typename(OBJECT(qdev
)),
1787 pci_dev
->devfn
, errp
);
1788 if (pci_dev
== NULL
)
1792 pc
->realize(pci_dev
, &local_err
);
1794 error_propagate(errp
, local_err
);
1795 do_pci_unregister_device(pci_dev
);
1801 is_default_rom
= false;
1802 if (pci_dev
->romfile
== NULL
&& pc
->romfile
!= NULL
) {
1803 pci_dev
->romfile
= g_strdup(pc
->romfile
);
1804 is_default_rom
= true;
1807 pci_add_option_rom(pci_dev
, is_default_rom
, &local_err
);
1809 error_propagate(errp
, local_err
);
1810 pci_qdev_unrealize(DEVICE(pci_dev
), NULL
);
1815 static void pci_default_realize(PCIDevice
*dev
, Error
**errp
)
1817 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(dev
);
1820 if (pc
->init(dev
) < 0) {
1821 error_setg(errp
, "Device initialization failed");
1827 PCIDevice
*pci_create_multifunction(PCIBus
*bus
, int devfn
, bool multifunction
,
1832 dev
= qdev_create(&bus
->qbus
, name
);
1833 qdev_prop_set_int32(dev
, "addr", devfn
);
1834 qdev_prop_set_bit(dev
, "multifunction", multifunction
);
1835 return PCI_DEVICE(dev
);
1838 PCIDevice
*pci_create_simple_multifunction(PCIBus
*bus
, int devfn
,
1842 PCIDevice
*dev
= pci_create_multifunction(bus
, devfn
, multifunction
, name
);
1843 qdev_init_nofail(&dev
->qdev
);
1847 PCIDevice
*pci_create(PCIBus
*bus
, int devfn
, const char *name
)
1849 return pci_create_multifunction(bus
, devfn
, false, name
);
1852 PCIDevice
*pci_create_simple(PCIBus
*bus
, int devfn
, const char *name
)
1854 return pci_create_simple_multifunction(bus
, devfn
, false, name
);
1857 static uint8_t pci_find_space(PCIDevice
*pdev
, uint8_t size
)
1859 int offset
= PCI_CONFIG_HEADER_SIZE
;
1861 for (i
= PCI_CONFIG_HEADER_SIZE
; i
< PCI_CONFIG_SPACE_SIZE
; ++i
) {
1864 else if (i
- offset
+ 1 == size
)
1870 static uint8_t pci_find_capability_list(PCIDevice
*pdev
, uint8_t cap_id
,
1875 if (!(pdev
->config
[PCI_STATUS
] & PCI_STATUS_CAP_LIST
))
1878 for (prev
= PCI_CAPABILITY_LIST
; (next
= pdev
->config
[prev
]);
1879 prev
= next
+ PCI_CAP_LIST_NEXT
)
1880 if (pdev
->config
[next
+ PCI_CAP_LIST_ID
] == cap_id
)
1888 static uint8_t pci_find_capability_at_offset(PCIDevice
*pdev
, uint8_t offset
)
1890 uint8_t next
, prev
, found
= 0;
1892 if (!(pdev
->used
[offset
])) {
1896 assert(pdev
->config
[PCI_STATUS
] & PCI_STATUS_CAP_LIST
);
1898 for (prev
= PCI_CAPABILITY_LIST
; (next
= pdev
->config
[prev
]);
1899 prev
= next
+ PCI_CAP_LIST_NEXT
) {
1900 if (next
<= offset
&& next
> found
) {
1907 /* Patch the PCI vendor and device ids in a PCI rom image if necessary.
1908 This is needed for an option rom which is used for more than one device. */
1909 static void pci_patch_ids(PCIDevice
*pdev
, uint8_t *ptr
, int size
)
1913 uint16_t rom_vendor_id
;
1914 uint16_t rom_device_id
;
1916 uint16_t pcir_offset
;
1919 /* Words in rom data are little endian (like in PCI configuration),
1920 so they can be read / written with pci_get_word / pci_set_word. */
1922 /* Only a valid rom will be patched. */
1923 rom_magic
= pci_get_word(ptr
);
1924 if (rom_magic
!= 0xaa55) {
1925 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic
);
1928 pcir_offset
= pci_get_word(ptr
+ 0x18);
1929 if (pcir_offset
+ 8 >= size
|| memcmp(ptr
+ pcir_offset
, "PCIR", 4)) {
1930 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset
);
1934 vendor_id
= pci_get_word(pdev
->config
+ PCI_VENDOR_ID
);
1935 device_id
= pci_get_word(pdev
->config
+ PCI_DEVICE_ID
);
1936 rom_vendor_id
= pci_get_word(ptr
+ pcir_offset
+ 4);
1937 rom_device_id
= pci_get_word(ptr
+ pcir_offset
+ 6);
1939 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev
->romfile
,
1940 vendor_id
, device_id
, rom_vendor_id
, rom_device_id
);
1944 if (vendor_id
!= rom_vendor_id
) {
1945 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */
1946 checksum
+= (uint8_t)rom_vendor_id
+ (uint8_t)(rom_vendor_id
>> 8);
1947 checksum
-= (uint8_t)vendor_id
+ (uint8_t)(vendor_id
>> 8);
1948 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr
[6], checksum
);
1950 pci_set_word(ptr
+ pcir_offset
+ 4, vendor_id
);
1953 if (device_id
!= rom_device_id
) {
1954 /* Patch device id and checksum (at offset 6 for etherboot roms). */
1955 checksum
+= (uint8_t)rom_device_id
+ (uint8_t)(rom_device_id
>> 8);
1956 checksum
-= (uint8_t)device_id
+ (uint8_t)(device_id
>> 8);
1957 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr
[6], checksum
);
1959 pci_set_word(ptr
+ pcir_offset
+ 6, device_id
);
1963 /* Add an option rom for the device */
1964 static void pci_add_option_rom(PCIDevice
*pdev
, bool is_default_rom
,
1971 const VMStateDescription
*vmsd
;
1975 if (strlen(pdev
->romfile
) == 0)
1978 if (!pdev
->rom_bar
) {
1980 * Load rom via fw_cfg instead of creating a rom bar,
1981 * for 0.11 compatibility.
1983 int class = pci_get_word(pdev
->config
+ PCI_CLASS_DEVICE
);
1986 * Hot-plugged devices can't use the option ROM
1987 * if the rom bar is disabled.
1989 if (DEVICE(pdev
)->hotplugged
) {
1990 error_setg(errp
, "Hot-plugged device without ROM bar"
1991 " can't have an option ROM");
1995 if (class == 0x0300) {
1996 rom_add_vga(pdev
->romfile
);
1998 rom_add_option(pdev
->romfile
, -1);
2003 path
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, pdev
->romfile
);
2005 path
= g_strdup(pdev
->romfile
);
2008 size
= get_image_size(path
);
2010 error_setg(errp
, "failed to find romfile \"%s\"", pdev
->romfile
);
2013 } else if (size
== 0) {
2014 error_setg(errp
, "romfile \"%s\" is empty", pdev
->romfile
);
2018 if (size
& (size
- 1)) {
2019 size
= 1 << qemu_fls(size
);
2022 vmsd
= qdev_get_vmsd(DEVICE(pdev
));
2025 snprintf(name
, sizeof(name
), "%s.rom", vmsd
->name
);
2027 snprintf(name
, sizeof(name
), "%s.rom", object_get_typename(OBJECT(pdev
)));
2029 pdev
->has_rom
= true;
2030 memory_region_init_ram(&pdev
->rom
, OBJECT(pdev
), name
, size
, &error_abort
);
2031 vmstate_register_ram(&pdev
->rom
, &pdev
->qdev
);
2032 ptr
= memory_region_get_ram_ptr(&pdev
->rom
);
2033 load_image(path
, ptr
);
2036 if (is_default_rom
) {
2037 /* Only the default rom images will be patched (if needed). */
2038 pci_patch_ids(pdev
, ptr
, size
);
2041 pci_register_bar(pdev
, PCI_ROM_SLOT
, 0, &pdev
->rom
);
2044 static void pci_del_option_rom(PCIDevice
*pdev
)
2049 vmstate_unregister_ram(&pdev
->rom
, &pdev
->qdev
);
2050 pdev
->has_rom
= false;
2055 * Reserve space and add capability to the linked list in pci config space
2058 * Find and reserve space and add capability to the linked list
2059 * in pci config space */
2060 int pci_add_capability(PCIDevice
*pdev
, uint8_t cap_id
,
2061 uint8_t offset
, uint8_t size
)
2064 Error
*local_err
= NULL
;
2066 ret
= pci_add_capability2(pdev
, cap_id
, offset
, size
, &local_err
);
2069 error_report_err(local_err
);
2071 /* success implies a positive offset in config space */
2077 int pci_add_capability2(PCIDevice
*pdev
, uint8_t cap_id
,
2078 uint8_t offset
, uint8_t size
,
2082 int i
, overlapping_cap
;
2085 offset
= pci_find_space(pdev
, size
);
2087 error_setg(errp
, "out of PCI config space");
2091 /* Verify that capabilities don't overlap. Note: device assignment
2092 * depends on this check to verify that the device is not broken.
2093 * Should never trigger for emulated devices, but it's helpful
2094 * for debugging these. */
2095 for (i
= offset
; i
< offset
+ size
; i
++) {
2096 overlapping_cap
= pci_find_capability_at_offset(pdev
, i
);
2097 if (overlapping_cap
) {
2098 error_setg(errp
, "%s:%02x:%02x.%x "
2099 "Attempt to add PCI capability %x at offset "
2100 "%x overlaps existing capability %x at offset %x",
2101 pci_root_bus_path(pdev
), pci_bus_num(pdev
->bus
),
2102 PCI_SLOT(pdev
->devfn
), PCI_FUNC(pdev
->devfn
),
2103 cap_id
, offset
, overlapping_cap
, i
);
2109 config
= pdev
->config
+ offset
;
2110 config
[PCI_CAP_LIST_ID
] = cap_id
;
2111 config
[PCI_CAP_LIST_NEXT
] = pdev
->config
[PCI_CAPABILITY_LIST
];
2112 pdev
->config
[PCI_CAPABILITY_LIST
] = offset
;
2113 pdev
->config
[PCI_STATUS
] |= PCI_STATUS_CAP_LIST
;
2114 memset(pdev
->used
+ offset
, 0xFF, QEMU_ALIGN_UP(size
, 4));
2115 /* Make capability read-only by default */
2116 memset(pdev
->wmask
+ offset
, 0, size
);
2117 /* Check capability by default */
2118 memset(pdev
->cmask
+ offset
, 0xFF, size
);
2122 /* Unlink capability from the pci config space. */
2123 void pci_del_capability(PCIDevice
*pdev
, uint8_t cap_id
, uint8_t size
)
2125 uint8_t prev
, offset
= pci_find_capability_list(pdev
, cap_id
, &prev
);
2128 pdev
->config
[prev
] = pdev
->config
[offset
+ PCI_CAP_LIST_NEXT
];
2129 /* Make capability writable again */
2130 memset(pdev
->wmask
+ offset
, 0xff, size
);
2131 memset(pdev
->w1cmask
+ offset
, 0, size
);
2132 /* Clear cmask as device-specific registers can't be checked */
2133 memset(pdev
->cmask
+ offset
, 0, size
);
2134 memset(pdev
->used
+ offset
, 0, QEMU_ALIGN_UP(size
, 4));
2136 if (!pdev
->config
[PCI_CAPABILITY_LIST
])
2137 pdev
->config
[PCI_STATUS
] &= ~PCI_STATUS_CAP_LIST
;
2140 uint8_t pci_find_capability(PCIDevice
*pdev
, uint8_t cap_id
)
2142 return pci_find_capability_list(pdev
, cap_id
, NULL
);
2145 static void pcibus_dev_print(Monitor
*mon
, DeviceState
*dev
, int indent
)
2147 PCIDevice
*d
= (PCIDevice
*)dev
;
2148 const pci_class_desc
*desc
;
2153 class = pci_get_word(d
->config
+ PCI_CLASS_DEVICE
);
2154 desc
= pci_class_descriptions
;
2155 while (desc
->desc
&& class != desc
->class)
2158 snprintf(ctxt
, sizeof(ctxt
), "%s", desc
->desc
);
2160 snprintf(ctxt
, sizeof(ctxt
), "Class %04x", class);
2163 monitor_printf(mon
, "%*sclass %s, addr %02x:%02x.%x, "
2164 "pci id %04x:%04x (sub %04x:%04x)\n",
2165 indent
, "", ctxt
, pci_bus_num(d
->bus
),
2166 PCI_SLOT(d
->devfn
), PCI_FUNC(d
->devfn
),
2167 pci_get_word(d
->config
+ PCI_VENDOR_ID
),
2168 pci_get_word(d
->config
+ PCI_DEVICE_ID
),
2169 pci_get_word(d
->config
+ PCI_SUBSYSTEM_VENDOR_ID
),
2170 pci_get_word(d
->config
+ PCI_SUBSYSTEM_ID
));
2171 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
2172 r
= &d
->io_regions
[i
];
2175 monitor_printf(mon
, "%*sbar %d: %s at 0x%"FMT_PCIBUS
2176 " [0x%"FMT_PCIBUS
"]\n",
2178 i
, r
->type
& PCI_BASE_ADDRESS_SPACE_IO
? "i/o" : "mem",
2179 r
->addr
, r
->addr
+ r
->size
- 1);
2183 static char *pci_dev_fw_name(DeviceState
*dev
, char *buf
, int len
)
2185 PCIDevice
*d
= (PCIDevice
*)dev
;
2186 const char *name
= NULL
;
2187 const pci_class_desc
*desc
= pci_class_descriptions
;
2188 int class = pci_get_word(d
->config
+ PCI_CLASS_DEVICE
);
2190 while (desc
->desc
&&
2191 (class & ~desc
->fw_ign_bits
) !=
2192 (desc
->class & ~desc
->fw_ign_bits
)) {
2197 name
= desc
->fw_name
;
2201 pstrcpy(buf
, len
, name
);
2203 snprintf(buf
, len
, "pci%04x,%04x",
2204 pci_get_word(d
->config
+ PCI_VENDOR_ID
),
2205 pci_get_word(d
->config
+ PCI_DEVICE_ID
));
2211 static char *pcibus_get_fw_dev_path(DeviceState
*dev
)
2213 PCIDevice
*d
= (PCIDevice
*)dev
;
2214 char path
[50], name
[33];
2217 off
= snprintf(path
, sizeof(path
), "%s@%x",
2218 pci_dev_fw_name(dev
, name
, sizeof name
),
2219 PCI_SLOT(d
->devfn
));
2220 if (PCI_FUNC(d
->devfn
))
2221 snprintf(path
+ off
, sizeof(path
) + off
, ",%x", PCI_FUNC(d
->devfn
));
2222 return g_strdup(path
);
2225 static char *pcibus_get_dev_path(DeviceState
*dev
)
2227 PCIDevice
*d
= container_of(dev
, PCIDevice
, qdev
);
2230 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function.
2231 * 00 is added here to make this format compatible with
2232 * domain:Bus:Slot.Func for systems without nested PCI bridges.
2233 * Slot.Function list specifies the slot and function numbers for all
2234 * devices on the path from root to the specific device. */
2235 const char *root_bus_path
;
2237 char slot
[] = ":SS.F";
2238 int slot_len
= sizeof slot
- 1 /* For '\0' */;
2243 root_bus_path
= pci_root_bus_path(d
);
2244 root_bus_len
= strlen(root_bus_path
);
2246 /* Calculate # of slots on path between device and root. */;
2248 for (t
= d
; t
; t
= t
->bus
->parent_dev
) {
2252 path_len
= root_bus_len
+ slot_len
* slot_depth
;
2254 /* Allocate memory, fill in the terminating null byte. */
2255 path
= g_malloc(path_len
+ 1 /* For '\0' */);
2256 path
[path_len
] = '\0';
2258 memcpy(path
, root_bus_path
, root_bus_len
);
2260 /* Fill in slot numbers. We walk up from device to root, so need to print
2261 * them in the reverse order, last to first. */
2262 p
= path
+ path_len
;
2263 for (t
= d
; t
; t
= t
->bus
->parent_dev
) {
2265 s
= snprintf(slot
, sizeof slot
, ":%02x.%x",
2266 PCI_SLOT(t
->devfn
), PCI_FUNC(t
->devfn
));
2267 assert(s
== slot_len
);
2268 memcpy(p
, slot
, slot_len
);
2274 static int pci_qdev_find_recursive(PCIBus
*bus
,
2275 const char *id
, PCIDevice
**pdev
)
2277 DeviceState
*qdev
= qdev_find_recursive(&bus
->qbus
, id
);
2282 /* roughly check if given qdev is pci device */
2283 if (object_dynamic_cast(OBJECT(qdev
), TYPE_PCI_DEVICE
)) {
2284 *pdev
= PCI_DEVICE(qdev
);
2290 int pci_qdev_find_device(const char *id
, PCIDevice
**pdev
)
2292 PCIHostState
*host_bridge
;
2295 QLIST_FOREACH(host_bridge
, &pci_host_bridges
, next
) {
2296 int tmp
= pci_qdev_find_recursive(host_bridge
->bus
, id
, pdev
);
2301 if (tmp
!= -ENODEV
) {
2309 MemoryRegion
*pci_address_space(PCIDevice
*dev
)
2311 return dev
->bus
->address_space_mem
;
2314 MemoryRegion
*pci_address_space_io(PCIDevice
*dev
)
2316 return dev
->bus
->address_space_io
;
2319 static void pci_device_class_init(ObjectClass
*klass
, void *data
)
2321 DeviceClass
*k
= DEVICE_CLASS(klass
);
2322 PCIDeviceClass
*pc
= PCI_DEVICE_CLASS(klass
);
2324 k
->realize
= pci_qdev_realize
;
2325 k
->unrealize
= pci_qdev_unrealize
;
2326 k
->bus_type
= TYPE_PCI_BUS
;
2327 k
->props
= pci_props
;
2328 pc
->realize
= pci_default_realize
;
2331 AddressSpace
*pci_device_iommu_address_space(PCIDevice
*dev
)
2333 PCIBus
*bus
= PCI_BUS(dev
->bus
);
2335 if (bus
->iommu_fn
) {
2336 return bus
->iommu_fn(bus
, bus
->iommu_opaque
, dev
->devfn
);
2339 if (bus
->parent_dev
) {
2340 /** We are ignoring the bus master DMA bit of the bridge
2341 * as it would complicate things such as VFIO for no good reason */
2342 return pci_device_iommu_address_space(bus
->parent_dev
);
2345 return &address_space_memory
;
2348 void pci_setup_iommu(PCIBus
*bus
, PCIIOMMUFunc fn
, void *opaque
)
2351 bus
->iommu_opaque
= opaque
;
2354 static void pci_dev_get_w64(PCIBus
*b
, PCIDevice
*dev
, void *opaque
)
2356 Range
*range
= opaque
;
2357 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(dev
);
2358 uint16_t cmd
= pci_get_word(dev
->config
+ PCI_COMMAND
);
2361 if (!(cmd
& PCI_COMMAND_MEMORY
)) {
2365 if (pc
->is_bridge
) {
2366 pcibus_t base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
2367 pcibus_t limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
2369 base
= MAX(base
, 0x1ULL
<< 32);
2371 if (limit
>= base
) {
2373 pref_range
.begin
= base
;
2374 pref_range
.end
= limit
+ 1;
2375 range_extend(range
, &pref_range
);
2378 for (i
= 0; i
< PCI_NUM_REGIONS
; ++i
) {
2379 PCIIORegion
*r
= &dev
->io_regions
[i
];
2383 (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) ||
2384 !(r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
)) {
2387 region_range
.begin
= pci_bar_address(dev
, i
, r
->type
, r
->size
);
2388 region_range
.end
= region_range
.begin
+ r
->size
;
2390 if (region_range
.begin
== PCI_BAR_UNMAPPED
) {
2394 region_range
.begin
= MAX(region_range
.begin
, 0x1ULL
<< 32);
2396 if (region_range
.end
- 1 >= region_range
.begin
) {
2397 range_extend(range
, ®ion_range
);
2402 void pci_bus_get_w64_range(PCIBus
*bus
, Range
*range
)
2404 range
->begin
= range
->end
= 0;
2405 pci_for_each_device_under_bus(bus
, pci_dev_get_w64
, range
);
2408 static const TypeInfo pci_device_type_info
= {
2409 .name
= TYPE_PCI_DEVICE
,
2410 .parent
= TYPE_DEVICE
,
2411 .instance_size
= sizeof(PCIDevice
),
2413 .class_size
= sizeof(PCIDeviceClass
),
2414 .class_init
= pci_device_class_init
,
2417 static void pci_register_types(void)
2419 type_register_static(&pci_bus_info
);
2420 type_register_static(&pcie_bus_info
);
2421 type_register_static(&pci_device_type_info
);
2424 type_init(pci_register_types
)