hw/pci/pci_bridge.c

   1 /*
   2  * QEMU PCI bus manager
   3  *
   4  * Copyright (c) 2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to dea
   8
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM
  22
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  */
  26 /*
  27  * split out from pci.c
  28  * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
  29  *                    VA Linux Systems Japan K.K.
  30  */
  31
  32 #include "hw/pci/pci_bridge.h"
  33 #include "hw/pci/pci_bus.h"
  34 #include "qemu/range.h"
  35
  36 /* PCI bridge subsystem vendor ID helper functions */
  37 #define PCI_SSVID_SIZEOF        8
  38 #define PCI_SSVID_SVID          4
  39 #define PCI_SSVID_SSID          6
  40
  41 int pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset,
  42                           uint16_t svid, uint16_t ssid)
  43 {
  44     int pos;
  45     pos = pci_add_capability(dev, PCI_CAP_ID_SSVID, offset, PCI_SSVID_SIZEOF);
  46     if (pos < 0) {
  47         return pos;
  48     }
  49
  50     pci_set_word(dev->config + pos + PCI_SSVID_SVID, svid);
  51     pci_set_word(dev->config + pos + PCI_SSVID_SSID, ssid);
  52     return pos;
  53 }
  54
  55 /* Accessor function to get parent bridge device from pci bus. */
  56 PCIDevice *pci_bridge_get_device(PCIBus *bus)
  57 {
  58     return bus->parent_dev;
  59 }
  60
  61 /* Accessor function to get secondary bus from pci-to-pci bridge device */
  62 PCIBus *pci_bridge_get_sec_bus(PCIBridge *br)
  63 {
  64     return &br->sec_bus;
  65 }
  66
  67 static uint32_t pci_config_get_io_base(const PCIDevice *d,
  68                                        uint32_t base, uint32_t base_upper16)
  69 {
  70     uint32_t val;
  71
  72     val = ((uint32_t)d->config[base] & PCI_IO_RANGE_MASK) << 8;
  73     if (d->config[base] & PCI_IO_RANGE_TYPE_32) {
  74         val |= (uint32_t)pci_get_word(d->config + base_upper16) << 16;
  75     }
  76     return val;
  77 }
  78
  79 static pcibus_t pci_config_get_memory_base(const PCIDevice *d, uint32_t base)
  80 {
  81     return ((pcibus_t)pci_get_word(d->config + base) & PCI_MEMORY_RANGE_MASK)
  82         << 16;
  83 }
  84
  85 static pcibus_t pci_config_get_pref_base(const PCIDevice *d,
  86                                          uint32_t base, uint32_t upper)
  87 {
  88     pcibus_t tmp;
  89     pcibus_t val;
  90
  91     tmp = (pcibus_t)pci_get_word(d->config + base);
  92     val = (tmp & PCI_PREF_RANGE_MASK) << 16;
  93     if (tmp & PCI_PREF_RANGE_TYPE_64) {
  94         val |= (pcibus_t)pci_get_long(d->config + upper) << 32;
  95     }
  96     return val;
  97 }
  98
  99 /* accessor function to get bridge filtering base address */
 100 pcibus_t pci_bridge_get_base(const PCIDevice *bridge, uint8_t type)
 101 {
 102     pcibus_t base;
 103     if (type & PCI_BASE_ADDRESS_SPACE_IO) {
 104         base = pci_config_get_io_base(bridge,
 105                                       PCI_IO_BASE, PCI_IO_BASE_UPPER16);
 106     } else {
 107         if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
 108             base = pci_config_get_pref_base(
 109                 bridge, PCI_PREF_MEMORY_BASE, PCI_PREF_BASE_UPPER32);
 110         } else {
 111             base = pci_config_get_memory_base(bridge, PCI_MEMORY_BASE);
 112         }
 113     }
 114
 115     return base;
 116 }
 117
 118 /* accessor funciton to get bridge filtering limit */
 119 pcibus_t pci_bridge_get_limit(const PCIDevice *bridge, uint8_t type)
 120 {
 121     pcibus_t limit;
 122     if (type & PCI_BASE_ADDRESS_SPACE_IO) {
 123         limit = pci_config_get_io_base(bridge,
 124                                       PCI_IO_LIMIT, PCI_IO_LIMIT_UPPER16);
 125         limit |= 0xfff;         /* PCI bridge spec 3.2.5.6. */
 126     } else {
 127         if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
 128             limit = pci_config_get_pref_base(
 129                 bridge, PCI_PREF_MEMORY_LIMIT, PCI_PREF_LIMIT_UPPER32);
 130         } else {
 131             limit = pci_config_get_memory_base(bridge, PCI_MEMORY_LIMIT);
 132         }
 133         limit |= 0xfffff;       /* PCI bridge spec 3.2.5.{1, 8}. */
 134     }
 135     return limit;
 136 }
 137
 138 static void pci_bridge_init_alias(PCIBridge *bridge, MemoryRegion *alias,
 139                                   uint8_t type, const char *name,
 140                                   MemoryRegion *space,
 141                                   MemoryRegion *parent_space,
 142                                   bool enabled)
 143 {
 144     PCIDevice *bridge_dev = PCI_DEVICE(bridge);
 145     pcibus_t base = pci_bridge_get_base(bridge_dev, type);
 146     pcibus_t limit = pci_bridge_get_limit(bridge_dev, type);
 147     /* TODO: this doesn't handle base = 0 limit = 2^64 - 1 correctly.
 148      * Apparently no way to do this with existing memory APIs. */
 149     pcibus_t size = enabled && limit >= base ? limit + 1 - base : 0;
 150
 151     memory_region_init_alias(alias, OBJECT(bridge), name, space, base, size);
 152     memory_region_add_subregion_overlap(parent_space, base, alias, 1);
 153 }
 154
 155 static void pci_bridge_init_vga_aliases(PCIBridge *br, PCIBus *parent,
 156                                         MemoryRegion *alias_vga)
 157 {
 158     PCIDevice *pd = PCI_DEVICE(br);
 159     uint16_t brctl = pci_get_word(pd->config + PCI_BRIDGE_CONTROL);
 160
 161     memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_IO_LO], OBJECT(br),
 162                              "pci_bridge_vga_io_lo", &br->address_space_io,
 163                              QEMU_PCI_VGA_IO_LO_BASE, QEMU_PCI_VGA_IO_LO_SIZE);
 164     memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_IO_HI], OBJECT(br),
 165                              "pci_bridge_vga_io_hi", &br->address_space_io,
 166                              QEMU_PCI_VGA_IO_HI_BASE, QEMU_PCI_VGA_IO_HI_SIZE);
 167     memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_MEM], OBJECT(br),
 168                              "pci_bridge_vga_mem", &br->address_space_mem,
 169                              QEMU_PCI_VGA_MEM_BASE, QEMU_PCI_VGA_MEM_SIZE);
 170
 171     if (brctl & PCI_BRIDGE_CTL_VGA) {
 172         pci_register_vga(pd, &alias_vga[QEMU_PCI_VGA_MEM],
 173                          &alias_vga[QEMU_PCI_VGA_IO_LO],
 174                          &alias_vga[QEMU_PCI_VGA_IO_HI]);
 175     }
 176 }
 177
 178 static PCIBridgeWindows *pci_bridge_region_init(PCIBridge *br)
 179 {
 180     PCIDevice *pd = PCI_DEVICE(br);
 181     PCIBus *parent = pd->bus;
 182     PCIBridgeWindows *w = g_new(PCIBridgeWindows, 1);
 183     uint16_t cmd = pci_get_word(pd->config + PCI_COMMAND);
 184
 185     pci_bridge_init_alias(br, &w->alias_pref_mem,
 186                           PCI_BASE_ADDRESS_MEM_PREFETCH,
 187                           "pci_bridge_pref_mem",
 188                           &br->address_space_mem,
 189                           parent->address_space_mem,
 190                           cmd & PCI_COMMAND_MEMORY);
 191     pci_bridge_init_alias(br, &w->alias_mem,
 192                           PCI_BASE_ADDRESS_SPACE_MEMORY,
 193                           "pci_bridge_mem",
 194                           &br->address_space_mem,
 195                           parent->address_space_mem,
 196                           cmd & PCI_COMMAND_MEMORY);
 197     pci_bridge_init_alias(br, &w->alias_io,
 198                           PCI_BASE_ADDRESS_SPACE_IO,
 199                           "pci_bridge_io",
 200                           &br->address_space_io,
 201                           parent->address_space_io,
 202                           cmd & PCI_COMMAND_IO);
 203
 204     pci_bridge_init_vga_aliases(br, parent, w->alias_vga);
 205
 206     return w;
 207 }
 208
 209 static void pci_bridge_region_del(PCIBridge *br, PCIBridgeWindows *w)
 210 {
 211     PCIDevice *pd = PCI_DEVICE(br);
 212     PCIBus *parent = pd->bus;
 213
 214     memory_region_del_subregion(parent->address_space_io, &w->alias_io);
 215     memory_region_del_subregion(parent->address_space_mem, &w->alias_mem);
 216     memory_region_del_subregion(parent->address_space_mem, &w->alias_pref_mem);
 217     pci_unregister_vga(pd);
 218 }
 219
 220 static void pci_bridge_region_cleanup(PCIBridge *br, PCIBridgeWindows *w)
 221 {
 222     memory_region_destroy(&w->alias_io);
 223     memory_region_destroy(&w->alias_mem);
 224     memory_region_destroy(&w->alias_pref_mem);
 225     memory_region_destroy(&w->alias_vga[QEMU_PCI_VGA_IO_LO]);
 226     memory_region_destroy(&w->alias_vga[QEMU_PCI_VGA_IO_HI]);
 227     memory_region_destroy(&w->alias_vga[QEMU_PCI_VGA_MEM]);
 228     g_free(w);
 229 }
 230
 231 void pci_bridge_update_mappings(PCIBridge *br)
 232 {
 233     PCIBridgeWindows *w = br->windows;
 234
 235     /* Make updates atomic to: handle the case of one VCPU updating the bridge
 236      * while another accesses an unaffected region. */
 237     memory_region_transaction_begin();
 238     pci_bridge_region_del(br, br->windows);
 239     br->windows = pci_bridge_region_init(br);
 240     memory_region_transaction_commit();
 241     pci_bridge_region_cleanup(br, w);
 242 }
 243
 244 /* default write_config function for PCI-to-PCI bridge */
 245 void pci_bridge_write_config(PCIDevice *d,
 246                              uint32_t address, uint32_t val, int len)
 247 {
 248     PCIBridge *s = PCI_BRIDGE(d);
 249     uint16_t oldctl = pci_get_word(d->config + PCI_BRIDGE_CONTROL);
 250     uint16_t newctl;
 251
 252     pci_default_write_config(d, address, val, len);
 253
 254     if (ranges_overlap(address, len, PCI_COMMAND, 2) ||
 255
 256         /* io base/limit */
 257         ranges_overlap(address, len, PCI_IO_BASE, 2) ||
 258
 259         /* memory base/limit, prefetchable base/limit and
 260            io base/limit upper 16 */
 261         ranges_overlap(address, len, PCI_MEMORY_BASE, 20) ||
 262
 263         /* vga enable */
 264         ranges_overlap(address, len, PCI_BRIDGE_CONTROL, 2)) {
 265         pci_bridge_update_mappings(s);
 266     }
 267
 268     newctl = pci_get_word(d->config + PCI_BRIDGE_CONTROL);
 269     if (~oldctl & newctl & PCI_BRIDGE_CTL_BUS_RESET) {
 270         /* Trigger hot reset on 0->1 transition. */
 271         pci_bus_reset(&s->sec_bus);
 272     }
 273 }
 274
 275 void pci_bridge_disable_base_limit(PCIDevice *dev)
 276 {
 277     uint8_t *conf = dev->config;
 278
 279     pci_byte_test_and_set_mask(conf + PCI_IO_BASE,
 280                                PCI_IO_RANGE_MASK & 0xff);
 281     pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT,
 282                                  PCI_IO_RANGE_MASK & 0xff);
 283     pci_word_test_and_set_mask(conf + PCI_MEMORY_BASE,
 284                                PCI_MEMORY_RANGE_MASK & 0xffff);
 285     pci_word_test_and_clear_mask(conf + PCI_MEMORY_LIMIT,
 286                                  PCI_MEMORY_RANGE_MASK & 0xffff);
 287     pci_word_test_and_set_mask(conf + PCI_PREF_MEMORY_BASE,
 288                                PCI_PREF_RANGE_MASK & 0xffff);
 289     pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_LIMIT,
 290                                  PCI_PREF_RANGE_MASK & 0xffff);
 291     pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0);
 292     pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0);
 293 }
 294
 295 /* reset bridge specific configuration registers */
 296 void pci_bridge_reset(DeviceState *qdev)
 297 {
 298     PCIDevice *dev = PCI_DEVICE(qdev);
 299     uint8_t *conf = dev->config;
 300
 301     conf[PCI_PRIMARY_BUS] = 0;
 302     conf[PCI_SECONDARY_BUS] = 0;
 303     conf[PCI_SUBORDINATE_BUS] = 0;
 304     conf[PCI_SEC_LATENCY_TIMER] = 0;
 305
 306     /*
 307      * the default values for base/limit registers aren't specified
 308      * in the PCI-to-PCI-bridge spec. So we don't thouch them here.
 309      * Each implementation can override it.
 310      * typical implementation does
 311      * zero base/limit registers or
 312      * disable forwarding: pci_bridge_disable_base_limit()
 313      * If disable forwarding is wanted, call pci_bridge_disable_base_limit()
 314      * after this function.
 315      */
 316     pci_byte_test_and_clear_mask(conf + PCI_IO_BASE,
 317                                  PCI_IO_RANGE_MASK & 0xff);
 318     pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT,
 319                                  PCI_IO_RANGE_MASK & 0xff);
 320     pci_word_test_and_clear_mask(conf + PCI_MEMORY_BASE,
 321                                  PCI_MEMORY_RANGE_MASK & 0xffff);
 322     pci_word_test_and_clear_mask(conf + PCI_MEMORY_LIMIT,
 323                                  PCI_MEMORY_RANGE_MASK & 0xffff);
 324     pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_BASE,
 325                                  PCI_PREF_RANGE_MASK & 0xffff);
 326     pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_LIMIT,
 327                                  PCI_PREF_RANGE_MASK & 0xffff);
 328     pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0);
 329     pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0);
 330
 331     pci_set_word(conf + PCI_BRIDGE_CONTROL, 0);
 332 }
 333
 334 /* default qdev initialization function for PCI-to-PCI bridge */
 335 int pci_bridge_initfn(PCIDevice *dev, const char *typename)
 336 {
 337     PCIBus *parent = dev->bus;
 338     PCIBridge *br = PCI_BRIDGE(dev);
 339     PCIBus *sec_bus = &br->sec_bus;
 340
 341     pci_word_test_and_set_mask(dev->config + PCI_STATUS,
 342                                PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
 343
 344     /*
 345      * TODO: We implement VGA Enable in the Bridge Control Register
 346      * therefore per the PCI to PCI bridge spec we must also implement
 347      * VGA Palette Snooping.  When done, set this bit writable:
 348      *
 349      * pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND,
 350      *                            PCI_COMMAND_VGA_PALETTE);
 351      */
 352
 353     pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_PCI);
 354     dev->config[PCI_HEADER_TYPE] =
 355         (dev->config[PCI_HEADER_TYPE] & PCI_HEADER_TYPE_MULTI_FUNCTION) |
 356         PCI_HEADER_TYPE_BRIDGE;
 357     pci_set_word(dev->config + PCI_SEC_STATUS,
 358                  PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
 359
 360     /*
 361      * If we don't specify the name, the bus will be addressed as <id>.0, where
 362      * id is the device id.
 363      * Since PCI Bridge devices have a single bus each, we don't need the index:
 364      * let users address the bus using the device name.
 365      */
 366     if (!br->bus_name && dev->qdev.id && *dev->qdev.id) {
 367             br->bus_name = dev->qdev.id;
 368     }
 369
 370     qbus_create_inplace(sec_bus, sizeof(br->sec_bus), typename, DEVICE(dev),
 371                         br->bus_name);
 372     sec_bus->parent_dev = dev;
 373     sec_bus->map_irq = br->map_irq ? br->map_irq : pci_swizzle_map_irq_fn;
 374     sec_bus->address_space_mem = &br->address_space_mem;
 375     memory_region_init(&br->address_space_mem, OBJECT(br), "pci_bridge_pci", INT64_MAX);
 376     sec_bus->address_space_io = &br->address_space_io;
 377     memory_region_init(&br->address_space_io, OBJECT(br), "pci_bridge_io", 65536);
 378     br->windows = pci_bridge_region_init(br);
 379     QLIST_INIT(&sec_bus->child);
 380     QLIST_INSERT_HEAD(&parent->child, sec_bus, sibling);
 381     return 0;
 382 }
 383
 384 /* default qdev clean up function for PCI-to-PCI bridge */
 385 void pci_bridge_exitfn(PCIDevice *pci_dev)
 386 {
 387     PCIBridge *s = PCI_BRIDGE(pci_dev);
 388     assert(QLIST_EMPTY(&s->sec_bus.child));
 389     QLIST_REMOVE(&s->sec_bus, sibling);
 390     pci_bridge_region_del(s, s->windows);
 391     pci_bridge_region_cleanup(s, s->windows);
 392     memory_region_destroy(&s->address_space_mem);
 393     memory_region_destroy(&s->address_space_io);
 394     /* qbus_free() is called automatically by qdev_free() */
 395 }
 396
 397 /*
 398  * before qdev initialization(qdev_init()), this function sets bus_name and
 399  * map_irq callback which are necessry for pci_bridge_initfn() to
 400  * initialize bus.
 401  */
 402 void pci_bridge_map_irq(PCIBridge *br, const char* bus_name,
 403                         pci_map_irq_fn map_irq)
 404 {
 405     br->map_irq = map_irq;
 406     br->bus_name = bus_name;
 407 }
 408
 409 static const TypeInfo pci_bridge_type_info = {
 410     .name = TYPE_PCI_BRIDGE,
 411     .parent = TYPE_PCI_DEVICE,
 412     .instance_size = sizeof(PCIBridge),
 413     .abstract = true,
 414 };
 415
 416 static void pci_bridge_register_types(void)
 417 {
 418     type_register_static(&pci_bridge_type_info);
 419 }
 420
 421 type_init(pci_bridge_register_types)