hw/pci/pci_host.c

   1 /*
   2  * pci_host.c
   3  *
   4  * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
   5  *                    VA Linux Systems Japan K.K.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "hw/pci/pci.h"
  23 #include "hw/pci/pci_bridge.h"
  24 #include "hw/pci/pci_host.h"
  25 #include "hw/pci/pci_bus.h"
  26 #include "trace.h"
  27
  28 /* debug PCI */
  29 //#define DEBUG_PCI
  30
  31 #ifdef DEBUG_PCI
  32 #define PCI_DPRINTF(fmt, ...) \
  33 do { printf("pci_host_data: " fmt , ## __VA_ARGS__); } while (0)
  34 #else
  35 #define PCI_DPRINTF(fmt, ...)
  36 #endif
  37
  38 /*
  39  * PCI address
  40  * bit 16 - 24: bus number
  41  * bit  8 - 15: devfun number
  42  * bit  0 -  7: offset in configuration space of a given pci device
  43  */
  44
  45 /* the helper function to get a PCIDevice* for a given pci address */
  46 static inline PCIDevice *pci_dev_find_by_addr(PCIBus *bus, uint32_t addr)
  47 {
  48     uint8_t bus_num = addr >> 16;
  49     uint8_t devfn = addr >> 8;
  50
  51     return pci_find_device(bus, bus_num, devfn);
  52 }
  53
  54 static void pci_adjust_config_limit(PCIBus *bus, uint32_t *limit)
  55 {
  56     if ((*limit > PCI_CONFIG_SPACE_SIZE) &&
  57         !pci_bus_allows_extended_config_space(bus)) {
  58         *limit = PCI_CONFIG_SPACE_SIZE;
  59     }
  60 }
  61
  62 void pci_host_config_write_common(PCIDevice *pci_dev, uint32_t addr,
  63                                   uint32_t limit, uint32_t val, uint32_t len)
  64 {
  65     pci_adjust_config_limit(pci_get_bus(pci_dev), &limit);
  66     if (limit <= addr) {
  67         return;
  68     }
  69
  70     assert(len <= 4);
  71     /* non-zero functions are only exposed when function 0 is present,
  72      * allowing direct removal of unexposed functions.
  73      */
  74     if (pci_dev->qdev.hotplugged && !pci_get_function_0(pci_dev)) {
  75         return;
  76     }
  77
  78     trace_pci_cfg_write(pci_dev->name, PCI_SLOT(pci_dev->devfn),
  79                         PCI_FUNC(pci_dev->devfn), addr, val);
  80     pci_dev->config_write(pci_dev, addr, val, MIN(len, limit - addr));
  81 }
  82
  83 uint32_t pci_host_config_read_common(PCIDevice *pci_dev, uint32_t addr,
  84                                      uint32_t limit, uint32_t len)
  85 {
  86     uint32_t ret;
  87
  88     pci_adjust_config_limit(pci_get_bus(pci_dev), &limit);
  89     if (limit <= addr) {
  90         return ~0x0;
  91     }
  92
  93     assert(len <= 4);
  94     /* non-zero functions are only exposed when function 0 is present,
  95      * allowing direct removal of unexposed functions.
  96      */
  97     if (pci_dev->qdev.hotplugged && !pci_get_function_0(pci_dev)) {
  98         return ~0x0;
  99     }
 100
 101     ret = pci_dev->config_read(pci_dev, addr, MIN(len, limit - addr));
 102     trace_pci_cfg_read(pci_dev->name, PCI_SLOT(pci_dev->devfn),
 103                        PCI_FUNC(pci_dev->devfn), addr, ret);
 104
 105     return ret;
 106 }
 107
 108 void pci_data_write(PCIBus *s, uint32_t addr, uint32_t val, int len)
 109 {
 110     PCIDevice *pci_dev = pci_dev_find_by_addr(s, addr);
 111     uint32_t config_addr = addr & (PCI_CONFIG_SPACE_SIZE - 1);
 112
 113     if (!pci_dev) {
 114         return;
 115     }
 116
 117     PCI_DPRINTF("%s: %s: addr=%02" PRIx32 " val=%08" PRIx32 " len=%d\n",
 118                 __func__, pci_dev->name, config_addr, val, len);
 119     pci_host_config_write_common(pci_dev, config_addr, PCI_CONFIG_SPACE_SIZE,
 120                                  val, len);
 121 }
 122
 123 uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len)
 124 {
 125     PCIDevice *pci_dev = pci_dev_find_by_addr(s, addr);
 126     uint32_t config_addr = addr & (PCI_CONFIG_SPACE_SIZE - 1);
 127     uint32_t val;
 128
 129     if (!pci_dev) {
 130         return ~0x0;
 131     }
 132
 133     val = pci_host_config_read_common(pci_dev, config_addr,
 134                                       PCI_CONFIG_SPACE_SIZE, len);
 135     PCI_DPRINTF("%s: %s: addr=%02"PRIx32" val=%08"PRIx32" len=%d\n",
 136                 __func__, pci_dev->name, config_addr, val, len);
 137
 138     return val;
 139 }
 140
 141 static void pci_host_config_write(void *opaque, hwaddr addr,
 142                                   uint64_t val, unsigned len)
 143 {
 144     PCIHostState *s = opaque;
 145
 146     PCI_DPRINTF("%s addr " TARGET_FMT_plx " len %d val %"PRIx64"\n",
 147                 __func__, addr, len, val);
 148     if (addr != 0 || len != 4) {
 149         return;
 150     }
 151     s->config_reg = val;
 152 }
 153
 154 static uint64_t pci_host_config_read(void *opaque, hwaddr addr,
 155                                      unsigned len)
 156 {
 157     PCIHostState *s = opaque;
 158     uint32_t val = s->config_reg;
 159
 160     PCI_DPRINTF("%s addr " TARGET_FMT_plx " len %d val %"PRIx32"\n",
 161                 __func__, addr, len, val);
 162     return val;
 163 }
 164
 165 static void pci_host_data_write(void *opaque, hwaddr addr,
 166                                 uint64_t val, unsigned len)
 167 {
 168     PCIHostState *s = opaque;
 169     PCI_DPRINTF("write addr " TARGET_FMT_plx " len %d val %x\n",
 170                 addr, len, (unsigned)val);
 171     if (s->config_reg & (1u << 31))
 172         pci_data_write(s->bus, s->config_reg | (addr & 3), val, len);
 173 }
 174
 175 static uint64_t pci_host_data_read(void *opaque,
 176                                    hwaddr addr, unsigned len)
 177 {
 178     PCIHostState *s = opaque;
 179     uint32_t val;
 180     if (!(s->config_reg & (1U << 31))) {
 181         return 0xffffffff;
 182     }
 183     val = pci_data_read(s->bus, s->config_reg | (addr & 3), len);
 184     PCI_DPRINTF("read addr " TARGET_FMT_plx " len %d val %x\n",
 185                 addr, len, val);
 186     return val;
 187 }
 188
 189 const MemoryRegionOps pci_host_conf_le_ops = {
 190     .read = pci_host_config_read,
 191     .write = pci_host_config_write,
 192     .endianness = DEVICE_LITTLE_ENDIAN,
 193 };
 194
 195 const MemoryRegionOps pci_host_conf_be_ops = {
 196     .read = pci_host_config_read,
 197     .write = pci_host_config_write,
 198     .endianness = DEVICE_BIG_ENDIAN,
 199 };
 200
 201 const MemoryRegionOps pci_host_data_le_ops = {
 202     .read = pci_host_data_read,
 203     .write = pci_host_data_write,
 204     .endianness = DEVICE_LITTLE_ENDIAN,
 205 };
 206
 207 const MemoryRegionOps pci_host_data_be_ops = {
 208     .read = pci_host_data_read,
 209     .write = pci_host_data_write,
 210     .endianness = DEVICE_BIG_ENDIAN,
 211 };
 212
 213 static const TypeInfo pci_host_type_info = {
 214     .name = TYPE_PCI_HOST_BRIDGE,
 215     .parent = TYPE_SYS_BUS_DEVICE,
 216     .abstract = true,
 217     .class_size = sizeof(PCIHostBridgeClass),
 218     .instance_size = sizeof(PCIHostState),
 219 };
 220
 221 static void pci_host_register_types(void)
 222 {
 223     type_register_static(&pci_host_type_info);
 224 }
 225
 226 type_init(pci_host_register_types)