hw/pci-bridge/xio3130_downstream.c

   1 /*
   2  * x3130_downstream.c
   3  * TI X3130 pci express downstream port switch
   4  *
   5  * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
   6  *                    VA Linux Systems Japan K.K.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License along
  19  * with this program; if not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include "qemu/osdep.h"
  23 #include "hw/pci/pci_ids.h"
  24 #include "hw/pci/msi.h"
  25 #include "hw/pci/pcie.h"
  26 #include "hw/pci/pcie_port.h"
  27 #include "migration/vmstate.h"
  28 #include "qapi/error.h"
  29 #include "qemu/module.h"
  30
  31 #define PCI_DEVICE_ID_TI_XIO3130D       0x8233  /* downstream port */
  32 #define XIO3130_REVISION                0x1
  33 #define XIO3130_MSI_OFFSET              0x70
  34 #define XIO3130_MSI_SUPPORTED_FLAGS     PCI_MSI_FLAGS_64BIT
  35 #define XIO3130_MSI_NR_VECTOR           1
  36 #define XIO3130_SSVID_OFFSET            0x80
  37 #define XIO3130_SSVID_SVID              0
  38 #define XIO3130_SSVID_SSID              0
  39 #define XIO3130_EXP_OFFSET              0x90
  40 #define XIO3130_AER_OFFSET              0x100
  41
  42 static void xio3130_downstream_write_config(PCIDevice *d, uint32_t address,
  43                                          uint32_t val, int len)
  44 {
  45     uint16_t slt_ctl, slt_sta;
  46
  47     pcie_cap_slot_get(d, &slt_ctl, &slt_sta);
  48     pci_bridge_write_config(d, address, val, len);
  49     pcie_cap_flr_write_config(d, address, val, len);
  50     pcie_cap_slot_write_config(d, slt_ctl, slt_sta, address, val, len);
  51     pcie_aer_write_config(d, address, val, len);
  52 }
  53
  54 static void xio3130_downstream_reset(DeviceState *qdev)
  55 {
  56     PCIDevice *d = PCI_DEVICE(qdev);
  57
  58     pcie_cap_deverr_reset(d);
  59     pcie_cap_slot_reset(d);
  60     pcie_cap_arifwd_reset(d);
  61     pci_bridge_reset(qdev);
  62 }
  63
  64 static void xio3130_downstream_realize(PCIDevice *d, Error **errp)
  65 {
  66     PCIEPort *p = PCIE_PORT(d);
  67     PCIESlot *s = PCIE_SLOT(d);
  68     int rc;
  69
  70     pci_bridge_initfn(d, TYPE_PCIE_BUS);
  71     pcie_port_init_reg(d);
  72
  73     rc = msi_init(d, XIO3130_MSI_OFFSET, XIO3130_MSI_NR_VECTOR,
  74                   XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT,
  75                   XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT,
  76                   errp);
  77     if (rc < 0) {
  78         assert(rc == -ENOTSUP);
  79         goto err_bridge;
  80     }
  81
  82     rc = pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET,
  83                                XIO3130_SSVID_SVID, XIO3130_SSVID_SSID,
  84                                errp);
  85     if (rc < 0) {
  86         goto err_bridge;
  87     }
  88
  89     rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_DOWNSTREAM,
  90                        p->port, errp);
  91     if (rc < 0) {
  92         goto err_msi;
  93     }
  94     pcie_cap_flr_init(d);
  95     pcie_cap_deverr_init(d);
  96     pcie_cap_slot_init(d, s->slot);
  97     pcie_cap_arifwd_init(d);
  98
  99     pcie_chassis_create(s->chassis);
 100     rc = pcie_chassis_add_slot(s);
 101     if (rc < 0) {
 102         error_setg(errp, "Can't add chassis slot, error %d", rc);
 103         goto err_pcie_cap;
 104     }
 105
 106     rc = pcie_aer_init(d, PCI_ERR_VER, XIO3130_AER_OFFSET,
 107                        PCI_ERR_SIZEOF, errp);
 108     if (rc < 0) {
 109         goto err;
 110     }
 111
 112     return;
 113
 114 err:
 115     pcie_chassis_del_slot(s);
 116 err_pcie_cap:
 117     pcie_cap_exit(d);
 118 err_msi:
 119     msi_uninit(d);
 120 err_bridge:
 121     pci_bridge_exitfn(d);
 122 }
 123
 124 static void xio3130_downstream_exitfn(PCIDevice *d)
 125 {
 126     PCIESlot *s = PCIE_SLOT(d);
 127
 128     pcie_aer_exit(d);
 129     pcie_chassis_del_slot(s);
 130     pcie_cap_exit(d);
 131     msi_uninit(d);
 132     pci_bridge_exitfn(d);
 133 }
 134
 135 static Property xio3130_downstream_props[] = {
 136     DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present,
 137                     QEMU_PCIE_SLTCAP_PCP_BITNR, true),
 138     DEFINE_PROP_END_OF_LIST()
 139 };
 140
 141 static const VMStateDescription vmstate_xio3130_downstream = {
 142     .name = "xio3130-express-downstream-port",
 143     .priority = MIG_PRI_PCI_BUS,
 144     .version_id = 1,
 145     .minimum_version_id = 1,
 146     .post_load = pcie_cap_slot_post_load,
 147     .fields = (VMStateField[]) {
 148         VMSTATE_PCI_DEVICE(parent_obj.parent_obj.parent_obj, PCIESlot),
 149         VMSTATE_STRUCT(parent_obj.parent_obj.parent_obj.exp.aer_log,
 150                        PCIESlot, 0, vmstate_pcie_aer_log, PCIEAERLog),
 151         VMSTATE_END_OF_LIST()
 152     }
 153 };
 154
 155 static void xio3130_downstream_class_init(ObjectClass *klass, void *data)
 156 {
 157     DeviceClass *dc = DEVICE_CLASS(klass);
 158     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 159
 160     k->is_bridge = true;
 161     k->config_write = xio3130_downstream_write_config;
 162     k->realize = xio3130_downstream_realize;
 163     k->exit = xio3130_downstream_exitfn;
 164     k->vendor_id = PCI_VENDOR_ID_TI;
 165     k->device_id = PCI_DEVICE_ID_TI_XIO3130D;
 166     k->revision = XIO3130_REVISION;
 167     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 168     dc->desc = "TI X3130 Downstream Port of PCI Express Switch";
 169     dc->reset = xio3130_downstream_reset;
 170     dc->vmsd = &vmstate_xio3130_downstream;
 171     dc->props = xio3130_downstream_props;
 172 }
 173
 174 static const TypeInfo xio3130_downstream_info = {
 175     .name          = "xio3130-downstream",
 176     .parent        = TYPE_PCIE_SLOT,
 177     .class_init    = xio3130_downstream_class_init,
 178     .interfaces = (InterfaceInfo[]) {
 179         { INTERFACE_PCIE_DEVICE },
 180         { }
 181     },
 182 };
 183
 184 static void xio3130_downstream_register_types(void)
 185 {
 186     type_register_static(&xio3130_downstream_info);
 187 }
 188
 189 type_init(xio3130_downstream_register_types)