hw/pci-host/apb.c

   1 /*
   2  * QEMU Ultrasparc APB PCI host
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  * Copyright (c) 2012,2013 Artyom Tarasenko
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 /* XXX This file and most of its contents are somewhat misnamed.  The
  27    Ultrasparc PCI host is called the PCI Bus Module (PBM).  The APB is
  28    the secondary PCI bridge.  */
  29
  30 #include "qemu/osdep.h"
  31 #include "hw/sysbus.h"
  32 #include "hw/pci/pci.h"
  33 #include "hw/pci/pci_host.h"
  34 #include "hw/pci/pci_bridge.h"
  35 #include "hw/pci/pci_bus.h"
  36 #include "hw/pci-host/apb.h"
  37 #include "sysemu/sysemu.h"
  38 #include "exec/address-spaces.h"
  39 #include "qemu/log.h"
  40
  41 /* debug APB */
  42 //#define DEBUG_APB
  43
  44 #ifdef DEBUG_APB
  45 #define APB_DPRINTF(fmt, ...) \
  46 do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
  47 #else
  48 #define APB_DPRINTF(fmt, ...)
  49 #endif
  50
  51 /* debug IOMMU */
  52 //#define DEBUG_IOMMU
  53
  54 #ifdef DEBUG_IOMMU
  55 #define IOMMU_DPRINTF(fmt, ...) \
  56 do { printf("IOMMU: " fmt , ## __VA_ARGS__); } while (0)
  57 #else
  58 #define IOMMU_DPRINTF(fmt, ...)
  59 #endif
  60
  61 /*
  62  * Chipset docs:
  63  * PBM: "UltraSPARC IIi User's Manual",
  64  * http://www.sun.com/processors/manuals/805-0087.pdf
  65  *
  66  * APB: "Advanced PCI Bridge (APB) User's Manual",
  67  * http://www.sun.com/processors/manuals/805-1251.pdf
  68  */
  69
  70 #define PBM_PCI_IMR_MASK    0x7fffffff
  71 #define PBM_PCI_IMR_ENABLED 0x80000000
  72
  73 #define POR          (1U << 31)
  74 #define SOFT_POR     (1U << 30)
  75 #define SOFT_XIR     (1U << 29)
  76 #define BTN_POR      (1U << 28)
  77 #define BTN_XIR      (1U << 27)
  78 #define RESET_MASK   0xf8000000
  79 #define RESET_WCMASK 0x98000000
  80 #define RESET_WMASK  0x60000000
  81
  82 #define MAX_IVEC 0x40
  83 #define NO_IRQ_REQUEST (MAX_IVEC + 1)
  84
  85 #define IOMMU_PAGE_SIZE_8K      (1ULL << 13)
  86 #define IOMMU_PAGE_MASK_8K      (~(IOMMU_PAGE_SIZE_8K - 1))
  87 #define IOMMU_PAGE_SIZE_64K     (1ULL << 16)
  88 #define IOMMU_PAGE_MASK_64K     (~(IOMMU_PAGE_SIZE_64K - 1))
  89
  90 #define IOMMU_NREGS             3
  91
  92 #define IOMMU_CTRL              0x0
  93 #define IOMMU_CTRL_TBW_SIZE     (1ULL << 2)
  94 #define IOMMU_CTRL_MMU_EN       (1ULL)
  95
  96 #define IOMMU_CTRL_TSB_SHIFT    16
  97
  98 #define IOMMU_BASE              0x8
  99 #define IOMMU_FLUSH             0x10
 100
 101 #define IOMMU_TTE_DATA_V        (1ULL << 63)
 102 #define IOMMU_TTE_DATA_SIZE     (1ULL << 61)
 103 #define IOMMU_TTE_DATA_W        (1ULL << 1)
 104
 105 #define IOMMU_TTE_PHYS_MASK_8K  0x1ffffffe000ULL
 106 #define IOMMU_TTE_PHYS_MASK_64K 0x1ffffff8000ULL
 107
 108 #define IOMMU_TSB_8K_OFFSET_MASK_8M    0x00000000007fe000ULL
 109 #define IOMMU_TSB_8K_OFFSET_MASK_16M   0x0000000000ffe000ULL
 110 #define IOMMU_TSB_8K_OFFSET_MASK_32M   0x0000000001ffe000ULL
 111 #define IOMMU_TSB_8K_OFFSET_MASK_64M   0x0000000003ffe000ULL
 112 #define IOMMU_TSB_8K_OFFSET_MASK_128M  0x0000000007ffe000ULL
 113 #define IOMMU_TSB_8K_OFFSET_MASK_256M  0x000000000fffe000ULL
 114 #define IOMMU_TSB_8K_OFFSET_MASK_512M  0x000000001fffe000ULL
 115 #define IOMMU_TSB_8K_OFFSET_MASK_1G    0x000000003fffe000ULL
 116
 117 #define IOMMU_TSB_64K_OFFSET_MASK_64M  0x0000000003ff0000ULL
 118 #define IOMMU_TSB_64K_OFFSET_MASK_128M 0x0000000007ff0000ULL
 119 #define IOMMU_TSB_64K_OFFSET_MASK_256M 0x000000000fff0000ULL
 120 #define IOMMU_TSB_64K_OFFSET_MASK_512M 0x000000001fff0000ULL
 121 #define IOMMU_TSB_64K_OFFSET_MASK_1G   0x000000003fff0000ULL
 122 #define IOMMU_TSB_64K_OFFSET_MASK_2G   0x000000007fff0000ULL
 123
 124 typedef struct IOMMUState {
 125     AddressSpace iommu_as;
 126     IOMMUMemoryRegion iommu;
 127
 128     uint64_t regs[IOMMU_NREGS];
 129 } IOMMUState;
 130
 131 #define TYPE_APB "pbm"
 132
 133 #define APB_DEVICE(obj) \
 134     OBJECT_CHECK(APBState, (obj), TYPE_APB)
 135
 136 #define TYPE_APB_IOMMU_MEMORY_REGION "pbm-iommu-memory-region"
 137
 138 typedef struct APBState {
 139     PCIHostState parent_obj;
 140
 141     MemoryRegion apb_config;
 142     MemoryRegion pci_config;
 143     MemoryRegion pci_mmio;
 144     MemoryRegion pci_ioport;
 145     uint64_t pci_irq_in;
 146     IOMMUState iommu;
 147     uint32_t pci_control[16];
 148     uint32_t pci_irq_map[8];
 149     uint32_t pci_err_irq_map[4];
 150     uint32_t obio_irq_map[32];
 151     qemu_irq *pbm_irqs;
 152     qemu_irq *ivec_irqs;
 153     unsigned int irq_request;
 154     uint32_t reset_control;
 155     unsigned int nr_resets;
 156 } APBState;
 157
 158 #define TYPE_PBM_PCI_BRIDGE "pbm-bridge"
 159 #define PBM_PCI_BRIDGE(obj) \
 160     OBJECT_CHECK(PBMPCIBridge, (obj), TYPE_PBM_PCI_BRIDGE)
 161
 162 typedef struct PBMPCIBridge {
 163     /*< private >*/
 164     PCIBridge parent_obj;
 165
 166     /* Is this busA with in-built devices (ebus)? */
 167     bool busA;
 168 } PBMPCIBridge;
 169
 170 static inline void pbm_set_request(APBState *s, unsigned int irq_num)
 171 {
 172     APB_DPRINTF("%s: request irq %d\n", __func__, irq_num);
 173
 174     s->irq_request = irq_num;
 175     qemu_set_irq(s->ivec_irqs[irq_num], 1);
 176 }
 177
 178 static inline void pbm_check_irqs(APBState *s)
 179 {
 180
 181     unsigned int i;
 182
 183     /* Previous request is not acknowledged, resubmit */
 184     if (s->irq_request != NO_IRQ_REQUEST) {
 185         pbm_set_request(s, s->irq_request);
 186         return;
 187     }
 188     /* no request pending */
 189     if (s->pci_irq_in == 0ULL) {
 190         return;
 191     }
 192     for (i = 0; i < 32; i++) {
 193         if (s->pci_irq_in & (1ULL << i)) {
 194             if (s->pci_irq_map[i >> 2] & PBM_PCI_IMR_ENABLED) {
 195                 pbm_set_request(s, i);
 196                 return;
 197             }
 198         }
 199     }
 200     for (i = 32; i < 64; i++) {
 201         if (s->pci_irq_in & (1ULL << i)) {
 202             if (s->obio_irq_map[i - 32] & PBM_PCI_IMR_ENABLED) {
 203                 pbm_set_request(s, i);
 204                 break;
 205             }
 206         }
 207     }
 208 }
 209
 210 static inline void pbm_clear_request(APBState *s, unsigned int irq_num)
 211 {
 212     APB_DPRINTF("%s: clear request irq %d\n", __func__, irq_num);
 213     qemu_set_irq(s->ivec_irqs[irq_num], 0);
 214     s->irq_request = NO_IRQ_REQUEST;
 215 }
 216
 217 static AddressSpace *pbm_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn)
 218 {
 219     IOMMUState *is = opaque;
 220
 221     return &is->iommu_as;
 222 }
 223
 224 /* Called from RCU critical section */
 225 static IOMMUTLBEntry pbm_translate_iommu(IOMMUMemoryRegion *iommu, hwaddr addr,
 226                                          IOMMUAccessFlags flag)
 227 {
 228     IOMMUState *is = container_of(iommu, IOMMUState, iommu);
 229     hwaddr baseaddr, offset;
 230     uint64_t tte;
 231     uint32_t tsbsize;
 232     IOMMUTLBEntry ret = {
 233         .target_as = &address_space_memory,
 234         .iova = 0,
 235         .translated_addr = 0,
 236         .addr_mask = ~(hwaddr)0,
 237         .perm = IOMMU_NONE,
 238     };
 239
 240     if (!(is->regs[IOMMU_CTRL >> 3] & IOMMU_CTRL_MMU_EN)) {
 241         /* IOMMU disabled, passthrough using standard 8K page */
 242         ret.iova = addr & IOMMU_PAGE_MASK_8K;
 243         ret.translated_addr = addr;
 244         ret.addr_mask = IOMMU_PAGE_MASK_8K;
 245         ret.perm = IOMMU_RW;
 246
 247         return ret;
 248     }
 249
 250     baseaddr = is->regs[IOMMU_BASE >> 3];
 251     tsbsize = (is->regs[IOMMU_CTRL >> 3] >> IOMMU_CTRL_TSB_SHIFT) & 0x7;
 252
 253     if (is->regs[IOMMU_CTRL >> 3] & IOMMU_CTRL_TBW_SIZE) {
 254         /* 64K */
 255         switch (tsbsize) {
 256         case 0:
 257             offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_64M) >> 13;
 258             break;
 259         case 1:
 260             offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_128M) >> 13;
 261             break;
 262         case 2:
 263             offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_256M) >> 13;
 264             break;
 265         case 3:
 266             offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_512M) >> 13;
 267             break;
 268         case 4:
 269             offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_1G) >> 13;
 270             break;
 271         case 5:
 272             offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_2G) >> 13;
 273             break;
 274         default:
 275             /* Not implemented, error */
 276             return ret;
 277         }
 278     } else {
 279         /* 8K */
 280         switch (tsbsize) {
 281         case 0:
 282             offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_8M) >> 10;
 283             break;
 284         case 1:
 285             offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_16M) >> 10;
 286             break;
 287         case 2:
 288             offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_32M) >> 10;
 289             break;
 290         case 3:
 291             offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_64M) >> 10;
 292             break;
 293         case 4:
 294             offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_128M) >> 10;
 295             break;
 296         case 5:
 297             offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_256M) >> 10;
 298             break;
 299         case 6:
 300             offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_512M) >> 10;
 301             break;
 302         case 7:
 303             offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_1G) >> 10;
 304             break;
 305         }
 306     }
 307
 308     tte = address_space_ldq_be(&address_space_memory, baseaddr + offset,
 309                                MEMTXATTRS_UNSPECIFIED, NULL);
 310
 311     if (!(tte & IOMMU_TTE_DATA_V)) {
 312         /* Invalid mapping */
 313         return ret;
 314     }
 315
 316     if (tte & IOMMU_TTE_DATA_W) {
 317         /* Writeable */
 318         ret.perm = IOMMU_RW;
 319     } else {
 320         ret.perm = IOMMU_RO;
 321     }
 322
 323     /* Extract phys */
 324     if (tte & IOMMU_TTE_DATA_SIZE) {
 325         /* 64K */
 326         ret.iova = addr & IOMMU_PAGE_MASK_64K;
 327         ret.translated_addr = tte & IOMMU_TTE_PHYS_MASK_64K;
 328         ret.addr_mask = (IOMMU_PAGE_SIZE_64K - 1);
 329     } else {
 330         /* 8K */
 331         ret.iova = addr & IOMMU_PAGE_MASK_8K;
 332         ret.translated_addr = tte & IOMMU_TTE_PHYS_MASK_8K;
 333         ret.addr_mask = (IOMMU_PAGE_SIZE_8K - 1);
 334     }
 335
 336     return ret;
 337 }
 338
 339 static void iommu_config_write(void *opaque, hwaddr addr,
 340                                uint64_t val, unsigned size)
 341 {
 342     IOMMUState *is = opaque;
 343
 344     IOMMU_DPRINTF("IOMMU config write: 0x%" HWADDR_PRIx " val: %" PRIx64
 345                   " size: %d\n", addr, val, size);
 346
 347     switch (addr) {
 348     case IOMMU_CTRL:
 349         if (size == 4) {
 350             is->regs[IOMMU_CTRL >> 3] &= 0xffffffffULL;
 351             is->regs[IOMMU_CTRL >> 3] |= val << 32;
 352         } else {
 353             is->regs[IOMMU_CTRL >> 3] = val;
 354         }
 355         break;
 356     case IOMMU_CTRL + 0x4:
 357         is->regs[IOMMU_CTRL >> 3] &= 0xffffffff00000000ULL;
 358         is->regs[IOMMU_CTRL >> 3] |= val & 0xffffffffULL;
 359         break;
 360     case IOMMU_BASE:
 361         if (size == 4) {
 362             is->regs[IOMMU_BASE >> 3] &= 0xffffffffULL;
 363             is->regs[IOMMU_BASE >> 3] |= val << 32;
 364         } else {
 365             is->regs[IOMMU_BASE >> 3] = val;
 366         }
 367         break;
 368     case IOMMU_BASE + 0x4:
 369         is->regs[IOMMU_BASE >> 3] &= 0xffffffff00000000ULL;
 370         is->regs[IOMMU_BASE >> 3] |= val & 0xffffffffULL;
 371         break;
 372     case IOMMU_FLUSH:
 373     case IOMMU_FLUSH + 0x4:
 374         break;
 375     default:
 376         qemu_log_mask(LOG_UNIMP,
 377                   "apb iommu: Unimplemented register write "
 378                   "reg 0x%" HWADDR_PRIx " size 0x%x value 0x%" PRIx64 "\n",
 379                   addr, size, val);
 380         break;
 381     }
 382 }
 383
 384 static uint64_t iommu_config_read(void *opaque, hwaddr addr, unsigned size)
 385 {
 386     IOMMUState *is = opaque;
 387     uint64_t val;
 388
 389     switch (addr) {
 390     case IOMMU_CTRL:
 391         if (size == 4) {
 392             val = is->regs[IOMMU_CTRL >> 3] >> 32;
 393         } else {
 394             val = is->regs[IOMMU_CTRL >> 3];
 395         }
 396         break;
 397     case IOMMU_CTRL + 0x4:
 398         val = is->regs[IOMMU_CTRL >> 3] & 0xffffffffULL;
 399         break;
 400     case IOMMU_BASE:
 401         if (size == 4) {
 402             val = is->regs[IOMMU_BASE >> 3] >> 32;
 403         } else {
 404             val = is->regs[IOMMU_BASE >> 3];
 405         }
 406         break;
 407     case IOMMU_BASE + 0x4:
 408         val = is->regs[IOMMU_BASE >> 3] & 0xffffffffULL;
 409         break;
 410     case IOMMU_FLUSH:
 411     case IOMMU_FLUSH + 0x4:
 412         val = 0;
 413         break;
 414     default:
 415         qemu_log_mask(LOG_UNIMP,
 416                       "apb iommu: Unimplemented register read "
 417                       "reg 0x%" HWADDR_PRIx " size 0x%x\n",
 418                       addr, size);
 419         val = 0;
 420         break;
 421     }
 422
 423     IOMMU_DPRINTF("IOMMU config read: 0x%" HWADDR_PRIx " val: %" PRIx64
 424                   " size: %d\n", addr, val, size);
 425
 426     return val;
 427 }
 428
 429 static void apb_config_writel (void *opaque, hwaddr addr,
 430                                uint64_t val, unsigned size)
 431 {
 432     APBState *s = opaque;
 433     IOMMUState *is = &s->iommu;
 434
 435     APB_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__, addr, val);
 436
 437     switch (addr & 0xffff) {
 438     case 0x30 ... 0x4f: /* DMA error registers */
 439         /* XXX: not implemented yet */
 440         break;
 441     case 0x200 ... 0x217: /* IOMMU */
 442         iommu_config_write(is, (addr & 0x1f), val, size);
 443         break;
 444     case 0xc00 ... 0xc3f: /* PCI interrupt control */
 445         if (addr & 4) {
 446             unsigned int ino = (addr & 0x3f) >> 3;
 447             s->pci_irq_map[ino] &= PBM_PCI_IMR_MASK;
 448             s->pci_irq_map[ino] |= val & ~PBM_PCI_IMR_MASK;
 449             if ((s->irq_request == ino) && !(val & ~PBM_PCI_IMR_MASK)) {
 450                 pbm_clear_request(s, ino);
 451             }
 452             pbm_check_irqs(s);
 453         }
 454         break;
 455     case 0x1000 ... 0x107f: /* OBIO interrupt control */
 456         if (addr & 4) {
 457             unsigned int ino = ((addr & 0xff) >> 3);
 458             s->obio_irq_map[ino] &= PBM_PCI_IMR_MASK;
 459             s->obio_irq_map[ino] |= val & ~PBM_PCI_IMR_MASK;
 460             if ((s->irq_request == (ino | 0x20))
 461                  && !(val & ~PBM_PCI_IMR_MASK)) {
 462                 pbm_clear_request(s, ino | 0x20);
 463             }
 464             pbm_check_irqs(s);
 465         }
 466         break;
 467     case 0x1400 ... 0x14ff: /* PCI interrupt clear */
 468         if (addr & 4) {
 469             unsigned int ino = (addr & 0xff) >> 5;
 470             if ((s->irq_request / 4)  == ino) {
 471                 pbm_clear_request(s, s->irq_request);
 472                 pbm_check_irqs(s);
 473             }
 474         }
 475         break;
 476     case 0x1800 ... 0x1860: /* OBIO interrupt clear */
 477         if (addr & 4) {
 478             unsigned int ino = ((addr & 0xff) >> 3) | 0x20;
 479             if (s->irq_request == ino) {
 480                 pbm_clear_request(s, ino);
 481                 pbm_check_irqs(s);
 482             }
 483         }
 484         break;
 485     case 0x2000 ... 0x202f: /* PCI control */
 486         s->pci_control[(addr & 0x3f) >> 2] = val;
 487         break;
 488     case 0xf020 ... 0xf027: /* Reset control */
 489         if (addr & 4) {
 490             val &= RESET_MASK;
 491             s->reset_control &= ~(val & RESET_WCMASK);
 492             s->reset_control |= val & RESET_WMASK;
 493             if (val & SOFT_POR) {
 494                 s->nr_resets = 0;
 495                 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 496             } else if (val & SOFT_XIR) {
 497                 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 498             }
 499         }
 500         break;
 501     case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
 502     case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
 503     case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
 504     case 0xf000 ... 0xf01f: /* FFB config, memory control */
 505         /* we don't care */
 506     default:
 507         break;
 508     }
 509 }
 510
 511 static uint64_t apb_config_readl (void *opaque,
 512                                   hwaddr addr, unsigned size)
 513 {
 514     APBState *s = opaque;
 515     IOMMUState *is = &s->iommu;
 516     uint32_t val;
 517
 518     switch (addr & 0xffff) {
 519     case 0x30 ... 0x4f: /* DMA error registers */
 520         val = 0;
 521         /* XXX: not implemented yet */
 522         break;
 523     case 0x200 ... 0x217: /* IOMMU */
 524         val = iommu_config_read(is, (addr & 0x1f), size);
 525         break;
 526     case 0xc00 ... 0xc3f: /* PCI interrupt control */
 527         if (addr & 4) {
 528             val = s->pci_irq_map[(addr & 0x3f) >> 3];
 529         } else {
 530             val = 0;
 531         }
 532         break;
 533     case 0x1000 ... 0x107f: /* OBIO interrupt control */
 534         if (addr & 4) {
 535             val = s->obio_irq_map[(addr & 0xff) >> 3];
 536         } else {
 537             val = 0;
 538         }
 539         break;
 540     case 0x1080 ... 0x108f: /* PCI bus error */
 541         if (addr & 4) {
 542             val = s->pci_err_irq_map[(addr & 0xf) >> 3];
 543         } else {
 544             val = 0;
 545         }
 546         break;
 547     case 0x2000 ... 0x202f: /* PCI control */
 548         val = s->pci_control[(addr & 0x3f) >> 2];
 549         break;
 550     case 0xf020 ... 0xf027: /* Reset control */
 551         if (addr & 4) {
 552             val = s->reset_control;
 553         } else {
 554             val = 0;
 555         }
 556         break;
 557     case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
 558     case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
 559     case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
 560     case 0xf000 ... 0xf01f: /* FFB config, memory control */
 561         /* we don't care */
 562     default:
 563         val = 0;
 564         break;
 565     }
 566     APB_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, val);
 567
 568     return val;
 569 }
 570
 571 static const MemoryRegionOps apb_config_ops = {
 572     .read = apb_config_readl,
 573     .write = apb_config_writel,
 574     .endianness = DEVICE_BIG_ENDIAN,
 575 };
 576
 577 static void apb_pci_config_write(void *opaque, hwaddr addr,
 578                                  uint64_t val, unsigned size)
 579 {
 580     APBState *s = opaque;
 581     PCIHostState *phb = PCI_HOST_BRIDGE(s);
 582
 583     APB_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__, addr, val);
 584     pci_data_write(phb->bus, addr, val, size);
 585 }
 586
 587 static uint64_t apb_pci_config_read(void *opaque, hwaddr addr,
 588                                     unsigned size)
 589 {
 590     uint32_t ret;
 591     APBState *s = opaque;
 592     PCIHostState *phb = PCI_HOST_BRIDGE(s);
 593
 594     ret = pci_data_read(phb->bus, addr, size);
 595     APB_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, ret);
 596     return ret;
 597 }
 598
 599 /* The APB host has an IRQ line for each IRQ line of each slot.  */
 600 static int pci_apb_map_irq(PCIDevice *pci_dev, int irq_num)
 601 {
 602     return ((pci_dev->devfn & 0x18) >> 1) + irq_num;
 603 }
 604
 605 static int pci_pbm_map_irq(PCIDevice *pci_dev, int irq_num)
 606 {
 607     int bus_offset;
 608     if (pci_dev->devfn & 1)
 609         bus_offset = 16;
 610     else
 611         bus_offset = 0;
 612     return (bus_offset + (PCI_SLOT(pci_dev->devfn) << 2) + irq_num) & 0x1f;
 613 }
 614
 615 static void pci_apb_set_irq(void *opaque, int irq_num, int level)
 616 {
 617     APBState *s = opaque;
 618
 619     APB_DPRINTF("%s: set irq_in %d level %d\n", __func__, irq_num, level);
 620     /* PCI IRQ map onto the first 32 INO.  */
 621     if (irq_num < 32) {
 622         if (level) {
 623             s->pci_irq_in |= 1ULL << irq_num;
 624             if (s->pci_irq_map[irq_num >> 2] & PBM_PCI_IMR_ENABLED) {
 625                 pbm_set_request(s, irq_num);
 626             }
 627         } else {
 628             s->pci_irq_in &= ~(1ULL << irq_num);
 629         }
 630     } else {
 631         /* OBIO IRQ map onto the next 32 INO.  */
 632         if (level) {
 633             APB_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num, level);
 634             s->pci_irq_in |= 1ULL << irq_num;
 635             if ((s->irq_request == NO_IRQ_REQUEST)
 636                 && (s->obio_irq_map[irq_num - 32] & PBM_PCI_IMR_ENABLED)) {
 637                 pbm_set_request(s, irq_num);
 638             }
 639         } else {
 640             s->pci_irq_in &= ~(1ULL << irq_num);
 641         }
 642     }
 643 }
 644
 645 static void apb_pci_bridge_realize(PCIDevice *dev, Error **errp)
 646 {
 647     /*
 648      * command register:
 649      * According to PCI bridge spec, after reset
 650      *   bus master bit is off
 651      *   memory space enable bit is off
 652      * According to manual (805-1251.pdf).
 653      *   the reset value should be zero unless the boot pin is tied high
 654      *   (which is true) and thus it should be PCI_COMMAND_MEMORY.
 655      */
 656     uint16_t cmd = PCI_COMMAND_MEMORY;
 657     PBMPCIBridge *br = PBM_PCI_BRIDGE(dev);
 658
 659     pci_bridge_initfn(dev, TYPE_PCI_BUS);
 660
 661     /* If initialising busA, ensure that we allow IO transactions so that
 662        we get the early serial console until OpenBIOS configures the bridge */
 663     if (br->busA) {
 664         cmd |= PCI_COMMAND_IO;
 665     }
 666
 667     pci_set_word(dev->config + PCI_COMMAND, cmd);
 668     pci_set_word(dev->config + PCI_STATUS,
 669                  PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
 670                  PCI_STATUS_DEVSEL_MEDIUM);
 671
 672     pci_bridge_update_mappings(PCI_BRIDGE(br));
 673 }
 674
 675 PCIBus *pci_apb_init(hwaddr special_base,
 676                      hwaddr mem_base,
 677                      qemu_irq *ivec_irqs, PCIBus **busA, PCIBus **busB,
 678                      qemu_irq **pbm_irqs)
 679 {
 680     DeviceState *dev;
 681     SysBusDevice *s;
 682     PCIHostState *phb;
 683     APBState *d;
 684     IOMMUState *is;
 685     PCIDevice *pci_dev;
 686     PCIBridge *br;
 687
 688     /* Ultrasparc PBM main bus */
 689     dev = qdev_create(NULL, TYPE_APB);
 690     d = APB_DEVICE(dev);
 691     phb = PCI_HOST_BRIDGE(dev);
 692     phb->bus = pci_register_bus(DEVICE(phb), "pci",
 693                                 pci_apb_set_irq, pci_pbm_map_irq, d,
 694                                 &d->pci_mmio,
 695                                 get_system_io(),
 696                                 0, 32, TYPE_PCI_BUS);
 697     qdev_init_nofail(dev);
 698     s = SYS_BUS_DEVICE(dev);
 699     /* apb_config */
 700     sysbus_mmio_map(s, 0, special_base);
 701     /* PCI configuration space */
 702     sysbus_mmio_map(s, 1, special_base + 0x1000000ULL);
 703     /* pci_ioport */
 704     sysbus_mmio_map(s, 2, special_base + 0x2000000ULL);
 705
 706     memory_region_init(&d->pci_mmio, OBJECT(s), "pci-mmio", 0x100000000ULL);
 707     memory_region_add_subregion(get_system_memory(), mem_base, &d->pci_mmio);
 708
 709     *pbm_irqs = d->pbm_irqs;
 710     d->ivec_irqs = ivec_irqs;
 711
 712     pci_create_simple(phb->bus, 0, "pbm-pci");
 713
 714     /* APB IOMMU */
 715     is = &d->iommu;
 716     memset(is, 0, sizeof(IOMMUState));
 717
 718     memory_region_init_iommu(&is->iommu, sizeof(is->iommu),
 719                              TYPE_APB_IOMMU_MEMORY_REGION, OBJECT(dev),
 720                              "iommu-apb", UINT64_MAX);
 721     address_space_init(&is->iommu_as, MEMORY_REGION(&is->iommu), "pbm-as");
 722     pci_setup_iommu(phb->bus, pbm_pci_dma_iommu, is);
 723
 724     /* APB secondary busses */
 725     pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 0), true,
 726                                    TYPE_PBM_PCI_BRIDGE);
 727     br = PCI_BRIDGE(pci_dev);
 728     pci_bridge_map_irq(br, "pciB", pci_apb_map_irq);
 729     qdev_init_nofail(&pci_dev->qdev);
 730     *busB = pci_bridge_get_sec_bus(br);
 731
 732     pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 1), true,
 733                                    TYPE_PBM_PCI_BRIDGE);
 734     br = PCI_BRIDGE(pci_dev);
 735     pci_bridge_map_irq(br, "pciA", pci_apb_map_irq);
 736     qdev_prop_set_bit(DEVICE(pci_dev), "busA", true);
 737     qdev_init_nofail(&pci_dev->qdev);
 738     *busA = pci_bridge_get_sec_bus(br);
 739
 740     return phb->bus;
 741 }
 742
 743 static void pci_pbm_reset(DeviceState *d)
 744 {
 745     unsigned int i;
 746     APBState *s = APB_DEVICE(d);
 747
 748     for (i = 0; i < 8; i++) {
 749         s->pci_irq_map[i] &= PBM_PCI_IMR_MASK;
 750     }
 751     for (i = 0; i < 32; i++) {
 752         s->obio_irq_map[i] &= PBM_PCI_IMR_MASK;
 753     }
 754
 755     s->irq_request = NO_IRQ_REQUEST;
 756     s->pci_irq_in = 0ULL;
 757
 758     if (s->nr_resets++ == 0) {
 759         /* Power on reset */
 760         s->reset_control = POR;
 761     }
 762 }
 763
 764 static const MemoryRegionOps pci_config_ops = {
 765     .read = apb_pci_config_read,
 766     .write = apb_pci_config_write,
 767     .endianness = DEVICE_LITTLE_ENDIAN,
 768 };
 769
 770 static int pci_pbm_init_device(SysBusDevice *dev)
 771 {
 772     APBState *s;
 773     unsigned int i;
 774
 775     s = APB_DEVICE(dev);
 776     for (i = 0; i < 8; i++) {
 777         s->pci_irq_map[i] = (0x1f << 6) | (i << 2);
 778     }
 779     for (i = 0; i < 2; i++) {
 780         s->pci_err_irq_map[i] = (0x1f << 6) | 0x30;
 781     }
 782     for (i = 0; i < 32; i++) {
 783         s->obio_irq_map[i] = ((0x1f << 6) | 0x20) + i;
 784     }
 785     s->pbm_irqs = qemu_allocate_irqs(pci_apb_set_irq, s, MAX_IVEC);
 786     s->irq_request = NO_IRQ_REQUEST;
 787     s->pci_irq_in = 0ULL;
 788
 789     /* apb_config */
 790     memory_region_init_io(&s->apb_config, OBJECT(s), &apb_config_ops, s,
 791                           "apb-config", 0x10000);
 792     /* at region 0 */
 793     sysbus_init_mmio(dev, &s->apb_config);
 794
 795     memory_region_init_io(&s->pci_config, OBJECT(s), &pci_config_ops, s,
 796                           "apb-pci-config", 0x1000000);
 797     /* at region 1 */
 798     sysbus_init_mmio(dev, &s->pci_config);
 799
 800     /* pci_ioport */
 801     memory_region_init_alias(&s->pci_ioport, OBJECT(s), "apb-pci-ioport",
 802                              get_system_io(), 0, 0x10000);
 803     /* at region 2 */
 804     sysbus_init_mmio(dev, &s->pci_ioport);
 805
 806     return 0;
 807 }
 808
 809 static void pbm_pci_host_realize(PCIDevice *d, Error **errp)
 810 {
 811     pci_set_word(d->config + PCI_COMMAND,
 812                  PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 813     pci_set_word(d->config + PCI_STATUS,
 814                  PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
 815                  PCI_STATUS_DEVSEL_MEDIUM);
 816 }
 817
 818 static void pbm_pci_host_class_init(ObjectClass *klass, void *data)
 819 {
 820     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 821     DeviceClass *dc = DEVICE_CLASS(klass);
 822
 823     k->realize = pbm_pci_host_realize;
 824     k->vendor_id = PCI_VENDOR_ID_SUN;
 825     k->device_id = PCI_DEVICE_ID_SUN_SABRE;
 826     k->class_id = PCI_CLASS_BRIDGE_HOST;
 827     /*
 828      * PCI-facing part of the host bridge, not usable without the
 829      * host-facing part, which can't be device_add'ed, yet.
 830      */
 831     dc->user_creatable = false;
 832 }
 833
 834 static const TypeInfo pbm_pci_host_info = {
 835     .name          = "pbm-pci",
 836     .parent        = TYPE_PCI_DEVICE,
 837     .instance_size = sizeof(PCIDevice),
 838     .class_init    = pbm_pci_host_class_init,
 839     .interfaces = (InterfaceInfo[]) {
 840         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 841         { },
 842     },
 843 };
 844
 845 static void pbm_host_class_init(ObjectClass *klass, void *data)
 846 {
 847     DeviceClass *dc = DEVICE_CLASS(klass);
 848     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 849
 850     k->init = pci_pbm_init_device;
 851     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 852     dc->reset = pci_pbm_reset;
 853 }
 854
 855 static const TypeInfo pbm_host_info = {
 856     .name          = TYPE_APB,
 857     .parent        = TYPE_PCI_HOST_BRIDGE,
 858     .instance_size = sizeof(APBState),
 859     .class_init    = pbm_host_class_init,
 860 };
 861
 862 static Property pbm_pci_properties[] = {
 863     DEFINE_PROP_BOOL("busA", PBMPCIBridge, busA, false),
 864     DEFINE_PROP_END_OF_LIST(),
 865 };
 866
 867 static void pbm_pci_bridge_class_init(ObjectClass *klass, void *data)
 868 {
 869     DeviceClass *dc = DEVICE_CLASS(klass);
 870     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 871
 872     k->realize = apb_pci_bridge_realize;
 873     k->exit = pci_bridge_exitfn;
 874     k->vendor_id = PCI_VENDOR_ID_SUN;
 875     k->device_id = PCI_DEVICE_ID_SUN_SIMBA;
 876     k->revision = 0x11;
 877     k->config_write = pci_bridge_write_config;
 878     k->is_bridge = 1;
 879     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 880     dc->reset = pci_bridge_reset;
 881     dc->vmsd = &vmstate_pci_device;
 882     dc->props = pbm_pci_properties;
 883 }
 884
 885 static const TypeInfo pbm_pci_bridge_info = {
 886     .name          = TYPE_PBM_PCI_BRIDGE,
 887     .parent        = TYPE_PCI_BRIDGE,
 888     .class_init    = pbm_pci_bridge_class_init,
 889     .instance_size = sizeof(PBMPCIBridge),
 890     .interfaces = (InterfaceInfo[]) {
 891         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 892         { },
 893     },
 894 };
 895
 896 static void pbm_iommu_memory_region_class_init(ObjectClass *klass, void *data)
 897 {
 898     IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass);
 899
 900     imrc->translate = pbm_translate_iommu;
 901 }
 902
 903 static const TypeInfo pbm_iommu_memory_region_info = {
 904     .parent = TYPE_IOMMU_MEMORY_REGION,
 905     .name = TYPE_APB_IOMMU_MEMORY_REGION,
 906     .class_init = pbm_iommu_memory_region_class_init,
 907 };
 908
 909 static void pbm_register_types(void)
 910 {
 911     type_register_static(&pbm_host_info);
 912     type_register_static(&pbm_pci_host_info);
 913     type_register_static(&pbm_pci_bridge_info);
 914     type_register_static(&pbm_iommu_memory_region_info);
 915 }
 916
 917 type_init(pbm_register_types)