hw/pci-host/bonito.c

   1 /*
   2  * bonito north bridge support
   3  *
   4  * Copyright (c) 2008 yajin (yajin@vm-kernel.org)
   5  * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com)
   6  *
   7  * This code is licensed under the GNU GPL v2.
   8  *
   9  * Contributions after 2012-01-13 are licensed under the terms of the
  10  * GNU GPL, version 2 or (at your option) any later version.
  11  */
  12
  13 /*
  14  * fuloong 2e mini pc has a bonito north bridge.
  15  */
  16
  17 /*
  18  * what is the meaning of devfn in qemu and IDSEL in bonito northbridge?
  19  *
  20  * devfn   pci_slot<<3  + funno
  21  * one pci bus can have 32 devices and each device can have 8 functions.
  22  *
  23  * In bonito north bridge, pci slot = IDSEL bit - 12.
  24  * For example, PCI_IDSEL_VIA686B = 17,
  25  * pci slot = 17-12=5
  26  *
  27  * so
  28  * VT686B_FUN0's devfn = (5<<3)+0
  29  * VT686B_FUN1's devfn = (5<<3)+1
  30  *
  31  * qemu also uses pci address for north bridge to access pci config register.
  32  * bus_no   [23:16]
  33  * dev_no   [15:11]
  34  * fun_no   [10:8]
  35  * reg_no   [7:2]
  36  *
  37  * so function bonito_sbridge_pciaddr for the translation from
  38  * north bridge address to pci address.
  39  */
  40
  41 #include "qemu/osdep.h"
  42 #include "qemu/units.h"
  43 #include "qapi/error.h"
  44 #include "qemu/error-report.h"
  45 #include "hw/pci/pci.h"
  46 #include "hw/irq.h"
  47 #include "hw/mips/mips.h"
  48 #include "hw/pci/pci_host.h"
  49 #include "migration/vmstate.h"
  50 #include "sysemu/reset.h"
  51 #include "sysemu/runstate.h"
  52 #include "exec/address-spaces.h"
  53 #include "hw/misc/unimp.h"
  54 #include "hw/registerfields.h"
  55 #include "qom/object.h"
  56
  57 /* #define DEBUG_BONITO */
  58
  59 #ifdef DEBUG_BONITO
  60 #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __func__, ##__VA_ARGS__)
  61 #else
  62 #define DPRINTF(fmt, ...)
  63 #endif
  64
  65 /* from linux soure code. include/asm-mips/mips-boards/bonito64.h*/
  66 #define BONITO_BOOT_BASE        0x1fc00000
  67 #define BONITO_BOOT_SIZE        0x00100000
  68 #define BONITO_BOOT_TOP         (BONITO_BOOT_BASE + BONITO_BOOT_SIZE - 1)
  69 #define BONITO_FLASH_BASE       0x1c000000
  70 #define BONITO_FLASH_SIZE       0x03000000
  71 #define BONITO_FLASH_TOP        (BONITO_FLASH_BASE + BONITO_FLASH_SIZE - 1)
  72 #define BONITO_SOCKET_BASE      0x1f800000
  73 #define BONITO_SOCKET_SIZE      0x00400000
  74 #define BONITO_SOCKET_TOP       (BONITO_SOCKET_BASE + BONITO_SOCKET_SIZE - 1)
  75 #define BONITO_REG_BASE         0x1fe00000
  76 #define BONITO_REG_SIZE         0x00040000
  77 #define BONITO_REG_TOP          (BONITO_REG_BASE + BONITO_REG_SIZE - 1)
  78 #define BONITO_DEV_BASE         0x1ff00000
  79 #define BONITO_DEV_SIZE         0x00100000
  80 #define BONITO_DEV_TOP          (BONITO_DEV_BASE + BONITO_DEV_SIZE - 1)
  81 #define BONITO_PCILO_BASE       0x10000000
  82 #define BONITO_PCILO_BASE_VA    0xb0000000
  83 #define BONITO_PCILO_SIZE       0x0c000000
  84 #define BONITO_PCILO_TOP        (BONITO_PCILO_BASE + BONITO_PCILO_SIZE - 1)
  85 #define BONITO_PCILO0_BASE      0x10000000
  86 #define BONITO_PCILO1_BASE      0x14000000
  87 #define BONITO_PCILO2_BASE      0x18000000
  88 #define BONITO_PCIHI_BASE       0x20000000
  89 #define BONITO_PCIHI_SIZE       0x60000000
  90 #define BONITO_PCIHI_TOP        (BONITO_PCIHI_BASE + BONITO_PCIHI_SIZE - 1)
  91 #define BONITO_PCIIO_BASE       0x1fd00000
  92 #define BONITO_PCIIO_BASE_VA    0xbfd00000
  93 #define BONITO_PCIIO_SIZE       0x00010000
  94 #define BONITO_PCIIO_TOP        (BONITO_PCIIO_BASE + BONITO_PCIIO_SIZE - 1)
  95 #define BONITO_PCICFG_BASE      0x1fe80000
  96 #define BONITO_PCICFG_SIZE      0x00080000
  97 #define BONITO_PCICFG_TOP       (BONITO_PCICFG_BASE + BONITO_PCICFG_SIZE - 1)
  98
  99
 100 #define BONITO_PCICONFIGBASE    0x00
 101 #define BONITO_REGBASE          0x100
 102
 103 #define BONITO_PCICONFIG_BASE   (BONITO_PCICONFIGBASE + BONITO_REG_BASE)
 104 #define BONITO_PCICONFIG_SIZE   (0x100)
 105
 106 #define BONITO_INTERNAL_REG_BASE  (BONITO_REGBASE + BONITO_REG_BASE)
 107 #define BONITO_INTERNAL_REG_SIZE  (0x70)
 108
 109 #define BONITO_SPCICONFIG_BASE  (BONITO_PCICFG_BASE)
 110 #define BONITO_SPCICONFIG_SIZE  (BONITO_PCICFG_SIZE)
 111
 112
 113
 114 /* 1. Bonito h/w Configuration */
 115 /* Power on register */
 116
 117 #define BONITO_BONPONCFG        (0x00 >> 2)      /* 0x100 */
 118
 119 /* PCI configuration register */
 120 #define BONITO_BONGENCFG_OFFSET 0x4
 121 #define BONITO_BONGENCFG        (BONITO_BONGENCFG_OFFSET >> 2)   /*0x104 */
 122 REG32(BONGENCFG,        0x104)
 123 FIELD(BONGENCFG, DEBUGMODE,      0, 1)
 124 FIELD(BONGENCFG, SNOOP,          1, 1)
 125 FIELD(BONGENCFG, CPUSELFRESET,   2, 1)
 126 FIELD(BONGENCFG, BYTESWAP,       6, 1)
 127 FIELD(BONGENCFG, UNCACHED,       7, 1)
 128 FIELD(BONGENCFG, PREFETCH,       8, 1)
 129 FIELD(BONGENCFG, WRITEBEHIND,    9, 1)
 130 FIELD(BONGENCFG, PCIQUEUE,      12, 1)
 131
 132 /* 2. IO & IDE configuration */
 133 #define BONITO_IODEVCFG         (0x08 >> 2)      /* 0x108 */
 134
 135 /* 3. IO & IDE configuration */
 136 #define BONITO_SDCFG            (0x0c >> 2)      /* 0x10c */
 137
 138 /* 4. PCI address map control */
 139 #define BONITO_PCIMAP           (0x10 >> 2)      /* 0x110 */
 140 #define BONITO_PCIMEMBASECFG    (0x14 >> 2)      /* 0x114 */
 141 #define BONITO_PCIMAP_CFG       (0x18 >> 2)      /* 0x118 */
 142
 143 /* 5. ICU & GPIO regs */
 144 /* GPIO Regs - r/w */
 145 #define BONITO_GPIODATA_OFFSET  0x1c
 146 #define BONITO_GPIODATA         (BONITO_GPIODATA_OFFSET >> 2)   /* 0x11c */
 147 #define BONITO_GPIOIE           (0x20 >> 2)      /* 0x120 */
 148
 149 /* ICU Configuration Regs - r/w */
 150 #define BONITO_INTEDGE          (0x24 >> 2)      /* 0x124 */
 151 #define BONITO_INTSTEER         (0x28 >> 2)      /* 0x128 */
 152 #define BONITO_INTPOL           (0x2c >> 2)      /* 0x12c */
 153
 154 /* ICU Enable Regs - IntEn & IntISR are r/o. */
 155 #define BONITO_INTENSET         (0x30 >> 2)      /* 0x130 */
 156 #define BONITO_INTENCLR         (0x34 >> 2)      /* 0x134 */
 157 #define BONITO_INTEN            (0x38 >> 2)      /* 0x138 */
 158 #define BONITO_INTISR           (0x3c >> 2)      /* 0x13c */
 159
 160 /* PCI mail boxes */
 161 #define BONITO_PCIMAIL0_OFFSET    0x40
 162 #define BONITO_PCIMAIL1_OFFSET    0x44
 163 #define BONITO_PCIMAIL2_OFFSET    0x48
 164 #define BONITO_PCIMAIL3_OFFSET    0x4c
 165 #define BONITO_PCIMAIL0         (0x40 >> 2)      /* 0x140 */
 166 #define BONITO_PCIMAIL1         (0x44 >> 2)      /* 0x144 */
 167 #define BONITO_PCIMAIL2         (0x48 >> 2)      /* 0x148 */
 168 #define BONITO_PCIMAIL3         (0x4c >> 2)      /* 0x14c */
 169
 170 /* 6. PCI cache */
 171 #define BONITO_PCICACHECTRL     (0x50 >> 2)      /* 0x150 */
 172 #define BONITO_PCICACHETAG      (0x54 >> 2)      /* 0x154 */
 173 #define BONITO_PCIBADADDR       (0x58 >> 2)      /* 0x158 */
 174 #define BONITO_PCIMSTAT         (0x5c >> 2)      /* 0x15c */
 175
 176 /* 7. other*/
 177 #define BONITO_TIMECFG          (0x60 >> 2)      /* 0x160 */
 178 #define BONITO_CPUCFG           (0x64 >> 2)      /* 0x164 */
 179 #define BONITO_DQCFG            (0x68 >> 2)      /* 0x168 */
 180 #define BONITO_MEMSIZE          (0x6C >> 2)      /* 0x16c */
 181
 182 #define BONITO_REGS             (0x70 >> 2)
 183
 184 /* PCI config for south bridge. type 0 */
 185 #define BONITO_PCICONF_IDSEL_MASK      0xfffff800     /* [31:11] */
 186 #define BONITO_PCICONF_IDSEL_OFFSET    11
 187 #define BONITO_PCICONF_FUN_MASK        0x700    /* [10:8] */
 188 #define BONITO_PCICONF_FUN_OFFSET      8
 189 #define BONITO_PCICONF_REG_MASK        0xFC
 190 #define BONITO_PCICONF_REG_OFFSET      0
 191
 192
 193 /* idsel BIT = pci slot number +12 */
 194 #define PCI_SLOT_BASE              12
 195 #define PCI_IDSEL_VIA686B_BIT      (17)
 196 #define PCI_IDSEL_VIA686B          (1 << PCI_IDSEL_VIA686B_BIT)
 197
 198 #define PCI_ADDR(busno , devno , funno , regno)  \
 199     ((PCI_BUILD_BDF(busno, PCI_DEVFN(devno , funno)) << 8) + (regno))
 200
 201 typedef struct BonitoState BonitoState;
 202
 203 struct PCIBonitoState {
 204     PCIDevice dev;
 205
 206     BonitoState *pcihost;
 207     uint32_t regs[BONITO_REGS];
 208
 209     struct bonldma {
 210         uint32_t ldmactrl;
 211         uint32_t ldmastat;
 212         uint32_t ldmaaddr;
 213         uint32_t ldmago;
 214     } bonldma;
 215
 216     /* Based at 1fe00300, bonito Copier */
 217     struct boncop {
 218         uint32_t copctrl;
 219         uint32_t copstat;
 220         uint32_t coppaddr;
 221         uint32_t copgo;
 222     } boncop;
 223
 224     /* Bonito registers */
 225     MemoryRegion iomem;
 226     MemoryRegion iomem_ldma;
 227     MemoryRegion iomem_cop;
 228     MemoryRegion bonito_pciio;
 229     MemoryRegion bonito_localio;
 230
 231 };
 232 typedef struct PCIBonitoState PCIBonitoState;
 233
 234 struct BonitoState {
 235     PCIHostState parent_obj;
 236     qemu_irq *pic;
 237     PCIBonitoState *pci_dev;
 238     MemoryRegion pci_mem;
 239 };
 240
 241 #define TYPE_BONITO_PCI_HOST_BRIDGE "Bonito-pcihost"
 242 OBJECT_DECLARE_SIMPLE_TYPE(BonitoState, BONITO_PCI_HOST_BRIDGE)
 243
 244 #define TYPE_PCI_BONITO "Bonito"
 245 OBJECT_DECLARE_SIMPLE_TYPE(PCIBonitoState, PCI_BONITO)
 246
 247 static void bonito_writel(void *opaque, hwaddr addr,
 248                           uint64_t val, unsigned size)
 249 {
 250     PCIBonitoState *s = opaque;
 251     uint32_t saddr;
 252     int reset = 0;
 253
 254     saddr = addr >> 2;
 255
 256     DPRINTF("bonito_writel "TARGET_FMT_plx" val %lx saddr %x\n",
 257             addr, val, saddr);
 258     switch (saddr) {
 259     case BONITO_BONPONCFG:
 260     case BONITO_IODEVCFG:
 261     case BONITO_SDCFG:
 262     case BONITO_PCIMAP:
 263     case BONITO_PCIMEMBASECFG:
 264     case BONITO_PCIMAP_CFG:
 265     case BONITO_GPIODATA:
 266     case BONITO_GPIOIE:
 267     case BONITO_INTEDGE:
 268     case BONITO_INTSTEER:
 269     case BONITO_INTPOL:
 270     case BONITO_PCIMAIL0:
 271     case BONITO_PCIMAIL1:
 272     case BONITO_PCIMAIL2:
 273     case BONITO_PCIMAIL3:
 274     case BONITO_PCICACHECTRL:
 275     case BONITO_PCICACHETAG:
 276     case BONITO_PCIBADADDR:
 277     case BONITO_PCIMSTAT:
 278     case BONITO_TIMECFG:
 279     case BONITO_CPUCFG:
 280     case BONITO_DQCFG:
 281     case BONITO_MEMSIZE:
 282         s->regs[saddr] = val;
 283         break;
 284     case BONITO_BONGENCFG:
 285         if (!(s->regs[saddr] & 0x04) && (val & 0x04)) {
 286             reset = 1; /* bit 2 jump from 0 to 1 cause reset */
 287         }
 288         s->regs[saddr] = val;
 289         if (reset) {
 290             qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 291         }
 292         break;
 293     case BONITO_INTENSET:
 294         s->regs[BONITO_INTENSET] = val;
 295         s->regs[BONITO_INTEN] |= val;
 296         break;
 297     case BONITO_INTENCLR:
 298         s->regs[BONITO_INTENCLR] = val;
 299         s->regs[BONITO_INTEN] &= ~val;
 300         break;
 301     case BONITO_INTEN:
 302     case BONITO_INTISR:
 303         DPRINTF("write to readonly bonito register %x\n", saddr);
 304         break;
 305     default:
 306         DPRINTF("write to unknown bonito register %x\n", saddr);
 307         break;
 308     }
 309 }
 310
 311 static uint64_t bonito_readl(void *opaque, hwaddr addr,
 312                              unsigned size)
 313 {
 314     PCIBonitoState *s = opaque;
 315     uint32_t saddr;
 316
 317     saddr = addr >> 2;
 318
 319     DPRINTF("bonito_readl "TARGET_FMT_plx"\n", addr);
 320     switch (saddr) {
 321     case BONITO_INTISR:
 322         return s->regs[saddr];
 323     default:
 324         return s->regs[saddr];
 325     }
 326 }
 327
 328 static const MemoryRegionOps bonito_ops = {
 329     .read = bonito_readl,
 330     .write = bonito_writel,
 331     .endianness = DEVICE_NATIVE_ENDIAN,
 332     .valid = {
 333         .min_access_size = 4,
 334         .max_access_size = 4,
 335     },
 336 };
 337
 338 static void bonito_pciconf_writel(void *opaque, hwaddr addr,
 339                                   uint64_t val, unsigned size)
 340 {
 341     PCIBonitoState *s = opaque;
 342     PCIDevice *d = PCI_DEVICE(s);
 343
 344     DPRINTF("bonito_pciconf_writel "TARGET_FMT_plx" val %lx\n", addr, val);
 345     d->config_write(d, addr, val, 4);
 346 }
 347
 348 static uint64_t bonito_pciconf_readl(void *opaque, hwaddr addr,
 349                                      unsigned size)
 350 {
 351
 352     PCIBonitoState *s = opaque;
 353     PCIDevice *d = PCI_DEVICE(s);
 354
 355     DPRINTF("bonito_pciconf_readl "TARGET_FMT_plx"\n", addr);
 356     return d->config_read(d, addr, 4);
 357 }
 358
 359 /* north bridge PCI configure space. 0x1fe0 0000 - 0x1fe0 00ff */
 360
 361 static const MemoryRegionOps bonito_pciconf_ops = {
 362     .read = bonito_pciconf_readl,
 363     .write = bonito_pciconf_writel,
 364     .endianness = DEVICE_NATIVE_ENDIAN,
 365     .valid = {
 366         .min_access_size = 4,
 367         .max_access_size = 4,
 368     },
 369 };
 370
 371 static uint64_t bonito_ldma_readl(void *opaque, hwaddr addr,
 372                                   unsigned size)
 373 {
 374     uint32_t val;
 375     PCIBonitoState *s = opaque;
 376
 377     if (addr >= sizeof(s->bonldma)) {
 378         return 0;
 379     }
 380
 381     val = ((uint32_t *)(&s->bonldma))[addr / sizeof(uint32_t)];
 382
 383     return val;
 384 }
 385
 386 static void bonito_ldma_writel(void *opaque, hwaddr addr,
 387                                uint64_t val, unsigned size)
 388 {
 389     PCIBonitoState *s = opaque;
 390
 391     if (addr >= sizeof(s->bonldma)) {
 392         return;
 393     }
 394
 395     ((uint32_t *)(&s->bonldma))[addr / sizeof(uint32_t)] = val & 0xffffffff;
 396 }
 397
 398 static const MemoryRegionOps bonito_ldma_ops = {
 399     .read = bonito_ldma_readl,
 400     .write = bonito_ldma_writel,
 401     .endianness = DEVICE_NATIVE_ENDIAN,
 402     .valid = {
 403         .min_access_size = 4,
 404         .max_access_size = 4,
 405     },
 406 };
 407
 408 static uint64_t bonito_cop_readl(void *opaque, hwaddr addr,
 409                                  unsigned size)
 410 {
 411     uint32_t val;
 412     PCIBonitoState *s = opaque;
 413
 414     if (addr >= sizeof(s->boncop)) {
 415         return 0;
 416     }
 417
 418     val = ((uint32_t *)(&s->boncop))[addr / sizeof(uint32_t)];
 419
 420     return val;
 421 }
 422
 423 static void bonito_cop_writel(void *opaque, hwaddr addr,
 424                               uint64_t val, unsigned size)
 425 {
 426     PCIBonitoState *s = opaque;
 427
 428     if (addr >= sizeof(s->boncop)) {
 429         return;
 430     }
 431
 432     ((uint32_t *)(&s->boncop))[addr / sizeof(uint32_t)] = val & 0xffffffff;
 433 }
 434
 435 static const MemoryRegionOps bonito_cop_ops = {
 436     .read = bonito_cop_readl,
 437     .write = bonito_cop_writel,
 438     .endianness = DEVICE_NATIVE_ENDIAN,
 439     .valid = {
 440         .min_access_size = 4,
 441         .max_access_size = 4,
 442     },
 443 };
 444
 445 static uint32_t bonito_sbridge_pciaddr(void *opaque, hwaddr addr)
 446 {
 447     PCIBonitoState *s = opaque;
 448     PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
 449     uint32_t cfgaddr;
 450     uint32_t idsel;
 451     uint32_t devno;
 452     uint32_t funno;
 453     uint32_t regno;
 454     uint32_t pciaddr;
 455
 456     /* support type0 pci config */
 457     if ((s->regs[BONITO_PCIMAP_CFG] & 0x10000) != 0x0) {
 458         return 0xffffffff;
 459     }
 460
 461     cfgaddr = addr & 0xffff;
 462     cfgaddr |= (s->regs[BONITO_PCIMAP_CFG] & 0xffff) << 16;
 463
 464     idsel = (cfgaddr & BONITO_PCICONF_IDSEL_MASK) >>
 465              BONITO_PCICONF_IDSEL_OFFSET;
 466     devno = ctz32(idsel);
 467     funno = (cfgaddr & BONITO_PCICONF_FUN_MASK) >> BONITO_PCICONF_FUN_OFFSET;
 468     regno = (cfgaddr & BONITO_PCICONF_REG_MASK) >> BONITO_PCICONF_REG_OFFSET;
 469
 470     if (idsel == 0) {
 471         error_report("error in bonito pci config address 0x" TARGET_FMT_plx
 472                      ",pcimap_cfg=0x%x", addr, s->regs[BONITO_PCIMAP_CFG]);
 473         exit(1);
 474     }
 475     pciaddr = PCI_ADDR(pci_bus_num(phb->bus), devno, funno, regno);
 476     DPRINTF("cfgaddr %x pciaddr %x busno %x devno %d funno %d regno %d\n",
 477         cfgaddr, pciaddr, pci_bus_num(phb->bus), devno, funno, regno);
 478
 479     return pciaddr;
 480 }
 481
 482 static void bonito_spciconf_write(void *opaque, hwaddr addr, uint64_t val,
 483                                   unsigned size)
 484 {
 485     PCIBonitoState *s = opaque;
 486     PCIDevice *d = PCI_DEVICE(s);
 487     PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
 488     uint32_t pciaddr;
 489     uint16_t status;
 490
 491     DPRINTF("bonito_spciconf_write "TARGET_FMT_plx" size %d val %lx\n",
 492             addr, size, val);
 493
 494     pciaddr = bonito_sbridge_pciaddr(s, addr);
 495
 496     if (pciaddr == 0xffffffff) {
 497         return;
 498     }
 499
 500     /* set the pci address in s->config_reg */
 501     phb->config_reg = (pciaddr) | (1u << 31);
 502     pci_data_write(phb->bus, phb->config_reg, val, size);
 503
 504     /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
 505     status = pci_get_word(d->config + PCI_STATUS);
 506     status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
 507     pci_set_word(d->config + PCI_STATUS, status);
 508 }
 509
 510 static uint64_t bonito_spciconf_read(void *opaque, hwaddr addr, unsigned size)
 511 {
 512     PCIBonitoState *s = opaque;
 513     PCIDevice *d = PCI_DEVICE(s);
 514     PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
 515     uint32_t pciaddr;
 516     uint16_t status;
 517
 518     DPRINTF("bonito_spciconf_read "TARGET_FMT_plx" size %d\n", addr, size);
 519
 520     pciaddr = bonito_sbridge_pciaddr(s, addr);
 521
 522     if (pciaddr == 0xffffffff) {
 523         return MAKE_64BIT_MASK(0, size * 8);
 524     }
 525
 526     /* set the pci address in s->config_reg */
 527     phb->config_reg = (pciaddr) | (1u << 31);
 528
 529     /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
 530     status = pci_get_word(d->config + PCI_STATUS);
 531     status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
 532     pci_set_word(d->config + PCI_STATUS, status);
 533
 534     return pci_data_read(phb->bus, phb->config_reg, size);
 535 }
 536
 537 /* south bridge PCI configure space. 0x1fe8 0000 - 0x1fef ffff */
 538 static const MemoryRegionOps bonito_spciconf_ops = {
 539     .read = bonito_spciconf_read,
 540     .write = bonito_spciconf_write,
 541     .valid.min_access_size = 1,
 542     .valid.max_access_size = 4,
 543     .impl.min_access_size = 1,
 544     .impl.max_access_size = 4,
 545     .endianness = DEVICE_NATIVE_ENDIAN,
 546 };
 547
 548 #define BONITO_IRQ_BASE 32
 549
 550 static void pci_bonito_set_irq(void *opaque, int irq_num, int level)
 551 {
 552     BonitoState *s = opaque;
 553     qemu_irq *pic = s->pic;
 554     PCIBonitoState *bonito_state = s->pci_dev;
 555     int internal_irq = irq_num - BONITO_IRQ_BASE;
 556
 557     if (bonito_state->regs[BONITO_INTEDGE] & (1 << internal_irq)) {
 558         qemu_irq_pulse(*pic);
 559     } else {   /* level triggered */
 560         if (bonito_state->regs[BONITO_INTPOL] & (1 << internal_irq)) {
 561             qemu_irq_raise(*pic);
 562         } else {
 563             qemu_irq_lower(*pic);
 564         }
 565     }
 566 }
 567
 568 /* map the original irq (0~3) to bonito irq (16~47, but 16~31 are unused) */
 569 static int pci_bonito_map_irq(PCIDevice *pci_dev, int irq_num)
 570 {
 571     int slot;
 572
 573     slot = PCI_SLOT(pci_dev->devfn);
 574
 575     switch (slot) {
 576     case 5:   /* FULOONG2E_VIA_SLOT, SouthBridge, IDE, USB, ACPI, AC97, MC97 */
 577         return irq_num % 4 + BONITO_IRQ_BASE;
 578     case 6:   /* FULOONG2E_ATI_SLOT, VGA */
 579         return 4 + BONITO_IRQ_BASE;
 580     case 7:   /* FULOONG2E_RTL_SLOT, RTL8139 */
 581         return 5 + BONITO_IRQ_BASE;
 582     case 8 ... 12: /* PCI slot 1 to 4 */
 583         return (slot - 8 + irq_num) + 6 + BONITO_IRQ_BASE;
 584     default:  /* Unknown device, don't do any translation */
 585         return irq_num;
 586     }
 587 }
 588
 589 static void bonito_reset(void *opaque)
 590 {
 591     PCIBonitoState *s = opaque;
 592     uint32_t val = 0;
 593
 594     /* set the default value of north bridge registers */
 595
 596     s->regs[BONITO_BONPONCFG] = 0xc40;
 597     val = FIELD_DP32(val, BONGENCFG, PCIQUEUE, 1);
 598     val = FIELD_DP32(val, BONGENCFG, WRITEBEHIND, 1);
 599     val = FIELD_DP32(val, BONGENCFG, PREFETCH, 1);
 600     val = FIELD_DP32(val, BONGENCFG, UNCACHED, 1);
 601     val = FIELD_DP32(val, BONGENCFG, CPUSELFRESET, 1);
 602     s->regs[BONITO_BONGENCFG] = val;
 603
 604     s->regs[BONITO_IODEVCFG] = 0x2bff8010;
 605     s->regs[BONITO_SDCFG] = 0x255e0091;
 606
 607     s->regs[BONITO_GPIODATA] = 0x1ff;
 608     s->regs[BONITO_GPIOIE] = 0x1ff;
 609     s->regs[BONITO_DQCFG] = 0x8;
 610     s->regs[BONITO_MEMSIZE] = 0x10000000;
 611     s->regs[BONITO_PCIMAP] = 0x6140;
 612 }
 613
 614 static const VMStateDescription vmstate_bonito = {
 615     .name = "Bonito",
 616     .version_id = 1,
 617     .minimum_version_id = 1,
 618     .fields = (VMStateField[]) {
 619         VMSTATE_PCI_DEVICE(dev, PCIBonitoState),
 620         VMSTATE_END_OF_LIST()
 621     }
 622 };
 623
 624 static void bonito_pcihost_realize(DeviceState *dev, Error **errp)
 625 {
 626     PCIHostState *phb = PCI_HOST_BRIDGE(dev);
 627     BonitoState *bs = BONITO_PCI_HOST_BRIDGE(dev);
 628     MemoryRegion *pcimem_lo_alias = g_new(MemoryRegion, 3);
 629
 630     memory_region_init(&bs->pci_mem, OBJECT(dev), "pci.mem", BONITO_PCIHI_SIZE);
 631     phb->bus = pci_register_root_bus(dev, "pci",
 632                                      pci_bonito_set_irq, pci_bonito_map_irq,
 633                                      dev, &bs->pci_mem, get_system_io(),
 634                                      PCI_DEVFN(5, 0), 32, TYPE_PCI_BUS);
 635
 636     for (size_t i = 0; i < 3; i++) {
 637         char *name = g_strdup_printf("pci.lomem%zu", i);
 638
 639         memory_region_init_alias(&pcimem_lo_alias[i], NULL, name,
 640                                  &bs->pci_mem, i * 64 * MiB, 64 * MiB);
 641         memory_region_add_subregion(get_system_memory(),
 642                                     BONITO_PCILO_BASE + i * 64 * MiB,
 643                                     &pcimem_lo_alias[i]);
 644         g_free(name);
 645     }
 646
 647     create_unimplemented_device("pci.io", BONITO_PCIIO_BASE, 1 * MiB);
 648 }
 649
 650 static void bonito_realize(PCIDevice *dev, Error **errp)
 651 {
 652     PCIBonitoState *s = PCI_BONITO(dev);
 653     SysBusDevice *sysbus = SYS_BUS_DEVICE(s->pcihost);
 654     PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
 655     BonitoState *bs = BONITO_PCI_HOST_BRIDGE(s->pcihost);
 656     MemoryRegion *pcimem_alias = g_new(MemoryRegion, 1);
 657
 658     /*
 659      * Bonito North Bridge, built on FPGA,
 660      * VENDOR_ID/DEVICE_ID are "undefined"
 661      */
 662     pci_config_set_prog_interface(dev->config, 0x00);
 663
 664     /* set the north bridge register mapping */
 665     memory_region_init_io(&s->iomem, OBJECT(s), &bonito_ops, s,
 666                           "north-bridge-register", BONITO_INTERNAL_REG_SIZE);
 667     sysbus_init_mmio(sysbus, &s->iomem);
 668     sysbus_mmio_map(sysbus, 0, BONITO_INTERNAL_REG_BASE);
 669
 670     /* set the north bridge pci configure  mapping */
 671     memory_region_init_io(&phb->conf_mem, OBJECT(s), &bonito_pciconf_ops, s,
 672                           "north-bridge-pci-config", BONITO_PCICONFIG_SIZE);
 673     sysbus_init_mmio(sysbus, &phb->conf_mem);
 674     sysbus_mmio_map(sysbus, 1, BONITO_PCICONFIG_BASE);
 675
 676     /* set the south bridge pci configure  mapping */
 677     memory_region_init_io(&phb->data_mem, OBJECT(s), &bonito_spciconf_ops, s,
 678                           "south-bridge-pci-config", BONITO_SPCICONFIG_SIZE);
 679     sysbus_init_mmio(sysbus, &phb->data_mem);
 680     sysbus_mmio_map(sysbus, 2, BONITO_SPCICONFIG_BASE);
 681
 682     create_unimplemented_device("bonito", BONITO_REG_BASE, BONITO_REG_SIZE);
 683
 684     memory_region_init_io(&s->iomem_ldma, OBJECT(s), &bonito_ldma_ops, s,
 685                           "ldma", 0x100);
 686     sysbus_init_mmio(sysbus, &s->iomem_ldma);
 687     sysbus_mmio_map(sysbus, 3, 0x1fe00200);
 688
 689     /* PCI copier */
 690     memory_region_init_io(&s->iomem_cop, OBJECT(s), &bonito_cop_ops, s,
 691                           "cop", 0x100);
 692     sysbus_init_mmio(sysbus, &s->iomem_cop);
 693     sysbus_mmio_map(sysbus, 4, 0x1fe00300);
 694
 695     create_unimplemented_device("ROMCS", BONITO_FLASH_BASE, 60 * MiB);
 696
 697     /* Map PCI IO Space  0x1fd0 0000 - 0x1fd1 0000 */
 698     memory_region_init_alias(&s->bonito_pciio, OBJECT(s), "isa_mmio",
 699                              get_system_io(), 0, BONITO_PCIIO_SIZE);
 700     sysbus_init_mmio(sysbus, &s->bonito_pciio);
 701     sysbus_mmio_map(sysbus, 5, BONITO_PCIIO_BASE);
 702
 703     /* add pci local io mapping */
 704
 705     memory_region_init_alias(&s->bonito_localio, OBJECT(s), "IOCS[0]",
 706                              get_system_io(), 0, 256 * KiB);
 707     sysbus_init_mmio(sysbus, &s->bonito_localio);
 708     sysbus_mmio_map(sysbus, 6, BONITO_DEV_BASE);
 709     create_unimplemented_device("IOCS[1]", BONITO_DEV_BASE + 1 * 256 * KiB,
 710                                 256 * KiB);
 711     create_unimplemented_device("IOCS[2]", BONITO_DEV_BASE + 2 * 256 * KiB,
 712                                 256 * KiB);
 713     create_unimplemented_device("IOCS[3]", BONITO_DEV_BASE + 3 * 256 * KiB,
 714                                 256 * KiB);
 715
 716     memory_region_init_alias(pcimem_alias, NULL, "pci.mem.alias",
 717                              &bs->pci_mem, 0, BONITO_PCIHI_SIZE);
 718     memory_region_add_subregion(get_system_memory(),
 719                                 BONITO_PCIHI_BASE, pcimem_alias);
 720     create_unimplemented_device("PCI_2",
 721                                 (hwaddr)BONITO_PCIHI_BASE + BONITO_PCIHI_SIZE,
 722                                 2 * GiB);
 723
 724     /* set the default value of north bridge pci config */
 725     pci_set_word(dev->config + PCI_COMMAND, 0x0000);
 726     pci_set_word(dev->config + PCI_STATUS, 0x0000);
 727     pci_set_word(dev->config + PCI_SUBSYSTEM_VENDOR_ID, 0x0000);
 728     pci_set_word(dev->config + PCI_SUBSYSTEM_ID, 0x0000);
 729
 730     pci_set_byte(dev->config + PCI_INTERRUPT_LINE, 0x00);
 731     pci_config_set_interrupt_pin(dev->config, 0x01); /* interrupt pin A */
 732
 733     pci_set_byte(dev->config + PCI_MIN_GNT, 0x3c);
 734     pci_set_byte(dev->config + PCI_MAX_LAT, 0x00);
 735
 736     qemu_register_reset(bonito_reset, s);
 737 }
 738
 739 PCIBus *bonito_init(qemu_irq *pic)
 740 {
 741     DeviceState *dev;
 742     BonitoState *pcihost;
 743     PCIHostState *phb;
 744     PCIBonitoState *s;
 745     PCIDevice *d;
 746
 747     dev = qdev_new(TYPE_BONITO_PCI_HOST_BRIDGE);
 748     phb = PCI_HOST_BRIDGE(dev);
 749     pcihost = BONITO_PCI_HOST_BRIDGE(dev);
 750     pcihost->pic = pic;
 751     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 752
 753     d = pci_new(PCI_DEVFN(0, 0), TYPE_PCI_BONITO);
 754     s = PCI_BONITO(d);
 755     s->pcihost = pcihost;
 756     pcihost->pci_dev = s;
 757     pci_realize_and_unref(d, phb->bus, &error_fatal);
 758
 759     return phb->bus;
 760 }
 761
 762 static void bonito_class_init(ObjectClass *klass, void *data)
 763 {
 764     DeviceClass *dc = DEVICE_CLASS(klass);
 765     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 766
 767     k->realize = bonito_realize;
 768     k->vendor_id = 0xdf53;
 769     k->device_id = 0x00d5;
 770     k->revision = 0x01;
 771     k->class_id = PCI_CLASS_BRIDGE_HOST;
 772     dc->desc = "Host bridge";
 773     dc->vmsd = &vmstate_bonito;
 774     /*
 775      * PCI-facing part of the host bridge, not usable without the
 776      * host-facing part, which can't be device_add'ed, yet.
 777      */
 778     dc->user_creatable = false;
 779 }
 780
 781 static const TypeInfo bonito_info = {
 782     .name          = TYPE_PCI_BONITO,
 783     .parent        = TYPE_PCI_DEVICE,
 784     .instance_size = sizeof(PCIBonitoState),
 785     .class_init    = bonito_class_init,
 786     .interfaces = (InterfaceInfo[]) {
 787         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 788         { },
 789     },
 790 };
 791
 792 static void bonito_pcihost_class_init(ObjectClass *klass, void *data)
 793 {
 794     DeviceClass *dc = DEVICE_CLASS(klass);
 795
 796     dc->realize = bonito_pcihost_realize;
 797 }
 798
 799 static const TypeInfo bonito_pcihost_info = {
 800     .name          = TYPE_BONITO_PCI_HOST_BRIDGE,
 801     .parent        = TYPE_PCI_HOST_BRIDGE,
 802     .instance_size = sizeof(BonitoState),
 803     .class_init    = bonito_pcihost_class_init,
 804 };
 805
 806 static void bonito_register_types(void)
 807 {
 808     type_register_static(&bonito_pcihost_info);
 809     type_register_static(&bonito_info);
 810 }
 811
 812 type_init(bonito_register_types)