hw/pci-host/designware.c

   1 /*
   2  * Copyright (c) 2018, Impinj, Inc.
   3  *
   4  * Designware PCIe IP block emulation
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see
  18  * <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qapi/error.h"
  23 #include "qemu/module.h"
  24 #include "hw/pci/msi.h"
  25 #include "hw/pci/pci_bridge.h"
  26 #include "hw/pci/pci_host.h"
  27 #include "hw/pci/pcie_port.h"
  28 #include "hw/pci-host/designware.h"
  29
  30 #define DESIGNWARE_PCIE_PORT_LINK_CONTROL          0x710
  31 #define DESIGNWARE_PCIE_PHY_DEBUG_R1               0x72C
  32 #define DESIGNWARE_PCIE_PHY_DEBUG_R1_XMLH_LINK_UP  BIT(4)
  33 #define DESIGNWARE_PCIE_LINK_WIDTH_SPEED_CONTROL   0x80C
  34 #define DESIGNWARE_PCIE_PORT_LOGIC_SPEED_CHANGE    BIT(17)
  35 #define DESIGNWARE_PCIE_MSI_ADDR_LO                0x820
  36 #define DESIGNWARE_PCIE_MSI_ADDR_HI                0x824
  37 #define DESIGNWARE_PCIE_MSI_INTR0_ENABLE           0x828
  38 #define DESIGNWARE_PCIE_MSI_INTR0_MASK             0x82C
  39 #define DESIGNWARE_PCIE_MSI_INTR0_STATUS           0x830
  40 #define DESIGNWARE_PCIE_ATU_VIEWPORT               0x900
  41 #define DESIGNWARE_PCIE_ATU_REGION_INBOUND         BIT(31)
  42 #define DESIGNWARE_PCIE_ATU_CR1                    0x904
  43 #define DESIGNWARE_PCIE_ATU_TYPE_MEM               (0x0 << 0)
  44 #define DESIGNWARE_PCIE_ATU_CR2                    0x908
  45 #define DESIGNWARE_PCIE_ATU_ENABLE                 BIT(31)
  46 #define DESIGNWARE_PCIE_ATU_LOWER_BASE             0x90C
  47 #define DESIGNWARE_PCIE_ATU_UPPER_BASE             0x910
  48 #define DESIGNWARE_PCIE_ATU_LIMIT                  0x914
  49 #define DESIGNWARE_PCIE_ATU_LOWER_TARGET           0x918
  50 #define DESIGNWARE_PCIE_ATU_BUS(x)                 (((x) >> 24) & 0xff)
  51 #define DESIGNWARE_PCIE_ATU_DEVFN(x)               (((x) >> 16) & 0xff)
  52 #define DESIGNWARE_PCIE_ATU_UPPER_TARGET           0x91C
  53
  54 static DesignwarePCIEHost *
  55 designware_pcie_root_to_host(DesignwarePCIERoot *root)
  56 {
  57     BusState *bus = qdev_get_parent_bus(DEVICE(root));
  58     return DESIGNWARE_PCIE_HOST(bus->parent);
  59 }
  60
  61 static void designware_pcie_root_msi_write(void *opaque, hwaddr addr,
  62                                            uint64_t val, unsigned len)
  63 {
  64     DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(opaque);
  65     DesignwarePCIEHost *host = designware_pcie_root_to_host(root);
  66
  67     root->msi.intr[0].status |= BIT(val) & root->msi.intr[0].enable;
  68
  69     if (root->msi.intr[0].status & ~root->msi.intr[0].mask) {
  70         qemu_set_irq(host->pci.irqs[0], 1);
  71     }
  72 }
  73
  74 static const MemoryRegionOps designware_pci_host_msi_ops = {
  75     .write = designware_pcie_root_msi_write,
  76     .endianness = DEVICE_LITTLE_ENDIAN,
  77     .valid = {
  78         .min_access_size = 4,
  79         .max_access_size = 4,
  80     },
  81 };
  82
  83 static void designware_pcie_root_update_msi_mapping(DesignwarePCIERoot *root)
  84
  85 {
  86     MemoryRegion *mem   = &root->msi.iomem;
  87     const uint64_t base = root->msi.base;
  88     const bool enable   = root->msi.intr[0].enable;
  89
  90     memory_region_set_address(mem, base);
  91     memory_region_set_enabled(mem, enable);
  92 }
  93
  94 static DesignwarePCIEViewport *
  95 designware_pcie_root_get_current_viewport(DesignwarePCIERoot *root)
  96 {
  97     const unsigned int idx = root->atu_viewport & 0xF;
  98     const unsigned int dir =
  99         !!(root->atu_viewport & DESIGNWARE_PCIE_ATU_REGION_INBOUND);
 100     return &root->viewports[dir][idx];
 101 }
 102
 103 static uint32_t
 104 designware_pcie_root_config_read(PCIDevice *d, uint32_t address, int len)
 105 {
 106     DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(d);
 107     DesignwarePCIEViewport *viewport =
 108         designware_pcie_root_get_current_viewport(root);
 109
 110     uint32_t val;
 111
 112     switch (address) {
 113     case DESIGNWARE_PCIE_PORT_LINK_CONTROL:
 114         /*
 115          * Linux guest uses this register only to configure number of
 116          * PCIE lane (which in our case is irrelevant) and doesn't
 117          * really care about the value it reads from this register
 118          */
 119         val = 0xDEADBEEF;
 120         break;
 121
 122     case DESIGNWARE_PCIE_LINK_WIDTH_SPEED_CONTROL:
 123         /*
 124          * To make sure that any code in guest waiting for speed
 125          * change does not time out we always report
 126          * PORT_LOGIC_SPEED_CHANGE as set
 127          */
 128         val = DESIGNWARE_PCIE_PORT_LOGIC_SPEED_CHANGE;
 129         break;
 130
 131     case DESIGNWARE_PCIE_MSI_ADDR_LO:
 132         val = root->msi.base;
 133         break;
 134
 135     case DESIGNWARE_PCIE_MSI_ADDR_HI:
 136         val = root->msi.base >> 32;
 137         break;
 138
 139     case DESIGNWARE_PCIE_MSI_INTR0_ENABLE:
 140         val = root->msi.intr[0].enable;
 141         break;
 142
 143     case DESIGNWARE_PCIE_MSI_INTR0_MASK:
 144         val = root->msi.intr[0].mask;
 145         break;
 146
 147     case DESIGNWARE_PCIE_MSI_INTR0_STATUS:
 148         val = root->msi.intr[0].status;
 149         break;
 150
 151     case DESIGNWARE_PCIE_PHY_DEBUG_R1:
 152         val = DESIGNWARE_PCIE_PHY_DEBUG_R1_XMLH_LINK_UP;
 153         break;
 154
 155     case DESIGNWARE_PCIE_ATU_VIEWPORT:
 156         val = root->atu_viewport;
 157         break;
 158
 159     case DESIGNWARE_PCIE_ATU_LOWER_BASE:
 160         val = viewport->base;
 161         break;
 162
 163     case DESIGNWARE_PCIE_ATU_UPPER_BASE:
 164         val = viewport->base >> 32;
 165         break;
 166
 167     case DESIGNWARE_PCIE_ATU_LOWER_TARGET:
 168         val = viewport->target;
 169         break;
 170
 171     case DESIGNWARE_PCIE_ATU_UPPER_TARGET:
 172         val = viewport->target >> 32;
 173         break;
 174
 175     case DESIGNWARE_PCIE_ATU_LIMIT:
 176         val = viewport->limit;
 177         break;
 178
 179     case DESIGNWARE_PCIE_ATU_CR1:
 180     case DESIGNWARE_PCIE_ATU_CR2:          /* FALLTHROUGH */
 181         val = viewport->cr[(address - DESIGNWARE_PCIE_ATU_CR1) /
 182                            sizeof(uint32_t)];
 183         break;
 184
 185     default:
 186         val = pci_default_read_config(d, address, len);
 187         break;
 188     }
 189
 190     return val;
 191 }
 192
 193 static uint64_t designware_pcie_root_data_access(void *opaque, hwaddr addr,
 194                                                  uint64_t *val, unsigned len)
 195 {
 196     DesignwarePCIEViewport *viewport = opaque;
 197     DesignwarePCIERoot *root = viewport->root;
 198
 199     const uint8_t busnum = DESIGNWARE_PCIE_ATU_BUS(viewport->target);
 200     const uint8_t devfn  = DESIGNWARE_PCIE_ATU_DEVFN(viewport->target);
 201     PCIBus    *pcibus    = pci_get_bus(PCI_DEVICE(root));
 202     PCIDevice *pcidev    = pci_find_device(pcibus, busnum, devfn);
 203
 204     if (pcidev) {
 205         addr &= pci_config_size(pcidev) - 1;
 206
 207         if (val) {
 208             pci_host_config_write_common(pcidev, addr,
 209                                          pci_config_size(pcidev),
 210                                          *val, len);
 211         } else {
 212             return pci_host_config_read_common(pcidev, addr,
 213                                                pci_config_size(pcidev),
 214                                                len);
 215         }
 216     }
 217
 218     return UINT64_MAX;
 219 }
 220
 221 static uint64_t designware_pcie_root_data_read(void *opaque, hwaddr addr,
 222                                                unsigned len)
 223 {
 224     return designware_pcie_root_data_access(opaque, addr, NULL, len);
 225 }
 226
 227 static void designware_pcie_root_data_write(void *opaque, hwaddr addr,
 228                                             uint64_t val, unsigned len)
 229 {
 230     designware_pcie_root_data_access(opaque, addr, &val, len);
 231 }
 232
 233 static const MemoryRegionOps designware_pci_host_conf_ops = {
 234     .read = designware_pcie_root_data_read,
 235     .write = designware_pcie_root_data_write,
 236     .endianness = DEVICE_LITTLE_ENDIAN,
 237     .valid = {
 238         .min_access_size = 1,
 239         .max_access_size = 4,
 240     },
 241 };
 242
 243 static void designware_pcie_update_viewport(DesignwarePCIERoot *root,
 244                                             DesignwarePCIEViewport *viewport)
 245 {
 246     const uint64_t target = viewport->target;
 247     const uint64_t base   = viewport->base;
 248     const uint64_t size   = (uint64_t)viewport->limit - base + 1;
 249     const bool enabled    = viewport->cr[1] & DESIGNWARE_PCIE_ATU_ENABLE;
 250
 251     MemoryRegion *current, *other;
 252
 253     if (viewport->cr[0] == DESIGNWARE_PCIE_ATU_TYPE_MEM) {
 254         current = &viewport->mem;
 255         other   = &viewport->cfg;
 256         memory_region_set_alias_offset(current, target);
 257     } else {
 258         current = &viewport->cfg;
 259         other   = &viewport->mem;
 260     }
 261
 262     /*
 263      * An outbound viewport can be reconfigure from being MEM to CFG,
 264      * to account for that we disable the "other" memory region that
 265      * becomes unused due to that fact.
 266      */
 267     memory_region_set_enabled(other, false);
 268     if (enabled) {
 269         memory_region_set_size(current, size);
 270         memory_region_set_address(current, base);
 271     }
 272     memory_region_set_enabled(current, enabled);
 273 }
 274
 275 static void designware_pcie_root_config_write(PCIDevice *d, uint32_t address,
 276                                               uint32_t val, int len)
 277 {
 278     DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(d);
 279     DesignwarePCIEHost *host = designware_pcie_root_to_host(root);
 280     DesignwarePCIEViewport *viewport =
 281         designware_pcie_root_get_current_viewport(root);
 282
 283     switch (address) {
 284     case DESIGNWARE_PCIE_PORT_LINK_CONTROL:
 285     case DESIGNWARE_PCIE_LINK_WIDTH_SPEED_CONTROL:
 286     case DESIGNWARE_PCIE_PHY_DEBUG_R1:
 287         /* No-op */
 288         break;
 289
 290     case DESIGNWARE_PCIE_MSI_ADDR_LO:
 291         root->msi.base &= 0xFFFFFFFF00000000ULL;
 292         root->msi.base |= val;
 293         break;
 294
 295     case DESIGNWARE_PCIE_MSI_ADDR_HI:
 296         root->msi.base &= 0x00000000FFFFFFFFULL;
 297         root->msi.base |= (uint64_t)val << 32;
 298         break;
 299
 300     case DESIGNWARE_PCIE_MSI_INTR0_ENABLE:
 301         root->msi.intr[0].enable = val;
 302         designware_pcie_root_update_msi_mapping(root);
 303         break;
 304
 305     case DESIGNWARE_PCIE_MSI_INTR0_MASK:
 306         root->msi.intr[0].mask = val;
 307         break;
 308
 309     case DESIGNWARE_PCIE_MSI_INTR0_STATUS:
 310         root->msi.intr[0].status ^= val;
 311         if (!root->msi.intr[0].status) {
 312             qemu_set_irq(host->pci.irqs[0], 0);
 313         }
 314         break;
 315
 316     case DESIGNWARE_PCIE_ATU_VIEWPORT:
 317         root->atu_viewport = val;
 318         break;
 319
 320     case DESIGNWARE_PCIE_ATU_LOWER_BASE:
 321         viewport->base &= 0xFFFFFFFF00000000ULL;
 322         viewport->base |= val;
 323         break;
 324
 325     case DESIGNWARE_PCIE_ATU_UPPER_BASE:
 326         viewport->base &= 0x00000000FFFFFFFFULL;
 327         viewport->base |= (uint64_t)val << 32;
 328         break;
 329
 330     case DESIGNWARE_PCIE_ATU_LOWER_TARGET:
 331         viewport->target &= 0xFFFFFFFF00000000ULL;
 332         viewport->target |= val;
 333         break;
 334
 335     case DESIGNWARE_PCIE_ATU_UPPER_TARGET:
 336         viewport->target &= 0x00000000FFFFFFFFULL;
 337         viewport->target |= val;
 338         break;
 339
 340     case DESIGNWARE_PCIE_ATU_LIMIT:
 341         viewport->limit = val;
 342         break;
 343
 344     case DESIGNWARE_PCIE_ATU_CR1:
 345         viewport->cr[0] = val;
 346         break;
 347     case DESIGNWARE_PCIE_ATU_CR2:
 348         viewport->cr[1] = val;
 349         designware_pcie_update_viewport(root, viewport);
 350         break;
 351
 352     default:
 353         pci_bridge_write_config(d, address, val, len);
 354         break;
 355     }
 356 }
 357
 358 static char *designware_pcie_viewport_name(const char *direction,
 359                                            unsigned int i,
 360                                            const char *type)
 361 {
 362     return g_strdup_printf("PCI %s Viewport %u [%s]",
 363                            direction, i, type);
 364 }
 365
 366 static void designware_pcie_root_realize(PCIDevice *dev, Error **errp)
 367 {
 368     DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(dev);
 369     DesignwarePCIEHost *host = designware_pcie_root_to_host(root);
 370     MemoryRegion *address_space = &host->pci.memory;
 371     PCIBridge *br = PCI_BRIDGE(dev);
 372     DesignwarePCIEViewport *viewport;
 373     /*
 374      * Dummy values used for initial configuration of MemoryRegions
 375      * that belong to a given viewport
 376      */
 377     const hwaddr dummy_offset = 0;
 378     const uint64_t dummy_size = 4;
 379     size_t i;
 380
 381     br->bus_name  = "dw-pcie";
 382
 383     pci_set_word(dev->config + PCI_COMMAND,
 384                  PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 385
 386     pci_config_set_interrupt_pin(dev->config, 1);
 387     pci_bridge_initfn(dev, TYPE_PCIE_BUS);
 388
 389     pcie_port_init_reg(dev);
 390
 391     pcie_cap_init(dev, 0x70, PCI_EXP_TYPE_ROOT_PORT,
 392                   0, &error_fatal);
 393
 394     msi_nonbroken = true;
 395     msi_init(dev, 0x50, 32, true, true, &error_fatal);
 396
 397     for (i = 0; i < DESIGNWARE_PCIE_NUM_VIEWPORTS; i++) {
 398         MemoryRegion *source, *destination, *mem;
 399         const char *direction;
 400         char *name;
 401
 402         viewport = &root->viewports[DESIGNWARE_PCIE_VIEWPORT_INBOUND][i];
 403         viewport->inbound = true;
 404         viewport->base    = 0x0000000000000000ULL;
 405         viewport->target  = 0x0000000000000000ULL;
 406         viewport->limit   = UINT32_MAX;
 407         viewport->cr[0]   = DESIGNWARE_PCIE_ATU_TYPE_MEM;
 408
 409         source      = &host->pci.address_space_root;
 410         destination = get_system_memory();
 411         direction   = "Inbound";
 412
 413         /*
 414          * Configure MemoryRegion implementing PCI -> CPU memory
 415          * access
 416          */
 417         mem  = &viewport->mem;
 418         name = designware_pcie_viewport_name(direction, i, "MEM");
 419         memory_region_init_alias(mem, OBJECT(root), name, destination,
 420                                  dummy_offset, dummy_size);
 421         memory_region_add_subregion_overlap(source, dummy_offset, mem, -1);
 422         memory_region_set_enabled(mem, false);
 423         g_free(name);
 424
 425         viewport = &root->viewports[DESIGNWARE_PCIE_VIEWPORT_OUTBOUND][i];
 426         viewport->root    = root;
 427         viewport->inbound = false;
 428         viewport->base    = 0x0000000000000000ULL;
 429         viewport->target  = 0x0000000000000000ULL;
 430         viewport->limit   = UINT32_MAX;
 431         viewport->cr[0]   = DESIGNWARE_PCIE_ATU_TYPE_MEM;
 432
 433         destination = &host->pci.memory;
 434         direction   = "Outbound";
 435         source      = get_system_memory();
 436
 437         /*
 438          * Configure MemoryRegion implementing CPU -> PCI memory
 439          * access
 440          */
 441         mem  = &viewport->mem;
 442         name = designware_pcie_viewport_name(direction, i, "MEM");
 443         memory_region_init_alias(mem, OBJECT(root), name, destination,
 444                                  dummy_offset, dummy_size);
 445         memory_region_add_subregion(source, dummy_offset, mem);
 446         memory_region_set_enabled(mem, false);
 447         g_free(name);
 448
 449         /*
 450          * Configure MemoryRegion implementing access to configuration
 451          * space
 452          */
 453         mem  = &viewport->cfg;
 454         name = designware_pcie_viewport_name(direction, i, "CFG");
 455         memory_region_init_io(&viewport->cfg, OBJECT(root),
 456                               &designware_pci_host_conf_ops,
 457                               viewport, name, dummy_size);
 458         memory_region_add_subregion(source, dummy_offset, mem);
 459         memory_region_set_enabled(mem, false);
 460         g_free(name);
 461     }
 462
 463     /*
 464      * If no inbound iATU windows are configured, HW defaults to
 465      * letting inbound TLPs to pass in. We emulate that by exlicitly
 466      * configuring first inbound window to cover all of target's
 467      * address space.
 468      *
 469      * NOTE: This will not work correctly for the case when first
 470      * configured inbound window is window 0
 471      */
 472     viewport = &root->viewports[DESIGNWARE_PCIE_VIEWPORT_INBOUND][0];
 473     viewport->cr[1] = DESIGNWARE_PCIE_ATU_ENABLE;
 474     designware_pcie_update_viewport(root, viewport);
 475
 476     memory_region_init_io(&root->msi.iomem, OBJECT(root),
 477                           &designware_pci_host_msi_ops,
 478                           root, "pcie-msi", 0x4);
 479     /*
 480      * We initially place MSI interrupt I/O region a adress 0 and
 481      * disable it. It'll be later moved to correct offset and enabled
 482      * in designware_pcie_root_update_msi_mapping() as a part of
 483      * initialization done by guest OS
 484      */
 485     memory_region_add_subregion(address_space, dummy_offset, &root->msi.iomem);
 486     memory_region_set_enabled(&root->msi.iomem, false);
 487 }
 488
 489 static void designware_pcie_set_irq(void *opaque, int irq_num, int level)
 490 {
 491     DesignwarePCIEHost *host = DESIGNWARE_PCIE_HOST(opaque);
 492
 493     qemu_set_irq(host->pci.irqs[irq_num], level);
 494 }
 495
 496 static const char *
 497 designware_pcie_host_root_bus_path(PCIHostState *host_bridge, PCIBus *rootbus)
 498 {
 499     return "0000:00";
 500 }
 501
 502 static const VMStateDescription vmstate_designware_pcie_msi_bank = {
 503     .name = "designware-pcie-msi-bank",
 504     .version_id = 1,
 505     .minimum_version_id = 1,
 506     .fields = (VMStateField[]) {
 507         VMSTATE_UINT32(enable, DesignwarePCIEMSIBank),
 508         VMSTATE_UINT32(mask, DesignwarePCIEMSIBank),
 509         VMSTATE_UINT32(status, DesignwarePCIEMSIBank),
 510         VMSTATE_END_OF_LIST()
 511     }
 512 };
 513
 514 static const VMStateDescription vmstate_designware_pcie_msi = {
 515     .name = "designware-pcie-msi",
 516     .version_id = 1,
 517     .minimum_version_id = 1,
 518     .fields = (VMStateField[]) {
 519         VMSTATE_UINT64(base, DesignwarePCIEMSI),
 520         VMSTATE_STRUCT_ARRAY(intr,
 521                              DesignwarePCIEMSI,
 522                              DESIGNWARE_PCIE_NUM_MSI_BANKS,
 523                              1,
 524                              vmstate_designware_pcie_msi_bank,
 525                              DesignwarePCIEMSIBank),
 526         VMSTATE_END_OF_LIST()
 527     }
 528 };
 529
 530 static const VMStateDescription vmstate_designware_pcie_viewport = {
 531     .name = "designware-pcie-viewport",
 532     .version_id = 1,
 533     .minimum_version_id = 1,
 534     .fields = (VMStateField[]) {
 535         VMSTATE_UINT64(base, DesignwarePCIEViewport),
 536         VMSTATE_UINT64(target, DesignwarePCIEViewport),
 537         VMSTATE_UINT32(limit, DesignwarePCIEViewport),
 538         VMSTATE_UINT32_ARRAY(cr, DesignwarePCIEViewport, 2),
 539         VMSTATE_END_OF_LIST()
 540     }
 541 };
 542
 543 static const VMStateDescription vmstate_designware_pcie_root = {
 544     .name = "designware-pcie-root",
 545     .version_id = 1,
 546     .minimum_version_id = 1,
 547     .fields = (VMStateField[]) {
 548         VMSTATE_PCI_DEVICE(parent_obj, PCIBridge),
 549         VMSTATE_UINT32(atu_viewport, DesignwarePCIERoot),
 550         VMSTATE_STRUCT_2DARRAY(viewports,
 551                                DesignwarePCIERoot,
 552                                2,
 553                                DESIGNWARE_PCIE_NUM_VIEWPORTS,
 554                                1,
 555                                vmstate_designware_pcie_viewport,
 556                                DesignwarePCIEViewport),
 557         VMSTATE_STRUCT(msi,
 558                        DesignwarePCIERoot,
 559                        1,
 560                        vmstate_designware_pcie_msi,
 561                        DesignwarePCIEMSI),
 562         VMSTATE_END_OF_LIST()
 563     }
 564 };
 565
 566 static void designware_pcie_root_class_init(ObjectClass *klass, void *data)
 567 {
 568     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 569     DeviceClass *dc = DEVICE_CLASS(klass);
 570
 571     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 572
 573     k->vendor_id = PCI_VENDOR_ID_SYNOPSYS;
 574     k->device_id = 0xABCD;
 575     k->revision = 0;
 576     k->class_id = PCI_CLASS_BRIDGE_PCI;
 577     k->is_bridge = true;
 578     k->exit = pci_bridge_exitfn;
 579     k->realize = designware_pcie_root_realize;
 580     k->config_read = designware_pcie_root_config_read;
 581     k->config_write = designware_pcie_root_config_write;
 582
 583     dc->reset = pci_bridge_reset;
 584     /*
 585      * PCI-facing part of the host bridge, not usable without the
 586      * host-facing part, which can't be device_add'ed, yet.
 587      */
 588     dc->user_creatable = false;
 589     dc->vmsd = &vmstate_designware_pcie_root;
 590 }
 591
 592 static uint64_t designware_pcie_host_mmio_read(void *opaque, hwaddr addr,
 593                                                unsigned int size)
 594 {
 595     PCIHostState *pci = PCI_HOST_BRIDGE(opaque);
 596     PCIDevice *device = pci_find_device(pci->bus, 0, 0);
 597
 598     return pci_host_config_read_common(device,
 599                                        addr,
 600                                        pci_config_size(device),
 601                                        size);
 602 }
 603
 604 static void designware_pcie_host_mmio_write(void *opaque, hwaddr addr,
 605                                             uint64_t val, unsigned int size)
 606 {
 607     PCIHostState *pci = PCI_HOST_BRIDGE(opaque);
 608     PCIDevice *device = pci_find_device(pci->bus, 0, 0);
 609
 610     return pci_host_config_write_common(device,
 611                                         addr,
 612                                         pci_config_size(device),
 613                                         val, size);
 614 }
 615
 616 static const MemoryRegionOps designware_pci_mmio_ops = {
 617     .read       = designware_pcie_host_mmio_read,
 618     .write      = designware_pcie_host_mmio_write,
 619     .endianness = DEVICE_LITTLE_ENDIAN,
 620     .impl = {
 621         /*
 622          * Our device would not work correctly if the guest was doing
 623          * unaligned access. This might not be a limitation on the real
 624          * device but in practice there is no reason for a guest to access
 625          * this device unaligned.
 626          */
 627         .min_access_size = 4,
 628         .max_access_size = 4,
 629         .unaligned = false,
 630     },
 631 };
 632
 633 static AddressSpace *designware_pcie_host_set_iommu(PCIBus *bus, void *opaque,
 634                                                     int devfn)
 635 {
 636     DesignwarePCIEHost *s = DESIGNWARE_PCIE_HOST(opaque);
 637
 638     return &s->pci.address_space;
 639 }
 640
 641 static void designware_pcie_host_realize(DeviceState *dev, Error **errp)
 642 {
 643     PCIHostState *pci = PCI_HOST_BRIDGE(dev);
 644     DesignwarePCIEHost *s = DESIGNWARE_PCIE_HOST(dev);
 645     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 646     size_t i;
 647
 648     for (i = 0; i < ARRAY_SIZE(s->pci.irqs); i++) {
 649         sysbus_init_irq(sbd, &s->pci.irqs[i]);
 650     }
 651
 652     memory_region_init_io(&s->mmio,
 653                           OBJECT(s),
 654                           &designware_pci_mmio_ops,
 655                           s,
 656                           "pcie.reg", 4 * 1024);
 657     sysbus_init_mmio(sbd, &s->mmio);
 658
 659     memory_region_init(&s->pci.io, OBJECT(s), "pcie-pio", 16);
 660     memory_region_init(&s->pci.memory, OBJECT(s),
 661                        "pcie-bus-memory",
 662                        UINT64_MAX);
 663
 664     pci->bus = pci_register_root_bus(dev, "pcie",
 665                                      designware_pcie_set_irq,
 666                                      pci_swizzle_map_irq_fn,
 667                                      s,
 668                                      &s->pci.memory,
 669                                      &s->pci.io,
 670                                      0, 4,
 671                                      TYPE_PCIE_BUS);
 672
 673     memory_region_init(&s->pci.address_space_root,
 674                        OBJECT(s),
 675                        "pcie-bus-address-space-root",
 676                        UINT64_MAX);
 677     memory_region_add_subregion(&s->pci.address_space_root,
 678                                 0x0, &s->pci.memory);
 679     address_space_init(&s->pci.address_space,
 680                        &s->pci.address_space_root,
 681                        "pcie-bus-address-space");
 682     pci_setup_iommu(pci->bus, designware_pcie_host_set_iommu, s);
 683
 684     qdev_set_parent_bus(DEVICE(&s->root), BUS(pci->bus));
 685     qdev_init_nofail(DEVICE(&s->root));
 686 }
 687
 688 static const VMStateDescription vmstate_designware_pcie_host = {
 689     .name = "designware-pcie-host",
 690     .version_id = 1,
 691     .minimum_version_id = 1,
 692     .fields = (VMStateField[]) {
 693         VMSTATE_STRUCT(root,
 694                        DesignwarePCIEHost,
 695                        1,
 696                        vmstate_designware_pcie_root,
 697                        DesignwarePCIERoot),
 698         VMSTATE_END_OF_LIST()
 699     }
 700 };
 701
 702 static void designware_pcie_host_class_init(ObjectClass *klass, void *data)
 703 {
 704     DeviceClass *dc = DEVICE_CLASS(klass);
 705     PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
 706
 707     hc->root_bus_path = designware_pcie_host_root_bus_path;
 708     dc->realize = designware_pcie_host_realize;
 709     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 710     dc->fw_name = "pci";
 711     dc->vmsd = &vmstate_designware_pcie_host;
 712 }
 713
 714 static void designware_pcie_host_init(Object *obj)
 715 {
 716     DesignwarePCIEHost *s = DESIGNWARE_PCIE_HOST(obj);
 717     DesignwarePCIERoot *root = &s->root;
 718
 719     object_initialize_child(obj, "root",  root, sizeof(*root),
 720                             TYPE_DESIGNWARE_PCIE_ROOT, &error_abort, NULL);
 721     qdev_prop_set_int32(DEVICE(root), "addr", PCI_DEVFN(0, 0));
 722     qdev_prop_set_bit(DEVICE(root), "multifunction", false);
 723 }
 724
 725 static const TypeInfo designware_pcie_root_info = {
 726     .name = TYPE_DESIGNWARE_PCIE_ROOT,
 727     .parent = TYPE_PCI_BRIDGE,
 728     .instance_size = sizeof(DesignwarePCIERoot),
 729     .class_init = designware_pcie_root_class_init,
 730     .interfaces = (InterfaceInfo[]) {
 731         { INTERFACE_PCIE_DEVICE },
 732         { }
 733     },
 734 };
 735
 736 static const TypeInfo designware_pcie_host_info = {
 737     .name       = TYPE_DESIGNWARE_PCIE_HOST,
 738     .parent     = TYPE_PCI_HOST_BRIDGE,
 739     .instance_size = sizeof(DesignwarePCIEHost),
 740     .instance_init = designware_pcie_host_init,
 741     .class_init = designware_pcie_host_class_init,
 742 };
 743
 744 static void designware_pcie_register(void)
 745 {
 746     type_register_static(&designware_pcie_root_info);
 747     type_register_static(&designware_pcie_host_info);
 748 }
 749 type_init(designware_pcie_register)