2 * QEMU PowerPC PowerNV (POWER9) PHB4 model
4 * Copyright (c) 2018-2020, IBM Corporation.
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
9 #include "qemu/osdep.h"
10 #include "qapi/error.h"
11 #include "qemu-common.h"
13 #include "target/ppc/cpu.h"
14 #include "hw/ppc/fdt.h"
15 #include "hw/pci-host/pnv_phb4_regs.h"
16 #include "hw/pci-host/pnv_phb4.h"
17 #include "hw/ppc/pnv_xscom.h"
18 #include "hw/pci/pci_bridge.h"
19 #include "hw/pci/pci_bus.h"
20 #include "hw/ppc/pnv.h"
21 #include "hw/qdev-properties.h"
22 #include "sysemu/sysemu.h"
26 #define phb_pec_error(pec, fmt, ...) \
27 qemu_log_mask(LOG_GUEST_ERROR, "phb4_pec[%d:%d]: " fmt "\n", \
28 (pec)->chip_id, (pec)->index, ## __VA_ARGS__)
31 static uint64_t pnv_pec_nest_xscom_read(void *opaque
, hwaddr addr
,
34 PnvPhb4PecState
*pec
= PNV_PHB4_PEC(opaque
);
35 uint32_t reg
= addr
>> 3;
37 /* TODO: add list of allowed registers and error out if not */
38 return pec
->nest_regs
[reg
];
41 static void pnv_pec_nest_xscom_write(void *opaque
, hwaddr addr
,
42 uint64_t val
, unsigned size
)
44 PnvPhb4PecState
*pec
= PNV_PHB4_PEC(opaque
);
45 uint32_t reg
= addr
>> 3;
48 case PEC_NEST_PBCQ_HW_CONFIG
:
49 case PEC_NEST_DROP_PRIO_CTRL
:
50 case PEC_NEST_PBCQ_ERR_INJECT
:
51 case PEC_NEST_PCI_NEST_CLK_TRACE_CTL
:
52 case PEC_NEST_PBCQ_PMON_CTRL
:
53 case PEC_NEST_PBCQ_PBUS_ADDR_EXT
:
54 case PEC_NEST_PBCQ_PRED_VEC_TIMEOUT
:
55 case PEC_NEST_CAPP_CTRL
:
56 case PEC_NEST_PBCQ_READ_STK_OVR
:
57 case PEC_NEST_PBCQ_WRITE_STK_OVR
:
58 case PEC_NEST_PBCQ_STORE_STK_OVR
:
59 case PEC_NEST_PBCQ_RETRY_BKOFF_CTRL
:
60 pec
->nest_regs
[reg
] = val
;
63 phb_pec_error(pec
, "%s @0x%"HWADDR_PRIx
"=%"PRIx64
"\n", __func__
,
68 static const MemoryRegionOps pnv_pec_nest_xscom_ops
= {
69 .read
= pnv_pec_nest_xscom_read
,
70 .write
= pnv_pec_nest_xscom_write
,
71 .valid
.min_access_size
= 8,
72 .valid
.max_access_size
= 8,
73 .impl
.min_access_size
= 8,
74 .impl
.max_access_size
= 8,
75 .endianness
= DEVICE_BIG_ENDIAN
,
78 static uint64_t pnv_pec_pci_xscom_read(void *opaque
, hwaddr addr
,
81 PnvPhb4PecState
*pec
= PNV_PHB4_PEC(opaque
);
82 uint32_t reg
= addr
>> 3;
84 /* TODO: add list of allowed registers and error out if not */
85 return pec
->pci_regs
[reg
];
88 static void pnv_pec_pci_xscom_write(void *opaque
, hwaddr addr
,
89 uint64_t val
, unsigned size
)
91 PnvPhb4PecState
*pec
= PNV_PHB4_PEC(opaque
);
92 uint32_t reg
= addr
>> 3;
95 case PEC_PCI_PBAIB_HW_CONFIG
:
96 case PEC_PCI_PBAIB_READ_STK_OVR
:
97 pec
->pci_regs
[reg
] = val
;
100 phb_pec_error(pec
, "%s @0x%"HWADDR_PRIx
"=%"PRIx64
"\n", __func__
,
105 static const MemoryRegionOps pnv_pec_pci_xscom_ops
= {
106 .read
= pnv_pec_pci_xscom_read
,
107 .write
= pnv_pec_pci_xscom_write
,
108 .valid
.min_access_size
= 8,
109 .valid
.max_access_size
= 8,
110 .impl
.min_access_size
= 8,
111 .impl
.max_access_size
= 8,
112 .endianness
= DEVICE_BIG_ENDIAN
,
115 static void pnv_pec_default_phb_realize(PnvPhb4PecState
*pec
,
119 PnvPHB4
*phb
= PNV_PHB4(qdev_new(TYPE_PNV_PHB4
));
120 int phb_id
= pnv_phb4_pec_get_phb_id(pec
, stack_no
);
122 object_property_set_link(OBJECT(phb
), "pec", OBJECT(pec
),
124 object_property_set_int(OBJECT(phb
), "chip-id", pec
->chip_id
,
126 object_property_set_int(OBJECT(phb
), "index", phb_id
,
129 if (!sysbus_realize(SYS_BUS_DEVICE(phb
), errp
)) {
133 /* Add a single Root port if running with defaults */
134 pnv_phb_attach_root_port(PCI_HOST_BRIDGE(phb
),
135 PNV_PHB4_PEC_GET_CLASS(pec
)->rp_model
);
139 static void pnv_pec_realize(DeviceState
*dev
, Error
**errp
)
141 PnvPhb4PecState
*pec
= PNV_PHB4_PEC(dev
);
142 PnvPhb4PecClass
*pecc
= PNV_PHB4_PEC_GET_CLASS(pec
);
146 if (pec
->index
>= PNV_CHIP_GET_CLASS(pec
->chip
)->num_pecs
) {
147 error_setg(errp
, "invalid PEC index: %d", pec
->index
);
151 pec
->num_phbs
= pecc
->num_phbs
[pec
->index
];
153 /* Create PHBs if running with defaults */
154 if (defaults_enabled()) {
155 for (i
= 0; i
< pec
->num_phbs
; i
++) {
156 pnv_pec_default_phb_realize(pec
, i
, errp
);
160 /* Initialize the XSCOM regions for the PEC registers */
161 snprintf(name
, sizeof(name
), "xscom-pec-%d.%d-nest", pec
->chip_id
,
163 pnv_xscom_region_init(&pec
->nest_regs_mr
, OBJECT(dev
),
164 &pnv_pec_nest_xscom_ops
, pec
, name
,
165 PHB4_PEC_NEST_REGS_COUNT
);
167 snprintf(name
, sizeof(name
), "xscom-pec-%d.%d-pci", pec
->chip_id
,
169 pnv_xscom_region_init(&pec
->pci_regs_mr
, OBJECT(dev
),
170 &pnv_pec_pci_xscom_ops
, pec
, name
,
171 PHB4_PEC_PCI_REGS_COUNT
);
174 static int pnv_pec_dt_xscom(PnvXScomInterface
*dev
, void *fdt
,
177 PnvPhb4PecState
*pec
= PNV_PHB4_PEC(dev
);
178 PnvPhb4PecClass
*pecc
= PNV_PHB4_PEC_GET_CLASS(dev
);
179 uint32_t nbase
= pecc
->xscom_nest_base(pec
);
180 uint32_t pbase
= pecc
->xscom_pci_base(pec
);
185 cpu_to_be32(pecc
->xscom_nest_size
),
187 cpu_to_be32(pecc
->xscom_pci_size
),
190 name
= g_strdup_printf("pbcq@%x", nbase
);
191 offset
= fdt_add_subnode(fdt
, xscom_offset
, name
);
195 _FDT((fdt_setprop(fdt
, offset
, "reg", reg
, sizeof(reg
))));
197 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,pec-index", pec
->index
)));
198 _FDT((fdt_setprop_cell(fdt
, offset
, "#address-cells", 1)));
199 _FDT((fdt_setprop_cell(fdt
, offset
, "#size-cells", 0)));
200 _FDT((fdt_setprop(fdt
, offset
, "compatible", pecc
->compat
,
201 pecc
->compat_size
)));
203 for (i
= 0; i
< pec
->num_phbs
; i
++) {
204 int phb_id
= pnv_phb4_pec_get_phb_id(pec
, i
);
207 name
= g_strdup_printf("stack@%x", i
);
208 stk_offset
= fdt_add_subnode(fdt
, offset
, name
);
211 _FDT((fdt_setprop(fdt
, stk_offset
, "compatible", pecc
->stk_compat
,
212 pecc
->stk_compat_size
)));
213 _FDT((fdt_setprop_cell(fdt
, stk_offset
, "reg", i
)));
214 _FDT((fdt_setprop_cell(fdt
, stk_offset
, "ibm,phb-index", phb_id
)));
220 static Property pnv_pec_properties
[] = {
221 DEFINE_PROP_UINT32("index", PnvPhb4PecState
, index
, 0),
222 DEFINE_PROP_UINT32("chip-id", PnvPhb4PecState
, chip_id
, 0),
223 DEFINE_PROP_LINK("chip", PnvPhb4PecState
, chip
, TYPE_PNV_CHIP
,
225 DEFINE_PROP_END_OF_LIST(),
228 static uint32_t pnv_pec_xscom_pci_base(PnvPhb4PecState
*pec
)
230 return PNV9_XSCOM_PEC_PCI_BASE
+ 0x1000000 * pec
->index
;
233 static uint32_t pnv_pec_xscom_nest_base(PnvPhb4PecState
*pec
)
235 return PNV9_XSCOM_PEC_NEST_BASE
+ 0x400 * pec
->index
;
243 static const uint32_t pnv_pec_num_phbs
[] = { 1, 2, 3 };
245 static void pnv_pec_class_init(ObjectClass
*klass
, void *data
)
247 DeviceClass
*dc
= DEVICE_CLASS(klass
);
248 PnvXScomInterfaceClass
*xdc
= PNV_XSCOM_INTERFACE_CLASS(klass
);
249 PnvPhb4PecClass
*pecc
= PNV_PHB4_PEC_CLASS(klass
);
250 static const char compat
[] = "ibm,power9-pbcq";
251 static const char stk_compat
[] = "ibm,power9-phb-stack";
253 xdc
->dt_xscom
= pnv_pec_dt_xscom
;
255 dc
->realize
= pnv_pec_realize
;
256 device_class_set_props(dc
, pnv_pec_properties
);
257 dc
->user_creatable
= false;
259 pecc
->xscom_nest_base
= pnv_pec_xscom_nest_base
;
260 pecc
->xscom_pci_base
= pnv_pec_xscom_pci_base
;
261 pecc
->xscom_nest_size
= PNV9_XSCOM_PEC_NEST_SIZE
;
262 pecc
->xscom_pci_size
= PNV9_XSCOM_PEC_PCI_SIZE
;
263 pecc
->compat
= compat
;
264 pecc
->compat_size
= sizeof(compat
);
265 pecc
->stk_compat
= stk_compat
;
266 pecc
->stk_compat_size
= sizeof(stk_compat
);
267 pecc
->version
= PNV_PHB4_VERSION
;
268 pecc
->num_phbs
= pnv_pec_num_phbs
;
269 pecc
->rp_model
= TYPE_PNV_PHB4_ROOT_PORT
;
272 static const TypeInfo pnv_pec_type_info
= {
273 .name
= TYPE_PNV_PHB4_PEC
,
274 .parent
= TYPE_DEVICE
,
275 .instance_size
= sizeof(PnvPhb4PecState
),
276 .class_init
= pnv_pec_class_init
,
277 .class_size
= sizeof(PnvPhb4PecClass
),
278 .interfaces
= (InterfaceInfo
[]) {
279 { TYPE_PNV_XSCOM_INTERFACE
},
284 static void pnv_pec_register_types(void)
286 type_register_static(&pnv_pec_type_info
);
289 type_init(pnv_pec_register_types
);