hw/pci-host/pnv_phb4_pec.c

   1 /*
   2  * QEMU PowerPC PowerNV (POWER9) PHB4 model
   3  *
   4  * Copyright (c) 2018-2020, IBM Corporation.
   5  *
   6  * This code is licensed under the GPL version 2 or later. See the
   7  * COPYING file in the top-level directory.
   8  */
   9 #include "qemu/osdep.h"
  10 #include "qapi/error.h"
  11 #include "qemu-common.h"
  12 #include "qemu/log.h"
  13 #include "target/ppc/cpu.h"
  14 #include "hw/ppc/fdt.h"
  15 #include "hw/pci-host/pnv_phb4_regs.h"
  16 #include "hw/pci-host/pnv_phb4.h"
  17 #include "hw/ppc/pnv_xscom.h"
  18 #include "hw/pci/pci_bridge.h"
  19 #include "hw/pci/pci_bus.h"
  20 #include "hw/ppc/pnv.h"
  21 #include "hw/qdev-properties.h"
  22 #include "sysemu/sysemu.h"
  23
  24 #include <libfdt.h>
  25
  26 #define phb_pec_error(pec, fmt, ...)                                    \
  27     qemu_log_mask(LOG_GUEST_ERROR, "phb4_pec[%d:%d]: " fmt "\n",        \
  28                   (pec)->chip_id, (pec)->index, ## __VA_ARGS__)
  29
  30
  31 static uint64_t pnv_pec_nest_xscom_read(void *opaque, hwaddr addr,
  32                                         unsigned size)
  33 {
  34     PnvPhb4PecState *pec = PNV_PHB4_PEC(opaque);
  35     uint32_t reg = addr >> 3;
  36
  37     /* TODO: add list of allowed registers and error out if not */
  38     return pec->nest_regs[reg];
  39 }
  40
  41 static void pnv_pec_nest_xscom_write(void *opaque, hwaddr addr,
  42                                      uint64_t val, unsigned size)
  43 {
  44     PnvPhb4PecState *pec = PNV_PHB4_PEC(opaque);
  45     uint32_t reg = addr >> 3;
  46
  47     switch (reg) {
  48     case PEC_NEST_PBCQ_HW_CONFIG:
  49     case PEC_NEST_DROP_PRIO_CTRL:
  50     case PEC_NEST_PBCQ_ERR_INJECT:
  51     case PEC_NEST_PCI_NEST_CLK_TRACE_CTL:
  52     case PEC_NEST_PBCQ_PMON_CTRL:
  53     case PEC_NEST_PBCQ_PBUS_ADDR_EXT:
  54     case PEC_NEST_PBCQ_PRED_VEC_TIMEOUT:
  55     case PEC_NEST_CAPP_CTRL:
  56     case PEC_NEST_PBCQ_READ_STK_OVR:
  57     case PEC_NEST_PBCQ_WRITE_STK_OVR:
  58     case PEC_NEST_PBCQ_STORE_STK_OVR:
  59     case PEC_NEST_PBCQ_RETRY_BKOFF_CTRL:
  60         pec->nest_regs[reg] = val;
  61         break;
  62     default:
  63         phb_pec_error(pec, "%s @0x%"HWADDR_PRIx"=%"PRIx64"\n", __func__,
  64                       addr, val);
  65     }
  66 }
  67
  68 static const MemoryRegionOps pnv_pec_nest_xscom_ops = {
  69     .read = pnv_pec_nest_xscom_read,
  70     .write = pnv_pec_nest_xscom_write,
  71     .valid.min_access_size = 8,
  72     .valid.max_access_size = 8,
  73     .impl.min_access_size = 8,
  74     .impl.max_access_size = 8,
  75     .endianness = DEVICE_BIG_ENDIAN,
  76 };
  77
  78 static uint64_t pnv_pec_pci_xscom_read(void *opaque, hwaddr addr,
  79                                        unsigned size)
  80 {
  81     PnvPhb4PecState *pec = PNV_PHB4_PEC(opaque);
  82     uint32_t reg = addr >> 3;
  83
  84     /* TODO: add list of allowed registers and error out if not */
  85     return pec->pci_regs[reg];
  86 }
  87
  88 static void pnv_pec_pci_xscom_write(void *opaque, hwaddr addr,
  89                                     uint64_t val, unsigned size)
  90 {
  91     PnvPhb4PecState *pec = PNV_PHB4_PEC(opaque);
  92     uint32_t reg = addr >> 3;
  93
  94     switch (reg) {
  95     case PEC_PCI_PBAIB_HW_CONFIG:
  96     case PEC_PCI_PBAIB_READ_STK_OVR:
  97         pec->pci_regs[reg] = val;
  98         break;
  99     default:
 100         phb_pec_error(pec, "%s @0x%"HWADDR_PRIx"=%"PRIx64"\n", __func__,
 101                       addr, val);
 102     }
 103 }
 104
 105 static const MemoryRegionOps pnv_pec_pci_xscom_ops = {
 106     .read = pnv_pec_pci_xscom_read,
 107     .write = pnv_pec_pci_xscom_write,
 108     .valid.min_access_size = 8,
 109     .valid.max_access_size = 8,
 110     .impl.min_access_size = 8,
 111     .impl.max_access_size = 8,
 112     .endianness = DEVICE_BIG_ENDIAN,
 113 };
 114
 115 static void pnv_pec_default_phb_realize(PnvPhb4PecState *pec,
 116                                         int stack_no,
 117                                         Error **errp)
 118 {
 119     PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
 120     PnvPHB4 *phb = PNV_PHB4(qdev_new(pecc->phb_type));
 121     int phb_id = pnv_phb4_pec_get_phb_id(pec, stack_no);
 122
 123     object_property_set_link(OBJECT(phb), "pec", OBJECT(pec),
 124                              &error_abort);
 125     object_property_set_int(OBJECT(phb), "chip-id", pec->chip_id,
 126                             &error_fatal);
 127     object_property_set_int(OBJECT(phb), "index", phb_id,
 128                             &error_fatal);
 129
 130     if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) {
 131         return;
 132     }
 133
 134     /* Add a single Root port if running with defaults */
 135     pnv_phb_attach_root_port(PCI_HOST_BRIDGE(phb), pecc->rp_model);
 136 }
 137
 138 static void pnv_pec_realize(DeviceState *dev, Error **errp)
 139 {
 140     PnvPhb4PecState *pec = PNV_PHB4_PEC(dev);
 141     PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
 142     char name[64];
 143     int i;
 144
 145     if (pec->index >= PNV_CHIP_GET_CLASS(pec->chip)->num_pecs) {
 146         error_setg(errp, "invalid PEC index: %d", pec->index);
 147         return;
 148     }
 149
 150     pec->num_phbs = pecc->num_phbs[pec->index];
 151
 152     /* Create PHBs if running with defaults */
 153     if (defaults_enabled()) {
 154         for (i = 0; i < pec->num_phbs; i++) {
 155             pnv_pec_default_phb_realize(pec, i, errp);
 156         }
 157     }
 158
 159     /* Initialize the XSCOM regions for the PEC registers */
 160     snprintf(name, sizeof(name), "xscom-pec-%d.%d-nest", pec->chip_id,
 161              pec->index);
 162     pnv_xscom_region_init(&pec->nest_regs_mr, OBJECT(dev),
 163                           &pnv_pec_nest_xscom_ops, pec, name,
 164                           PHB4_PEC_NEST_REGS_COUNT);
 165
 166     snprintf(name, sizeof(name), "xscom-pec-%d.%d-pci", pec->chip_id,
 167              pec->index);
 168     pnv_xscom_region_init(&pec->pci_regs_mr, OBJECT(dev),
 169                           &pnv_pec_pci_xscom_ops, pec, name,
 170                           PHB4_PEC_PCI_REGS_COUNT);
 171 }
 172
 173 static int pnv_pec_dt_xscom(PnvXScomInterface *dev, void *fdt,
 174                             int xscom_offset)
 175 {
 176     PnvPhb4PecState *pec = PNV_PHB4_PEC(dev);
 177     PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(dev);
 178     uint32_t nbase = pecc->xscom_nest_base(pec);
 179     uint32_t pbase = pecc->xscom_pci_base(pec);
 180     int offset, i;
 181     char *name;
 182     uint32_t reg[] = {
 183         cpu_to_be32(nbase),
 184         cpu_to_be32(pecc->xscom_nest_size),
 185         cpu_to_be32(pbase),
 186         cpu_to_be32(pecc->xscom_pci_size),
 187     };
 188
 189     name = g_strdup_printf("pbcq@%x", nbase);
 190     offset = fdt_add_subnode(fdt, xscom_offset, name);
 191     _FDT(offset);
 192     g_free(name);
 193
 194     _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))));
 195
 196     _FDT((fdt_setprop_cell(fdt, offset, "ibm,pec-index", pec->index)));
 197     _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 1)));
 198     _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 0)));
 199     _FDT((fdt_setprop(fdt, offset, "compatible", pecc->compat,
 200                       pecc->compat_size)));
 201
 202     for (i = 0; i < pec->num_phbs; i++) {
 203         int phb_id = pnv_phb4_pec_get_phb_id(pec, i);
 204         int stk_offset;
 205
 206         name = g_strdup_printf("stack@%x", i);
 207         stk_offset = fdt_add_subnode(fdt, offset, name);
 208         _FDT(stk_offset);
 209         g_free(name);
 210         _FDT((fdt_setprop(fdt, stk_offset, "compatible", pecc->stk_compat,
 211                           pecc->stk_compat_size)));
 212         _FDT((fdt_setprop_cell(fdt, stk_offset, "reg", i)));
 213         _FDT((fdt_setprop_cell(fdt, stk_offset, "ibm,phb-index", phb_id)));
 214     }
 215
 216     return 0;
 217 }
 218
 219 static Property pnv_pec_properties[] = {
 220         DEFINE_PROP_UINT32("index", PnvPhb4PecState, index, 0),
 221         DEFINE_PROP_UINT32("chip-id", PnvPhb4PecState, chip_id, 0),
 222         DEFINE_PROP_LINK("chip", PnvPhb4PecState, chip, TYPE_PNV_CHIP,
 223                          PnvChip *),
 224         DEFINE_PROP_END_OF_LIST(),
 225 };
 226
 227 static uint32_t pnv_pec_xscom_pci_base(PnvPhb4PecState *pec)
 228 {
 229     return PNV9_XSCOM_PEC_PCI_BASE + 0x1000000 * pec->index;
 230 }
 231
 232 static uint32_t pnv_pec_xscom_nest_base(PnvPhb4PecState *pec)
 233 {
 234     return PNV9_XSCOM_PEC_NEST_BASE + 0x400 * pec->index;
 235 }
 236
 237 /*
 238  * PEC0 -> 1 phb
 239  * PEC1 -> 2 phb
 240  * PEC2 -> 3 phbs
 241  */
 242 static const uint32_t pnv_pec_num_phbs[] = { 1, 2, 3 };
 243
 244 static void pnv_pec_class_init(ObjectClass *klass, void *data)
 245 {
 246     DeviceClass *dc = DEVICE_CLASS(klass);
 247     PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass);
 248     PnvPhb4PecClass *pecc = PNV_PHB4_PEC_CLASS(klass);
 249     static const char compat[] = "ibm,power9-pbcq";
 250     static const char stk_compat[] = "ibm,power9-phb-stack";
 251
 252     xdc->dt_xscom = pnv_pec_dt_xscom;
 253
 254     dc->realize = pnv_pec_realize;
 255     device_class_set_props(dc, pnv_pec_properties);
 256     dc->user_creatable = false;
 257
 258     pecc->xscom_nest_base = pnv_pec_xscom_nest_base;
 259     pecc->xscom_pci_base  = pnv_pec_xscom_pci_base;
 260     pecc->xscom_nest_size = PNV9_XSCOM_PEC_NEST_SIZE;
 261     pecc->xscom_pci_size  = PNV9_XSCOM_PEC_PCI_SIZE;
 262     pecc->compat = compat;
 263     pecc->compat_size = sizeof(compat);
 264     pecc->stk_compat = stk_compat;
 265     pecc->stk_compat_size = sizeof(stk_compat);
 266     pecc->version = PNV_PHB4_VERSION;
 267     pecc->phb_type = TYPE_PNV_PHB4;
 268     pecc->num_phbs = pnv_pec_num_phbs;
 269     pecc->rp_model = TYPE_PNV_PHB4_ROOT_PORT;
 270 }
 271
 272 static const TypeInfo pnv_pec_type_info = {
 273     .name          = TYPE_PNV_PHB4_PEC,
 274     .parent        = TYPE_DEVICE,
 275     .instance_size = sizeof(PnvPhb4PecState),
 276     .class_init    = pnv_pec_class_init,
 277     .class_size    = sizeof(PnvPhb4PecClass),
 278     .interfaces    = (InterfaceInfo[]) {
 279         { TYPE_PNV_XSCOM_INTERFACE },
 280         { }
 281     }
 282 };
 283
 284 /*
 285  * POWER10 definitions
 286  */
 287
 288 static uint32_t pnv_phb5_pec_xscom_pci_base(PnvPhb4PecState *pec)
 289 {
 290     return PNV10_XSCOM_PEC_PCI_BASE + 0x1000000 * pec->index;
 291 }
 292
 293 static uint32_t pnv_phb5_pec_xscom_nest_base(PnvPhb4PecState *pec)
 294 {
 295     /* index goes down ... */
 296     return PNV10_XSCOM_PEC_NEST_BASE - 0x1000000 * pec->index;
 297 }
 298
 299 /*
 300  * PEC0 -> 3 stacks
 301  * PEC1 -> 3 stacks
 302  */
 303 static const uint32_t pnv_phb5_pec_num_stacks[] = { 3, 3 };
 304
 305 static void pnv_phb5_pec_class_init(ObjectClass *klass, void *data)
 306 {
 307     PnvPhb4PecClass *pecc = PNV_PHB4_PEC_CLASS(klass);
 308     static const char compat[] = "ibm,power10-pbcq";
 309     static const char stk_compat[] = "ibm,power10-phb-stack";
 310
 311     pecc->xscom_nest_base = pnv_phb5_pec_xscom_nest_base;
 312     pecc->xscom_pci_base  = pnv_phb5_pec_xscom_pci_base;
 313     pecc->xscom_nest_size = PNV10_XSCOM_PEC_NEST_SIZE;
 314     pecc->xscom_pci_size  = PNV10_XSCOM_PEC_PCI_SIZE;
 315     pecc->compat = compat;
 316     pecc->compat_size = sizeof(compat);
 317     pecc->stk_compat = stk_compat;
 318     pecc->stk_compat_size = sizeof(stk_compat);
 319     pecc->version = PNV_PHB5_VERSION;
 320     pecc->phb_type = TYPE_PNV_PHB5;
 321     pecc->num_phbs = pnv_phb5_pec_num_stacks;
 322     pecc->rp_model = TYPE_PNV_PHB5_ROOT_PORT;
 323 }
 324
 325 static const TypeInfo pnv_phb5_pec_type_info = {
 326     .name          = TYPE_PNV_PHB5_PEC,
 327     .parent        = TYPE_PNV_PHB4_PEC,
 328     .instance_size = sizeof(PnvPhb4PecState),
 329     .class_init    = pnv_phb5_pec_class_init,
 330     .class_size    = sizeof(PnvPhb4PecClass),
 331     .interfaces    = (InterfaceInfo[]) {
 332         { TYPE_PNV_XSCOM_INTERFACE },
 333         { }
 334     }
 335 };
 336
 337 static void pnv_pec_register_types(void)
 338 {
 339     type_register_static(&pnv_pec_type_info);
 340     type_register_static(&pnv_phb5_pec_type_info);
 341 }
 342
 343 type_init(pnv_pec_register_types);