hw/pci-host/ppce500.c

   1 /*
   2  * QEMU PowerPC E500 embedded processors pci controller emulation
   3  *
   4  * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
   5  *
   6  * Author: Yu Liu,     <yu.liu@freescale.com>
   7  *
   8  * This file is derived from hw/ppc4xx_pci.c,
   9  * the copyright for that material belongs to the original owners.
  10  *
  11  * This is free software; you can redistribute it and/or modify
  12  * it under the terms of  the GNU General  Public License as published by
  13  * the Free Software Foundation;  either version 2 of the  License, or
  14  * (at your option) any later version.
  15  */
  16
  17 #include "qemu/osdep.h"
  18 #include "hw/hw.h"
  19 #include "hw/irq.h"
  20 #include "hw/ppc/e500-ccsr.h"
  21 #include "hw/pci/pci.h"
  22 #include "hw/pci/pci_host.h"
  23 #include "qemu/bswap.h"
  24 #include "qemu/module.h"
  25 #include "hw/pci-host/ppce500.h"
  26
  27 #ifdef DEBUG_PCI
  28 #define pci_debug(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__)
  29 #else
  30 #define pci_debug(fmt, ...)
  31 #endif
  32
  33 #define PCIE500_CFGADDR       0x0
  34 #define PCIE500_CFGDATA       0x4
  35 #define PCIE500_REG_BASE      0xC00
  36 #define PCIE500_ALL_SIZE      0x1000
  37 #define PCIE500_REG_SIZE      (PCIE500_ALL_SIZE - PCIE500_REG_BASE)
  38
  39 #define PCIE500_PCI_IOLEN     0x10000ULL
  40
  41 #define PPCE500_PCI_CONFIG_ADDR         0x0
  42 #define PPCE500_PCI_CONFIG_DATA         0x4
  43 #define PPCE500_PCI_INTACK              0x8
  44
  45 #define PPCE500_PCI_OW1                 (0xC20 - PCIE500_REG_BASE)
  46 #define PPCE500_PCI_OW2                 (0xC40 - PCIE500_REG_BASE)
  47 #define PPCE500_PCI_OW3                 (0xC60 - PCIE500_REG_BASE)
  48 #define PPCE500_PCI_OW4                 (0xC80 - PCIE500_REG_BASE)
  49 #define PPCE500_PCI_IW3                 (0xDA0 - PCIE500_REG_BASE)
  50 #define PPCE500_PCI_IW2                 (0xDC0 - PCIE500_REG_BASE)
  51 #define PPCE500_PCI_IW1                 (0xDE0 - PCIE500_REG_BASE)
  52
  53 #define PPCE500_PCI_GASKET_TIMR         (0xE20 - PCIE500_REG_BASE)
  54
  55 #define PCI_POTAR               0x0
  56 #define PCI_POTEAR              0x4
  57 #define PCI_POWBAR              0x8
  58 #define PCI_POWAR               0x10
  59
  60 #define PCI_PITAR               0x0
  61 #define PCI_PIWBAR              0x8
  62 #define PCI_PIWBEAR             0xC
  63 #define PCI_PIWAR               0x10
  64
  65 #define PPCE500_PCI_NR_POBS     5
  66 #define PPCE500_PCI_NR_PIBS     3
  67
  68 #define PIWAR_EN                0x80000000      /* Enable */
  69 #define PIWAR_PF                0x20000000      /* prefetch */
  70 #define PIWAR_TGI_LOCAL         0x00f00000      /* target - local memory */
  71 #define PIWAR_READ_SNOOP        0x00050000
  72 #define PIWAR_WRITE_SNOOP       0x00005000
  73 #define PIWAR_SZ_MASK           0x0000003f
  74
  75 struct  pci_outbound {
  76     uint32_t potar;
  77     uint32_t potear;
  78     uint32_t powbar;
  79     uint32_t powar;
  80     MemoryRegion mem;
  81 };
  82
  83 struct pci_inbound {
  84     uint32_t pitar;
  85     uint32_t piwbar;
  86     uint32_t piwbear;
  87     uint32_t piwar;
  88     MemoryRegion mem;
  89 };
  90
  91 #define TYPE_PPC_E500_PCI_HOST_BRIDGE "e500-pcihost"
  92
  93 #define PPC_E500_PCI_HOST_BRIDGE(obj) \
  94     OBJECT_CHECK(PPCE500PCIState, (obj), TYPE_PPC_E500_PCI_HOST_BRIDGE)
  95
  96 struct PPCE500PCIState {
  97     PCIHostState parent_obj;
  98
  99     struct pci_outbound pob[PPCE500_PCI_NR_POBS];
 100     struct pci_inbound pib[PPCE500_PCI_NR_PIBS];
 101     uint32_t gasket_time;
 102     qemu_irq irq[PCI_NUM_PINS];
 103     uint32_t irq_num[PCI_NUM_PINS];
 104     uint32_t first_slot;
 105     uint32_t first_pin_irq;
 106     AddressSpace bm_as;
 107     MemoryRegion bm;
 108     /* mmio maps */
 109     MemoryRegion container;
 110     MemoryRegion iomem;
 111     MemoryRegion pio;
 112     MemoryRegion busmem;
 113 };
 114
 115 #define TYPE_PPC_E500_PCI_BRIDGE "e500-host-bridge"
 116 #define PPC_E500_PCI_BRIDGE(obj) \
 117     OBJECT_CHECK(PPCE500PCIBridgeState, (obj), TYPE_PPC_E500_PCI_BRIDGE)
 118
 119 struct PPCE500PCIBridgeState {
 120     /*< private >*/
 121     PCIDevice parent;
 122     /*< public >*/
 123
 124     MemoryRegion bar0;
 125 };
 126
 127 typedef struct PPCE500PCIBridgeState PPCE500PCIBridgeState;
 128 typedef struct PPCE500PCIState PPCE500PCIState;
 129
 130 static uint64_t pci_reg_read4(void *opaque, hwaddr addr,
 131                               unsigned size)
 132 {
 133     PPCE500PCIState *pci = opaque;
 134     unsigned long win;
 135     uint32_t value = 0;
 136     int idx;
 137
 138     win = addr & 0xfe0;
 139
 140     switch (win) {
 141     case PPCE500_PCI_OW1:
 142     case PPCE500_PCI_OW2:
 143     case PPCE500_PCI_OW3:
 144     case PPCE500_PCI_OW4:
 145         idx = (addr >> 5) & 0x7;
 146         switch (addr & 0x1F) {
 147         case PCI_POTAR:
 148             value = pci->pob[idx].potar;
 149             break;
 150         case PCI_POTEAR:
 151             value = pci->pob[idx].potear;
 152             break;
 153         case PCI_POWBAR:
 154             value = pci->pob[idx].powbar;
 155             break;
 156         case PCI_POWAR:
 157             value = pci->pob[idx].powar;
 158             break;
 159         default:
 160             break;
 161         }
 162         break;
 163
 164     case PPCE500_PCI_IW3:
 165     case PPCE500_PCI_IW2:
 166     case PPCE500_PCI_IW1:
 167         idx = ((addr >> 5) & 0x3) - 1;
 168         switch (addr & 0x1F) {
 169         case PCI_PITAR:
 170             value = pci->pib[idx].pitar;
 171             break;
 172         case PCI_PIWBAR:
 173             value = pci->pib[idx].piwbar;
 174             break;
 175         case PCI_PIWBEAR:
 176             value = pci->pib[idx].piwbear;
 177             break;
 178         case PCI_PIWAR:
 179             value = pci->pib[idx].piwar;
 180             break;
 181         default:
 182             break;
 183         };
 184         break;
 185
 186     case PPCE500_PCI_GASKET_TIMR:
 187         value = pci->gasket_time;
 188         break;
 189
 190     default:
 191         break;
 192     }
 193
 194     pci_debug("%s: win:%lx(addr:" TARGET_FMT_plx ") -> value:%x\n", __func__,
 195               win, addr, value);
 196     return value;
 197 }
 198
 199 /* DMA mapping */
 200 static void e500_update_piw(PPCE500PCIState *pci, int idx)
 201 {
 202     uint64_t tar = ((uint64_t)pci->pib[idx].pitar) << 12;
 203     uint64_t wbar = ((uint64_t)pci->pib[idx].piwbar) << 12;
 204     uint64_t war = pci->pib[idx].piwar;
 205     uint64_t size = 2ULL << (war & PIWAR_SZ_MASK);
 206     MemoryRegion *address_space_mem = get_system_memory();
 207     MemoryRegion *mem = &pci->pib[idx].mem;
 208     MemoryRegion *bm = &pci->bm;
 209     char *name;
 210
 211     if (memory_region_is_mapped(mem)) {
 212         /* Before we modify anything, unmap and destroy the region */
 213         memory_region_del_subregion(bm, mem);
 214         object_unparent(OBJECT(mem));
 215     }
 216
 217     if (!(war & PIWAR_EN)) {
 218         /* Not enabled, nothing to do */
 219         return;
 220     }
 221
 222     name = g_strdup_printf("PCI Inbound Window %d", idx);
 223     memory_region_init_alias(mem, OBJECT(pci), name, address_space_mem, tar,
 224                              size);
 225     memory_region_add_subregion_overlap(bm, wbar, mem, -1);
 226     g_free(name);
 227
 228     pci_debug("%s: Added window of size=%#lx from PCI=%#lx to CPU=%#lx\n",
 229               __func__, size, wbar, tar);
 230 }
 231
 232 /* BAR mapping */
 233 static void e500_update_pow(PPCE500PCIState *pci, int idx)
 234 {
 235     uint64_t tar = ((uint64_t)pci->pob[idx].potar) << 12;
 236     uint64_t wbar = ((uint64_t)pci->pob[idx].powbar) << 12;
 237     uint64_t war = pci->pob[idx].powar;
 238     uint64_t size = 2ULL << (war & PIWAR_SZ_MASK);
 239     MemoryRegion *mem = &pci->pob[idx].mem;
 240     MemoryRegion *address_space_mem = get_system_memory();
 241     char *name;
 242
 243     if (memory_region_is_mapped(mem)) {
 244         /* Before we modify anything, unmap and destroy the region */
 245         memory_region_del_subregion(address_space_mem, mem);
 246         object_unparent(OBJECT(mem));
 247     }
 248
 249     if (!(war & PIWAR_EN)) {
 250         /* Not enabled, nothing to do */
 251         return;
 252     }
 253
 254     name = g_strdup_printf("PCI Outbound Window %d", idx);
 255     memory_region_init_alias(mem, OBJECT(pci), name, &pci->busmem, tar,
 256                              size);
 257     memory_region_add_subregion(address_space_mem, wbar, mem);
 258     g_free(name);
 259
 260     pci_debug("%s: Added window of size=%#lx from CPU=%#lx to PCI=%#lx\n",
 261               __func__, size, wbar, tar);
 262 }
 263
 264 static void pci_reg_write4(void *opaque, hwaddr addr,
 265                            uint64_t value, unsigned size)
 266 {
 267     PPCE500PCIState *pci = opaque;
 268     unsigned long win;
 269     int idx;
 270
 271     win = addr & 0xfe0;
 272
 273     pci_debug("%s: value:%x -> win:%lx(addr:" TARGET_FMT_plx ")\n",
 274               __func__, (unsigned)value, win, addr);
 275
 276     switch (win) {
 277     case PPCE500_PCI_OW1:
 278     case PPCE500_PCI_OW2:
 279     case PPCE500_PCI_OW3:
 280     case PPCE500_PCI_OW4:
 281         idx = (addr >> 5) & 0x7;
 282         switch (addr & 0x1F) {
 283         case PCI_POTAR:
 284             pci->pob[idx].potar = value;
 285             e500_update_pow(pci, idx);
 286             break;
 287         case PCI_POTEAR:
 288             pci->pob[idx].potear = value;
 289             e500_update_pow(pci, idx);
 290             break;
 291         case PCI_POWBAR:
 292             pci->pob[idx].powbar = value;
 293             e500_update_pow(pci, idx);
 294             break;
 295         case PCI_POWAR:
 296             pci->pob[idx].powar = value;
 297             e500_update_pow(pci, idx);
 298             break;
 299         default:
 300             break;
 301         };
 302         break;
 303
 304     case PPCE500_PCI_IW3:
 305     case PPCE500_PCI_IW2:
 306     case PPCE500_PCI_IW1:
 307         idx = ((addr >> 5) & 0x3) - 1;
 308         switch (addr & 0x1F) {
 309         case PCI_PITAR:
 310             pci->pib[idx].pitar = value;
 311             e500_update_piw(pci, idx);
 312             break;
 313         case PCI_PIWBAR:
 314             pci->pib[idx].piwbar = value;
 315             e500_update_piw(pci, idx);
 316             break;
 317         case PCI_PIWBEAR:
 318             pci->pib[idx].piwbear = value;
 319             e500_update_piw(pci, idx);
 320             break;
 321         case PCI_PIWAR:
 322             pci->pib[idx].piwar = value;
 323             e500_update_piw(pci, idx);
 324             break;
 325         default:
 326             break;
 327         };
 328         break;
 329
 330     case PPCE500_PCI_GASKET_TIMR:
 331         pci->gasket_time = value;
 332         break;
 333
 334     default:
 335         break;
 336     };
 337 }
 338
 339 static const MemoryRegionOps e500_pci_reg_ops = {
 340     .read = pci_reg_read4,
 341     .write = pci_reg_write4,
 342     .endianness = DEVICE_BIG_ENDIAN,
 343 };
 344
 345 static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int pin)
 346 {
 347     int devno = pci_dev->devfn >> 3;
 348     int ret;
 349
 350     ret = ppce500_pci_map_irq_slot(devno, pin);
 351
 352     pci_debug("%s: devfn %x irq %d -> %d  devno:%x\n", __func__,
 353            pci_dev->devfn, pin, ret, devno);
 354
 355     return ret;
 356 }
 357
 358 static void mpc85xx_pci_set_irq(void *opaque, int pin, int level)
 359 {
 360     PPCE500PCIState *s = opaque;
 361     qemu_irq *pic = s->irq;
 362
 363     pci_debug("%s: PCI irq %d, level:%d\n", __func__, pin , level);
 364
 365     qemu_set_irq(pic[pin], level);
 366 }
 367
 368 static PCIINTxRoute e500_route_intx_pin_to_irq(void *opaque, int pin)
 369 {
 370     PCIINTxRoute route;
 371     PPCE500PCIState *s = opaque;
 372
 373     route.mode = PCI_INTX_ENABLED;
 374     route.irq = s->irq_num[pin];
 375
 376     pci_debug("%s: PCI irq-pin = %d, irq_num= %d\n", __func__, pin, route.irq);
 377     return route;
 378 }
 379
 380 static const VMStateDescription vmstate_pci_outbound = {
 381     .name = "pci_outbound",
 382     .version_id = 0,
 383     .minimum_version_id = 0,
 384     .fields = (VMStateField[]) {
 385         VMSTATE_UINT32(potar, struct pci_outbound),
 386         VMSTATE_UINT32(potear, struct pci_outbound),
 387         VMSTATE_UINT32(powbar, struct pci_outbound),
 388         VMSTATE_UINT32(powar, struct pci_outbound),
 389         VMSTATE_END_OF_LIST()
 390     }
 391 };
 392
 393 static const VMStateDescription vmstate_pci_inbound = {
 394     .name = "pci_inbound",
 395     .version_id = 0,
 396     .minimum_version_id = 0,
 397     .fields = (VMStateField[]) {
 398         VMSTATE_UINT32(pitar, struct pci_inbound),
 399         VMSTATE_UINT32(piwbar, struct pci_inbound),
 400         VMSTATE_UINT32(piwbear, struct pci_inbound),
 401         VMSTATE_UINT32(piwar, struct pci_inbound),
 402         VMSTATE_END_OF_LIST()
 403     }
 404 };
 405
 406 static const VMStateDescription vmstate_ppce500_pci = {
 407     .name = "ppce500_pci",
 408     .version_id = 1,
 409     .minimum_version_id = 1,
 410     .fields = (VMStateField[]) {
 411         VMSTATE_STRUCT_ARRAY(pob, PPCE500PCIState, PPCE500_PCI_NR_POBS, 1,
 412                              vmstate_pci_outbound, struct pci_outbound),
 413         VMSTATE_STRUCT_ARRAY(pib, PPCE500PCIState, PPCE500_PCI_NR_PIBS, 1,
 414                              vmstate_pci_inbound, struct pci_inbound),
 415         VMSTATE_UINT32(gasket_time, PPCE500PCIState),
 416         VMSTATE_END_OF_LIST()
 417     }
 418 };
 419
 420 #include "exec/address-spaces.h"
 421
 422 static void e500_pcihost_bridge_realize(PCIDevice *d, Error **errp)
 423 {
 424     PPCE500PCIBridgeState *b = PPC_E500_PCI_BRIDGE(d);
 425     PPCE500CCSRState *ccsr = CCSR(container_get(qdev_get_machine(),
 426                                   "/e500-ccsr"));
 427
 428     memory_region_init_alias(&b->bar0, OBJECT(ccsr), "e500-pci-bar0", &ccsr->ccsr_space,
 429                              0, int128_get64(ccsr->ccsr_space.size));
 430     pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &b->bar0);
 431 }
 432
 433 static AddressSpace *e500_pcihost_set_iommu(PCIBus *bus, void *opaque,
 434                                             int devfn)
 435 {
 436     PPCE500PCIState *s = opaque;
 437
 438     return &s->bm_as;
 439 }
 440
 441 static void e500_pcihost_realize(DeviceState *dev, Error **errp)
 442 {
 443     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 444     PCIHostState *h;
 445     PPCE500PCIState *s;
 446     PCIBus *b;
 447     int i;
 448
 449     h = PCI_HOST_BRIDGE(dev);
 450     s = PPC_E500_PCI_HOST_BRIDGE(dev);
 451
 452     for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
 453         sysbus_init_irq(sbd, &s->irq[i]);
 454     }
 455
 456     for (i = 0; i < PCI_NUM_PINS; i++) {
 457         s->irq_num[i] = s->first_pin_irq + i;
 458     }
 459
 460     memory_region_init(&s->pio, OBJECT(s), "pci-pio", PCIE500_PCI_IOLEN);
 461     memory_region_init(&s->busmem, OBJECT(s), "pci bus memory", UINT64_MAX);
 462
 463     /* PIO lives at the bottom of our bus space */
 464     memory_region_add_subregion_overlap(&s->busmem, 0, &s->pio, -2);
 465
 466     b = pci_register_root_bus(dev, NULL, mpc85xx_pci_set_irq,
 467                               mpc85xx_pci_map_irq, s, &s->busmem, &s->pio,
 468                               PCI_DEVFN(s->first_slot, 0), 4, TYPE_PCI_BUS);
 469     h->bus = b;
 470
 471     /* Set up PCI view of memory */
 472     memory_region_init(&s->bm, OBJECT(s), "bm-e500", UINT64_MAX);
 473     memory_region_add_subregion(&s->bm, 0x0, &s->busmem);
 474     address_space_init(&s->bm_as, &s->bm, "pci-bm");
 475     pci_setup_iommu(b, e500_pcihost_set_iommu, s);
 476
 477     pci_create_simple(b, 0, "e500-host-bridge");
 478
 479     memory_region_init(&s->container, OBJECT(h), "pci-container", PCIE500_ALL_SIZE);
 480     memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_be_ops, h,
 481                           "pci-conf-idx", 4);
 482     memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, h,
 483                           "pci-conf-data", 4);
 484     memory_region_init_io(&s->iomem, OBJECT(s), &e500_pci_reg_ops, s,
 485                           "pci.reg", PCIE500_REG_SIZE);
 486     memory_region_add_subregion(&s->container, PCIE500_CFGADDR, &h->conf_mem);
 487     memory_region_add_subregion(&s->container, PCIE500_CFGDATA, &h->data_mem);
 488     memory_region_add_subregion(&s->container, PCIE500_REG_BASE, &s->iomem);
 489     sysbus_init_mmio(sbd, &s->container);
 490     pci_bus_set_route_irq_fn(b, e500_route_intx_pin_to_irq);
 491 }
 492
 493 static void e500_host_bridge_class_init(ObjectClass *klass, void *data)
 494 {
 495     DeviceClass *dc = DEVICE_CLASS(klass);
 496     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 497
 498     k->realize = e500_pcihost_bridge_realize;
 499     k->vendor_id = PCI_VENDOR_ID_FREESCALE;
 500     k->device_id = PCI_DEVICE_ID_MPC8533E;
 501     k->class_id = PCI_CLASS_PROCESSOR_POWERPC;
 502     dc->desc = "Host bridge";
 503     /*
 504      * PCI-facing part of the host bridge, not usable without the
 505      * host-facing part, which can't be device_add'ed, yet.
 506      */
 507     dc->user_creatable = false;
 508 }
 509
 510 static const TypeInfo e500_host_bridge_info = {
 511     .name          = "e500-host-bridge",
 512     .parent        = TYPE_PCI_DEVICE,
 513     .instance_size = sizeof(PPCE500PCIBridgeState),
 514     .class_init    = e500_host_bridge_class_init,
 515     .interfaces = (InterfaceInfo[]) {
 516         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 517         { },
 518     },
 519 };
 520
 521 static Property pcihost_properties[] = {
 522     DEFINE_PROP_UINT32("first_slot", PPCE500PCIState, first_slot, 0x11),
 523     DEFINE_PROP_UINT32("first_pin_irq", PPCE500PCIState, first_pin_irq, 0x1),
 524     DEFINE_PROP_END_OF_LIST(),
 525 };
 526
 527 static void e500_pcihost_class_init(ObjectClass *klass, void *data)
 528 {
 529     DeviceClass *dc = DEVICE_CLASS(klass);
 530
 531     dc->realize = e500_pcihost_realize;
 532     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 533     dc->props = pcihost_properties;
 534     dc->vmsd = &vmstate_ppce500_pci;
 535 }
 536
 537 static const TypeInfo e500_pcihost_info = {
 538     .name          = TYPE_PPC_E500_PCI_HOST_BRIDGE,
 539     .parent        = TYPE_PCI_HOST_BRIDGE,
 540     .instance_size = sizeof(PPCE500PCIState),
 541     .class_init    = e500_pcihost_class_init,
 542 };
 543
 544 static void e500_pci_register_types(void)
 545 {
 546     type_register_static(&e500_pcihost_info);
 547     type_register_static(&e500_host_bridge_info);
 548 }
 549
 550 type_init(e500_pci_register_types)