hw/pci-host/prep.c

   1 /*
   2  * QEMU PREP PCI host
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  * Copyright (c) 2011-2013 Andreas Färber
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "hw/hw.h"
  27 #include "hw/pci/pci.h"
  28 #include "hw/pci/pci_bus.h"
  29 #include "hw/pci/pci_host.h"
  30 #include "hw/i386/pc.h"
  31 #include "hw/loader.h"
  32 #include "exec/address-spaces.h"
  33 #include "elf.h"
  34
  35 #define TYPE_RAVEN_PCI_DEVICE "raven"
  36 #define TYPE_RAVEN_PCI_HOST_BRIDGE "raven-pcihost"
  37
  38 #define RAVEN_PCI_DEVICE(obj) \
  39     OBJECT_CHECK(RavenPCIState, (obj), TYPE_RAVEN_PCI_DEVICE)
  40
  41 typedef struct RavenPCIState {
  42     PCIDevice dev;
  43
  44     uint32_t elf_machine;
  45     char *bios_name;
  46     MemoryRegion bios;
  47 } RavenPCIState;
  48
  49 #define RAVEN_PCI_HOST_BRIDGE(obj) \
  50     OBJECT_CHECK(PREPPCIState, (obj), TYPE_RAVEN_PCI_HOST_BRIDGE)
  51
  52 typedef struct PRePPCIState {
  53     PCIHostState parent_obj;
  54
  55     MemoryRegion intack;
  56     qemu_irq irq[PCI_NUM_PINS];
  57     PCIBus pci_bus;
  58     RavenPCIState pci_dev;
  59 } PREPPCIState;
  60
  61 #define BIOS_SIZE (1024 * 1024)
  62
  63 static inline uint32_t PPC_PCIIO_config(hwaddr addr)
  64 {
  65     int i;
  66
  67     for (i = 0; i < 11; i++) {
  68         if ((addr & (1 << (11 + i))) != 0) {
  69             break;
  70         }
  71     }
  72     return (addr & 0x7ff) |  (i << 11);
  73 }
  74
  75 static void ppc_pci_io_write(void *opaque, hwaddr addr,
  76                              uint64_t val, unsigned int size)
  77 {
  78     PREPPCIState *s = opaque;
  79     PCIHostState *phb = PCI_HOST_BRIDGE(s);
  80     pci_data_write(phb->bus, PPC_PCIIO_config(addr), val, size);
  81 }
  82
  83 static uint64_t ppc_pci_io_read(void *opaque, hwaddr addr,
  84                                 unsigned int size)
  85 {
  86     PREPPCIState *s = opaque;
  87     PCIHostState *phb = PCI_HOST_BRIDGE(s);
  88     return pci_data_read(phb->bus, PPC_PCIIO_config(addr), size);
  89 }
  90
  91 static const MemoryRegionOps PPC_PCIIO_ops = {
  92     .read = ppc_pci_io_read,
  93     .write = ppc_pci_io_write,
  94     .endianness = DEVICE_LITTLE_ENDIAN,
  95 };
  96
  97 static uint64_t ppc_intack_read(void *opaque, hwaddr addr,
  98                                 unsigned int size)
  99 {
 100     return pic_read_irq(isa_pic);
 101 }
 102
 103 static const MemoryRegionOps PPC_intack_ops = {
 104     .read = ppc_intack_read,
 105     .valid = {
 106         .max_access_size = 1,
 107     },
 108 };
 109
 110 static int prep_map_irq(PCIDevice *pci_dev, int irq_num)
 111 {
 112     return (irq_num + (pci_dev->devfn >> 3)) & 1;
 113 }
 114
 115 static void prep_set_irq(void *opaque, int irq_num, int level)
 116 {
 117     qemu_irq *pic = opaque;
 118
 119     qemu_set_irq(pic[irq_num] , level);
 120 }
 121
 122 static void raven_pcihost_realizefn(DeviceState *d, Error **errp)
 123 {
 124     SysBusDevice *dev = SYS_BUS_DEVICE(d);
 125     PCIHostState *h = PCI_HOST_BRIDGE(dev);
 126     PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(dev);
 127     MemoryRegion *address_space_mem = get_system_memory();
 128     int i;
 129
 130     isa_mem_base = 0xc0000000;
 131
 132     for (i = 0; i < PCI_NUM_PINS; i++) {
 133         sysbus_init_irq(dev, &s->irq[i]);
 134     }
 135
 136     pci_bus_irqs(&s->pci_bus, prep_set_irq, prep_map_irq, s->irq, PCI_NUM_PINS);
 137
 138     memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_be_ops, s,
 139                           "pci-conf-idx", 1);
 140     sysbus_add_io(dev, 0xcf8, &h->conf_mem);
 141     sysbus_init_ioports(&h->busdev, 0xcf8, 1);
 142
 143     memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_be_ops, s,
 144                           "pci-conf-data", 1);
 145     sysbus_add_io(dev, 0xcfc, &h->data_mem);
 146     sysbus_init_ioports(&h->busdev, 0xcfc, 1);
 147
 148     memory_region_init_io(&h->mmcfg, OBJECT(s), &PPC_PCIIO_ops, s, "pciio", 0x00400000);
 149     memory_region_add_subregion(address_space_mem, 0x80800000, &h->mmcfg);
 150
 151     memory_region_init_io(&s->intack, OBJECT(s), &PPC_intack_ops, s, "pci-intack", 1);
 152     memory_region_add_subregion(address_space_mem, 0xbffffff0, &s->intack);
 153
 154     /* TODO Remove once realize propagates to child devices. */
 155     object_property_set_bool(OBJECT(&s->pci_dev), true, "realized", errp);
 156 }
 157
 158 static void raven_pcihost_initfn(Object *obj)
 159 {
 160     PCIHostState *h = PCI_HOST_BRIDGE(obj);
 161     PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(obj);
 162     MemoryRegion *address_space_mem = get_system_memory();
 163     MemoryRegion *address_space_io = get_system_io();
 164     DeviceState *pci_dev;
 165
 166     pci_bus_new_inplace(&s->pci_bus, sizeof(s->pci_bus), DEVICE(obj), NULL,
 167                         address_space_mem, address_space_io, 0, TYPE_PCI_BUS);
 168     h->bus = &s->pci_bus;
 169
 170     object_initialize(&s->pci_dev, sizeof(s->pci_dev), TYPE_RAVEN_PCI_DEVICE);
 171     pci_dev = DEVICE(&s->pci_dev);
 172     qdev_set_parent_bus(pci_dev, BUS(&s->pci_bus));
 173     object_property_set_int(OBJECT(&s->pci_dev), PCI_DEVFN(0, 0), "addr",
 174                             NULL);
 175     qdev_prop_set_bit(pci_dev, "multifunction", false);
 176 }
 177
 178 static int raven_init(PCIDevice *d)
 179 {
 180     RavenPCIState *s = RAVEN_PCI_DEVICE(d);
 181     char *filename;
 182     int bios_size = -1;
 183
 184     d->config[0x0C] = 0x08; // cache_line_size
 185     d->config[0x0D] = 0x10; // latency_timer
 186     d->config[0x34] = 0x00; // capabilities_pointer
 187
 188     memory_region_init_ram(&s->bios, OBJECT(s), "bios", BIOS_SIZE);
 189     memory_region_set_readonly(&s->bios, true);
 190     memory_region_add_subregion(get_system_memory(), (uint32_t)(-BIOS_SIZE),
 191                                 &s->bios);
 192     vmstate_register_ram_global(&s->bios);
 193     if (s->bios_name) {
 194         filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, s->bios_name);
 195         if (filename) {
 196             if (s->elf_machine != EM_NONE) {
 197                 bios_size = load_elf(filename, NULL, NULL, NULL,
 198                                      NULL, NULL, 1, s->elf_machine, 0);
 199             }
 200             if (bios_size < 0) {
 201                 bios_size = get_image_size(filename);
 202                 if (bios_size > 0 && bios_size <= BIOS_SIZE) {
 203                     hwaddr bios_addr;
 204                     bios_size = (bios_size + 0xfff) & ~0xfff;
 205                     bios_addr = (uint32_t)(-BIOS_SIZE);
 206                     bios_size = load_image_targphys(filename, bios_addr,
 207                                                     bios_size);
 208                 }
 209             }
 210         }
 211         if (bios_size < 0 || bios_size > BIOS_SIZE) {
 212             hw_error("qemu: could not load bios image '%s'\n", s->bios_name);
 213         }
 214         if (filename) {
 215             g_free(filename);
 216         }
 217     }
 218
 219     return 0;
 220 }
 221
 222 static const VMStateDescription vmstate_raven = {
 223     .name = "raven",
 224     .version_id = 0,
 225     .minimum_version_id = 0,
 226     .fields = (VMStateField[]) {
 227         VMSTATE_PCI_DEVICE(dev, RavenPCIState),
 228         VMSTATE_END_OF_LIST()
 229     },
 230 };
 231
 232 static void raven_class_init(ObjectClass *klass, void *data)
 233 {
 234     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 235     DeviceClass *dc = DEVICE_CLASS(klass);
 236
 237     k->init = raven_init;
 238     k->vendor_id = PCI_VENDOR_ID_MOTOROLA;
 239     k->device_id = PCI_DEVICE_ID_MOTOROLA_RAVEN;
 240     k->revision = 0x00;
 241     k->class_id = PCI_CLASS_BRIDGE_HOST;
 242     dc->desc = "PReP Host Bridge - Motorola Raven";
 243     dc->vmsd = &vmstate_raven;
 244     /*
 245      * PCI-facing part of the host bridge, not usable without the
 246      * host-facing part, which can't be device_add'ed, yet.
 247      */
 248     dc->cannot_instantiate_with_device_add_yet = true;
 249 }
 250
 251 static const TypeInfo raven_info = {
 252     .name = TYPE_RAVEN_PCI_DEVICE,
 253     .parent = TYPE_PCI_DEVICE,
 254     .instance_size = sizeof(RavenPCIState),
 255     .class_init = raven_class_init,
 256 };
 257
 258 static Property raven_pcihost_properties[] = {
 259     DEFINE_PROP_UINT32("elf-machine", PREPPCIState, pci_dev.elf_machine,
 260                        EM_NONE),
 261     DEFINE_PROP_STRING("bios-name", PREPPCIState, pci_dev.bios_name),
 262     DEFINE_PROP_END_OF_LIST()
 263 };
 264
 265 static void raven_pcihost_class_init(ObjectClass *klass, void *data)
 266 {
 267     DeviceClass *dc = DEVICE_CLASS(klass);
 268
 269     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 270     dc->realize = raven_pcihost_realizefn;
 271     dc->props = raven_pcihost_properties;
 272     dc->fw_name = "pci";
 273 }
 274
 275 static const TypeInfo raven_pcihost_info = {
 276     .name = TYPE_RAVEN_PCI_HOST_BRIDGE,
 277     .parent = TYPE_PCI_HOST_BRIDGE,
 278     .instance_size = sizeof(PREPPCIState),
 279     .instance_init = raven_pcihost_initfn,
 280     .class_init = raven_pcihost_class_init,
 281 };
 282
 283 static void raven_register_types(void)
 284 {
 285     type_register_static(&raven_pcihost_info);
 286     type_register_static(&raven_info);
 287 }
 288
 289 type_init(raven_register_types)