hw/pci-host/q35.c

   1 /*
   2  * QEMU MCH/ICH9 PCI Bridge Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  * Copyright (c) 2009, 2010, 2011
   6  *               Isaku Yamahata <yamahata at valinux co jp>
   7  *               VA Linux Systems Japan K.K.
   8  * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
   9  *
  10  * This is based on piix.c, but heavily modified.
  11  *
  12  * Permission is hereby granted, free of charge, to any person obtaining a copy
  13  * of this software and associated documentation files (the "Software"), to deal
  14  * in the Software without restriction, including without limitation the rights
  15  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  16  * copies of the Software, and to permit persons to whom the Software is
  17  * furnished to do so, subject to the following conditions:
  18  *
  19  * The above copyright notice and this permission notice shall be included in
  20  * all copies or substantial portions of the Software.
  21  *
  22  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  23  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  24  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  25  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  26  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  27  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  28  * THE SOFTWARE.
  29  */
  30 #include "qemu/osdep.h"
  31 #include "hw/hw.h"
  32 #include "hw/pci-host/q35.h"
  33 #include "qapi/error.h"
  34 #include "qapi/visitor.h"
  35
  36 /****************************************************************************
  37  * Q35 host
  38  */
  39
  40 static void q35_host_realize(DeviceState *dev, Error **errp)
  41 {
  42     PCIHostState *pci = PCI_HOST_BRIDGE(dev);
  43     Q35PCIHost *s = Q35_HOST_DEVICE(dev);
  44     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
  45
  46     sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem);
  47     sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, 4);
  48
  49     sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem);
  50     sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4);
  51
  52     pci->bus = pci_bus_new(DEVICE(s), "pcie.0",
  53                            s->mch.pci_address_space, s->mch.address_space_io,
  54                            0, TYPE_PCIE_BUS);
  55     PC_MACHINE(qdev_get_machine())->bus = pci->bus;
  56     qdev_set_parent_bus(DEVICE(&s->mch), BUS(pci->bus));
  57     qdev_init_nofail(DEVICE(&s->mch));
  58 }
  59
  60 static const char *q35_host_root_bus_path(PCIHostState *host_bridge,
  61                                           PCIBus *rootbus)
  62 {
  63     Q35PCIHost *s = Q35_HOST_DEVICE(host_bridge);
  64
  65      /* For backwards compat with old device paths */
  66     if (s->mch.short_root_bus) {
  67         return "0000";
  68     }
  69     return "0000:00";
  70 }
  71
  72 static void q35_host_get_pci_hole_start(Object *obj, Visitor *v,
  73                                         const char *name, void *opaque,
  74                                         Error **errp)
  75 {
  76     Q35PCIHost *s = Q35_HOST_DEVICE(obj);
  77     uint64_t val64;
  78     uint32_t value;
  79
  80     val64 = range_is_empty(&s->mch.pci_hole)
  81         ? 0 : range_lob(&s->mch.pci_hole);
  82     value = val64;
  83     assert(value == val64);
  84     visit_type_uint32(v, name, &value, errp);
  85 }
  86
  87 static void q35_host_get_pci_hole_end(Object *obj, Visitor *v,
  88                                       const char *name, void *opaque,
  89                                       Error **errp)
  90 {
  91     Q35PCIHost *s = Q35_HOST_DEVICE(obj);
  92     uint64_t val64;
  93     uint32_t value;
  94
  95     val64 = range_is_empty(&s->mch.pci_hole)
  96         ? 0 : range_upb(&s->mch.pci_hole) + 1;
  97     value = val64;
  98     assert(value == val64);
  99     visit_type_uint32(v, name, &value, errp);
 100 }
 101
 102 static void q35_host_get_pci_hole64_start(Object *obj, Visitor *v,
 103                                           const char *name, void *opaque,
 104                                           Error **errp)
 105 {
 106     PCIHostState *h = PCI_HOST_BRIDGE(obj);
 107     Range w64;
 108     uint64_t value;
 109
 110     pci_bus_get_w64_range(h->bus, &w64);
 111     value = range_is_empty(&w64) ? 0 : range_lob(&w64);
 112     visit_type_uint64(v, name, &value, errp);
 113 }
 114
 115 static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v,
 116                                         const char *name, void *opaque,
 117                                         Error **errp)
 118 {
 119     PCIHostState *h = PCI_HOST_BRIDGE(obj);
 120     Range w64;
 121     uint64_t value;
 122
 123     pci_bus_get_w64_range(h->bus, &w64);
 124     value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1;
 125     visit_type_uint64(v, name, &value, errp);
 126 }
 127
 128 static void q35_host_get_mmcfg_size(Object *obj, Visitor *v, const char *name,
 129                                     void *opaque, Error **errp)
 130 {
 131     PCIExpressHost *e = PCIE_HOST_BRIDGE(obj);
 132
 133     visit_type_uint64(v, name, &e->size, errp);
 134 }
 135
 136 static Property q35_host_props[] = {
 137     DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, Q35PCIHost, parent_obj.base_addr,
 138                         MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT),
 139     DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost,
 140                      mch.pci_hole64_size, DEFAULT_PCI_HOLE64_SIZE),
 141     DEFINE_PROP_UINT32("short_root_bus", Q35PCIHost, mch.short_root_bus, 0),
 142     DEFINE_PROP_SIZE(PCI_HOST_BELOW_4G_MEM_SIZE, Q35PCIHost,
 143                      mch.below_4g_mem_size, 0),
 144     DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MEM_SIZE, Q35PCIHost,
 145                      mch.above_4g_mem_size, 0),
 146     DEFINE_PROP_END_OF_LIST(),
 147 };
 148
 149 static void q35_host_class_init(ObjectClass *klass, void *data)
 150 {
 151     DeviceClass *dc = DEVICE_CLASS(klass);
 152     PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
 153
 154     hc->root_bus_path = q35_host_root_bus_path;
 155     dc->realize = q35_host_realize;
 156     dc->props = q35_host_props;
 157     /* Reason: needs to be wired up by pc_q35_init */
 158     dc->user_creatable = false;
 159     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 160     dc->fw_name = "pci";
 161 }
 162
 163 static void q35_host_initfn(Object *obj)
 164 {
 165     Q35PCIHost *s = Q35_HOST_DEVICE(obj);
 166     PCIHostState *phb = PCI_HOST_BRIDGE(obj);
 167
 168     memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb,
 169                           "pci-conf-idx", 4);
 170     memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb,
 171                           "pci-conf-data", 4);
 172
 173     object_initialize(&s->mch, sizeof(s->mch), TYPE_MCH_PCI_DEVICE);
 174     object_property_add_child(OBJECT(s), "mch", OBJECT(&s->mch), NULL);
 175     qdev_prop_set_int32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0));
 176     qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false);
 177
 178     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "uint32",
 179                         q35_host_get_pci_hole_start,
 180                         NULL, NULL, NULL, NULL);
 181
 182     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "uint32",
 183                         q35_host_get_pci_hole_end,
 184                         NULL, NULL, NULL, NULL);
 185
 186     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "uint64",
 187                         q35_host_get_pci_hole64_start,
 188                         NULL, NULL, NULL, NULL);
 189
 190     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "uint64",
 191                         q35_host_get_pci_hole64_end,
 192                         NULL, NULL, NULL, NULL);
 193
 194     object_property_add(obj, PCIE_HOST_MCFG_SIZE, "uint64",
 195                         q35_host_get_mmcfg_size,
 196                         NULL, NULL, NULL, NULL);
 197
 198     object_property_add_link(obj, MCH_HOST_PROP_RAM_MEM, TYPE_MEMORY_REGION,
 199                              (Object **) &s->mch.ram_memory,
 200                              qdev_prop_allow_set_link_before_realize, 0, NULL);
 201
 202     object_property_add_link(obj, MCH_HOST_PROP_PCI_MEM, TYPE_MEMORY_REGION,
 203                              (Object **) &s->mch.pci_address_space,
 204                              qdev_prop_allow_set_link_before_realize, 0, NULL);
 205
 206     object_property_add_link(obj, MCH_HOST_PROP_SYSTEM_MEM, TYPE_MEMORY_REGION,
 207                              (Object **) &s->mch.system_memory,
 208                              qdev_prop_allow_set_link_before_realize, 0, NULL);
 209
 210     object_property_add_link(obj, MCH_HOST_PROP_IO_MEM, TYPE_MEMORY_REGION,
 211                              (Object **) &s->mch.address_space_io,
 212                              qdev_prop_allow_set_link_before_realize, 0, NULL);
 213
 214     /* Leave enough space for the biggest MCFG BAR */
 215     /* TODO: this matches current bios behaviour, but
 216      * it's not a power of two, which means an MTRR
 217      * can't cover it exactly.
 218      */
 219     range_set_bounds(&s->mch.pci_hole,
 220             MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT + MCH_HOST_BRIDGE_PCIEXBAR_MAX,
 221             IO_APIC_DEFAULT_ADDRESS - 1);
 222 }
 223
 224 static const TypeInfo q35_host_info = {
 225     .name       = TYPE_Q35_HOST_DEVICE,
 226     .parent     = TYPE_PCIE_HOST_BRIDGE,
 227     .instance_size = sizeof(Q35PCIHost),
 228     .instance_init = q35_host_initfn,
 229     .class_init = q35_host_class_init,
 230 };
 231
 232 /****************************************************************************
 233  * MCH D0:F0
 234  */
 235
 236 static uint64_t tseg_blackhole_read(void *ptr, hwaddr reg, unsigned size)
 237 {
 238     return 0xffffffff;
 239 }
 240
 241 static void tseg_blackhole_write(void *opaque, hwaddr addr, uint64_t val,
 242                                  unsigned width)
 243 {
 244     /* nothing */
 245 }
 246
 247 static const MemoryRegionOps tseg_blackhole_ops = {
 248     .read = tseg_blackhole_read,
 249     .write = tseg_blackhole_write,
 250     .endianness = DEVICE_NATIVE_ENDIAN,
 251     .valid.min_access_size = 1,
 252     .valid.max_access_size = 4,
 253     .impl.min_access_size = 4,
 254     .impl.max_access_size = 4,
 255     .endianness = DEVICE_LITTLE_ENDIAN,
 256 };
 257
 258 /* PCIe MMCFG */
 259 static void mch_update_pciexbar(MCHPCIState *mch)
 260 {
 261     PCIDevice *pci_dev = PCI_DEVICE(mch);
 262     BusState *bus = qdev_get_parent_bus(DEVICE(mch));
 263     PCIExpressHost *pehb = PCIE_HOST_BRIDGE(bus->parent);
 264
 265     uint64_t pciexbar;
 266     int enable;
 267     uint64_t addr;
 268     uint64_t addr_mask;
 269     uint32_t length;
 270
 271     pciexbar = pci_get_quad(pci_dev->config + MCH_HOST_BRIDGE_PCIEXBAR);
 272     enable = pciexbar & MCH_HOST_BRIDGE_PCIEXBAREN;
 273     addr_mask = MCH_HOST_BRIDGE_PCIEXBAR_ADMSK;
 274     switch (pciexbar & MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) {
 275     case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M:
 276         length = 256 * 1024 * 1024;
 277         break;
 278     case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M:
 279         length = 128 * 1024 * 1024;
 280         addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK |
 281             MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
 282         break;
 283     case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M:
 284         length = 64 * 1024 * 1024;
 285         addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
 286         break;
 287     case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD:
 288     default:
 289         abort();
 290     }
 291     addr = pciexbar & addr_mask;
 292     pcie_host_mmcfg_update(pehb, enable, addr, length);
 293     /* Leave enough space for the MCFG BAR */
 294     /*
 295      * TODO: this matches current bios behaviour, but it's not a power of two,
 296      * which means an MTRR can't cover it exactly.
 297      */
 298     if (enable) {
 299         range_set_bounds(&mch->pci_hole,
 300                          addr + length,
 301                          IO_APIC_DEFAULT_ADDRESS - 1);
 302     } else {
 303         range_set_bounds(&mch->pci_hole,
 304                          MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT,
 305                          IO_APIC_DEFAULT_ADDRESS - 1);
 306     }
 307 }
 308
 309 /* PAM */
 310 static void mch_update_pam(MCHPCIState *mch)
 311 {
 312     PCIDevice *pd = PCI_DEVICE(mch);
 313     int i;
 314
 315     memory_region_transaction_begin();
 316     for (i = 0; i < 13; i++) {
 317         pam_update(&mch->pam_regions[i], i,
 318                    pd->config[MCH_HOST_BRIDGE_PAM0 + (DIV_ROUND_UP(i, 2))]);
 319     }
 320     memory_region_transaction_commit();
 321 }
 322
 323 /* SMRAM */
 324 static void mch_update_smram(MCHPCIState *mch)
 325 {
 326     PCIDevice *pd = PCI_DEVICE(mch);
 327     bool h_smrame = (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME);
 328     uint32_t tseg_size;
 329
 330     /* implement SMRAM.D_LCK */
 331     if (pd->config[MCH_HOST_BRIDGE_SMRAM] & MCH_HOST_BRIDGE_SMRAM_D_LCK) {
 332         pd->config[MCH_HOST_BRIDGE_SMRAM] &= ~MCH_HOST_BRIDGE_SMRAM_D_OPEN;
 333         pd->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK_LCK;
 334         pd->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK_LCK;
 335     }
 336
 337     memory_region_transaction_begin();
 338
 339     if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_D_OPEN) {
 340         /* Hide (!) low SMRAM if H_SMRAME = 1 */
 341         memory_region_set_enabled(&mch->smram_region, h_smrame);
 342         /* Show high SMRAM if H_SMRAME = 1 */
 343         memory_region_set_enabled(&mch->open_high_smram, h_smrame);
 344     } else {
 345         /* Hide high SMRAM and low SMRAM */
 346         memory_region_set_enabled(&mch->smram_region, true);
 347         memory_region_set_enabled(&mch->open_high_smram, false);
 348     }
 349
 350     if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_G_SMRAME) {
 351         memory_region_set_enabled(&mch->low_smram, !h_smrame);
 352         memory_region_set_enabled(&mch->high_smram, h_smrame);
 353     } else {
 354         memory_region_set_enabled(&mch->low_smram, false);
 355         memory_region_set_enabled(&mch->high_smram, false);
 356     }
 357
 358     if (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_T_EN) {
 359         switch (pd->config[MCH_HOST_BRIDGE_ESMRAMC] &
 360                 MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK) {
 361         case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB:
 362             tseg_size = 1024 * 1024;
 363             break;
 364         case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB:
 365             tseg_size = 1024 * 1024 * 2;
 366             break;
 367         case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB:
 368             tseg_size = 1024 * 1024 * 8;
 369             break;
 370         default:
 371             tseg_size = 1024 * 1024 * (uint32_t)mch->ext_tseg_mbytes;
 372             break;
 373         }
 374     } else {
 375         tseg_size = 0;
 376     }
 377     memory_region_del_subregion(mch->system_memory, &mch->tseg_blackhole);
 378     memory_region_set_enabled(&mch->tseg_blackhole, tseg_size);
 379     memory_region_set_size(&mch->tseg_blackhole, tseg_size);
 380     memory_region_add_subregion_overlap(mch->system_memory,
 381                                         mch->below_4g_mem_size - tseg_size,
 382                                         &mch->tseg_blackhole, 1);
 383
 384     memory_region_set_enabled(&mch->tseg_window, tseg_size);
 385     memory_region_set_size(&mch->tseg_window, tseg_size);
 386     memory_region_set_address(&mch->tseg_window,
 387                               mch->below_4g_mem_size - tseg_size);
 388     memory_region_set_alias_offset(&mch->tseg_window,
 389                                    mch->below_4g_mem_size - tseg_size);
 390
 391     memory_region_transaction_commit();
 392 }
 393
 394 static void mch_update_ext_tseg_mbytes(MCHPCIState *mch)
 395 {
 396     PCIDevice *pd = PCI_DEVICE(mch);
 397     uint8_t *reg = pd->config + MCH_HOST_BRIDGE_EXT_TSEG_MBYTES;
 398
 399     if (mch->ext_tseg_mbytes > 0 &&
 400         pci_get_word(reg) == MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY) {
 401         pci_set_word(reg, mch->ext_tseg_mbytes);
 402     }
 403 }
 404
 405 static void mch_write_config(PCIDevice *d,
 406                               uint32_t address, uint32_t val, int len)
 407 {
 408     MCHPCIState *mch = MCH_PCI_DEVICE(d);
 409
 410     pci_default_write_config(d, address, val, len);
 411
 412     if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0,
 413                        MCH_HOST_BRIDGE_PAM_SIZE)) {
 414         mch_update_pam(mch);
 415     }
 416
 417     if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PCIEXBAR,
 418                        MCH_HOST_BRIDGE_PCIEXBAR_SIZE)) {
 419         mch_update_pciexbar(mch);
 420     }
 421
 422     if (ranges_overlap(address, len, MCH_HOST_BRIDGE_SMRAM,
 423                        MCH_HOST_BRIDGE_SMRAM_SIZE)) {
 424         mch_update_smram(mch);
 425     }
 426
 427     if (ranges_overlap(address, len, MCH_HOST_BRIDGE_EXT_TSEG_MBYTES,
 428                        MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_SIZE)) {
 429         mch_update_ext_tseg_mbytes(mch);
 430     }
 431 }
 432
 433 static void mch_update(MCHPCIState *mch)
 434 {
 435     mch_update_pciexbar(mch);
 436     mch_update_pam(mch);
 437     mch_update_smram(mch);
 438     mch_update_ext_tseg_mbytes(mch);
 439 }
 440
 441 static int mch_post_load(void *opaque, int version_id)
 442 {
 443     MCHPCIState *mch = opaque;
 444     mch_update(mch);
 445     return 0;
 446 }
 447
 448 static const VMStateDescription vmstate_mch = {
 449     .name = "mch",
 450     .version_id = 1,
 451     .minimum_version_id = 1,
 452     .post_load = mch_post_load,
 453     .fields = (VMStateField[]) {
 454         VMSTATE_PCI_DEVICE(parent_obj, MCHPCIState),
 455         /* Used to be smm_enabled, which was basically always zero because
 456          * SeaBIOS hardly uses SMM.  SMRAM is now handled by CPU code.
 457          */
 458         VMSTATE_UNUSED(1),
 459         VMSTATE_END_OF_LIST()
 460     }
 461 };
 462
 463 static void mch_reset(DeviceState *qdev)
 464 {
 465     PCIDevice *d = PCI_DEVICE(qdev);
 466     MCHPCIState *mch = MCH_PCI_DEVICE(d);
 467
 468     pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR,
 469                  MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT);
 470
 471     d->config[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT;
 472     d->config[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_DEFAULT;
 473     d->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK;
 474     d->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK;
 475
 476     if (mch->ext_tseg_mbytes > 0) {
 477         pci_set_word(d->config + MCH_HOST_BRIDGE_EXT_TSEG_MBYTES,
 478                      MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY);
 479     }
 480
 481     mch_update(mch);
 482 }
 483
 484 static void mch_realize(PCIDevice *d, Error **errp)
 485 {
 486     int i;
 487     MCHPCIState *mch = MCH_PCI_DEVICE(d);
 488
 489     if (mch->ext_tseg_mbytes > MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_MAX) {
 490         error_setg(errp, "invalid extended-tseg-mbytes value: %" PRIu16,
 491                    mch->ext_tseg_mbytes);
 492         return;
 493     }
 494
 495     /* setup pci memory mapping */
 496     pc_pci_as_mapping_init(OBJECT(mch), mch->system_memory,
 497                            mch->pci_address_space);
 498
 499     /* if *disabled* show SMRAM to all CPUs */
 500     memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region",
 501                              mch->pci_address_space, 0xa0000, 0x20000);
 502     memory_region_add_subregion_overlap(mch->system_memory, 0xa0000,
 503                                         &mch->smram_region, 1);
 504     memory_region_set_enabled(&mch->smram_region, true);
 505
 506     memory_region_init_alias(&mch->open_high_smram, OBJECT(mch), "smram-open-high",
 507                              mch->ram_memory, 0xa0000, 0x20000);
 508     memory_region_add_subregion_overlap(mch->system_memory, 0xfeda0000,
 509                                         &mch->open_high_smram, 1);
 510     memory_region_set_enabled(&mch->open_high_smram, false);
 511
 512     /* smram, as seen by SMM CPUs */
 513     memory_region_init(&mch->smram, OBJECT(mch), "smram", 1ull << 32);
 514     memory_region_set_enabled(&mch->smram, true);
 515     memory_region_init_alias(&mch->low_smram, OBJECT(mch), "smram-low",
 516                              mch->ram_memory, 0xa0000, 0x20000);
 517     memory_region_set_enabled(&mch->low_smram, true);
 518     memory_region_add_subregion(&mch->smram, 0xa0000, &mch->low_smram);
 519     memory_region_init_alias(&mch->high_smram, OBJECT(mch), "smram-high",
 520                              mch->ram_memory, 0xa0000, 0x20000);
 521     memory_region_set_enabled(&mch->high_smram, true);
 522     memory_region_add_subregion(&mch->smram, 0xfeda0000, &mch->high_smram);
 523
 524     memory_region_init_io(&mch->tseg_blackhole, OBJECT(mch),
 525                           &tseg_blackhole_ops, NULL,
 526                           "tseg-blackhole", 0);
 527     memory_region_set_enabled(&mch->tseg_blackhole, false);
 528     memory_region_add_subregion_overlap(mch->system_memory,
 529                                         mch->below_4g_mem_size,
 530                                         &mch->tseg_blackhole, 1);
 531
 532     memory_region_init_alias(&mch->tseg_window, OBJECT(mch), "tseg-window",
 533                              mch->ram_memory, mch->below_4g_mem_size, 0);
 534     memory_region_set_enabled(&mch->tseg_window, false);
 535     memory_region_add_subregion(&mch->smram, mch->below_4g_mem_size,
 536                                 &mch->tseg_window);
 537     object_property_add_const_link(qdev_get_machine(), "smram",
 538                                    OBJECT(&mch->smram), &error_abort);
 539
 540     init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory,
 541              mch->pci_address_space, &mch->pam_regions[0],
 542              PAM_BIOS_BASE, PAM_BIOS_SIZE);
 543     for (i = 0; i < 12; ++i) {
 544         init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory,
 545                  mch->pci_address_space, &mch->pam_regions[i+1],
 546                  PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE);
 547     }
 548 }
 549
 550 uint64_t mch_mcfg_base(void)
 551 {
 552     bool ambiguous;
 553     Object *o = object_resolve_path_type("", TYPE_MCH_PCI_DEVICE, &ambiguous);
 554     if (!o) {
 555         return 0;
 556     }
 557     return MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT;
 558 }
 559
 560 static Property mch_props[] = {
 561     DEFINE_PROP_UINT16("extended-tseg-mbytes", MCHPCIState, ext_tseg_mbytes,
 562                        16),
 563     DEFINE_PROP_END_OF_LIST(),
 564 };
 565
 566 static void mch_class_init(ObjectClass *klass, void *data)
 567 {
 568     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 569     DeviceClass *dc = DEVICE_CLASS(klass);
 570
 571     k->realize = mch_realize;
 572     k->config_write = mch_write_config;
 573     dc->reset = mch_reset;
 574     dc->props = mch_props;
 575     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 576     dc->desc = "Host bridge";
 577     dc->vmsd = &vmstate_mch;
 578     k->vendor_id = PCI_VENDOR_ID_INTEL;
 579     k->device_id = PCI_DEVICE_ID_INTEL_Q35_MCH;
 580     k->revision = MCH_HOST_BRIDGE_REVISION_DEFAULT;
 581     k->class_id = PCI_CLASS_BRIDGE_HOST;
 582     /*
 583      * PCI-facing part of the host bridge, not usable without the
 584      * host-facing part, which can't be device_add'ed, yet.
 585      */
 586     dc->user_creatable = false;
 587 }
 588
 589 static const TypeInfo mch_info = {
 590     .name = TYPE_MCH_PCI_DEVICE,
 591     .parent = TYPE_PCI_DEVICE,
 592     .instance_size = sizeof(MCHPCIState),
 593     .class_init = mch_class_init,
 594     .interfaces = (InterfaceInfo[]) {
 595         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 596         { },
 597     },
 598 };
 599
 600 static void q35_register(void)
 601 {
 602     type_register_static(&mch_info);
 603     type_register_static(&q35_host_info);
 604 }
 605
 606 type_init(q35_register);