4 * Copyright (c) 2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
30 #include "qemu-objects.h"
34 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
36 # define PCI_DPRINTF(format, ...) do { } while (0)
42 pci_set_irq_fn set_irq
;
43 pci_map_irq_fn map_irq
;
44 pci_hotplug_fn hotplug
;
45 DeviceState
*hotplug_qdev
;
47 PCIDevice
*devices
[256];
48 PCIDevice
*parent_dev
;
49 target_phys_addr_t mem_base
;
51 QLIST_HEAD(, PCIBus
) child
; /* this will be replaced by qdev later */
52 QLIST_ENTRY(PCIBus
) sibling
;/* this will be replaced by qdev later */
54 /* The bus IRQ state is the logical OR of the connected devices.
55 Keep a count of the number of devices with raised IRQs. */
60 static void pcibus_dev_print(Monitor
*mon
, DeviceState
*dev
, int indent
);
61 static char *pcibus_get_dev_path(DeviceState
*dev
);
63 static struct BusInfo pci_bus_info
= {
65 .size
= sizeof(PCIBus
),
66 .print_dev
= pcibus_dev_print
,
67 .get_dev_path
= pcibus_get_dev_path
,
68 .props
= (Property
[]) {
69 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice
, devfn
, -1),
70 DEFINE_PROP_STRING("romfile", PCIDevice
, romfile
),
71 DEFINE_PROP_UINT32("rombar", PCIDevice
, rom_bar
, 1),
72 DEFINE_PROP_BIT("multifunction", PCIDevice
, cap_present
,
73 QEMU_PCI_CAP_MULTIFUNCTION_BITNR
, false),
74 DEFINE_PROP_END_OF_LIST()
78 static void pci_update_mappings(PCIDevice
*d
);
79 static void pci_set_irq(void *opaque
, int irq_num
, int level
);
80 static int pci_add_option_rom(PCIDevice
*pdev
);
81 static void pci_del_option_rom(PCIDevice
*pdev
);
83 static uint16_t pci_default_sub_vendor_id
= PCI_SUBVENDOR_ID_REDHAT_QUMRANET
;
84 static uint16_t pci_default_sub_device_id
= PCI_SUBDEVICE_ID_QEMU
;
89 QLIST_ENTRY(PCIHostBus
) next
;
91 static QLIST_HEAD(, PCIHostBus
) host_buses
;
93 static const VMStateDescription vmstate_pcibus
= {
96 .minimum_version_id
= 1,
97 .minimum_version_id_old
= 1,
98 .fields
= (VMStateField
[]) {
99 VMSTATE_INT32_EQUAL(nirq
, PCIBus
),
100 VMSTATE_VARRAY_INT32(irq_count
, PCIBus
, nirq
, 0, vmstate_info_int32
, int32_t),
101 VMSTATE_END_OF_LIST()
105 static int pci_bar(PCIDevice
*d
, int reg
)
109 if (reg
!= PCI_ROM_SLOT
)
110 return PCI_BASE_ADDRESS_0
+ reg
* 4;
112 type
= d
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
113 return type
== PCI_HEADER_TYPE_BRIDGE
? PCI_ROM_ADDRESS1
: PCI_ROM_ADDRESS
;
116 static inline int pci_irq_state(PCIDevice
*d
, int irq_num
)
118 return (d
->irq_state
>> irq_num
) & 0x1;
121 static inline void pci_set_irq_state(PCIDevice
*d
, int irq_num
, int level
)
123 d
->irq_state
&= ~(0x1 << irq_num
);
124 d
->irq_state
|= level
<< irq_num
;
127 static void pci_change_irq_level(PCIDevice
*pci_dev
, int irq_num
, int change
)
132 irq_num
= bus
->map_irq(pci_dev
, irq_num
);
135 pci_dev
= bus
->parent_dev
;
137 bus
->irq_count
[irq_num
] += change
;
138 bus
->set_irq(bus
->irq_opaque
, irq_num
, bus
->irq_count
[irq_num
] != 0);
141 /* Update interrupt status bit in config space on interrupt
143 static void pci_update_irq_status(PCIDevice
*dev
)
145 if (dev
->irq_state
) {
146 dev
->config
[PCI_STATUS
] |= PCI_STATUS_INTERRUPT
;
148 dev
->config
[PCI_STATUS
] &= ~PCI_STATUS_INTERRUPT
;
152 static void pci_device_reset(PCIDevice
*dev
)
157 pci_update_irq_status(dev
);
158 dev
->config
[PCI_COMMAND
] &= ~(PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
|
160 dev
->config
[PCI_CACHE_LINE_SIZE
] = 0x0;
161 dev
->config
[PCI_INTERRUPT_LINE
] = 0x0;
162 for (r
= 0; r
< PCI_NUM_REGIONS
; ++r
) {
163 if (!dev
->io_regions
[r
].size
) {
166 pci_set_long(dev
->config
+ pci_bar(dev
, r
), dev
->io_regions
[r
].type
);
168 pci_update_mappings(dev
);
171 static void pci_bus_reset(void *opaque
)
173 PCIBus
*bus
= opaque
;
176 for (i
= 0; i
< bus
->nirq
; i
++) {
177 bus
->irq_count
[i
] = 0;
179 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); ++i
) {
180 if (bus
->devices
[i
]) {
181 pci_device_reset(bus
->devices
[i
]);
186 static void pci_host_bus_register(int domain
, PCIBus
*bus
)
188 struct PCIHostBus
*host
;
189 host
= qemu_mallocz(sizeof(*host
));
190 host
->domain
= domain
;
192 QLIST_INSERT_HEAD(&host_buses
, host
, next
);
195 PCIBus
*pci_find_root_bus(int domain
)
197 struct PCIHostBus
*host
;
199 QLIST_FOREACH(host
, &host_buses
, next
) {
200 if (host
->domain
== domain
) {
208 int pci_find_domain(const PCIBus
*bus
)
211 struct PCIHostBus
*host
;
213 /* obtain root bus */
214 while ((d
= bus
->parent_dev
) != NULL
) {
218 QLIST_FOREACH(host
, &host_buses
, next
) {
219 if (host
->bus
== bus
) {
224 abort(); /* should not be reached */
228 void pci_bus_new_inplace(PCIBus
*bus
, DeviceState
*parent
,
229 const char *name
, int devfn_min
)
231 qbus_create_inplace(&bus
->qbus
, &pci_bus_info
, parent
, name
);
232 assert(PCI_FUNC(devfn_min
) == 0);
233 bus
->devfn_min
= devfn_min
;
236 QLIST_INIT(&bus
->child
);
237 pci_host_bus_register(0, bus
); /* for now only pci domain 0 is supported */
239 vmstate_register(NULL
, -1, &vmstate_pcibus
, bus
);
240 qemu_register_reset(pci_bus_reset
, bus
);
243 PCIBus
*pci_bus_new(DeviceState
*parent
, const char *name
, int devfn_min
)
247 bus
= qemu_mallocz(sizeof(*bus
));
248 bus
->qbus
.qdev_allocated
= 1;
249 pci_bus_new_inplace(bus
, parent
, name
, devfn_min
);
253 void pci_bus_irqs(PCIBus
*bus
, pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
254 void *irq_opaque
, int nirq
)
256 bus
->set_irq
= set_irq
;
257 bus
->map_irq
= map_irq
;
258 bus
->irq_opaque
= irq_opaque
;
260 bus
->irq_count
= qemu_mallocz(nirq
* sizeof(bus
->irq_count
[0]));
263 void pci_bus_hotplug(PCIBus
*bus
, pci_hotplug_fn hotplug
, DeviceState
*qdev
)
265 bus
->qbus
.allow_hotplug
= 1;
266 bus
->hotplug
= hotplug
;
267 bus
->hotplug_qdev
= qdev
;
270 void pci_bus_set_mem_base(PCIBus
*bus
, target_phys_addr_t base
)
272 bus
->mem_base
= base
;
275 PCIBus
*pci_register_bus(DeviceState
*parent
, const char *name
,
276 pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
277 void *irq_opaque
, int devfn_min
, int nirq
)
281 bus
= pci_bus_new(parent
, name
, devfn_min
);
282 pci_bus_irqs(bus
, set_irq
, map_irq
, irq_opaque
, nirq
);
286 static void pci_register_secondary_bus(PCIBus
*parent
,
289 pci_map_irq_fn map_irq
,
292 qbus_create_inplace(&bus
->qbus
, &pci_bus_info
, &dev
->qdev
, name
);
293 bus
->map_irq
= map_irq
;
294 bus
->parent_dev
= dev
;
296 QLIST_INIT(&bus
->child
);
297 QLIST_INSERT_HEAD(&parent
->child
, bus
, sibling
);
300 static void pci_unregister_secondary_bus(PCIBus
*bus
)
302 assert(QLIST_EMPTY(&bus
->child
));
303 QLIST_REMOVE(bus
, sibling
);
306 int pci_bus_num(PCIBus
*s
)
309 return 0; /* pci host bridge */
310 return s
->parent_dev
->config
[PCI_SECONDARY_BUS
];
313 static int get_pci_config_device(QEMUFile
*f
, void *pv
, size_t size
)
315 PCIDevice
*s
= container_of(pv
, PCIDevice
, config
);
319 assert(size
== pci_config_size(s
));
320 config
= qemu_malloc(size
);
322 qemu_get_buffer(f
, config
, size
);
323 for (i
= 0; i
< size
; ++i
) {
324 if ((config
[i
] ^ s
->config
[i
]) & s
->cmask
[i
] & ~s
->wmask
[i
]) {
329 memcpy(s
->config
, config
, size
);
331 pci_update_mappings(s
);
337 /* just put buffer */
338 static void put_pci_config_device(QEMUFile
*f
, void *pv
, size_t size
)
340 const uint8_t **v
= pv
;
341 assert(size
== pci_config_size(container_of(pv
, PCIDevice
, config
)));
342 qemu_put_buffer(f
, *v
, size
);
345 static VMStateInfo vmstate_info_pci_config
= {
346 .name
= "pci config",
347 .get
= get_pci_config_device
,
348 .put
= put_pci_config_device
,
351 static int get_pci_irq_state(QEMUFile
*f
, void *pv
, size_t size
)
353 PCIDevice
*s
= container_of(pv
, PCIDevice
, irq_state
);
354 uint32_t irq_state
[PCI_NUM_PINS
];
356 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
357 irq_state
[i
] = qemu_get_be32(f
);
358 if (irq_state
[i
] != 0x1 && irq_state
[i
] != 0) {
359 fprintf(stderr
, "irq state %d: must be 0 or 1.\n",
365 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
366 pci_set_irq_state(s
, i
, irq_state
[i
]);
372 static void put_pci_irq_state(QEMUFile
*f
, void *pv
, size_t size
)
375 PCIDevice
*s
= container_of(pv
, PCIDevice
, irq_state
);
377 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
378 qemu_put_be32(f
, pci_irq_state(s
, i
));
382 static VMStateInfo vmstate_info_pci_irq_state
= {
383 .name
= "pci irq state",
384 .get
= get_pci_irq_state
,
385 .put
= put_pci_irq_state
,
388 const VMStateDescription vmstate_pci_device
= {
391 .minimum_version_id
= 1,
392 .minimum_version_id_old
= 1,
393 .fields
= (VMStateField
[]) {
394 VMSTATE_INT32_LE(version_id
, PCIDevice
),
395 VMSTATE_BUFFER_UNSAFE_INFO(config
, PCIDevice
, 0,
396 vmstate_info_pci_config
,
397 PCI_CONFIG_SPACE_SIZE
),
398 VMSTATE_BUFFER_UNSAFE_INFO(irq_state
, PCIDevice
, 2,
399 vmstate_info_pci_irq_state
,
400 PCI_NUM_PINS
* sizeof(int32_t)),
401 VMSTATE_END_OF_LIST()
405 const VMStateDescription vmstate_pcie_device
= {
408 .minimum_version_id
= 1,
409 .minimum_version_id_old
= 1,
410 .fields
= (VMStateField
[]) {
411 VMSTATE_INT32_LE(version_id
, PCIDevice
),
412 VMSTATE_BUFFER_UNSAFE_INFO(config
, PCIDevice
, 0,
413 vmstate_info_pci_config
,
414 PCIE_CONFIG_SPACE_SIZE
),
415 VMSTATE_BUFFER_UNSAFE_INFO(irq_state
, PCIDevice
, 2,
416 vmstate_info_pci_irq_state
,
417 PCI_NUM_PINS
* sizeof(int32_t)),
418 VMSTATE_END_OF_LIST()
422 static inline const VMStateDescription
*pci_get_vmstate(PCIDevice
*s
)
424 return pci_is_express(s
) ? &vmstate_pcie_device
: &vmstate_pci_device
;
427 void pci_device_save(PCIDevice
*s
, QEMUFile
*f
)
429 /* Clear interrupt status bit: it is implicit
430 * in irq_state which we are saving.
431 * This makes us compatible with old devices
432 * which never set or clear this bit. */
433 s
->config
[PCI_STATUS
] &= ~PCI_STATUS_INTERRUPT
;
434 vmstate_save_state(f
, pci_get_vmstate(s
), s
);
435 /* Restore the interrupt status bit. */
436 pci_update_irq_status(s
);
439 int pci_device_load(PCIDevice
*s
, QEMUFile
*f
)
442 ret
= vmstate_load_state(f
, pci_get_vmstate(s
), s
, s
->version_id
);
443 /* Restore the interrupt status bit. */
444 pci_update_irq_status(s
);
448 static void pci_set_default_subsystem_id(PCIDevice
*pci_dev
)
450 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_VENDOR_ID
,
451 pci_default_sub_vendor_id
);
452 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_ID
,
453 pci_default_sub_device_id
);
457 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
459 static int pci_parse_devaddr(const char *addr
, int *domp
, int *busp
, unsigned *slotp
)
464 unsigned long dom
= 0, bus
= 0;
468 val
= strtoul(p
, &e
, 16);
474 val
= strtoul(p
, &e
, 16);
481 val
= strtoul(p
, &e
, 16);
487 if (dom
> 0xffff || bus
> 0xff || val
> 0x1f)
495 /* Note: QEMU doesn't implement domains other than 0 */
496 if (!pci_find_bus(pci_find_root_bus(dom
), bus
))
505 int pci_read_devaddr(Monitor
*mon
, const char *addr
, int *domp
, int *busp
,
508 /* strip legacy tag */
509 if (!strncmp(addr
, "pci_addr=", 9)) {
512 if (pci_parse_devaddr(addr
, domp
, busp
, slotp
)) {
513 monitor_printf(mon
, "Invalid pci address\n");
519 PCIBus
*pci_get_bus_devfn(int *devfnp
, const char *devaddr
)
526 return pci_find_bus(pci_find_root_bus(0), 0);
529 if (pci_parse_devaddr(devaddr
, &dom
, &bus
, &slot
) < 0) {
534 return pci_find_bus(pci_find_root_bus(dom
), bus
);
537 static void pci_init_cmask(PCIDevice
*dev
)
539 pci_set_word(dev
->cmask
+ PCI_VENDOR_ID
, 0xffff);
540 pci_set_word(dev
->cmask
+ PCI_DEVICE_ID
, 0xffff);
541 dev
->cmask
[PCI_STATUS
] = PCI_STATUS_CAP_LIST
;
542 dev
->cmask
[PCI_REVISION_ID
] = 0xff;
543 dev
->cmask
[PCI_CLASS_PROG
] = 0xff;
544 pci_set_word(dev
->cmask
+ PCI_CLASS_DEVICE
, 0xffff);
545 dev
->cmask
[PCI_HEADER_TYPE
] = 0xff;
546 dev
->cmask
[PCI_CAPABILITY_LIST
] = 0xff;
549 static void pci_init_wmask(PCIDevice
*dev
)
551 int config_size
= pci_config_size(dev
);
553 dev
->wmask
[PCI_CACHE_LINE_SIZE
] = 0xff;
554 dev
->wmask
[PCI_INTERRUPT_LINE
] = 0xff;
555 pci_set_word(dev
->wmask
+ PCI_COMMAND
,
556 PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
|
557 PCI_COMMAND_INTX_DISABLE
);
559 memset(dev
->wmask
+ PCI_CONFIG_HEADER_SIZE
, 0xff,
560 config_size
- PCI_CONFIG_HEADER_SIZE
);
563 static void pci_init_wmask_bridge(PCIDevice
*d
)
565 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
566 PCI_SEC_LETENCY_TIMER */
567 memset(d
->wmask
+ PCI_PRIMARY_BUS
, 0xff, 4);
570 d
->wmask
[PCI_IO_BASE
] = PCI_IO_RANGE_MASK
& 0xff;
571 d
->wmask
[PCI_IO_LIMIT
] = PCI_IO_RANGE_MASK
& 0xff;
572 pci_set_word(d
->wmask
+ PCI_MEMORY_BASE
,
573 PCI_MEMORY_RANGE_MASK
& 0xffff);
574 pci_set_word(d
->wmask
+ PCI_MEMORY_LIMIT
,
575 PCI_MEMORY_RANGE_MASK
& 0xffff);
576 pci_set_word(d
->wmask
+ PCI_PREF_MEMORY_BASE
,
577 PCI_PREF_RANGE_MASK
& 0xffff);
578 pci_set_word(d
->wmask
+ PCI_PREF_MEMORY_LIMIT
,
579 PCI_PREF_RANGE_MASK
& 0xffff);
581 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
582 memset(d
->wmask
+ PCI_PREF_BASE_UPPER32
, 0xff, 8);
584 pci_set_word(d
->wmask
+ PCI_BRIDGE_CONTROL
, 0xffff);
587 static int pci_init_multifunction(PCIBus
*bus
, PCIDevice
*dev
)
589 uint8_t slot
= PCI_SLOT(dev
->devfn
);
592 if (dev
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
) {
593 dev
->config
[PCI_HEADER_TYPE
] |= PCI_HEADER_TYPE_MULTI_FUNCTION
;
597 * multifuction bit is interpreted in two ways as follows.
598 * - all functions must set the bit to 1.
600 * - function 0 must set the bit, but the rest function (> 0)
601 * is allowed to leave the bit to 0.
602 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
604 * So OS (at least Linux) checks the bit of only function 0,
605 * and doesn't see the bit of function > 0.
607 * The below check allows both interpretation.
609 if (PCI_FUNC(dev
->devfn
)) {
610 PCIDevice
*f0
= bus
->devices
[PCI_DEVFN(slot
, 0)];
611 if (f0
&& !(f0
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
)) {
612 /* function 0 should set multifunction bit */
613 error_report("PCI: single function device can't be populated "
614 "in function %x.%x", slot
, PCI_FUNC(dev
->devfn
));
620 if (dev
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
) {
623 /* function 0 indicates single function, so function > 0 must be NULL */
624 for (func
= 1; func
< PCI_FUNC_MAX
; ++func
) {
625 if (bus
->devices
[PCI_DEVFN(slot
, func
)]) {
626 error_report("PCI: %x.0 indicates single function, "
627 "but %x.%x is already populated.",
635 static void pci_config_alloc(PCIDevice
*pci_dev
)
637 int config_size
= pci_config_size(pci_dev
);
639 pci_dev
->config
= qemu_mallocz(config_size
);
640 pci_dev
->cmask
= qemu_mallocz(config_size
);
641 pci_dev
->wmask
= qemu_mallocz(config_size
);
642 pci_dev
->used
= qemu_mallocz(config_size
);
645 static void pci_config_free(PCIDevice
*pci_dev
)
647 qemu_free(pci_dev
->config
);
648 qemu_free(pci_dev
->cmask
);
649 qemu_free(pci_dev
->wmask
);
650 qemu_free(pci_dev
->used
);
653 /* -1 for devfn means auto assign */
654 static PCIDevice
*do_pci_register_device(PCIDevice
*pci_dev
, PCIBus
*bus
,
655 const char *name
, int devfn
,
656 PCIConfigReadFunc
*config_read
,
657 PCIConfigWriteFunc
*config_write
,
661 for(devfn
= bus
->devfn_min
; devfn
< ARRAY_SIZE(bus
->devices
);
662 devfn
+= PCI_FUNC_MAX
) {
663 if (!bus
->devices
[devfn
])
666 error_report("PCI: no slot/function available for %s, all in use", name
);
669 } else if (bus
->devices
[devfn
]) {
670 error_report("PCI: slot %d function %d not available for %s, in use by %s",
671 PCI_SLOT(devfn
), PCI_FUNC(devfn
), name
, bus
->devices
[devfn
]->name
);
675 pci_dev
->devfn
= devfn
;
676 pstrcpy(pci_dev
->name
, sizeof(pci_dev
->name
), name
);
677 pci_dev
->irq_state
= 0;
678 pci_config_alloc(pci_dev
);
681 pci_set_default_subsystem_id(pci_dev
);
683 pci_init_cmask(pci_dev
);
684 pci_init_wmask(pci_dev
);
686 pci_init_wmask_bridge(pci_dev
);
688 if (pci_init_multifunction(bus
, pci_dev
)) {
689 pci_config_free(pci_dev
);
694 config_read
= pci_default_read_config
;
696 config_write
= pci_default_write_config
;
697 pci_dev
->config_read
= config_read
;
698 pci_dev
->config_write
= config_write
;
699 bus
->devices
[devfn
] = pci_dev
;
700 pci_dev
->irq
= qemu_allocate_irqs(pci_set_irq
, pci_dev
, PCI_NUM_PINS
);
701 pci_dev
->version_id
= 2; /* Current pci device vmstate version */
705 static void do_pci_unregister_device(PCIDevice
*pci_dev
)
707 qemu_free_irqs(pci_dev
->irq
);
708 pci_dev
->bus
->devices
[pci_dev
->devfn
] = NULL
;
709 pci_config_free(pci_dev
);
712 PCIDevice
*pci_register_device(PCIBus
*bus
, const char *name
,
713 int instance_size
, int devfn
,
714 PCIConfigReadFunc
*config_read
,
715 PCIConfigWriteFunc
*config_write
)
719 pci_dev
= qemu_mallocz(instance_size
);
720 pci_dev
= do_pci_register_device(pci_dev
, bus
, name
, devfn
,
721 config_read
, config_write
,
722 PCI_HEADER_TYPE_NORMAL
);
723 if (pci_dev
== NULL
) {
724 hw_error("PCI: can't register device\n");
729 static target_phys_addr_t
pci_to_cpu_addr(PCIBus
*bus
,
730 target_phys_addr_t addr
)
732 return addr
+ bus
->mem_base
;
735 static void pci_unregister_io_regions(PCIDevice
*pci_dev
)
740 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
741 r
= &pci_dev
->io_regions
[i
];
742 if (!r
->size
|| r
->addr
== PCI_BAR_UNMAPPED
)
744 if (r
->type
== PCI_BASE_ADDRESS_SPACE_IO
) {
745 isa_unassign_ioport(r
->addr
, r
->filtered_size
);
747 cpu_register_physical_memory(pci_to_cpu_addr(pci_dev
->bus
,
755 static int pci_unregister_device(DeviceState
*dev
)
757 PCIDevice
*pci_dev
= DO_UPCAST(PCIDevice
, qdev
, dev
);
758 PCIDeviceInfo
*info
= DO_UPCAST(PCIDeviceInfo
, qdev
, dev
->info
);
762 ret
= info
->exit(pci_dev
);
766 pci_unregister_io_regions(pci_dev
);
767 pci_del_option_rom(pci_dev
);
768 do_pci_unregister_device(pci_dev
);
772 void pci_register_bar(PCIDevice
*pci_dev
, int region_num
,
773 pcibus_t size
, int type
,
774 PCIMapIORegionFunc
*map_func
)
780 if ((unsigned int)region_num
>= PCI_NUM_REGIONS
)
783 if (size
& (size
-1)) {
784 fprintf(stderr
, "ERROR: PCI region size must be pow2 "
785 "type=0x%x, size=0x%"FMT_PCIBUS
"\n", type
, size
);
789 r
= &pci_dev
->io_regions
[region_num
];
790 r
->addr
= PCI_BAR_UNMAPPED
;
792 r
->filtered_size
= size
;
794 r
->map_func
= map_func
;
797 addr
= pci_bar(pci_dev
, region_num
);
798 if (region_num
== PCI_ROM_SLOT
) {
799 /* ROM enable bit is writeable */
800 wmask
|= PCI_ROM_ADDRESS_ENABLE
;
802 pci_set_long(pci_dev
->config
+ addr
, type
);
803 if (!(r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) &&
804 r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
805 pci_set_quad(pci_dev
->wmask
+ addr
, wmask
);
806 pci_set_quad(pci_dev
->cmask
+ addr
, ~0ULL);
808 pci_set_long(pci_dev
->wmask
+ addr
, wmask
& 0xffffffff);
809 pci_set_long(pci_dev
->cmask
+ addr
, 0xffffffff);
813 static uint32_t pci_config_get_io_base(PCIDevice
*d
,
814 uint32_t base
, uint32_t base_upper16
)
818 val
= ((uint32_t)d
->config
[base
] & PCI_IO_RANGE_MASK
) << 8;
819 if (d
->config
[base
] & PCI_IO_RANGE_TYPE_32
) {
820 val
|= (uint32_t)pci_get_word(d
->config
+ base_upper16
) << 16;
825 static pcibus_t
pci_config_get_memory_base(PCIDevice
*d
, uint32_t base
)
827 return ((pcibus_t
)pci_get_word(d
->config
+ base
) & PCI_MEMORY_RANGE_MASK
)
831 static pcibus_t
pci_config_get_pref_base(PCIDevice
*d
,
832 uint32_t base
, uint32_t upper
)
837 tmp
= (pcibus_t
)pci_get_word(d
->config
+ base
);
838 val
= (tmp
& PCI_PREF_RANGE_MASK
) << 16;
839 if (tmp
& PCI_PREF_RANGE_TYPE_64
) {
840 val
|= (pcibus_t
)pci_get_long(d
->config
+ upper
) << 32;
845 static pcibus_t
pci_bridge_get_base(PCIDevice
*bridge
, uint8_t type
)
848 if (type
& PCI_BASE_ADDRESS_SPACE_IO
) {
849 base
= pci_config_get_io_base(bridge
,
850 PCI_IO_BASE
, PCI_IO_BASE_UPPER16
);
852 if (type
& PCI_BASE_ADDRESS_MEM_PREFETCH
) {
853 base
= pci_config_get_pref_base(
854 bridge
, PCI_PREF_MEMORY_BASE
, PCI_PREF_BASE_UPPER32
);
856 base
= pci_config_get_memory_base(bridge
, PCI_MEMORY_BASE
);
863 static pcibus_t
pci_bridge_get_limit(PCIDevice
*bridge
, uint8_t type
)
866 if (type
& PCI_BASE_ADDRESS_SPACE_IO
) {
867 limit
= pci_config_get_io_base(bridge
,
868 PCI_IO_LIMIT
, PCI_IO_LIMIT_UPPER16
);
869 limit
|= 0xfff; /* PCI bridge spec 3.2.5.6. */
871 if (type
& PCI_BASE_ADDRESS_MEM_PREFETCH
) {
872 limit
= pci_config_get_pref_base(
873 bridge
, PCI_PREF_MEMORY_LIMIT
, PCI_PREF_LIMIT_UPPER32
);
875 limit
= pci_config_get_memory_base(bridge
, PCI_MEMORY_LIMIT
);
877 limit
|= 0xfffff; /* PCI bridge spec 3.2.5.{1, 8}. */
882 static void pci_bridge_filter(PCIDevice
*d
, pcibus_t
*addr
, pcibus_t
*size
,
885 pcibus_t base
= *addr
;
886 pcibus_t limit
= *addr
+ *size
- 1;
889 for (br
= d
->bus
->parent_dev
; br
; br
= br
->bus
->parent_dev
) {
890 uint16_t cmd
= pci_get_word(d
->config
+ PCI_COMMAND
);
892 if (type
& PCI_BASE_ADDRESS_SPACE_IO
) {
893 if (!(cmd
& PCI_COMMAND_IO
)) {
897 if (!(cmd
& PCI_COMMAND_MEMORY
)) {
902 base
= MAX(base
, pci_bridge_get_base(br
, type
));
903 limit
= MIN(limit
, pci_bridge_get_limit(br
, type
));
910 *size
= limit
- base
+ 1;
913 *addr
= PCI_BAR_UNMAPPED
;
917 static pcibus_t
pci_bar_address(PCIDevice
*d
,
918 int reg
, uint8_t type
, pcibus_t size
)
920 pcibus_t new_addr
, last_addr
;
921 int bar
= pci_bar(d
, reg
);
922 uint16_t cmd
= pci_get_word(d
->config
+ PCI_COMMAND
);
924 if (type
& PCI_BASE_ADDRESS_SPACE_IO
) {
925 if (!(cmd
& PCI_COMMAND_IO
)) {
926 return PCI_BAR_UNMAPPED
;
928 new_addr
= pci_get_long(d
->config
+ bar
) & ~(size
- 1);
929 last_addr
= new_addr
+ size
- 1;
930 /* NOTE: we have only 64K ioports on PC */
931 if (last_addr
<= new_addr
|| new_addr
== 0 || last_addr
> UINT16_MAX
) {
932 return PCI_BAR_UNMAPPED
;
937 if (!(cmd
& PCI_COMMAND_MEMORY
)) {
938 return PCI_BAR_UNMAPPED
;
940 if (type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
941 new_addr
= pci_get_quad(d
->config
+ bar
);
943 new_addr
= pci_get_long(d
->config
+ bar
);
945 /* the ROM slot has a specific enable bit */
946 if (reg
== PCI_ROM_SLOT
&& !(new_addr
& PCI_ROM_ADDRESS_ENABLE
)) {
947 return PCI_BAR_UNMAPPED
;
949 new_addr
&= ~(size
- 1);
950 last_addr
= new_addr
+ size
- 1;
951 /* NOTE: we do not support wrapping */
952 /* XXX: as we cannot support really dynamic
953 mappings, we handle specific values as invalid
955 if (last_addr
<= new_addr
|| new_addr
== 0 ||
956 last_addr
== PCI_BAR_UNMAPPED
) {
957 return PCI_BAR_UNMAPPED
;
960 /* Now pcibus_t is 64bit.
961 * Check if 32 bit BAR wraps around explicitly.
962 * Without this, PC ide doesn't work well.
963 * TODO: remove this work around.
965 if (!(type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) && last_addr
>= UINT32_MAX
) {
966 return PCI_BAR_UNMAPPED
;
970 * OS is allowed to set BAR beyond its addressable
971 * bits. For example, 32 bit OS can set 64bit bar
972 * to >4G. Check it. TODO: we might need to support
973 * it in the future for e.g. PAE.
975 if (last_addr
>= TARGET_PHYS_ADDR_MAX
) {
976 return PCI_BAR_UNMAPPED
;
982 static void pci_update_mappings(PCIDevice
*d
)
986 pcibus_t new_addr
, filtered_size
;
988 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
989 r
= &d
->io_regions
[i
];
991 /* this region isn't registered */
995 new_addr
= pci_bar_address(d
, i
, r
->type
, r
->size
);
997 /* bridge filtering */
998 filtered_size
= r
->size
;
999 if (new_addr
!= PCI_BAR_UNMAPPED
) {
1000 pci_bridge_filter(d
, &new_addr
, &filtered_size
, r
->type
);
1003 /* This bar isn't changed */
1004 if (new_addr
== r
->addr
&& filtered_size
== r
->filtered_size
)
1007 /* now do the real mapping */
1008 if (r
->addr
!= PCI_BAR_UNMAPPED
) {
1009 if (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) {
1011 /* NOTE: specific hack for IDE in PC case:
1012 only one byte must be mapped. */
1013 class = pci_get_word(d
->config
+ PCI_CLASS_DEVICE
);
1014 if (class == 0x0101 && r
->size
== 4) {
1015 isa_unassign_ioport(r
->addr
+ 2, 1);
1017 isa_unassign_ioport(r
->addr
, r
->filtered_size
);
1020 cpu_register_physical_memory(pci_to_cpu_addr(d
->bus
, r
->addr
),
1023 qemu_unregister_coalesced_mmio(r
->addr
, r
->filtered_size
);
1027 r
->filtered_size
= filtered_size
;
1028 if (r
->addr
!= PCI_BAR_UNMAPPED
) {
1030 * TODO: currently almost all the map funcions assumes
1031 * filtered_size == size and addr & ~(size - 1) == addr.
1032 * However with bridge filtering, they aren't always true.
1033 * Teach them such cases, such that filtered_size < size and
1034 * addr & (size - 1) != 0.
1036 if (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) {
1037 r
->map_func(d
, i
, r
->addr
, r
->filtered_size
, r
->type
);
1039 r
->map_func(d
, i
, pci_to_cpu_addr(d
->bus
, r
->addr
),
1040 r
->filtered_size
, r
->type
);
1046 static inline int pci_irq_disabled(PCIDevice
*d
)
1048 return pci_get_word(d
->config
+ PCI_COMMAND
) & PCI_COMMAND_INTX_DISABLE
;
1051 /* Called after interrupt disabled field update in config space,
1052 * assert/deassert interrupts if necessary.
1053 * Gets original interrupt disable bit value (before update). */
1054 static void pci_update_irq_disabled(PCIDevice
*d
, int was_irq_disabled
)
1056 int i
, disabled
= pci_irq_disabled(d
);
1057 if (disabled
== was_irq_disabled
)
1059 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
1060 int state
= pci_irq_state(d
, i
);
1061 pci_change_irq_level(d
, i
, disabled
? -state
: state
);
1065 uint32_t pci_default_read_config(PCIDevice
*d
,
1066 uint32_t address
, int len
)
1069 assert(len
== 1 || len
== 2 || len
== 4);
1070 len
= MIN(len
, pci_config_size(d
) - address
);
1071 memcpy(&val
, d
->config
+ address
, len
);
1072 return le32_to_cpu(val
);
1075 void pci_default_write_config(PCIDevice
*d
, uint32_t addr
, uint32_t val
, int l
)
1077 int i
, was_irq_disabled
= pci_irq_disabled(d
);
1078 uint32_t config_size
= pci_config_size(d
);
1080 for (i
= 0; i
< l
&& addr
+ i
< config_size
; val
>>= 8, ++i
) {
1081 uint8_t wmask
= d
->wmask
[addr
+ i
];
1082 d
->config
[addr
+ i
] = (d
->config
[addr
+ i
] & ~wmask
) | (val
& wmask
);
1084 if (ranges_overlap(addr
, l
, PCI_BASE_ADDRESS_0
, 24) ||
1085 ranges_overlap(addr
, l
, PCI_ROM_ADDRESS
, 4) ||
1086 ranges_overlap(addr
, l
, PCI_ROM_ADDRESS1
, 4) ||
1087 range_covers_byte(addr
, l
, PCI_COMMAND
))
1088 pci_update_mappings(d
);
1090 if (range_covers_byte(addr
, l
, PCI_COMMAND
))
1091 pci_update_irq_disabled(d
, was_irq_disabled
);
1094 /***********************************************************/
1095 /* generic PCI irq support */
1097 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1098 static void pci_set_irq(void *opaque
, int irq_num
, int level
)
1100 PCIDevice
*pci_dev
= opaque
;
1103 change
= level
- pci_irq_state(pci_dev
, irq_num
);
1107 pci_set_irq_state(pci_dev
, irq_num
, level
);
1108 pci_update_irq_status(pci_dev
);
1109 if (pci_irq_disabled(pci_dev
))
1111 pci_change_irq_level(pci_dev
, irq_num
, change
);
1114 /***********************************************************/
1115 /* monitor info on PCI */
1122 static const pci_class_desc pci_class_descriptions
[] =
1124 { 0x0100, "SCSI controller"},
1125 { 0x0101, "IDE controller"},
1126 { 0x0102, "Floppy controller"},
1127 { 0x0103, "IPI controller"},
1128 { 0x0104, "RAID controller"},
1129 { 0x0106, "SATA controller"},
1130 { 0x0107, "SAS controller"},
1131 { 0x0180, "Storage controller"},
1132 { 0x0200, "Ethernet controller"},
1133 { 0x0201, "Token Ring controller"},
1134 { 0x0202, "FDDI controller"},
1135 { 0x0203, "ATM controller"},
1136 { 0x0280, "Network controller"},
1137 { 0x0300, "VGA controller"},
1138 { 0x0301, "XGA controller"},
1139 { 0x0302, "3D controller"},
1140 { 0x0380, "Display controller"},
1141 { 0x0400, "Video controller"},
1142 { 0x0401, "Audio controller"},
1144 { 0x0480, "Multimedia controller"},
1145 { 0x0500, "RAM controller"},
1146 { 0x0501, "Flash controller"},
1147 { 0x0580, "Memory controller"},
1148 { 0x0600, "Host bridge"},
1149 { 0x0601, "ISA bridge"},
1150 { 0x0602, "EISA bridge"},
1151 { 0x0603, "MC bridge"},
1152 { 0x0604, "PCI bridge"},
1153 { 0x0605, "PCMCIA bridge"},
1154 { 0x0606, "NUBUS bridge"},
1155 { 0x0607, "CARDBUS bridge"},
1156 { 0x0608, "RACEWAY bridge"},
1157 { 0x0680, "Bridge"},
1158 { 0x0c03, "USB controller"},
1162 static void pci_for_each_device_under_bus(PCIBus
*bus
,
1163 void (*fn
)(PCIBus
*b
, PCIDevice
*d
))
1168 for(devfn
= 0; devfn
< ARRAY_SIZE(bus
->devices
); devfn
++) {
1169 d
= bus
->devices
[devfn
];
1176 void pci_for_each_device(PCIBus
*bus
, int bus_num
,
1177 void (*fn
)(PCIBus
*b
, PCIDevice
*d
))
1179 bus
= pci_find_bus(bus
, bus_num
);
1182 pci_for_each_device_under_bus(bus
, fn
);
1186 static void pci_device_print(Monitor
*mon
, QDict
*device
)
1190 uint64_t addr
, size
;
1192 monitor_printf(mon
, " Bus %2" PRId64
", ", qdict_get_int(device
, "bus"));
1193 monitor_printf(mon
, "device %3" PRId64
", function %" PRId64
":\n",
1194 qdict_get_int(device
, "slot"),
1195 qdict_get_int(device
, "function"));
1196 monitor_printf(mon
, " ");
1198 qdict
= qdict_get_qdict(device
, "class_info");
1199 if (qdict_haskey(qdict
, "desc")) {
1200 monitor_printf(mon
, "%s", qdict_get_str(qdict
, "desc"));
1202 monitor_printf(mon
, "Class %04" PRId64
, qdict_get_int(qdict
, "class"));
1205 qdict
= qdict_get_qdict(device
, "id");
1206 monitor_printf(mon
, ": PCI device %04" PRIx64
":%04" PRIx64
"\n",
1207 qdict_get_int(qdict
, "device"),
1208 qdict_get_int(qdict
, "vendor"));
1210 if (qdict_haskey(device
, "irq")) {
1211 monitor_printf(mon
, " IRQ %" PRId64
".\n",
1212 qdict_get_int(device
, "irq"));
1215 if (qdict_haskey(device
, "pci_bridge")) {
1218 qdict
= qdict_get_qdict(device
, "pci_bridge");
1220 info
= qdict_get_qdict(qdict
, "bus");
1221 monitor_printf(mon
, " BUS %" PRId64
".\n",
1222 qdict_get_int(info
, "number"));
1223 monitor_printf(mon
, " secondary bus %" PRId64
".\n",
1224 qdict_get_int(info
, "secondary"));
1225 monitor_printf(mon
, " subordinate bus %" PRId64
".\n",
1226 qdict_get_int(info
, "subordinate"));
1228 info
= qdict_get_qdict(qdict
, "io_range");
1229 monitor_printf(mon
, " IO range [0x%04"PRIx64
", 0x%04"PRIx64
"]\n",
1230 qdict_get_int(info
, "base"),
1231 qdict_get_int(info
, "limit"));
1233 info
= qdict_get_qdict(qdict
, "memory_range");
1235 " memory range [0x%08"PRIx64
", 0x%08"PRIx64
"]\n",
1236 qdict_get_int(info
, "base"),
1237 qdict_get_int(info
, "limit"));
1239 info
= qdict_get_qdict(qdict
, "prefetchable_range");
1240 monitor_printf(mon
, " prefetchable memory range "
1241 "[0x%08"PRIx64
", 0x%08"PRIx64
"]\n",
1242 qdict_get_int(info
, "base"),
1243 qdict_get_int(info
, "limit"));
1246 QLIST_FOREACH_ENTRY(qdict_get_qlist(device
, "regions"), entry
) {
1247 qdict
= qobject_to_qdict(qlist_entry_obj(entry
));
1248 monitor_printf(mon
, " BAR%d: ", (int) qdict_get_int(qdict
, "bar"));
1250 addr
= qdict_get_int(qdict
, "address");
1251 size
= qdict_get_int(qdict
, "size");
1253 if (!strcmp(qdict_get_str(qdict
, "type"), "io")) {
1254 monitor_printf(mon
, "I/O at 0x%04"FMT_PCIBUS
1255 " [0x%04"FMT_PCIBUS
"].\n",
1256 addr
, addr
+ size
- 1);
1258 monitor_printf(mon
, "%d bit%s memory at 0x%08"FMT_PCIBUS
1259 " [0x%08"FMT_PCIBUS
"].\n",
1260 qdict_get_bool(qdict
, "mem_type_64") ? 64 : 32,
1261 qdict_get_bool(qdict
, "prefetch") ?
1262 " prefetchable" : "", addr
, addr
+ size
- 1);
1266 monitor_printf(mon
, " id \"%s\"\n", qdict_get_str(device
, "qdev_id"));
1268 if (qdict_haskey(device
, "pci_bridge")) {
1269 qdict
= qdict_get_qdict(device
, "pci_bridge");
1270 if (qdict_haskey(qdict
, "devices")) {
1272 QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict
, "devices"), dev
) {
1273 pci_device_print(mon
, qobject_to_qdict(qlist_entry_obj(dev
)));
1279 void do_pci_info_print(Monitor
*mon
, const QObject
*data
)
1281 QListEntry
*bus
, *dev
;
1283 QLIST_FOREACH_ENTRY(qobject_to_qlist(data
), bus
) {
1284 QDict
*qdict
= qobject_to_qdict(qlist_entry_obj(bus
));
1285 QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict
, "devices"), dev
) {
1286 pci_device_print(mon
, qobject_to_qdict(qlist_entry_obj(dev
)));
1291 static QObject
*pci_get_dev_class(const PCIDevice
*dev
)
1294 const pci_class_desc
*desc
;
1296 class = pci_get_word(dev
->config
+ PCI_CLASS_DEVICE
);
1297 desc
= pci_class_descriptions
;
1298 while (desc
->desc
&& class != desc
->class)
1302 return qobject_from_jsonf("{ 'desc': %s, 'class': %d }",
1305 return qobject_from_jsonf("{ 'class': %d }", class);
1309 static QObject
*pci_get_dev_id(const PCIDevice
*dev
)
1311 return qobject_from_jsonf("{ 'device': %d, 'vendor': %d }",
1312 pci_get_word(dev
->config
+ PCI_VENDOR_ID
),
1313 pci_get_word(dev
->config
+ PCI_DEVICE_ID
));
1316 static QObject
*pci_get_regions_list(const PCIDevice
*dev
)
1319 QList
*regions_list
;
1321 regions_list
= qlist_new();
1323 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1325 const PCIIORegion
*r
= &dev
->io_regions
[i
];
1331 if (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) {
1332 obj
= qobject_from_jsonf("{ 'bar': %d, 'type': 'io', "
1333 "'address': %" PRId64
", "
1334 "'size': %" PRId64
" }",
1335 i
, r
->addr
, r
->size
);
1337 int mem_type_64
= r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
;
1339 obj
= qobject_from_jsonf("{ 'bar': %d, 'type': 'memory', "
1340 "'mem_type_64': %i, 'prefetch': %i, "
1341 "'address': %" PRId64
", "
1342 "'size': %" PRId64
" }",
1344 r
->type
& PCI_BASE_ADDRESS_MEM_PREFETCH
,
1348 qlist_append_obj(regions_list
, obj
);
1351 return QOBJECT(regions_list
);
1354 static QObject
*pci_get_devices_list(PCIBus
*bus
, int bus_num
);
1356 static QObject
*pci_get_dev_dict(PCIDevice
*dev
, PCIBus
*bus
, int bus_num
)
1361 obj
= qobject_from_jsonf("{ 'bus': %d, 'slot': %d, 'function': %d," "'class_info': %p, 'id': %p, 'regions': %p,"
1364 PCI_SLOT(dev
->devfn
), PCI_FUNC(dev
->devfn
),
1365 pci_get_dev_class(dev
), pci_get_dev_id(dev
),
1366 pci_get_regions_list(dev
),
1367 dev
->qdev
.id
? dev
->qdev
.id
: "");
1369 if (dev
->config
[PCI_INTERRUPT_PIN
] != 0) {
1370 QDict
*qdict
= qobject_to_qdict(obj
);
1371 qdict_put(qdict
, "irq", qint_from_int(dev
->config
[PCI_INTERRUPT_LINE
]));
1374 type
= dev
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
1375 if (type
== PCI_HEADER_TYPE_BRIDGE
) {
1377 QObject
*pci_bridge
;
1379 pci_bridge
= qobject_from_jsonf("{ 'bus': "
1380 "{ 'number': %d, 'secondary': %d, 'subordinate': %d }, "
1381 "'io_range': { 'base': %" PRId64
", 'limit': %" PRId64
"}, "
1382 "'memory_range': { 'base': %" PRId64
", 'limit': %" PRId64
"}, "
1383 "'prefetchable_range': { 'base': %" PRId64
", 'limit': %" PRId64
"} }",
1384 dev
->config
[PCI_PRIMARY_BUS
], dev
->config
[PCI_SECONDARY_BUS
],
1385 dev
->config
[PCI_SUBORDINATE_BUS
],
1386 pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_IO
),
1387 pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_IO
),
1388 pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
),
1389 pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
),
1390 pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
|
1391 PCI_BASE_ADDRESS_MEM_PREFETCH
),
1392 pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
|
1393 PCI_BASE_ADDRESS_MEM_PREFETCH
));
1395 if (dev
->config
[PCI_SECONDARY_BUS
] != 0) {
1396 PCIBus
*child_bus
= pci_find_bus(bus
, dev
->config
[PCI_SECONDARY_BUS
]);
1399 qdict
= qobject_to_qdict(pci_bridge
);
1400 qdict_put_obj(qdict
, "devices",
1401 pci_get_devices_list(child_bus
,
1402 dev
->config
[PCI_SECONDARY_BUS
]));
1405 qdict
= qobject_to_qdict(obj
);
1406 qdict_put_obj(qdict
, "pci_bridge", pci_bridge
);
1412 static QObject
*pci_get_devices_list(PCIBus
*bus
, int bus_num
)
1418 dev_list
= qlist_new();
1420 for (devfn
= 0; devfn
< ARRAY_SIZE(bus
->devices
); devfn
++) {
1421 dev
= bus
->devices
[devfn
];
1423 qlist_append_obj(dev_list
, pci_get_dev_dict(dev
, bus
, bus_num
));
1427 return QOBJECT(dev_list
);
1430 static QObject
*pci_get_bus_dict(PCIBus
*bus
, int bus_num
)
1432 bus
= pci_find_bus(bus
, bus_num
);
1434 return qobject_from_jsonf("{ 'bus': %d, 'devices': %p }",
1435 bus_num
, pci_get_devices_list(bus
, bus_num
));
1441 void do_pci_info(Monitor
*mon
, QObject
**ret_data
)
1444 struct PCIHostBus
*host
;
1446 bus_list
= qlist_new();
1448 QLIST_FOREACH(host
, &host_buses
, next
) {
1449 QObject
*obj
= pci_get_bus_dict(host
->bus
, 0);
1451 qlist_append_obj(bus_list
, obj
);
1455 *ret_data
= QOBJECT(bus_list
);
1458 static const char * const pci_nic_models
[] = {
1470 static const char * const pci_nic_names
[] = {
1482 /* Initialize a PCI NIC. */
1483 /* FIXME callers should check for failure, but don't */
1484 PCIDevice
*pci_nic_init(NICInfo
*nd
, const char *default_model
,
1485 const char *default_devaddr
)
1487 const char *devaddr
= nd
->devaddr
? nd
->devaddr
: default_devaddr
;
1494 i
= qemu_find_nic_model(nd
, pci_nic_models
, default_model
);
1498 bus
= pci_get_bus_devfn(&devfn
, devaddr
);
1500 error_report("Invalid PCI device address %s for device %s",
1501 devaddr
, pci_nic_names
[i
]);
1505 pci_dev
= pci_create(bus
, devfn
, pci_nic_names
[i
]);
1506 dev
= &pci_dev
->qdev
;
1507 qdev_set_nic_properties(dev
, nd
);
1508 if (qdev_init(dev
) < 0)
1513 PCIDevice
*pci_nic_init_nofail(NICInfo
*nd
, const char *default_model
,
1514 const char *default_devaddr
)
1518 if (qemu_show_nic_models(nd
->model
, pci_nic_models
))
1521 res
= pci_nic_init(nd
, default_model
, default_devaddr
);
1535 static void pci_bridge_update_mappings_fn(PCIBus
*b
, PCIDevice
*d
)
1537 pci_update_mappings(d
);
1540 static void pci_bridge_update_mappings(PCIBus
*b
)
1544 pci_for_each_device_under_bus(b
, pci_bridge_update_mappings_fn
);
1546 QLIST_FOREACH(child
, &b
->child
, sibling
) {
1547 pci_bridge_update_mappings(child
);
1551 static void pci_bridge_write_config(PCIDevice
*d
,
1552 uint32_t address
, uint32_t val
, int len
)
1554 pci_default_write_config(d
, address
, val
, len
);
1556 if (/* io base/limit */
1557 ranges_overlap(address
, len
, PCI_IO_BASE
, 2) ||
1559 /* memory base/limit, prefetchable base/limit and
1560 io base/limit upper 16 */
1561 ranges_overlap(address
, len
, PCI_MEMORY_BASE
, 20)) {
1562 pci_bridge_update_mappings(d
->bus
);
1566 PCIBus
*pci_find_bus(PCIBus
*bus
, int bus_num
)
1574 if (pci_bus_num(bus
) == bus_num
) {
1579 if (!bus
->parent_dev
/* host pci bridge */ ||
1580 (bus
->parent_dev
->config
[PCI_SECONDARY_BUS
] < bus_num
&&
1581 bus_num
<= bus
->parent_dev
->config
[PCI_SUBORDINATE_BUS
])) {
1582 for (; bus
; bus
= sec
) {
1583 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
1584 assert(sec
->parent_dev
);
1585 if (sec
->parent_dev
->config
[PCI_SECONDARY_BUS
] == bus_num
) {
1588 if (sec
->parent_dev
->config
[PCI_SECONDARY_BUS
] < bus_num
&&
1589 bus_num
<= sec
->parent_dev
->config
[PCI_SUBORDINATE_BUS
]) {
1599 PCIDevice
*pci_find_device(PCIBus
*bus
, int bus_num
, int slot
, int function
)
1601 bus
= pci_find_bus(bus
, bus_num
);
1606 return bus
->devices
[PCI_DEVFN(slot
, function
)];
1609 static int pci_bridge_initfn(PCIDevice
*dev
)
1611 PCIBridge
*s
= DO_UPCAST(PCIBridge
, dev
, dev
);
1613 pci_config_set_vendor_id(s
->dev
.config
, s
->vid
);
1614 pci_config_set_device_id(s
->dev
.config
, s
->did
);
1616 pci_set_word(dev
->config
+ PCI_STATUS
,
1617 PCI_STATUS_66MHZ
| PCI_STATUS_FAST_BACK
);
1618 pci_config_set_class(dev
->config
, PCI_CLASS_BRIDGE_PCI
);
1619 dev
->config
[PCI_HEADER_TYPE
] =
1620 (dev
->config
[PCI_HEADER_TYPE
] & PCI_HEADER_TYPE_MULTI_FUNCTION
) |
1621 PCI_HEADER_TYPE_BRIDGE
;
1622 pci_set_word(dev
->config
+ PCI_SEC_STATUS
,
1623 PCI_STATUS_66MHZ
| PCI_STATUS_FAST_BACK
);
1627 static int pci_bridge_exitfn(PCIDevice
*pci_dev
)
1629 PCIBridge
*s
= DO_UPCAST(PCIBridge
, dev
, pci_dev
);
1630 PCIBus
*bus
= &s
->bus
;
1631 pci_unregister_secondary_bus(bus
);
1635 PCIBus
*pci_bridge_init(PCIBus
*bus
, int devfn
, bool multifunction
,
1636 uint16_t vid
, uint16_t did
,
1637 pci_map_irq_fn map_irq
, const char *name
)
1642 dev
= pci_create_multifunction(bus
, devfn
, multifunction
, "pci-bridge");
1643 qdev_prop_set_uint32(&dev
->qdev
, "vendorid", vid
);
1644 qdev_prop_set_uint32(&dev
->qdev
, "deviceid", did
);
1645 qdev_init_nofail(&dev
->qdev
);
1647 s
= DO_UPCAST(PCIBridge
, dev
, dev
);
1648 pci_register_secondary_bus(bus
, &s
->bus
, &s
->dev
, map_irq
, name
);
1652 PCIDevice
*pci_bridge_get_device(PCIBus
*bus
)
1654 return bus
->parent_dev
;
1657 static int pci_qdev_init(DeviceState
*qdev
, DeviceInfo
*base
)
1659 PCIDevice
*pci_dev
= (PCIDevice
*)qdev
;
1660 PCIDeviceInfo
*info
= container_of(base
, PCIDeviceInfo
, qdev
);
1664 /* initialize cap_present for pci_is_express() and pci_config_size() */
1665 if (info
->is_express
) {
1666 pci_dev
->cap_present
|= QEMU_PCI_CAP_EXPRESS
;
1669 bus
= FROM_QBUS(PCIBus
, qdev_get_parent_bus(qdev
));
1670 devfn
= pci_dev
->devfn
;
1671 pci_dev
= do_pci_register_device(pci_dev
, bus
, base
->name
, devfn
,
1672 info
->config_read
, info
->config_write
,
1674 if (pci_dev
== NULL
)
1676 rc
= info
->init(pci_dev
);
1678 do_pci_unregister_device(pci_dev
);
1683 if (pci_dev
->romfile
== NULL
&& info
->romfile
!= NULL
)
1684 pci_dev
->romfile
= qemu_strdup(info
->romfile
);
1685 pci_add_option_rom(pci_dev
);
1687 if (qdev
->hotplugged
)
1688 bus
->hotplug(bus
->hotplug_qdev
, pci_dev
, 1);
1692 static int pci_unplug_device(DeviceState
*qdev
)
1694 PCIDevice
*dev
= DO_UPCAST(PCIDevice
, qdev
, qdev
);
1696 dev
->bus
->hotplug(dev
->bus
->hotplug_qdev
, dev
, 0);
1700 void pci_qdev_register(PCIDeviceInfo
*info
)
1702 info
->qdev
.init
= pci_qdev_init
;
1703 info
->qdev
.unplug
= pci_unplug_device
;
1704 info
->qdev
.exit
= pci_unregister_device
;
1705 info
->qdev
.bus_info
= &pci_bus_info
;
1706 qdev_register(&info
->qdev
);
1709 void pci_qdev_register_many(PCIDeviceInfo
*info
)
1711 while (info
->qdev
.name
) {
1712 pci_qdev_register(info
);
1717 PCIDevice
*pci_create_multifunction(PCIBus
*bus
, int devfn
, bool multifunction
,
1722 dev
= qdev_create(&bus
->qbus
, name
);
1723 qdev_prop_set_uint32(dev
, "addr", devfn
);
1724 qdev_prop_set_bit(dev
, "multifunction", multifunction
);
1725 return DO_UPCAST(PCIDevice
, qdev
, dev
);
1728 PCIDevice
*pci_create_simple_multifunction(PCIBus
*bus
, int devfn
,
1732 PCIDevice
*dev
= pci_create_multifunction(bus
, devfn
, multifunction
, name
);
1733 qdev_init_nofail(&dev
->qdev
);
1737 PCIDevice
*pci_create(PCIBus
*bus
, int devfn
, const char *name
)
1739 return pci_create_multifunction(bus
, devfn
, false, name
);
1742 PCIDevice
*pci_create_simple(PCIBus
*bus
, int devfn
, const char *name
)
1744 return pci_create_simple_multifunction(bus
, devfn
, false, name
);
1747 static int pci_find_space(PCIDevice
*pdev
, uint8_t size
)
1749 int config_size
= pci_config_size(pdev
);
1750 int offset
= PCI_CONFIG_HEADER_SIZE
;
1752 for (i
= PCI_CONFIG_HEADER_SIZE
; i
< config_size
; ++i
)
1755 else if (i
- offset
+ 1 == size
)
1760 static uint8_t pci_find_capability_list(PCIDevice
*pdev
, uint8_t cap_id
,
1765 if (!(pdev
->config
[PCI_STATUS
] & PCI_STATUS_CAP_LIST
))
1768 for (prev
= PCI_CAPABILITY_LIST
; (next
= pdev
->config
[prev
]);
1769 prev
= next
+ PCI_CAP_LIST_NEXT
)
1770 if (pdev
->config
[next
+ PCI_CAP_LIST_ID
] == cap_id
)
1778 static void pci_map_option_rom(PCIDevice
*pdev
, int region_num
, pcibus_t addr
, pcibus_t size
, int type
)
1780 cpu_register_physical_memory(addr
, size
, pdev
->rom_offset
);
1783 /* Add an option rom for the device */
1784 static int pci_add_option_rom(PCIDevice
*pdev
)
1793 if (strlen(pdev
->romfile
) == 0)
1796 if (!pdev
->rom_bar
) {
1798 * Load rom via fw_cfg instead of creating a rom bar,
1799 * for 0.11 compatibility.
1801 int class = pci_get_word(pdev
->config
+ PCI_CLASS_DEVICE
);
1802 if (class == 0x0300) {
1803 rom_add_vga(pdev
->romfile
);
1805 rom_add_option(pdev
->romfile
);
1810 path
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, pdev
->romfile
);
1812 path
= qemu_strdup(pdev
->romfile
);
1815 size
= get_image_size(path
);
1817 error_report("%s: failed to find romfile \"%s\"",
1818 __FUNCTION__
, pdev
->romfile
);
1821 if (size
& (size
- 1)) {
1822 size
= 1 << qemu_fls(size
);
1825 if (pdev
->qdev
.info
->vmsd
)
1826 snprintf(name
, sizeof(name
), "%s.rom", pdev
->qdev
.info
->vmsd
->name
);
1828 snprintf(name
, sizeof(name
), "%s.rom", pdev
->qdev
.info
->name
);
1829 pdev
->rom_offset
= qemu_ram_alloc(&pdev
->qdev
, name
, size
);
1831 ptr
= qemu_get_ram_ptr(pdev
->rom_offset
);
1832 load_image(path
, ptr
);
1835 pci_register_bar(pdev
, PCI_ROM_SLOT
, size
,
1836 0, pci_map_option_rom
);
1841 static void pci_del_option_rom(PCIDevice
*pdev
)
1843 if (!pdev
->rom_offset
)
1846 qemu_ram_free(pdev
->rom_offset
);
1847 pdev
->rom_offset
= 0;
1850 /* Reserve space and add capability to the linked list in pci config space */
1851 int pci_add_capability_at_offset(PCIDevice
*pdev
, uint8_t cap_id
,
1852 uint8_t offset
, uint8_t size
)
1854 uint8_t *config
= pdev
->config
+ offset
;
1855 config
[PCI_CAP_LIST_ID
] = cap_id
;
1856 config
[PCI_CAP_LIST_NEXT
] = pdev
->config
[PCI_CAPABILITY_LIST
];
1857 pdev
->config
[PCI_CAPABILITY_LIST
] = offset
;
1858 pdev
->config
[PCI_STATUS
] |= PCI_STATUS_CAP_LIST
;
1859 memset(pdev
->used
+ offset
, 0xFF, size
);
1860 /* Make capability read-only by default */
1861 memset(pdev
->wmask
+ offset
, 0, size
);
1862 /* Check capability by default */
1863 memset(pdev
->cmask
+ offset
, 0xFF, size
);
1867 /* Find and reserve space and add capability to the linked list
1868 * in pci config space */
1869 int pci_add_capability(PCIDevice
*pdev
, uint8_t cap_id
, uint8_t size
)
1871 uint8_t offset
= pci_find_space(pdev
, size
);
1875 return pci_add_capability_at_offset(pdev
, cap_id
, offset
, size
);
1878 /* Unlink capability from the pci config space. */
1879 void pci_del_capability(PCIDevice
*pdev
, uint8_t cap_id
, uint8_t size
)
1881 uint8_t prev
, offset
= pci_find_capability_list(pdev
, cap_id
, &prev
);
1884 pdev
->config
[prev
] = pdev
->config
[offset
+ PCI_CAP_LIST_NEXT
];
1885 /* Make capability writeable again */
1886 memset(pdev
->wmask
+ offset
, 0xff, size
);
1887 /* Clear cmask as device-specific registers can't be checked */
1888 memset(pdev
->cmask
+ offset
, 0, size
);
1889 memset(pdev
->used
+ offset
, 0, size
);
1891 if (!pdev
->config
[PCI_CAPABILITY_LIST
])
1892 pdev
->config
[PCI_STATUS
] &= ~PCI_STATUS_CAP_LIST
;
1895 /* Reserve space for capability at a known offset (to call after load). */
1896 void pci_reserve_capability(PCIDevice
*pdev
, uint8_t offset
, uint8_t size
)
1898 memset(pdev
->used
+ offset
, 0xff, size
);
1901 uint8_t pci_find_capability(PCIDevice
*pdev
, uint8_t cap_id
)
1903 return pci_find_capability_list(pdev
, cap_id
, NULL
);
1906 static void pcibus_dev_print(Monitor
*mon
, DeviceState
*dev
, int indent
)
1908 PCIDevice
*d
= (PCIDevice
*)dev
;
1909 const pci_class_desc
*desc
;
1914 class = pci_get_word(d
->config
+ PCI_CLASS_DEVICE
);
1915 desc
= pci_class_descriptions
;
1916 while (desc
->desc
&& class != desc
->class)
1919 snprintf(ctxt
, sizeof(ctxt
), "%s", desc
->desc
);
1921 snprintf(ctxt
, sizeof(ctxt
), "Class %04x", class);
1924 monitor_printf(mon
, "%*sclass %s, addr %02x:%02x.%x, "
1925 "pci id %04x:%04x (sub %04x:%04x)\n",
1927 d
->config
[PCI_SECONDARY_BUS
],
1928 PCI_SLOT(d
->devfn
), PCI_FUNC(d
->devfn
),
1929 pci_get_word(d
->config
+ PCI_VENDOR_ID
),
1930 pci_get_word(d
->config
+ PCI_DEVICE_ID
),
1931 pci_get_word(d
->config
+ PCI_SUBSYSTEM_VENDOR_ID
),
1932 pci_get_word(d
->config
+ PCI_SUBSYSTEM_ID
));
1933 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1934 r
= &d
->io_regions
[i
];
1937 monitor_printf(mon
, "%*sbar %d: %s at 0x%"FMT_PCIBUS
1938 " [0x%"FMT_PCIBUS
"]\n",
1940 i
, r
->type
& PCI_BASE_ADDRESS_SPACE_IO
? "i/o" : "mem",
1941 r
->addr
, r
->addr
+ r
->size
- 1);
1945 static char *pcibus_get_dev_path(DeviceState
*dev
)
1947 PCIDevice
*d
= (PCIDevice
*)dev
;
1950 snprintf(path
, sizeof(path
), "%04x:%02x:%02x.%x",
1951 pci_find_domain(d
->bus
), d
->config
[PCI_SECONDARY_BUS
],
1952 PCI_SLOT(d
->devfn
), PCI_FUNC(d
->devfn
));
1954 return strdup(path
);
1957 static PCIDeviceInfo bridge_info
= {
1958 .qdev
.name
= "pci-bridge",
1959 .qdev
.size
= sizeof(PCIBridge
),
1960 .init
= pci_bridge_initfn
,
1961 .exit
= pci_bridge_exitfn
,
1962 .config_write
= pci_bridge_write_config
,
1964 .qdev
.props
= (Property
[]) {
1965 DEFINE_PROP_HEX32("vendorid", PCIBridge
, vid
, 0),
1966 DEFINE_PROP_HEX32("deviceid", PCIBridge
, did
, 0),
1967 DEFINE_PROP_END_OF_LIST(),
1971 static void pci_register_devices(void)
1973 pci_qdev_register(&bridge_info
);
1976 device_init(pci_register_devices
)