hw/pci.c

   1 /*
   2  * QEMU PCI bus manager
   3  *
   4  * Copyright (c) 2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "monitor.h"
  27 #include "net.h"
  28 #include "sysemu.h"
  29
  30 //#define DEBUG_PCI
  31
  32 struct PCIBus {
  33     BusState qbus;
  34     int bus_num;
  35     int devfn_min;
  36     pci_set_irq_fn set_irq;
  37     pci_map_irq_fn map_irq;
  38     uint32_t config_reg; /* XXX: suppress */
  39     /* low level pic */
  40     SetIRQFunc *low_set_irq;
  41     qemu_irq *irq_opaque;
  42     PCIDevice *devices[256];
  43     PCIDevice *parent_dev;
  44     PCIBus *next;
  45     /* The bus IRQ state is the logical OR of the connected devices.
  46        Keep a count of the number of devices with raised IRQs.  */
  47     int nirq;
  48     int *irq_count;
  49 };
  50
  51 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
  52
  53 static struct BusInfo pci_bus_info = {
  54     .name       = "PCI",
  55     .size       = sizeof(PCIBus),
  56     .print_dev  = pcibus_dev_print,
  57 };
  58
  59 static void pci_update_mappings(PCIDevice *d);
  60 static void pci_set_irq(void *opaque, int irq_num, int level);
  61
  62 target_phys_addr_t pci_mem_base;
  63 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
  64 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
  65 static PCIBus *first_bus;
  66
  67 static void pcibus_save(QEMUFile *f, void *opaque)
  68 {
  69     PCIBus *bus = (PCIBus *)opaque;
  70     int i;
  71
  72     qemu_put_be32(f, bus->nirq);
  73     for (i = 0; i < bus->nirq; i++)
  74         qemu_put_be32(f, bus->irq_count[i]);
  75 }
  76
  77 static int  pcibus_load(QEMUFile *f, void *opaque, int version_id)
  78 {
  79     PCIBus *bus = (PCIBus *)opaque;
  80     int i, nirq;
  81
  82     if (version_id != 1)
  83         return -EINVAL;
  84
  85     nirq = qemu_get_be32(f);
  86     if (bus->nirq != nirq) {
  87         fprintf(stderr, "pcibus_load: nirq mismatch: src=%d dst=%d\n",
  88                 nirq, bus->nirq);
  89         return -EINVAL;
  90     }
  91
  92     for (i = 0; i < nirq; i++)
  93         bus->irq_count[i] = qemu_get_be32(f);
  94
  95     return 0;
  96 }
  97
  98 static void pci_bus_reset(void *opaque)
  99 {
 100     PCIBus *bus = (PCIBus *)opaque;
 101     int i;
 102
 103     for (i = 0; i < bus->nirq; i++) {
 104         bus->irq_count[i] = 0;
 105     }
 106     for (i = 0; i < 256; i++) {
 107         if (bus->devices[i])
 108             memset(bus->devices[i]->irq_state, 0,
 109                    sizeof(bus->devices[i]->irq_state));
 110     }
 111 }
 112
 113 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 114                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 115                          qemu_irq *pic, int devfn_min, int nirq)
 116 {
 117     PCIBus *bus;
 118     static int nbus = 0;
 119
 120     bus = FROM_QBUS(PCIBus, qbus_create(&pci_bus_info, parent, name));
 121     bus->set_irq = set_irq;
 122     bus->map_irq = map_irq;
 123     bus->irq_opaque = pic;
 124     bus->devfn_min = devfn_min;
 125     bus->nirq = nirq;
 126     bus->irq_count = qemu_malloc(nirq * sizeof(bus->irq_count[0]));
 127     bus->next = first_bus;
 128     first_bus = bus;
 129     register_savevm("PCIBUS", nbus++, 1, pcibus_save, pcibus_load, bus);
 130     qemu_register_reset(pci_bus_reset, bus);
 131     return bus;
 132 }
 133
 134 static PCIBus *pci_register_secondary_bus(PCIDevice *dev, pci_map_irq_fn map_irq)
 135 {
 136     PCIBus *bus;
 137     bus = qemu_mallocz(sizeof(PCIBus));
 138     bus->map_irq = map_irq;
 139     bus->parent_dev = dev;
 140     bus->next = dev->bus->next;
 141     dev->bus->next = bus;
 142     return bus;
 143 }
 144
 145 int pci_bus_num(PCIBus *s)
 146 {
 147     return s->bus_num;
 148 }
 149
 150 void pci_device_save(PCIDevice *s, QEMUFile *f)
 151 {
 152     int i;
 153
 154     qemu_put_be32(f, 2); /* PCI device version */
 155     qemu_put_buffer(f, s->config, 256);
 156     for (i = 0; i < 4; i++)
 157         qemu_put_be32(f, s->irq_state[i]);
 158 }
 159
 160 int pci_device_load(PCIDevice *s, QEMUFile *f)
 161 {
 162     uint8_t config[PCI_CONFIG_SPACE_SIZE];
 163     uint32_t version_id;
 164     int i;
 165
 166     version_id = qemu_get_be32(f);
 167     if (version_id > 2)
 168         return -EINVAL;
 169     qemu_get_buffer(f, config, sizeof config);
 170     for (i = 0; i < sizeof config; ++i)
 171         if ((config[i] ^ s->config[i]) & s->cmask[i] & ~s->wmask[i])
 172             return -EINVAL;
 173     memcpy(s->config, config, sizeof config);
 174
 175     pci_update_mappings(s);
 176
 177     if (version_id >= 2)
 178         for (i = 0; i < 4; i ++)
 179             s->irq_state[i] = qemu_get_be32(f);
 180     return 0;
 181 }
 182
 183 static int pci_set_default_subsystem_id(PCIDevice *pci_dev)
 184 {
 185     uint16_t *id;
 186
 187     id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]);
 188     id[0] = cpu_to_le16(pci_default_sub_vendor_id);
 189     id[1] = cpu_to_le16(pci_default_sub_device_id);
 190     return 0;
 191 }
 192
 193 /*
 194  * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
 195  */
 196 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
 197 {
 198     const char *p;
 199     char *e;
 200     unsigned long val;
 201     unsigned long dom = 0, bus = 0;
 202     unsigned slot = 0;
 203
 204     p = addr;
 205     val = strtoul(p, &e, 16);
 206     if (e == p)
 207         return -1;
 208     if (*e == ':') {
 209         bus = val;
 210         p = e + 1;
 211         val = strtoul(p, &e, 16);
 212         if (e == p)
 213             return -1;
 214         if (*e == ':') {
 215             dom = bus;
 216             bus = val;
 217             p = e + 1;
 218             val = strtoul(p, &e, 16);
 219             if (e == p)
 220                 return -1;
 221         }
 222     }
 223
 224     if (dom > 0xffff || bus > 0xff || val > 0x1f)
 225         return -1;
 226
 227     slot = val;
 228
 229     if (*e)
 230         return -1;
 231
 232     /* Note: QEMU doesn't implement domains other than 0 */
 233     if (dom != 0 || pci_find_bus(bus) == NULL)
 234         return -1;
 235
 236     *domp = dom;
 237     *busp = bus;
 238     *slotp = slot;
 239     return 0;
 240 }
 241
 242 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 243                      unsigned *slotp)
 244 {
 245     /* strip legacy tag */
 246     if (!strncmp(addr, "pci_addr=", 9)) {
 247         addr += 9;
 248     }
 249     if (pci_parse_devaddr(addr, domp, busp, slotp)) {
 250         monitor_printf(mon, "Invalid pci address\n");
 251         return -1;
 252     }
 253     return 0;
 254 }
 255
 256 static PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
 257 {
 258     int dom, bus;
 259     unsigned slot;
 260
 261     if (!devaddr) {
 262         *devfnp = -1;
 263         return pci_find_bus(0);
 264     }
 265
 266     if (pci_parse_devaddr(devaddr, &dom, &bus, &slot) < 0) {
 267         return NULL;
 268     }
 269
 270     *devfnp = slot << 3;
 271     return pci_find_bus(bus);
 272 }
 273
 274 static void pci_init_cmask(PCIDevice *dev)
 275 {
 276     pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
 277     pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
 278     dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
 279     dev->cmask[PCI_REVISION_ID] = 0xff;
 280     dev->cmask[PCI_CLASS_PROG] = 0xff;
 281     pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
 282     dev->cmask[PCI_HEADER_TYPE] = 0xff;
 283     dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
 284 }
 285
 286 static void pci_init_wmask(PCIDevice *dev)
 287 {
 288     int i;
 289     dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
 290     dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
 291     dev->wmask[PCI_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEMORY
 292                               | PCI_COMMAND_MASTER;
 293     for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i)
 294         dev->wmask[i] = 0xff;
 295 }
 296
 297 /* -1 for devfn means auto assign */
 298 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
 299                                          const char *name, int devfn,
 300                                          PCIConfigReadFunc *config_read,
 301                                          PCIConfigWriteFunc *config_write)
 302 {
 303     if (devfn < 0) {
 304         for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
 305             if (!bus->devices[devfn])
 306                 goto found;
 307         }
 308         return NULL;
 309     found: ;
 310     } else if (bus->devices[devfn]) {
 311         return NULL;
 312     }
 313     pci_dev->bus = bus;
 314     pci_dev->devfn = devfn;
 315     pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
 316     memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state));
 317     pci_set_default_subsystem_id(pci_dev);
 318     pci_init_cmask(pci_dev);
 319     pci_init_wmask(pci_dev);
 320
 321     if (!config_read)
 322         config_read = pci_default_read_config;
 323     if (!config_write)
 324         config_write = pci_default_write_config;
 325     pci_dev->config_read = config_read;
 326     pci_dev->config_write = config_write;
 327     bus->devices[devfn] = pci_dev;
 328     pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, 4);
 329     return pci_dev;
 330 }
 331
 332 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 333                                int instance_size, int devfn,
 334                                PCIConfigReadFunc *config_read,
 335                                PCIConfigWriteFunc *config_write)
 336 {
 337     PCIDevice *pci_dev;
 338
 339     pci_dev = qemu_mallocz(instance_size);
 340     pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
 341                                      config_read, config_write);
 342     return pci_dev;
 343 }
 344 static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
 345 {
 346     return addr + pci_mem_base;
 347 }
 348
 349 static void pci_unregister_io_regions(PCIDevice *pci_dev)
 350 {
 351     PCIIORegion *r;
 352     int i;
 353
 354     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 355         r = &pci_dev->io_regions[i];
 356         if (!r->size || r->addr == -1)
 357             continue;
 358         if (r->type == PCI_ADDRESS_SPACE_IO) {
 359             isa_unassign_ioport(r->addr, r->size);
 360         } else {
 361             cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 362                                                      r->size,
 363                                                      IO_MEM_UNASSIGNED);
 364         }
 365     }
 366 }
 367
 368 int pci_unregister_device(PCIDevice *pci_dev)
 369 {
 370     int ret = 0;
 371
 372     if (pci_dev->unregister)
 373         ret = pci_dev->unregister(pci_dev);
 374     if (ret)
 375         return ret;
 376
 377     pci_unregister_io_regions(pci_dev);
 378
 379     qemu_free_irqs(pci_dev->irq);
 380     pci_dev->bus->devices[pci_dev->devfn] = NULL;
 381     qdev_free(&pci_dev->qdev);
 382     return 0;
 383 }
 384
 385 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 386                             uint32_t size, int type,
 387                             PCIMapIORegionFunc *map_func)
 388 {
 389     PCIIORegion *r;
 390     uint32_t addr;
 391     uint32_t wmask;
 392
 393     if ((unsigned int)region_num >= PCI_NUM_REGIONS)
 394         return;
 395
 396     if (size & (size-1)) {
 397         fprintf(stderr, "ERROR: PCI region size must be pow2 "
 398                     "type=0x%x, size=0x%x\n", type, size);
 399         exit(1);
 400     }
 401
 402     r = &pci_dev->io_regions[region_num];
 403     r->addr = -1;
 404     r->size = size;
 405     r->type = type;
 406     r->map_func = map_func;
 407
 408     wmask = ~(size - 1);
 409     if (region_num == PCI_ROM_SLOT) {
 410         addr = 0x30;
 411         /* ROM enable bit is writeable */
 412         wmask |= 1;
 413     } else {
 414         addr = 0x10 + region_num * 4;
 415     }
 416     *(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type);
 417     *(uint32_t *)(pci_dev->wmask + addr) = cpu_to_le32(wmask);
 418     *(uint32_t *)(pci_dev->cmask + addr) = 0xffffffff;
 419 }
 420
 421 static void pci_update_mappings(PCIDevice *d)
 422 {
 423     PCIIORegion *r;
 424     int cmd, i;
 425     uint32_t last_addr, new_addr, config_ofs;
 426
 427     cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
 428     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 429         r = &d->io_regions[i];
 430         if (i == PCI_ROM_SLOT) {
 431             config_ofs = 0x30;
 432         } else {
 433             config_ofs = 0x10 + i * 4;
 434         }
 435         if (r->size != 0) {
 436             if (r->type & PCI_ADDRESS_SPACE_IO) {
 437                 if (cmd & PCI_COMMAND_IO) {
 438                     new_addr = le32_to_cpu(*(uint32_t *)(d->config +
 439                                                          config_ofs));
 440                     new_addr = new_addr & ~(r->size - 1);
 441                     last_addr = new_addr + r->size - 1;
 442                     /* NOTE: we have only 64K ioports on PC */
 443                     if (last_addr <= new_addr || new_addr == 0 ||
 444                         last_addr >= 0x10000) {
 445                         new_addr = -1;
 446                     }
 447                 } else {
 448                     new_addr = -1;
 449                 }
 450             } else {
 451                 if (cmd & PCI_COMMAND_MEMORY) {
 452                     new_addr = le32_to_cpu(*(uint32_t *)(d->config +
 453                                                          config_ofs));
 454                     /* the ROM slot has a specific enable bit */
 455                     if (i == PCI_ROM_SLOT && !(new_addr & 1))
 456                         goto no_mem_map;
 457                     new_addr = new_addr & ~(r->size - 1);
 458                     last_addr = new_addr + r->size - 1;
 459                     /* NOTE: we do not support wrapping */
 460                     /* XXX: as we cannot support really dynamic
 461                        mappings, we handle specific values as invalid
 462                        mappings. */
 463                     if (last_addr <= new_addr || new_addr == 0 ||
 464                         last_addr == -1) {
 465                         new_addr = -1;
 466                     }
 467                 } else {
 468                 no_mem_map:
 469                     new_addr = -1;
 470                 }
 471             }
 472             /* now do the real mapping */
 473             if (new_addr != r->addr) {
 474                 if (r->addr != -1) {
 475                     if (r->type & PCI_ADDRESS_SPACE_IO) {
 476                         int class;
 477                         /* NOTE: specific hack for IDE in PC case:
 478                            only one byte must be mapped. */
 479                         class = d->config[0x0a] | (d->config[0x0b] << 8);
 480                         if (class == 0x0101 && r->size == 4) {
 481                             isa_unassign_ioport(r->addr + 2, 1);
 482                         } else {
 483                             isa_unassign_ioport(r->addr, r->size);
 484                         }
 485                     } else {
 486                         cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 487                                                      r->size,
 488                                                      IO_MEM_UNASSIGNED);
 489                         qemu_unregister_coalesced_mmio(r->addr, r->size);
 490                     }
 491                 }
 492                 r->addr = new_addr;
 493                 if (r->addr != -1) {
 494                     r->map_func(d, i, r->addr, r->size, r->type);
 495                 }
 496             }
 497         }
 498     }
 499 }
 500
 501 uint32_t pci_default_read_config(PCIDevice *d,
 502                                  uint32_t address, int len)
 503 {
 504     uint32_t val;
 505
 506     switch(len) {
 507     default:
 508     case 4:
 509         if (address <= 0xfc) {
 510             val = le32_to_cpu(*(uint32_t *)(d->config + address));
 511             break;
 512         }
 513         /* fall through */
 514     case 2:
 515         if (address <= 0xfe) {
 516             val = le16_to_cpu(*(uint16_t *)(d->config + address));
 517             break;
 518         }
 519         /* fall through */
 520     case 1:
 521         val = d->config[address];
 522         break;
 523     }
 524     return val;
 525 }
 526
 527 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
 528 {
 529     uint8_t orig[PCI_CONFIG_SPACE_SIZE];
 530     int i;
 531
 532     /* not efficient, but simple */
 533     memcpy(orig, d->config, PCI_CONFIG_SPACE_SIZE);
 534     for(i = 0; i < l && addr < PCI_CONFIG_SPACE_SIZE; val >>= 8, ++i, ++addr) {
 535         uint8_t wmask = d->wmask[addr];
 536         d->config[addr] = (d->config[addr] & ~wmask) | (val & wmask);
 537     }
 538     if (memcmp(orig + PCI_BASE_ADDRESS_0, d->config + PCI_BASE_ADDRESS_0, 24)
 539         || ((orig[PCI_COMMAND] ^ d->config[PCI_COMMAND])
 540             & (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)))
 541         pci_update_mappings(d);
 542 }
 543
 544 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len)
 545 {
 546     PCIBus *s = opaque;
 547     PCIDevice *pci_dev;
 548     int config_addr, bus_num;
 549
 550 #if defined(DEBUG_PCI) && 0
 551     printf("pci_data_write: addr=%08x val=%08x len=%d\n",
 552            addr, val, len);
 553 #endif
 554     bus_num = (addr >> 16) & 0xff;
 555     while (s && s->bus_num != bus_num)
 556         s = s->next;
 557     if (!s)
 558         return;
 559     pci_dev = s->devices[(addr >> 8) & 0xff];
 560     if (!pci_dev)
 561         return;
 562     config_addr = addr & 0xff;
 563 #if defined(DEBUG_PCI)
 564     printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
 565            pci_dev->name, config_addr, val, len);
 566 #endif
 567     pci_dev->config_write(pci_dev, config_addr, val, len);
 568 }
 569
 570 uint32_t pci_data_read(void *opaque, uint32_t addr, int len)
 571 {
 572     PCIBus *s = opaque;
 573     PCIDevice *pci_dev;
 574     int config_addr, bus_num;
 575     uint32_t val;
 576
 577     bus_num = (addr >> 16) & 0xff;
 578     while (s && s->bus_num != bus_num)
 579         s= s->next;
 580     if (!s)
 581         goto fail;
 582     pci_dev = s->devices[(addr >> 8) & 0xff];
 583     if (!pci_dev) {
 584     fail:
 585         switch(len) {
 586         case 1:
 587             val = 0xff;
 588             break;
 589         case 2:
 590             val = 0xffff;
 591             break;
 592         default:
 593         case 4:
 594             val = 0xffffffff;
 595             break;
 596         }
 597         goto the_end;
 598     }
 599     config_addr = addr & 0xff;
 600     val = pci_dev->config_read(pci_dev, config_addr, len);
 601 #if defined(DEBUG_PCI)
 602     printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
 603            pci_dev->name, config_addr, val, len);
 604 #endif
 605  the_end:
 606 #if defined(DEBUG_PCI) && 0
 607     printf("pci_data_read: addr=%08x val=%08x len=%d\n",
 608            addr, val, len);
 609 #endif
 610     return val;
 611 }
 612
 613 /***********************************************************/
 614 /* generic PCI irq support */
 615
 616 /* 0 <= irq_num <= 3. level must be 0 or 1 */
 617 static void pci_set_irq(void *opaque, int irq_num, int level)
 618 {
 619     PCIDevice *pci_dev = (PCIDevice *)opaque;
 620     PCIBus *bus;
 621     int change;
 622
 623     change = level - pci_dev->irq_state[irq_num];
 624     if (!change)
 625         return;
 626
 627     pci_dev->irq_state[irq_num] = level;
 628     for (;;) {
 629         bus = pci_dev->bus;
 630         irq_num = bus->map_irq(pci_dev, irq_num);
 631         if (bus->set_irq)
 632             break;
 633         pci_dev = bus->parent_dev;
 634     }
 635     bus->irq_count[irq_num] += change;
 636     bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
 637 }
 638
 639 /***********************************************************/
 640 /* monitor info on PCI */
 641
 642 typedef struct {
 643     uint16_t class;
 644     const char *desc;
 645 } pci_class_desc;
 646
 647 static const pci_class_desc pci_class_descriptions[] =
 648 {
 649     { 0x0100, "SCSI controller"},
 650     { 0x0101, "IDE controller"},
 651     { 0x0102, "Floppy controller"},
 652     { 0x0103, "IPI controller"},
 653     { 0x0104, "RAID controller"},
 654     { 0x0106, "SATA controller"},
 655     { 0x0107, "SAS controller"},
 656     { 0x0180, "Storage controller"},
 657     { 0x0200, "Ethernet controller"},
 658     { 0x0201, "Token Ring controller"},
 659     { 0x0202, "FDDI controller"},
 660     { 0x0203, "ATM controller"},
 661     { 0x0280, "Network controller"},
 662     { 0x0300, "VGA controller"},
 663     { 0x0301, "XGA controller"},
 664     { 0x0302, "3D controller"},
 665     { 0x0380, "Display controller"},
 666     { 0x0400, "Video controller"},
 667     { 0x0401, "Audio controller"},
 668     { 0x0402, "Phone"},
 669     { 0x0480, "Multimedia controller"},
 670     { 0x0500, "RAM controller"},
 671     { 0x0501, "Flash controller"},
 672     { 0x0580, "Memory controller"},
 673     { 0x0600, "Host bridge"},
 674     { 0x0601, "ISA bridge"},
 675     { 0x0602, "EISA bridge"},
 676     { 0x0603, "MC bridge"},
 677     { 0x0604, "PCI bridge"},
 678     { 0x0605, "PCMCIA bridge"},
 679     { 0x0606, "NUBUS bridge"},
 680     { 0x0607, "CARDBUS bridge"},
 681     { 0x0608, "RACEWAY bridge"},
 682     { 0x0680, "Bridge"},
 683     { 0x0c03, "USB controller"},
 684     { 0, NULL}
 685 };
 686
 687 static void pci_info_device(PCIDevice *d)
 688 {
 689     Monitor *mon = cur_mon;
 690     int i, class;
 691     PCIIORegion *r;
 692     const pci_class_desc *desc;
 693
 694     monitor_printf(mon, "  Bus %2d, device %3d, function %d:\n",
 695                    d->bus->bus_num, d->devfn >> 3, d->devfn & 7);
 696     class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
 697     monitor_printf(mon, "    ");
 698     desc = pci_class_descriptions;
 699     while (desc->desc && class != desc->class)
 700         desc++;
 701     if (desc->desc) {
 702         monitor_printf(mon, "%s", desc->desc);
 703     } else {
 704         monitor_printf(mon, "Class %04x", class);
 705     }
 706     monitor_printf(mon, ": PCI device %04x:%04x\n",
 707            le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
 708            le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));
 709
 710     if (d->config[PCI_INTERRUPT_PIN] != 0) {
 711         monitor_printf(mon, "      IRQ %d.\n",
 712                        d->config[PCI_INTERRUPT_LINE]);
 713     }
 714     if (class == 0x0604) {
 715         monitor_printf(mon, "      BUS %d.\n", d->config[0x19]);
 716     }
 717     for(i = 0;i < PCI_NUM_REGIONS; i++) {
 718         r = &d->io_regions[i];
 719         if (r->size != 0) {
 720             monitor_printf(mon, "      BAR%d: ", i);
 721             if (r->type & PCI_ADDRESS_SPACE_IO) {
 722                 monitor_printf(mon, "I/O at 0x%04x [0x%04x].\n",
 723                                r->addr, r->addr + r->size - 1);
 724             } else {
 725                 monitor_printf(mon, "32 bit memory at 0x%08x [0x%08x].\n",
 726                                r->addr, r->addr + r->size - 1);
 727             }
 728         }
 729     }
 730     if (class == 0x0604 && d->config[0x19] != 0) {
 731         pci_for_each_device(d->config[0x19], pci_info_device);
 732     }
 733 }
 734
 735 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d))
 736 {
 737     PCIBus *bus = first_bus;
 738     PCIDevice *d;
 739     int devfn;
 740
 741     while (bus && bus->bus_num != bus_num)
 742         bus = bus->next;
 743     if (bus) {
 744         for(devfn = 0; devfn < 256; devfn++) {
 745             d = bus->devices[devfn];
 746             if (d)
 747                 fn(d);
 748         }
 749     }
 750 }
 751
 752 void pci_info(Monitor *mon)
 753 {
 754     pci_for_each_device(0, pci_info_device);
 755 }
 756
 757 PCIDevice *pci_create(const char *name, const char *devaddr)
 758 {
 759     PCIBus *bus;
 760     int devfn;
 761     DeviceState *dev;
 762
 763     bus = pci_get_bus_devfn(&devfn, devaddr);
 764     if (!bus) {
 765         fprintf(stderr, "Invalid PCI device address %s for device %s\n",
 766                 devaddr, name);
 767         exit(1);
 768     }
 769
 770     dev = qdev_create(&bus->qbus, name);
 771     qdev_set_prop_int(dev, "devfn", devfn);
 772     return (PCIDevice *)dev;
 773 }
 774
 775 static const char * const pci_nic_models[] = {
 776     "ne2k_pci",
 777     "i82551",
 778     "i82557b",
 779     "i82559er",
 780     "rtl8139",
 781     "e1000",
 782     "pcnet",
 783     "virtio",
 784     NULL
 785 };
 786
 787 static const char * const pci_nic_names[] = {
 788     "ne2k_pci",
 789     "i82551",
 790     "i82557b",
 791     "i82559er",
 792     "rtl8139",
 793     "e1000",
 794     "pcnet",
 795     "virtio-net-pci",
 796     NULL
 797 };
 798
 799 /* Initialize a PCI NIC.  */
 800 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
 801                         const char *default_devaddr)
 802 {
 803     const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
 804     PCIDevice *pci_dev;
 805     DeviceState *dev;
 806     int i;
 807
 808     qemu_check_nic_model_list(nd, pci_nic_models, default_model);
 809
 810     for (i = 0; pci_nic_models[i]; i++) {
 811         if (strcmp(nd->model, pci_nic_models[i]) == 0) {
 812             pci_dev = pci_create(pci_nic_names[i], devaddr);
 813             dev = &pci_dev->qdev;
 814             qdev_set_netdev(dev, nd);
 815             qdev_init(dev);
 816             nd->private = dev;
 817             return pci_dev;
 818         }
 819     }
 820
 821     return NULL;
 822 }
 823
 824 typedef struct {
 825     PCIDevice dev;
 826     PCIBus *bus;
 827 } PCIBridge;
 828
 829 static void pci_bridge_write_config(PCIDevice *d,
 830                              uint32_t address, uint32_t val, int len)
 831 {
 832     PCIBridge *s = (PCIBridge *)d;
 833
 834     pci_default_write_config(d, address, val, len);
 835     s->bus->bus_num = d->config[PCI_SECONDARY_BUS];
 836 }
 837
 838 PCIBus *pci_find_bus(int bus_num)
 839 {
 840     PCIBus *bus = first_bus;
 841
 842     while (bus && bus->bus_num != bus_num)
 843         bus = bus->next;
 844
 845     return bus;
 846 }
 847
 848 PCIDevice *pci_find_device(int bus_num, int slot, int function)
 849 {
 850     PCIBus *bus = pci_find_bus(bus_num);
 851
 852     if (!bus)
 853         return NULL;
 854
 855     return bus->devices[PCI_DEVFN(slot, function)];
 856 }
 857
 858 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
 859                         pci_map_irq_fn map_irq, const char *name)
 860 {
 861     PCIBridge *s;
 862     s = (PCIBridge *)pci_register_device(bus, name, sizeof(PCIBridge),
 863                                          devfn, NULL, pci_bridge_write_config);
 864
 865     pci_config_set_vendor_id(s->dev.config, vid);
 866     pci_config_set_device_id(s->dev.config, did);
 867
 868     s->dev.config[0x04] = 0x06; // command = bus master, pci mem
 869     s->dev.config[0x05] = 0x00;
 870     s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
 871     s->dev.config[0x07] = 0x00; // status = fast devsel
 872     s->dev.config[0x08] = 0x00; // revision
 873     s->dev.config[0x09] = 0x00; // programming i/f
 874     pci_config_set_class(s->dev.config, PCI_CLASS_BRIDGE_PCI);
 875     s->dev.config[0x0D] = 0x10; // latency_timer
 876     s->dev.config[PCI_HEADER_TYPE] =
 877         PCI_HEADER_TYPE_MULTI_FUNCTION | PCI_HEADER_TYPE_BRIDGE; // header_type
 878     s->dev.config[0x1E] = 0xa0; // secondary status
 879
 880     s->bus = pci_register_secondary_bus(&s->dev, map_irq);
 881     return s->bus;
 882 }
 883
 884 static void pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
 885 {
 886     PCIDevice *pci_dev = (PCIDevice *)qdev;
 887     PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
 888     PCIBus *bus;
 889     int devfn;
 890
 891     bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
 892     devfn = qdev_get_prop_int(qdev, "devfn", -1);
 893     pci_dev = do_pci_register_device(pci_dev, bus, "FIXME", devfn,
 894                                      info->config_read, info->config_write);
 895     assert(pci_dev);
 896     info->init(pci_dev);
 897 }
 898
 899 void pci_qdev_register(PCIDeviceInfo *info)
 900 {
 901     info->qdev.init = pci_qdev_init;
 902     info->qdev.bus_info = &pci_bus_info;
 903     qdev_register(&info->qdev);
 904 }
 905
 906 void pci_qdev_register_many(PCIDeviceInfo *info)
 907 {
 908     while (info->qdev.name) {
 909         pci_qdev_register(info);
 910         info++;
 911     }
 912 }
 913
 914 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
 915 {
 916     DeviceState *dev;
 917
 918     dev = qdev_create(&bus->qbus, name);
 919     qdev_set_prop_int(dev, "devfn", devfn);
 920     qdev_init(dev);
 921
 922     return (PCIDevice *)dev;
 923 }
 924
 925 static int pci_find_space(PCIDevice *pdev, uint8_t size)
 926 {
 927     int offset = PCI_CONFIG_HEADER_SIZE;
 928     int i;
 929     for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i)
 930         if (pdev->used[i])
 931             offset = i + 1;
 932         else if (i - offset + 1 == size)
 933             return offset;
 934     return 0;
 935 }
 936
 937 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
 938                                         uint8_t *prev_p)
 939 {
 940     uint8_t next, prev;
 941
 942     if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
 943         return 0;
 944
 945     for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
 946          prev = next + PCI_CAP_LIST_NEXT)
 947         if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
 948             break;
 949
 950     if (prev_p)
 951         *prev_p = prev;
 952     return next;
 953 }
 954
 955 /* Reserve space and add capability to the linked list in pci config space */
 956 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
 957 {
 958     uint8_t offset = pci_find_space(pdev, size);
 959     uint8_t *config = pdev->config + offset;
 960     if (!offset)
 961         return -ENOSPC;
 962     config[PCI_CAP_LIST_ID] = cap_id;
 963     config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
 964     pdev->config[PCI_CAPABILITY_LIST] = offset;
 965     pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
 966     memset(pdev->used + offset, 0xFF, size);
 967     /* Make capability read-only by default */
 968     memset(pdev->wmask + offset, 0, size);
 969     /* Check capability by default */
 970     memset(pdev->cmask + offset, 0xFF, size);
 971     return offset;
 972 }
 973
 974 /* Unlink capability from the pci config space. */
 975 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
 976 {
 977     uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
 978     if (!offset)
 979         return;
 980     pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
 981     /* Make capability writeable again */
 982     memset(pdev->wmask + offset, 0xff, size);
 983     /* Clear cmask as device-specific registers can't be checked */
 984     memset(pdev->cmask + offset, 0, size);
 985     memset(pdev->used + offset, 0, size);
 986
 987     if (!pdev->config[PCI_CAPABILITY_LIST])
 988         pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
 989 }
 990
 991 /* Reserve space for capability at a known offset (to call after load). */
 992 void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
 993 {
 994     memset(pdev->used + offset, 0xff, size);
 995 }
 996
 997 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
 998 {
 999     return pci_find_capability_list(pdev, cap_id, NULL);
1000 }
1001
1002 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
1003 {
1004     PCIDevice *d = (PCIDevice *)dev;
1005     const pci_class_desc *desc;
1006     char ctxt[64];
1007     PCIIORegion *r;
1008     int i, class;
1009
1010     class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
1011     desc = pci_class_descriptions;
1012     while (desc->desc && class != desc->class)
1013         desc++;
1014     if (desc->desc) {
1015         snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
1016     } else {
1017         snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
1018     }
1019
1020     monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
1021                    "pci id %04x:%04x (sub %04x:%04x)\n",
1022                    indent, "", ctxt,
1023                    d->bus->bus_num, d->devfn >> 3, d->devfn & 7,
1024                    le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
1025                    le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))),
1026                    le16_to_cpu(*((uint16_t *)(d->config + PCI_SUBSYSTEM_VENDOR_ID))),
1027                    le16_to_cpu(*((uint16_t *)(d->config + PCI_SUBSYSTEM_ID))));
1028     for (i = 0; i < PCI_NUM_REGIONS; i++) {
1029         r = &d->io_regions[i];
1030         if (!r->size)
1031             continue;
1032         monitor_printf(mon, "%*sbar %d: %s at 0x%x [0x%x]\n", indent, "",
1033                        i, r->type & PCI_ADDRESS_SPACE_IO ? "i/o" : "mem",
1034                        r->addr, r->addr + r->size - 1);
1035     }
1036 }