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pci: add API to get a BAR's mapped address
[mirror_qemu.git] / hw / pci.c
1 /*
2 * QEMU PCI bus manager
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "pci.h"
26 #include "pci_bridge.h"
27 #include "pci_internals.h"
28 #include "monitor.h"
29 #include "net.h"
30 #include "sysemu.h"
31 #include "loader.h"
32 #include "qemu-objects.h"
33 #include "range.h"
34
35 //#define DEBUG_PCI
36 #ifdef DEBUG_PCI
37 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
38 #else
39 # define PCI_DPRINTF(format, ...) do { } while (0)
40 #endif
41
42 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
43 static char *pcibus_get_dev_path(DeviceState *dev);
44 static char *pcibus_get_fw_dev_path(DeviceState *dev);
45 static int pcibus_reset(BusState *qbus);
46
47 struct BusInfo pci_bus_info = {
48 .name = "PCI",
49 .size = sizeof(PCIBus),
50 .print_dev = pcibus_dev_print,
51 .get_dev_path = pcibus_get_dev_path,
52 .get_fw_dev_path = pcibus_get_fw_dev_path,
53 .reset = pcibus_reset,
54 .props = (Property[]) {
55 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
56 DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
57 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1),
58 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
59 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
60 DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present,
61 QEMU_PCI_CAP_SERR_BITNR, true),
62 DEFINE_PROP_END_OF_LIST()
63 }
64 };
65
66 static void pci_update_mappings(PCIDevice *d);
67 static void pci_set_irq(void *opaque, int irq_num, int level);
68 static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom);
69 static void pci_del_option_rom(PCIDevice *pdev);
70
71 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
72 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
73
74 struct PCIHostBus {
75 int domain;
76 struct PCIBus *bus;
77 QLIST_ENTRY(PCIHostBus) next;
78 };
79 static QLIST_HEAD(, PCIHostBus) host_buses;
80
81 static const VMStateDescription vmstate_pcibus = {
82 .name = "PCIBUS",
83 .version_id = 1,
84 .minimum_version_id = 1,
85 .minimum_version_id_old = 1,
86 .fields = (VMStateField []) {
87 VMSTATE_INT32_EQUAL(nirq, PCIBus),
88 VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t),
89 VMSTATE_END_OF_LIST()
90 }
91 };
92
93 static int pci_bar(PCIDevice *d, int reg)
94 {
95 uint8_t type;
96
97 if (reg != PCI_ROM_SLOT)
98 return PCI_BASE_ADDRESS_0 + reg * 4;
99
100 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
101 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
102 }
103
104 static inline int pci_irq_state(PCIDevice *d, int irq_num)
105 {
106 return (d->irq_state >> irq_num) & 0x1;
107 }
108
109 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
110 {
111 d->irq_state &= ~(0x1 << irq_num);
112 d->irq_state |= level << irq_num;
113 }
114
115 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
116 {
117 PCIBus *bus;
118 for (;;) {
119 bus = pci_dev->bus;
120 irq_num = bus->map_irq(pci_dev, irq_num);
121 if (bus->set_irq)
122 break;
123 pci_dev = bus->parent_dev;
124 }
125 bus->irq_count[irq_num] += change;
126 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
127 }
128
129 int pci_bus_get_irq_level(PCIBus *bus, int irq_num)
130 {
131 assert(irq_num >= 0);
132 assert(irq_num < bus->nirq);
133 return !!bus->irq_count[irq_num];
134 }
135
136 /* Update interrupt status bit in config space on interrupt
137 * state change. */
138 static void pci_update_irq_status(PCIDevice *dev)
139 {
140 if (dev->irq_state) {
141 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
142 } else {
143 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
144 }
145 }
146
147 void pci_device_deassert_intx(PCIDevice *dev)
148 {
149 int i;
150 for (i = 0; i < PCI_NUM_PINS; ++i) {
151 qemu_set_irq(dev->irq[i], 0);
152 }
153 }
154
155 /*
156 * This function is called on #RST and FLR.
157 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
158 */
159 void pci_device_reset(PCIDevice *dev)
160 {
161 int r;
162 /* TODO: call the below unconditionally once all pci devices
163 * are qdevified */
164 if (dev->qdev.info) {
165 qdev_reset_all(&dev->qdev);
166 }
167
168 dev->irq_state = 0;
169 pci_update_irq_status(dev);
170 pci_device_deassert_intx(dev);
171 /* Clear all writable bits */
172 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND,
173 pci_get_word(dev->wmask + PCI_COMMAND) |
174 pci_get_word(dev->w1cmask + PCI_COMMAND));
175 pci_word_test_and_clear_mask(dev->config + PCI_STATUS,
176 pci_get_word(dev->wmask + PCI_STATUS) |
177 pci_get_word(dev->w1cmask + PCI_STATUS));
178 dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
179 dev->config[PCI_INTERRUPT_LINE] = 0x0;
180 for (r = 0; r < PCI_NUM_REGIONS; ++r) {
181 PCIIORegion *region = &dev->io_regions[r];
182 if (!region->size) {
183 continue;
184 }
185
186 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&
187 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
188 pci_set_quad(dev->config + pci_bar(dev, r), region->type);
189 } else {
190 pci_set_long(dev->config + pci_bar(dev, r), region->type);
191 }
192 }
193 pci_update_mappings(dev);
194 }
195
196 /*
197 * Trigger pci bus reset under a given bus.
198 * To be called on RST# assert.
199 */
200 void pci_bus_reset(PCIBus *bus)
201 {
202 int i;
203
204 for (i = 0; i < bus->nirq; i++) {
205 bus->irq_count[i] = 0;
206 }
207 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
208 if (bus->devices[i]) {
209 pci_device_reset(bus->devices[i]);
210 }
211 }
212 }
213
214 static int pcibus_reset(BusState *qbus)
215 {
216 pci_bus_reset(DO_UPCAST(PCIBus, qbus, qbus));
217
218 /* topology traverse is done by pci_bus_reset().
219 Tell qbus/qdev walker not to traverse the tree */
220 return 1;
221 }
222
223 static void pci_host_bus_register(int domain, PCIBus *bus)
224 {
225 struct PCIHostBus *host;
226 host = qemu_mallocz(sizeof(*host));
227 host->domain = domain;
228 host->bus = bus;
229 QLIST_INSERT_HEAD(&host_buses, host, next);
230 }
231
232 PCIBus *pci_find_root_bus(int domain)
233 {
234 struct PCIHostBus *host;
235
236 QLIST_FOREACH(host, &host_buses, next) {
237 if (host->domain == domain) {
238 return host->bus;
239 }
240 }
241
242 return NULL;
243 }
244
245 int pci_find_domain(const PCIBus *bus)
246 {
247 PCIDevice *d;
248 struct PCIHostBus *host;
249
250 /* obtain root bus */
251 while ((d = bus->parent_dev) != NULL) {
252 bus = d->bus;
253 }
254
255 QLIST_FOREACH(host, &host_buses, next) {
256 if (host->bus == bus) {
257 return host->domain;
258 }
259 }
260
261 abort(); /* should not be reached */
262 return -1;
263 }
264
265 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
266 const char *name,
267 MemoryRegion *address_space,
268 uint8_t devfn_min)
269 {
270 qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name);
271 assert(PCI_FUNC(devfn_min) == 0);
272 bus->devfn_min = devfn_min;
273 bus->address_space = address_space;
274
275 /* host bridge */
276 QLIST_INIT(&bus->child);
277 pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */
278
279 vmstate_register(NULL, -1, &vmstate_pcibus, bus);
280 }
281
282 PCIBus *pci_bus_new(DeviceState *parent, const char *name,
283 MemoryRegion *address_space, uint8_t devfn_min)
284 {
285 PCIBus *bus;
286
287 bus = qemu_mallocz(sizeof(*bus));
288 bus->qbus.qdev_allocated = 1;
289 pci_bus_new_inplace(bus, parent, name, address_space, devfn_min);
290 return bus;
291 }
292
293 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
294 void *irq_opaque, int nirq)
295 {
296 bus->set_irq = set_irq;
297 bus->map_irq = map_irq;
298 bus->irq_opaque = irq_opaque;
299 bus->nirq = nirq;
300 bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0]));
301 }
302
303 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *qdev)
304 {
305 bus->qbus.allow_hotplug = 1;
306 bus->hotplug = hotplug;
307 bus->hotplug_qdev = qdev;
308 }
309
310 void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base)
311 {
312 bus->mem_base = base;
313 }
314
315 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
316 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
317 void *irq_opaque,
318 MemoryRegion *address_space,
319 uint8_t devfn_min, int nirq)
320 {
321 PCIBus *bus;
322
323 bus = pci_bus_new(parent, name, address_space, devfn_min);
324 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
325 return bus;
326 }
327
328 int pci_bus_num(PCIBus *s)
329 {
330 if (!s->parent_dev)
331 return 0; /* pci host bridge */
332 return s->parent_dev->config[PCI_SECONDARY_BUS];
333 }
334
335 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
336 {
337 PCIDevice *s = container_of(pv, PCIDevice, config);
338 uint8_t *config;
339 int i;
340
341 assert(size == pci_config_size(s));
342 config = qemu_malloc(size);
343
344 qemu_get_buffer(f, config, size);
345 for (i = 0; i < size; ++i) {
346 if ((config[i] ^ s->config[i]) &
347 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) {
348 qemu_free(config);
349 return -EINVAL;
350 }
351 }
352 memcpy(s->config, config, size);
353
354 pci_update_mappings(s);
355
356 qemu_free(config);
357 return 0;
358 }
359
360 /* just put buffer */
361 static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
362 {
363 const uint8_t **v = pv;
364 assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
365 qemu_put_buffer(f, *v, size);
366 }
367
368 static VMStateInfo vmstate_info_pci_config = {
369 .name = "pci config",
370 .get = get_pci_config_device,
371 .put = put_pci_config_device,
372 };
373
374 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size)
375 {
376 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
377 uint32_t irq_state[PCI_NUM_PINS];
378 int i;
379 for (i = 0; i < PCI_NUM_PINS; ++i) {
380 irq_state[i] = qemu_get_be32(f);
381 if (irq_state[i] != 0x1 && irq_state[i] != 0) {
382 fprintf(stderr, "irq state %d: must be 0 or 1.\n",
383 irq_state[i]);
384 return -EINVAL;
385 }
386 }
387
388 for (i = 0; i < PCI_NUM_PINS; ++i) {
389 pci_set_irq_state(s, i, irq_state[i]);
390 }
391
392 return 0;
393 }
394
395 static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size)
396 {
397 int i;
398 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
399
400 for (i = 0; i < PCI_NUM_PINS; ++i) {
401 qemu_put_be32(f, pci_irq_state(s, i));
402 }
403 }
404
405 static VMStateInfo vmstate_info_pci_irq_state = {
406 .name = "pci irq state",
407 .get = get_pci_irq_state,
408 .put = put_pci_irq_state,
409 };
410
411 const VMStateDescription vmstate_pci_device = {
412 .name = "PCIDevice",
413 .version_id = 2,
414 .minimum_version_id = 1,
415 .minimum_version_id_old = 1,
416 .fields = (VMStateField []) {
417 VMSTATE_INT32_LE(version_id, PCIDevice),
418 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
419 vmstate_info_pci_config,
420 PCI_CONFIG_SPACE_SIZE),
421 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
422 vmstate_info_pci_irq_state,
423 PCI_NUM_PINS * sizeof(int32_t)),
424 VMSTATE_END_OF_LIST()
425 }
426 };
427
428 const VMStateDescription vmstate_pcie_device = {
429 .name = "PCIDevice",
430 .version_id = 2,
431 .minimum_version_id = 1,
432 .minimum_version_id_old = 1,
433 .fields = (VMStateField []) {
434 VMSTATE_INT32_LE(version_id, PCIDevice),
435 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
436 vmstate_info_pci_config,
437 PCIE_CONFIG_SPACE_SIZE),
438 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
439 vmstate_info_pci_irq_state,
440 PCI_NUM_PINS * sizeof(int32_t)),
441 VMSTATE_END_OF_LIST()
442 }
443 };
444
445 static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s)
446 {
447 return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
448 }
449
450 void pci_device_save(PCIDevice *s, QEMUFile *f)
451 {
452 /* Clear interrupt status bit: it is implicit
453 * in irq_state which we are saving.
454 * This makes us compatible with old devices
455 * which never set or clear this bit. */
456 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
457 vmstate_save_state(f, pci_get_vmstate(s), s);
458 /* Restore the interrupt status bit. */
459 pci_update_irq_status(s);
460 }
461
462 int pci_device_load(PCIDevice *s, QEMUFile *f)
463 {
464 int ret;
465 ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);
466 /* Restore the interrupt status bit. */
467 pci_update_irq_status(s);
468 return ret;
469 }
470
471 static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
472 {
473 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
474 pci_default_sub_vendor_id);
475 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
476 pci_default_sub_device_id);
477 }
478
479 /*
480 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
481 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
482 */
483 int pci_parse_devaddr(const char *addr, int *domp, int *busp,
484 unsigned int *slotp, unsigned int *funcp)
485 {
486 const char *p;
487 char *e;
488 unsigned long val;
489 unsigned long dom = 0, bus = 0;
490 unsigned int slot = 0;
491 unsigned int func = 0;
492
493 p = addr;
494 val = strtoul(p, &e, 16);
495 if (e == p)
496 return -1;
497 if (*e == ':') {
498 bus = val;
499 p = e + 1;
500 val = strtoul(p, &e, 16);
501 if (e == p)
502 return -1;
503 if (*e == ':') {
504 dom = bus;
505 bus = val;
506 p = e + 1;
507 val = strtoul(p, &e, 16);
508 if (e == p)
509 return -1;
510 }
511 }
512
513 slot = val;
514
515 if (funcp != NULL) {
516 if (*e != '.')
517 return -1;
518
519 p = e + 1;
520 val = strtoul(p, &e, 16);
521 if (e == p)
522 return -1;
523
524 func = val;
525 }
526
527 /* if funcp == NULL func is 0 */
528 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7)
529 return -1;
530
531 if (*e)
532 return -1;
533
534 /* Note: QEMU doesn't implement domains other than 0 */
535 if (!pci_find_bus(pci_find_root_bus(dom), bus))
536 return -1;
537
538 *domp = dom;
539 *busp = bus;
540 *slotp = slot;
541 if (funcp != NULL)
542 *funcp = func;
543 return 0;
544 }
545
546 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
547 unsigned *slotp)
548 {
549 /* strip legacy tag */
550 if (!strncmp(addr, "pci_addr=", 9)) {
551 addr += 9;
552 }
553 if (pci_parse_devaddr(addr, domp, busp, slotp, NULL)) {
554 monitor_printf(mon, "Invalid pci address\n");
555 return -1;
556 }
557 return 0;
558 }
559
560 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
561 {
562 int dom, bus;
563 unsigned slot;
564
565 if (!devaddr) {
566 *devfnp = -1;
567 return pci_find_bus(pci_find_root_bus(0), 0);
568 }
569
570 if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) {
571 return NULL;
572 }
573
574 *devfnp = PCI_DEVFN(slot, 0);
575 return pci_find_bus(pci_find_root_bus(dom), bus);
576 }
577
578 static void pci_init_cmask(PCIDevice *dev)
579 {
580 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
581 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
582 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
583 dev->cmask[PCI_REVISION_ID] = 0xff;
584 dev->cmask[PCI_CLASS_PROG] = 0xff;
585 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
586 dev->cmask[PCI_HEADER_TYPE] = 0xff;
587 dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
588 }
589
590 static void pci_init_wmask(PCIDevice *dev)
591 {
592 int config_size = pci_config_size(dev);
593
594 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
595 dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
596 pci_set_word(dev->wmask + PCI_COMMAND,
597 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
598 PCI_COMMAND_INTX_DISABLE);
599 if (dev->cap_present & QEMU_PCI_CAP_SERR) {
600 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR);
601 }
602
603 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
604 config_size - PCI_CONFIG_HEADER_SIZE);
605 }
606
607 static void pci_init_w1cmask(PCIDevice *dev)
608 {
609 /*
610 * Note: It's okay to set w1cmask even for readonly bits as
611 * long as their value is hardwired to 0.
612 */
613 pci_set_word(dev->w1cmask + PCI_STATUS,
614 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT |
615 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT |
616 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
617 }
618
619 static void pci_init_wmask_bridge(PCIDevice *d)
620 {
621 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
622 PCI_SEC_LETENCY_TIMER */
623 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
624
625 /* base and limit */
626 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
627 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
628 pci_set_word(d->wmask + PCI_MEMORY_BASE,
629 PCI_MEMORY_RANGE_MASK & 0xffff);
630 pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
631 PCI_MEMORY_RANGE_MASK & 0xffff);
632 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
633 PCI_PREF_RANGE_MASK & 0xffff);
634 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
635 PCI_PREF_RANGE_MASK & 0xffff);
636
637 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
638 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
639
640 /* TODO: add this define to pci_regs.h in linux and then in qemu. */
641 #define PCI_BRIDGE_CTL_VGA_16BIT 0x10 /* VGA 16-bit decode */
642 #define PCI_BRIDGE_CTL_DISCARD 0x100 /* Primary discard timer */
643 #define PCI_BRIDGE_CTL_SEC_DISCARD 0x200 /* Secondary discard timer */
644 #define PCI_BRIDGE_CTL_DISCARD_STATUS 0x400 /* Discard timer status */
645 #define PCI_BRIDGE_CTL_DISCARD_SERR 0x800 /* Discard timer SERR# enable */
646 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL,
647 PCI_BRIDGE_CTL_PARITY |
648 PCI_BRIDGE_CTL_SERR |
649 PCI_BRIDGE_CTL_ISA |
650 PCI_BRIDGE_CTL_VGA |
651 PCI_BRIDGE_CTL_VGA_16BIT |
652 PCI_BRIDGE_CTL_MASTER_ABORT |
653 PCI_BRIDGE_CTL_BUS_RESET |
654 PCI_BRIDGE_CTL_FAST_BACK |
655 PCI_BRIDGE_CTL_DISCARD |
656 PCI_BRIDGE_CTL_SEC_DISCARD |
657 PCI_BRIDGE_CTL_DISCARD_SERR);
658 /* Below does not do anything as we never set this bit, put here for
659 * completeness. */
660 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL,
661 PCI_BRIDGE_CTL_DISCARD_STATUS);
662 }
663
664 static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev)
665 {
666 uint8_t slot = PCI_SLOT(dev->devfn);
667 uint8_t func;
668
669 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
670 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
671 }
672
673 /*
674 * multifunction bit is interpreted in two ways as follows.
675 * - all functions must set the bit to 1.
676 * Example: Intel X53
677 * - function 0 must set the bit, but the rest function (> 0)
678 * is allowed to leave the bit to 0.
679 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
680 *
681 * So OS (at least Linux) checks the bit of only function 0,
682 * and doesn't see the bit of function > 0.
683 *
684 * The below check allows both interpretation.
685 */
686 if (PCI_FUNC(dev->devfn)) {
687 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)];
688 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) {
689 /* function 0 should set multifunction bit */
690 error_report("PCI: single function device can't be populated "
691 "in function %x.%x", slot, PCI_FUNC(dev->devfn));
692 return -1;
693 }
694 return 0;
695 }
696
697 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
698 return 0;
699 }
700 /* function 0 indicates single function, so function > 0 must be NULL */
701 for (func = 1; func < PCI_FUNC_MAX; ++func) {
702 if (bus->devices[PCI_DEVFN(slot, func)]) {
703 error_report("PCI: %x.0 indicates single function, "
704 "but %x.%x is already populated.",
705 slot, slot, func);
706 return -1;
707 }
708 }
709 return 0;
710 }
711
712 static void pci_config_alloc(PCIDevice *pci_dev)
713 {
714 int config_size = pci_config_size(pci_dev);
715
716 pci_dev->config = qemu_mallocz(config_size);
717 pci_dev->cmask = qemu_mallocz(config_size);
718 pci_dev->wmask = qemu_mallocz(config_size);
719 pci_dev->w1cmask = qemu_mallocz(config_size);
720 pci_dev->used = qemu_mallocz(config_size);
721 }
722
723 static void pci_config_free(PCIDevice *pci_dev)
724 {
725 qemu_free(pci_dev->config);
726 qemu_free(pci_dev->cmask);
727 qemu_free(pci_dev->wmask);
728 qemu_free(pci_dev->w1cmask);
729 qemu_free(pci_dev->used);
730 }
731
732 /* -1 for devfn means auto assign */
733 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
734 const char *name, int devfn,
735 const PCIDeviceInfo *info)
736 {
737 PCIConfigReadFunc *config_read = info->config_read;
738 PCIConfigWriteFunc *config_write = info->config_write;
739
740 if (devfn < 0) {
741 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
742 devfn += PCI_FUNC_MAX) {
743 if (!bus->devices[devfn])
744 goto found;
745 }
746 error_report("PCI: no slot/function available for %s, all in use", name);
747 return NULL;
748 found: ;
749 } else if (bus->devices[devfn]) {
750 error_report("PCI: slot %d function %d not available for %s, in use by %s",
751 PCI_SLOT(devfn), PCI_FUNC(devfn), name, bus->devices[devfn]->name);
752 return NULL;
753 }
754 pci_dev->bus = bus;
755 pci_dev->devfn = devfn;
756 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
757 pci_dev->irq_state = 0;
758 pci_config_alloc(pci_dev);
759
760 pci_config_set_vendor_id(pci_dev->config, info->vendor_id);
761 pci_config_set_device_id(pci_dev->config, info->device_id);
762 pci_config_set_revision(pci_dev->config, info->revision);
763 pci_config_set_class(pci_dev->config, info->class_id);
764
765 if (!info->is_bridge) {
766 if (info->subsystem_vendor_id || info->subsystem_id) {
767 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
768 info->subsystem_vendor_id);
769 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
770 info->subsystem_id);
771 } else {
772 pci_set_default_subsystem_id(pci_dev);
773 }
774 } else {
775 /* subsystem_vendor_id/subsystem_id are only for header type 0 */
776 assert(!info->subsystem_vendor_id);
777 assert(!info->subsystem_id);
778 }
779 pci_init_cmask(pci_dev);
780 pci_init_wmask(pci_dev);
781 pci_init_w1cmask(pci_dev);
782 if (info->is_bridge) {
783 pci_init_wmask_bridge(pci_dev);
784 }
785 if (pci_init_multifunction(bus, pci_dev)) {
786 pci_config_free(pci_dev);
787 return NULL;
788 }
789
790 if (!config_read)
791 config_read = pci_default_read_config;
792 if (!config_write)
793 config_write = pci_default_write_config;
794 pci_dev->config_read = config_read;
795 pci_dev->config_write = config_write;
796 bus->devices[devfn] = pci_dev;
797 pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS);
798 pci_dev->version_id = 2; /* Current pci device vmstate version */
799 return pci_dev;
800 }
801
802 static void do_pci_unregister_device(PCIDevice *pci_dev)
803 {
804 qemu_free_irqs(pci_dev->irq);
805 pci_dev->bus->devices[pci_dev->devfn] = NULL;
806 pci_config_free(pci_dev);
807 }
808
809 /* TODO: obsolete. eliminate this once all pci devices are qdevifed. */
810 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
811 int instance_size, int devfn,
812 PCIConfigReadFunc *config_read,
813 PCIConfigWriteFunc *config_write)
814 {
815 PCIDevice *pci_dev;
816 PCIDeviceInfo info = {
817 .config_read = config_read,
818 .config_write = config_write,
819 };
820
821 pci_dev = qemu_mallocz(instance_size);
822 pci_dev = do_pci_register_device(pci_dev, bus, name, devfn, &info);
823 if (pci_dev == NULL) {
824 hw_error("PCI: can't register device\n");
825 }
826 return pci_dev;
827 }
828
829 static target_phys_addr_t pci_to_cpu_addr(PCIBus *bus,
830 target_phys_addr_t addr)
831 {
832 return addr + bus->mem_base;
833 }
834
835 static void pci_unregister_io_regions(PCIDevice *pci_dev)
836 {
837 PCIIORegion *r;
838 int i;
839
840 for(i = 0; i < PCI_NUM_REGIONS; i++) {
841 r = &pci_dev->io_regions[i];
842 if (!r->size || r->addr == PCI_BAR_UNMAPPED)
843 continue;
844 if (r->type == PCI_BASE_ADDRESS_SPACE_IO) {
845 isa_unassign_ioport(r->addr, r->filtered_size);
846 } else {
847 if (r->memory) {
848 memory_region_del_subregion(pci_dev->bus->address_space,
849 r->memory);
850 } else {
851 cpu_register_physical_memory(pci_to_cpu_addr(pci_dev->bus,
852 r->addr),
853 r->filtered_size,
854 IO_MEM_UNASSIGNED);
855 }
856 }
857 }
858 }
859
860 static int pci_unregister_device(DeviceState *dev)
861 {
862 PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
863 PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info);
864 int ret = 0;
865
866 if (info->exit)
867 ret = info->exit(pci_dev);
868 if (ret)
869 return ret;
870
871 pci_unregister_io_regions(pci_dev);
872 pci_del_option_rom(pci_dev);
873 qemu_free(pci_dev->romfile);
874 do_pci_unregister_device(pci_dev);
875 return 0;
876 }
877
878 void pci_register_bar(PCIDevice *pci_dev, int region_num,
879 pcibus_t size, uint8_t type,
880 PCIMapIORegionFunc *map_func)
881 {
882 PCIIORegion *r;
883 uint32_t addr;
884 uint64_t wmask;
885
886 assert(region_num >= 0);
887 assert(region_num < PCI_NUM_REGIONS);
888 if (size & (size-1)) {
889 fprintf(stderr, "ERROR: PCI region size must be pow2 "
890 "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
891 exit(1);
892 }
893
894 r = &pci_dev->io_regions[region_num];
895 r->addr = PCI_BAR_UNMAPPED;
896 r->size = size;
897 r->filtered_size = size;
898 r->type = type;
899 r->map_func = map_func;
900 r->ram_addr = IO_MEM_UNASSIGNED;
901 r->memory = NULL;
902
903 wmask = ~(size - 1);
904 addr = pci_bar(pci_dev, region_num);
905 if (region_num == PCI_ROM_SLOT) {
906 /* ROM enable bit is writable */
907 wmask |= PCI_ROM_ADDRESS_ENABLE;
908 }
909 pci_set_long(pci_dev->config + addr, type);
910 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
911 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
912 pci_set_quad(pci_dev->wmask + addr, wmask);
913 pci_set_quad(pci_dev->cmask + addr, ~0ULL);
914 } else {
915 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
916 pci_set_long(pci_dev->cmask + addr, 0xffffffff);
917 }
918 }
919
920 static void pci_simple_bar_mapfunc(PCIDevice *pci_dev, int region_num,
921 pcibus_t addr, pcibus_t size, int type)
922 {
923 cpu_register_physical_memory(addr, size,
924 pci_dev->io_regions[region_num].ram_addr);
925 }
926
927 static void pci_simple_bar_mapfunc_region(PCIDevice *pci_dev, int region_num,
928 pcibus_t addr, pcibus_t size,
929 int type)
930 {
931 memory_region_add_subregion_overlap(pci_dev->bus->address_space,
932 addr,
933 pci_dev->io_regions[region_num].memory,
934 1);
935 }
936
937 void pci_register_bar_simple(PCIDevice *pci_dev, int region_num,
938 pcibus_t size, uint8_t attr, ram_addr_t ram_addr)
939 {
940 pci_register_bar(pci_dev, region_num, size,
941 PCI_BASE_ADDRESS_SPACE_MEMORY | attr,
942 pci_simple_bar_mapfunc);
943 pci_dev->io_regions[region_num].ram_addr = ram_addr;
944 }
945
946 void pci_register_bar_region(PCIDevice *pci_dev, int region_num,
947 uint8_t attr, MemoryRegion *memory)
948 {
949 pci_register_bar(pci_dev, region_num, memory_region_size(memory),
950 PCI_BASE_ADDRESS_SPACE_MEMORY | attr,
951 pci_simple_bar_mapfunc_region);
952 pci_dev->io_regions[region_num].memory = memory;
953 }
954
955 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num)
956 {
957 return pci_dev->io_regions[region_num].addr;
958 }
959
960 static void pci_bridge_filter(PCIDevice *d, pcibus_t *addr, pcibus_t *size,
961 uint8_t type)
962 {
963 pcibus_t base = *addr;
964 pcibus_t limit = *addr + *size - 1;
965 PCIDevice *br;
966
967 for (br = d->bus->parent_dev; br; br = br->bus->parent_dev) {
968 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
969
970 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
971 if (!(cmd & PCI_COMMAND_IO)) {
972 goto no_map;
973 }
974 } else {
975 if (!(cmd & PCI_COMMAND_MEMORY)) {
976 goto no_map;
977 }
978 }
979
980 base = MAX(base, pci_bridge_get_base(br, type));
981 limit = MIN(limit, pci_bridge_get_limit(br, type));
982 }
983
984 if (base > limit) {
985 goto no_map;
986 }
987 *addr = base;
988 *size = limit - base + 1;
989 return;
990 no_map:
991 *addr = PCI_BAR_UNMAPPED;
992 *size = 0;
993 }
994
995 static pcibus_t pci_bar_address(PCIDevice *d,
996 int reg, uint8_t type, pcibus_t size)
997 {
998 pcibus_t new_addr, last_addr;
999 int bar = pci_bar(d, reg);
1000 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
1001
1002 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
1003 if (!(cmd & PCI_COMMAND_IO)) {
1004 return PCI_BAR_UNMAPPED;
1005 }
1006 new_addr = pci_get_long(d->config + bar) & ~(size - 1);
1007 last_addr = new_addr + size - 1;
1008 /* NOTE: we have only 64K ioports on PC */
1009 if (last_addr <= new_addr || new_addr == 0 || last_addr > UINT16_MAX) {
1010 return PCI_BAR_UNMAPPED;
1011 }
1012 return new_addr;
1013 }
1014
1015 if (!(cmd & PCI_COMMAND_MEMORY)) {
1016 return PCI_BAR_UNMAPPED;
1017 }
1018 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
1019 new_addr = pci_get_quad(d->config + bar);
1020 } else {
1021 new_addr = pci_get_long(d->config + bar);
1022 }
1023 /* the ROM slot has a specific enable bit */
1024 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
1025 return PCI_BAR_UNMAPPED;
1026 }
1027 new_addr &= ~(size - 1);
1028 last_addr = new_addr + size - 1;
1029 /* NOTE: we do not support wrapping */
1030 /* XXX: as we cannot support really dynamic
1031 mappings, we handle specific values as invalid
1032 mappings. */
1033 if (last_addr <= new_addr || new_addr == 0 ||
1034 last_addr == PCI_BAR_UNMAPPED) {
1035 return PCI_BAR_UNMAPPED;
1036 }
1037
1038 /* Now pcibus_t is 64bit.
1039 * Check if 32 bit BAR wraps around explicitly.
1040 * Without this, PC ide doesn't work well.
1041 * TODO: remove this work around.
1042 */
1043 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
1044 return PCI_BAR_UNMAPPED;
1045 }
1046
1047 /*
1048 * OS is allowed to set BAR beyond its addressable
1049 * bits. For example, 32 bit OS can set 64bit bar
1050 * to >4G. Check it. TODO: we might need to support
1051 * it in the future for e.g. PAE.
1052 */
1053 if (last_addr >= TARGET_PHYS_ADDR_MAX) {
1054 return PCI_BAR_UNMAPPED;
1055 }
1056
1057 return new_addr;
1058 }
1059
1060 static void pci_update_mappings(PCIDevice *d)
1061 {
1062 PCIIORegion *r;
1063 int i;
1064 pcibus_t new_addr, filtered_size;
1065
1066 for(i = 0; i < PCI_NUM_REGIONS; i++) {
1067 r = &d->io_regions[i];
1068
1069 /* this region isn't registered */
1070 if (!r->size)
1071 continue;
1072
1073 new_addr = pci_bar_address(d, i, r->type, r->size);
1074
1075 /* bridge filtering */
1076 filtered_size = r->size;
1077 if (new_addr != PCI_BAR_UNMAPPED) {
1078 pci_bridge_filter(d, &new_addr, &filtered_size, r->type);
1079 }
1080
1081 /* This bar isn't changed */
1082 if (new_addr == r->addr && filtered_size == r->filtered_size)
1083 continue;
1084
1085 /* now do the real mapping */
1086 if (r->addr != PCI_BAR_UNMAPPED) {
1087 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1088 int class;
1089 /* NOTE: specific hack for IDE in PC case:
1090 only one byte must be mapped. */
1091 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
1092 if (class == 0x0101 && r->size == 4) {
1093 isa_unassign_ioport(r->addr + 2, 1);
1094 } else {
1095 isa_unassign_ioport(r->addr, r->filtered_size);
1096 }
1097 } else {
1098 if (r->memory) {
1099 memory_region_del_subregion(d->bus->address_space,
1100 r->memory);
1101 } else {
1102 cpu_register_physical_memory(pci_to_cpu_addr(d->bus,
1103 r->addr),
1104 r->filtered_size,
1105 IO_MEM_UNASSIGNED);
1106 qemu_unregister_coalesced_mmio(r->addr, r->filtered_size);
1107 }
1108 }
1109 }
1110 r->addr = new_addr;
1111 r->filtered_size = filtered_size;
1112 if (r->addr != PCI_BAR_UNMAPPED) {
1113 /*
1114 * TODO: currently almost all the map funcions assumes
1115 * filtered_size == size and addr & ~(size - 1) == addr.
1116 * However with bridge filtering, they aren't always true.
1117 * Teach them such cases, such that filtered_size < size and
1118 * addr & (size - 1) != 0.
1119 */
1120 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1121 r->map_func(d, i, r->addr, r->filtered_size, r->type);
1122 } else {
1123 r->map_func(d, i, pci_to_cpu_addr(d->bus, r->addr),
1124 r->filtered_size, r->type);
1125 }
1126 }
1127 }
1128 }
1129
1130 static inline int pci_irq_disabled(PCIDevice *d)
1131 {
1132 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
1133 }
1134
1135 /* Called after interrupt disabled field update in config space,
1136 * assert/deassert interrupts if necessary.
1137 * Gets original interrupt disable bit value (before update). */
1138 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
1139 {
1140 int i, disabled = pci_irq_disabled(d);
1141 if (disabled == was_irq_disabled)
1142 return;
1143 for (i = 0; i < PCI_NUM_PINS; ++i) {
1144 int state = pci_irq_state(d, i);
1145 pci_change_irq_level(d, i, disabled ? -state : state);
1146 }
1147 }
1148
1149 uint32_t pci_default_read_config(PCIDevice *d,
1150 uint32_t address, int len)
1151 {
1152 uint32_t val = 0;
1153
1154 memcpy(&val, d->config + address, len);
1155 return le32_to_cpu(val);
1156 }
1157
1158 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
1159 {
1160 int i, was_irq_disabled = pci_irq_disabled(d);
1161
1162 for (i = 0; i < l; val >>= 8, ++i) {
1163 uint8_t wmask = d->wmask[addr + i];
1164 uint8_t w1cmask = d->w1cmask[addr + i];
1165 assert(!(wmask & w1cmask));
1166 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
1167 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
1168 }
1169 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
1170 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
1171 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
1172 range_covers_byte(addr, l, PCI_COMMAND))
1173 pci_update_mappings(d);
1174
1175 if (range_covers_byte(addr, l, PCI_COMMAND))
1176 pci_update_irq_disabled(d, was_irq_disabled);
1177 }
1178
1179 /***********************************************************/
1180 /* generic PCI irq support */
1181
1182 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1183 static void pci_set_irq(void *opaque, int irq_num, int level)
1184 {
1185 PCIDevice *pci_dev = opaque;
1186 int change;
1187
1188 change = level - pci_irq_state(pci_dev, irq_num);
1189 if (!change)
1190 return;
1191
1192 pci_set_irq_state(pci_dev, irq_num, level);
1193 pci_update_irq_status(pci_dev);
1194 if (pci_irq_disabled(pci_dev))
1195 return;
1196 pci_change_irq_level(pci_dev, irq_num, change);
1197 }
1198
1199 /***********************************************************/
1200 /* monitor info on PCI */
1201
1202 typedef struct {
1203 uint16_t class;
1204 const char *desc;
1205 const char *fw_name;
1206 uint16_t fw_ign_bits;
1207 } pci_class_desc;
1208
1209 static const pci_class_desc pci_class_descriptions[] =
1210 {
1211 { 0x0001, "VGA controller", "display"},
1212 { 0x0100, "SCSI controller", "scsi"},
1213 { 0x0101, "IDE controller", "ide"},
1214 { 0x0102, "Floppy controller", "fdc"},
1215 { 0x0103, "IPI controller", "ipi"},
1216 { 0x0104, "RAID controller", "raid"},
1217 { 0x0106, "SATA controller"},
1218 { 0x0107, "SAS controller"},
1219 { 0x0180, "Storage controller"},
1220 { 0x0200, "Ethernet controller", "ethernet"},
1221 { 0x0201, "Token Ring controller", "token-ring"},
1222 { 0x0202, "FDDI controller", "fddi"},
1223 { 0x0203, "ATM controller", "atm"},
1224 { 0x0280, "Network controller"},
1225 { 0x0300, "VGA controller", "display", 0x00ff},
1226 { 0x0301, "XGA controller"},
1227 { 0x0302, "3D controller"},
1228 { 0x0380, "Display controller"},
1229 { 0x0400, "Video controller", "video"},
1230 { 0x0401, "Audio controller", "sound"},
1231 { 0x0402, "Phone"},
1232 { 0x0403, "Audio controller", "sound"},
1233 { 0x0480, "Multimedia controller"},
1234 { 0x0500, "RAM controller", "memory"},
1235 { 0x0501, "Flash controller", "flash"},
1236 { 0x0580, "Memory controller"},
1237 { 0x0600, "Host bridge", "host"},
1238 { 0x0601, "ISA bridge", "isa"},
1239 { 0x0602, "EISA bridge", "eisa"},
1240 { 0x0603, "MC bridge", "mca"},
1241 { 0x0604, "PCI bridge", "pci"},
1242 { 0x0605, "PCMCIA bridge", "pcmcia"},
1243 { 0x0606, "NUBUS bridge", "nubus"},
1244 { 0x0607, "CARDBUS bridge", "cardbus"},
1245 { 0x0608, "RACEWAY bridge"},
1246 { 0x0680, "Bridge"},
1247 { 0x0700, "Serial port", "serial"},
1248 { 0x0701, "Parallel port", "parallel"},
1249 { 0x0800, "Interrupt controller", "interrupt-controller"},
1250 { 0x0801, "DMA controller", "dma-controller"},
1251 { 0x0802, "Timer", "timer"},
1252 { 0x0803, "RTC", "rtc"},
1253 { 0x0900, "Keyboard", "keyboard"},
1254 { 0x0901, "Pen", "pen"},
1255 { 0x0902, "Mouse", "mouse"},
1256 { 0x0A00, "Dock station", "dock", 0x00ff},
1257 { 0x0B00, "i386 cpu", "cpu", 0x00ff},
1258 { 0x0c00, "Fireware contorller", "fireware"},
1259 { 0x0c01, "Access bus controller", "access-bus"},
1260 { 0x0c02, "SSA controller", "ssa"},
1261 { 0x0c03, "USB controller", "usb"},
1262 { 0x0c04, "Fibre channel controller", "fibre-channel"},
1263 { 0, NULL}
1264 };
1265
1266 static void pci_for_each_device_under_bus(PCIBus *bus,
1267 void (*fn)(PCIBus *b, PCIDevice *d))
1268 {
1269 PCIDevice *d;
1270 int devfn;
1271
1272 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1273 d = bus->devices[devfn];
1274 if (d) {
1275 fn(bus, d);
1276 }
1277 }
1278 }
1279
1280 void pci_for_each_device(PCIBus *bus, int bus_num,
1281 void (*fn)(PCIBus *b, PCIDevice *d))
1282 {
1283 bus = pci_find_bus(bus, bus_num);
1284
1285 if (bus) {
1286 pci_for_each_device_under_bus(bus, fn);
1287 }
1288 }
1289
1290 static void pci_device_print(Monitor *mon, QDict *device)
1291 {
1292 QDict *qdict;
1293 QListEntry *entry;
1294 uint64_t addr, size;
1295
1296 monitor_printf(mon, " Bus %2" PRId64 ", ", qdict_get_int(device, "bus"));
1297 monitor_printf(mon, "device %3" PRId64 ", function %" PRId64 ":\n",
1298 qdict_get_int(device, "slot"),
1299 qdict_get_int(device, "function"));
1300 monitor_printf(mon, " ");
1301
1302 qdict = qdict_get_qdict(device, "class_info");
1303 if (qdict_haskey(qdict, "desc")) {
1304 monitor_printf(mon, "%s", qdict_get_str(qdict, "desc"));
1305 } else {
1306 monitor_printf(mon, "Class %04" PRId64, qdict_get_int(qdict, "class"));
1307 }
1308
1309 qdict = qdict_get_qdict(device, "id");
1310 monitor_printf(mon, ": PCI device %04" PRIx64 ":%04" PRIx64 "\n",
1311 qdict_get_int(qdict, "device"),
1312 qdict_get_int(qdict, "vendor"));
1313
1314 if (qdict_haskey(device, "irq")) {
1315 monitor_printf(mon, " IRQ %" PRId64 ".\n",
1316 qdict_get_int(device, "irq"));
1317 }
1318
1319 if (qdict_haskey(device, "pci_bridge")) {
1320 QDict *info;
1321
1322 qdict = qdict_get_qdict(device, "pci_bridge");
1323
1324 info = qdict_get_qdict(qdict, "bus");
1325 monitor_printf(mon, " BUS %" PRId64 ".\n",
1326 qdict_get_int(info, "number"));
1327 monitor_printf(mon, " secondary bus %" PRId64 ".\n",
1328 qdict_get_int(info, "secondary"));
1329 monitor_printf(mon, " subordinate bus %" PRId64 ".\n",
1330 qdict_get_int(info, "subordinate"));
1331
1332 info = qdict_get_qdict(qdict, "io_range");
1333 monitor_printf(mon, " IO range [0x%04"PRIx64", 0x%04"PRIx64"]\n",
1334 qdict_get_int(info, "base"),
1335 qdict_get_int(info, "limit"));
1336
1337 info = qdict_get_qdict(qdict, "memory_range");
1338 monitor_printf(mon,
1339 " memory range [0x%08"PRIx64", 0x%08"PRIx64"]\n",
1340 qdict_get_int(info, "base"),
1341 qdict_get_int(info, "limit"));
1342
1343 info = qdict_get_qdict(qdict, "prefetchable_range");
1344 monitor_printf(mon, " prefetchable memory range "
1345 "[0x%08"PRIx64", 0x%08"PRIx64"]\n",
1346 qdict_get_int(info, "base"),
1347 qdict_get_int(info, "limit"));
1348 }
1349
1350 QLIST_FOREACH_ENTRY(qdict_get_qlist(device, "regions"), entry) {
1351 qdict = qobject_to_qdict(qlist_entry_obj(entry));
1352 monitor_printf(mon, " BAR%d: ", (int) qdict_get_int(qdict, "bar"));
1353
1354 addr = qdict_get_int(qdict, "address");
1355 size = qdict_get_int(qdict, "size");
1356
1357 if (!strcmp(qdict_get_str(qdict, "type"), "io")) {
1358 monitor_printf(mon, "I/O at 0x%04"FMT_PCIBUS
1359 " [0x%04"FMT_PCIBUS"].\n",
1360 addr, addr + size - 1);
1361 } else {
1362 monitor_printf(mon, "%d bit%s memory at 0x%08"FMT_PCIBUS
1363 " [0x%08"FMT_PCIBUS"].\n",
1364 qdict_get_bool(qdict, "mem_type_64") ? 64 : 32,
1365 qdict_get_bool(qdict, "prefetch") ?
1366 " prefetchable" : "", addr, addr + size - 1);
1367 }
1368 }
1369
1370 monitor_printf(mon, " id \"%s\"\n", qdict_get_str(device, "qdev_id"));
1371
1372 if (qdict_haskey(device, "pci_bridge")) {
1373 qdict = qdict_get_qdict(device, "pci_bridge");
1374 if (qdict_haskey(qdict, "devices")) {
1375 QListEntry *dev;
1376 QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
1377 pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev)));
1378 }
1379 }
1380 }
1381 }
1382
1383 void do_pci_info_print(Monitor *mon, const QObject *data)
1384 {
1385 QListEntry *bus, *dev;
1386
1387 QLIST_FOREACH_ENTRY(qobject_to_qlist(data), bus) {
1388 QDict *qdict = qobject_to_qdict(qlist_entry_obj(bus));
1389 QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
1390 pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev)));
1391 }
1392 }
1393 }
1394
1395 static QObject *pci_get_dev_class(const PCIDevice *dev)
1396 {
1397 int class;
1398 const pci_class_desc *desc;
1399
1400 class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
1401 desc = pci_class_descriptions;
1402 while (desc->desc && class != desc->class)
1403 desc++;
1404
1405 if (desc->desc) {
1406 return qobject_from_jsonf("{ 'desc': %s, 'class': %d }",
1407 desc->desc, class);
1408 } else {
1409 return qobject_from_jsonf("{ 'class': %d }", class);
1410 }
1411 }
1412
1413 static QObject *pci_get_dev_id(const PCIDevice *dev)
1414 {
1415 return qobject_from_jsonf("{ 'device': %d, 'vendor': %d }",
1416 pci_get_word(dev->config + PCI_VENDOR_ID),
1417 pci_get_word(dev->config + PCI_DEVICE_ID));
1418 }
1419
1420 static QObject *pci_get_regions_list(const PCIDevice *dev)
1421 {
1422 int i;
1423 QList *regions_list;
1424
1425 regions_list = qlist_new();
1426
1427 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1428 QObject *obj;
1429 const PCIIORegion *r = &dev->io_regions[i];
1430
1431 if (!r->size) {
1432 continue;
1433 }
1434
1435 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1436 obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'io', "
1437 "'address': %" PRId64 ", "
1438 "'size': %" PRId64 " }",
1439 i, r->addr, r->size);
1440 } else {
1441 int mem_type_64 = r->type & PCI_BASE_ADDRESS_MEM_TYPE_64;
1442
1443 obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'memory', "
1444 "'mem_type_64': %i, 'prefetch': %i, "
1445 "'address': %" PRId64 ", "
1446 "'size': %" PRId64 " }",
1447 i, mem_type_64,
1448 r->type & PCI_BASE_ADDRESS_MEM_PREFETCH,
1449 r->addr, r->size);
1450 }
1451
1452 qlist_append_obj(regions_list, obj);
1453 }
1454
1455 return QOBJECT(regions_list);
1456 }
1457
1458 static QObject *pci_get_devices_list(PCIBus *bus, int bus_num);
1459
1460 static QObject *pci_get_dev_dict(PCIDevice *dev, PCIBus *bus, int bus_num)
1461 {
1462 uint8_t type;
1463 QObject *obj;
1464
1465 obj = qobject_from_jsonf("{ 'bus': %d, 'slot': %d, 'function': %d," "'class_info': %p, 'id': %p, 'regions': %p,"
1466 " 'qdev_id': %s }",
1467 bus_num,
1468 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
1469 pci_get_dev_class(dev), pci_get_dev_id(dev),
1470 pci_get_regions_list(dev),
1471 dev->qdev.id ? dev->qdev.id : "");
1472
1473 if (dev->config[PCI_INTERRUPT_PIN] != 0) {
1474 QDict *qdict = qobject_to_qdict(obj);
1475 qdict_put(qdict, "irq", qint_from_int(dev->config[PCI_INTERRUPT_LINE]));
1476 }
1477
1478 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
1479 if (type == PCI_HEADER_TYPE_BRIDGE) {
1480 QDict *qdict;
1481 QObject *pci_bridge;
1482
1483 pci_bridge = qobject_from_jsonf("{ 'bus': "
1484 "{ 'number': %d, 'secondary': %d, 'subordinate': %d }, "
1485 "'io_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
1486 "'memory_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
1487 "'prefetchable_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "} }",
1488 dev->config[PCI_PRIMARY_BUS], dev->config[PCI_SECONDARY_BUS],
1489 dev->config[PCI_SUBORDINATE_BUS],
1490 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO),
1491 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO),
1492 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
1493 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
1494 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
1495 PCI_BASE_ADDRESS_MEM_PREFETCH),
1496 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
1497 PCI_BASE_ADDRESS_MEM_PREFETCH));
1498
1499 if (dev->config[PCI_SECONDARY_BUS] != 0) {
1500 PCIBus *child_bus = pci_find_bus(bus, dev->config[PCI_SECONDARY_BUS]);
1501
1502 if (child_bus) {
1503 qdict = qobject_to_qdict(pci_bridge);
1504 qdict_put_obj(qdict, "devices",
1505 pci_get_devices_list(child_bus,
1506 dev->config[PCI_SECONDARY_BUS]));
1507 }
1508 }
1509 qdict = qobject_to_qdict(obj);
1510 qdict_put_obj(qdict, "pci_bridge", pci_bridge);
1511 }
1512
1513 return obj;
1514 }
1515
1516 static QObject *pci_get_devices_list(PCIBus *bus, int bus_num)
1517 {
1518 int devfn;
1519 PCIDevice *dev;
1520 QList *dev_list;
1521
1522 dev_list = qlist_new();
1523
1524 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1525 dev = bus->devices[devfn];
1526 if (dev) {
1527 qlist_append_obj(dev_list, pci_get_dev_dict(dev, bus, bus_num));
1528 }
1529 }
1530
1531 return QOBJECT(dev_list);
1532 }
1533
1534 static QObject *pci_get_bus_dict(PCIBus *bus, int bus_num)
1535 {
1536 bus = pci_find_bus(bus, bus_num);
1537 if (bus) {
1538 return qobject_from_jsonf("{ 'bus': %d, 'devices': %p }",
1539 bus_num, pci_get_devices_list(bus, bus_num));
1540 }
1541
1542 return NULL;
1543 }
1544
1545 void do_pci_info(Monitor *mon, QObject **ret_data)
1546 {
1547 QList *bus_list;
1548 struct PCIHostBus *host;
1549
1550 bus_list = qlist_new();
1551
1552 QLIST_FOREACH(host, &host_buses, next) {
1553 QObject *obj = pci_get_bus_dict(host->bus, 0);
1554 if (obj) {
1555 qlist_append_obj(bus_list, obj);
1556 }
1557 }
1558
1559 *ret_data = QOBJECT(bus_list);
1560 }
1561
1562 static const char * const pci_nic_models[] = {
1563 "ne2k_pci",
1564 "i82551",
1565 "i82557b",
1566 "i82559er",
1567 "rtl8139",
1568 "e1000",
1569 "pcnet",
1570 "virtio",
1571 NULL
1572 };
1573
1574 static const char * const pci_nic_names[] = {
1575 "ne2k_pci",
1576 "i82551",
1577 "i82557b",
1578 "i82559er",
1579 "rtl8139",
1580 "e1000",
1581 "pcnet",
1582 "virtio-net-pci",
1583 NULL
1584 };
1585
1586 /* Initialize a PCI NIC. */
1587 /* FIXME callers should check for failure, but don't */
1588 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
1589 const char *default_devaddr)
1590 {
1591 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
1592 PCIBus *bus;
1593 int devfn;
1594 PCIDevice *pci_dev;
1595 DeviceState *dev;
1596 int i;
1597
1598 i = qemu_find_nic_model(nd, pci_nic_models, default_model);
1599 if (i < 0)
1600 return NULL;
1601
1602 bus = pci_get_bus_devfn(&devfn, devaddr);
1603 if (!bus) {
1604 error_report("Invalid PCI device address %s for device %s",
1605 devaddr, pci_nic_names[i]);
1606 return NULL;
1607 }
1608
1609 pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
1610 dev = &pci_dev->qdev;
1611 qdev_set_nic_properties(dev, nd);
1612 if (qdev_init(dev) < 0)
1613 return NULL;
1614 return pci_dev;
1615 }
1616
1617 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
1618 const char *default_devaddr)
1619 {
1620 PCIDevice *res;
1621
1622 if (qemu_show_nic_models(nd->model, pci_nic_models))
1623 exit(0);
1624
1625 res = pci_nic_init(nd, default_model, default_devaddr);
1626 if (!res)
1627 exit(1);
1628 return res;
1629 }
1630
1631 static void pci_bridge_update_mappings_fn(PCIBus *b, PCIDevice *d)
1632 {
1633 pci_update_mappings(d);
1634 }
1635
1636 void pci_bridge_update_mappings(PCIBus *b)
1637 {
1638 PCIBus *child;
1639
1640 pci_for_each_device_under_bus(b, pci_bridge_update_mappings_fn);
1641
1642 QLIST_FOREACH(child, &b->child, sibling) {
1643 pci_bridge_update_mappings(child);
1644 }
1645 }
1646
1647 /* Whether a given bus number is in range of the secondary
1648 * bus of the given bridge device. */
1649 static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num)
1650 {
1651 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) &
1652 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ &&
1653 dev->config[PCI_SECONDARY_BUS] < bus_num &&
1654 bus_num <= dev->config[PCI_SUBORDINATE_BUS];
1655 }
1656
1657 PCIBus *pci_find_bus(PCIBus *bus, int bus_num)
1658 {
1659 PCIBus *sec;
1660
1661 if (!bus) {
1662 return NULL;
1663 }
1664
1665 if (pci_bus_num(bus) == bus_num) {
1666 return bus;
1667 }
1668
1669 /* Consider all bus numbers in range for the host pci bridge. */
1670 if (bus->parent_dev &&
1671 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) {
1672 return NULL;
1673 }
1674
1675 /* try child bus */
1676 for (; bus; bus = sec) {
1677 QLIST_FOREACH(sec, &bus->child, sibling) {
1678 assert(sec->parent_dev);
1679 if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) {
1680 return sec;
1681 }
1682 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) {
1683 break;
1684 }
1685 }
1686 }
1687
1688 return NULL;
1689 }
1690
1691 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn)
1692 {
1693 bus = pci_find_bus(bus, bus_num);
1694
1695 if (!bus)
1696 return NULL;
1697
1698 return bus->devices[devfn];
1699 }
1700
1701 static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
1702 {
1703 PCIDevice *pci_dev = (PCIDevice *)qdev;
1704 PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
1705 PCIBus *bus;
1706 int rc;
1707 bool is_default_rom;
1708
1709 /* initialize cap_present for pci_is_express() and pci_config_size() */
1710 if (info->is_express) {
1711 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1712 }
1713
1714 bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
1715 pci_dev = do_pci_register_device(pci_dev, bus, base->name,
1716 pci_dev->devfn, info);
1717 if (pci_dev == NULL)
1718 return -1;
1719 if (qdev->hotplugged && info->no_hotplug) {
1720 qerror_report(QERR_DEVICE_NO_HOTPLUG, info->qdev.name);
1721 do_pci_unregister_device(pci_dev);
1722 return -1;
1723 }
1724 if (info->init) {
1725 rc = info->init(pci_dev);
1726 if (rc != 0) {
1727 do_pci_unregister_device(pci_dev);
1728 return rc;
1729 }
1730 }
1731
1732 /* rom loading */
1733 is_default_rom = false;
1734 if (pci_dev->romfile == NULL && info->romfile != NULL) {
1735 pci_dev->romfile = qemu_strdup(info->romfile);
1736 is_default_rom = true;
1737 }
1738 pci_add_option_rom(pci_dev, is_default_rom);
1739
1740 if (bus->hotplug) {
1741 /* Let buses differentiate between hotplug and when device is
1742 * enabled during qemu machine creation. */
1743 rc = bus->hotplug(bus->hotplug_qdev, pci_dev,
1744 qdev->hotplugged ? PCI_HOTPLUG_ENABLED:
1745 PCI_COLDPLUG_ENABLED);
1746 if (rc != 0) {
1747 int r = pci_unregister_device(&pci_dev->qdev);
1748 assert(!r);
1749 return rc;
1750 }
1751 }
1752 return 0;
1753 }
1754
1755 static int pci_unplug_device(DeviceState *qdev)
1756 {
1757 PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev);
1758 PCIDeviceInfo *info = container_of(qdev->info, PCIDeviceInfo, qdev);
1759
1760 if (info->no_hotplug) {
1761 qerror_report(QERR_DEVICE_NO_HOTPLUG, info->qdev.name);
1762 return -1;
1763 }
1764 return dev->bus->hotplug(dev->bus->hotplug_qdev, dev,
1765 PCI_HOTPLUG_DISABLED);
1766 }
1767
1768 void pci_qdev_register(PCIDeviceInfo *info)
1769 {
1770 info->qdev.init = pci_qdev_init;
1771 info->qdev.unplug = pci_unplug_device;
1772 info->qdev.exit = pci_unregister_device;
1773 info->qdev.bus_info = &pci_bus_info;
1774 qdev_register(&info->qdev);
1775 }
1776
1777 void pci_qdev_register_many(PCIDeviceInfo *info)
1778 {
1779 while (info->qdev.name) {
1780 pci_qdev_register(info);
1781 info++;
1782 }
1783 }
1784
1785 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
1786 const char *name)
1787 {
1788 DeviceState *dev;
1789
1790 dev = qdev_create(&bus->qbus, name);
1791 qdev_prop_set_uint32(dev, "addr", devfn);
1792 qdev_prop_set_bit(dev, "multifunction", multifunction);
1793 return DO_UPCAST(PCIDevice, qdev, dev);
1794 }
1795
1796 PCIDevice *pci_try_create_multifunction(PCIBus *bus, int devfn,
1797 bool multifunction,
1798 const char *name)
1799 {
1800 DeviceState *dev;
1801
1802 dev = qdev_try_create(&bus->qbus, name);
1803 if (!dev) {
1804 return NULL;
1805 }
1806 qdev_prop_set_uint32(dev, "addr", devfn);
1807 qdev_prop_set_bit(dev, "multifunction", multifunction);
1808 return DO_UPCAST(PCIDevice, qdev, dev);
1809 }
1810
1811 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
1812 bool multifunction,
1813 const char *name)
1814 {
1815 PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name);
1816 qdev_init_nofail(&dev->qdev);
1817 return dev;
1818 }
1819
1820 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
1821 {
1822 return pci_create_multifunction(bus, devfn, false, name);
1823 }
1824
1825 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
1826 {
1827 return pci_create_simple_multifunction(bus, devfn, false, name);
1828 }
1829
1830 PCIDevice *pci_try_create(PCIBus *bus, int devfn, const char *name)
1831 {
1832 return pci_try_create_multifunction(bus, devfn, false, name);
1833 }
1834
1835 static int pci_find_space(PCIDevice *pdev, uint8_t size)
1836 {
1837 int config_size = pci_config_size(pdev);
1838 int offset = PCI_CONFIG_HEADER_SIZE;
1839 int i;
1840 for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)
1841 if (pdev->used[i])
1842 offset = i + 1;
1843 else if (i - offset + 1 == size)
1844 return offset;
1845 return 0;
1846 }
1847
1848 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
1849 uint8_t *prev_p)
1850 {
1851 uint8_t next, prev;
1852
1853 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
1854 return 0;
1855
1856 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1857 prev = next + PCI_CAP_LIST_NEXT)
1858 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
1859 break;
1860
1861 if (prev_p)
1862 *prev_p = prev;
1863 return next;
1864 }
1865
1866 static void pci_map_option_rom(PCIDevice *pdev, int region_num, pcibus_t addr, pcibus_t size, int type)
1867 {
1868 cpu_register_physical_memory(addr, size, pdev->rom_offset);
1869 }
1870
1871 /* Patch the PCI vendor and device ids in a PCI rom image if necessary.
1872 This is needed for an option rom which is used for more than one device. */
1873 static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size)
1874 {
1875 uint16_t vendor_id;
1876 uint16_t device_id;
1877 uint16_t rom_vendor_id;
1878 uint16_t rom_device_id;
1879 uint16_t rom_magic;
1880 uint16_t pcir_offset;
1881 uint8_t checksum;
1882
1883 /* Words in rom data are little endian (like in PCI configuration),
1884 so they can be read / written with pci_get_word / pci_set_word. */
1885
1886 /* Only a valid rom will be patched. */
1887 rom_magic = pci_get_word(ptr);
1888 if (rom_magic != 0xaa55) {
1889 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic);
1890 return;
1891 }
1892 pcir_offset = pci_get_word(ptr + 0x18);
1893 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) {
1894 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset);
1895 return;
1896 }
1897
1898 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID);
1899 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID);
1900 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4);
1901 rom_device_id = pci_get_word(ptr + pcir_offset + 6);
1902
1903 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile,
1904 vendor_id, device_id, rom_vendor_id, rom_device_id);
1905
1906 checksum = ptr[6];
1907
1908 if (vendor_id != rom_vendor_id) {
1909 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */
1910 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8);
1911 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8);
1912 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
1913 ptr[6] = checksum;
1914 pci_set_word(ptr + pcir_offset + 4, vendor_id);
1915 }
1916
1917 if (device_id != rom_device_id) {
1918 /* Patch device id and checksum (at offset 6 for etherboot roms). */
1919 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8);
1920 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8);
1921 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
1922 ptr[6] = checksum;
1923 pci_set_word(ptr + pcir_offset + 6, device_id);
1924 }
1925 }
1926
1927 /* Add an option rom for the device */
1928 static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom)
1929 {
1930 int size;
1931 char *path;
1932 void *ptr;
1933 char name[32];
1934
1935 if (!pdev->romfile)
1936 return 0;
1937 if (strlen(pdev->romfile) == 0)
1938 return 0;
1939
1940 if (!pdev->rom_bar) {
1941 /*
1942 * Load rom via fw_cfg instead of creating a rom bar,
1943 * for 0.11 compatibility.
1944 */
1945 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
1946 if (class == 0x0300) {
1947 rom_add_vga(pdev->romfile);
1948 } else {
1949 rom_add_option(pdev->romfile, -1);
1950 }
1951 return 0;
1952 }
1953
1954 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
1955 if (path == NULL) {
1956 path = qemu_strdup(pdev->romfile);
1957 }
1958
1959 size = get_image_size(path);
1960 if (size < 0) {
1961 error_report("%s: failed to find romfile \"%s\"",
1962 __FUNCTION__, pdev->romfile);
1963 qemu_free(path);
1964 return -1;
1965 }
1966 if (size & (size - 1)) {
1967 size = 1 << qemu_fls(size);
1968 }
1969
1970 if (pdev->qdev.info->vmsd)
1971 snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->vmsd->name);
1972 else
1973 snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->name);
1974 pdev->rom_offset = qemu_ram_alloc(&pdev->qdev, name, size);
1975
1976 ptr = qemu_get_ram_ptr(pdev->rom_offset);
1977 load_image(path, ptr);
1978 qemu_free(path);
1979
1980 if (is_default_rom) {
1981 /* Only the default rom images will be patched (if needed). */
1982 pci_patch_ids(pdev, ptr, size);
1983 }
1984
1985 qemu_put_ram_ptr(ptr);
1986
1987 pci_register_bar(pdev, PCI_ROM_SLOT, size,
1988 0, pci_map_option_rom);
1989
1990 return 0;
1991 }
1992
1993 static void pci_del_option_rom(PCIDevice *pdev)
1994 {
1995 if (!pdev->rom_offset)
1996 return;
1997
1998 qemu_ram_free(pdev->rom_offset);
1999 pdev->rom_offset = 0;
2000 }
2001
2002 /*
2003 * if !offset
2004 * Reserve space and add capability to the linked list in pci config space
2005 *
2006 * if offset = 0,
2007 * Find and reserve space and add capability to the linked list
2008 * in pci config space */
2009 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
2010 uint8_t offset, uint8_t size)
2011 {
2012 uint8_t *config;
2013 if (!offset) {
2014 offset = pci_find_space(pdev, size);
2015 if (!offset) {
2016 return -ENOSPC;
2017 }
2018 }
2019
2020 config = pdev->config + offset;
2021 config[PCI_CAP_LIST_ID] = cap_id;
2022 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
2023 pdev->config[PCI_CAPABILITY_LIST] = offset;
2024 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
2025 memset(pdev->used + offset, 0xFF, size);
2026 /* Make capability read-only by default */
2027 memset(pdev->wmask + offset, 0, size);
2028 /* Check capability by default */
2029 memset(pdev->cmask + offset, 0xFF, size);
2030 return offset;
2031 }
2032
2033 /* Unlink capability from the pci config space. */
2034 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
2035 {
2036 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
2037 if (!offset)
2038 return;
2039 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
2040 /* Make capability writable again */
2041 memset(pdev->wmask + offset, 0xff, size);
2042 memset(pdev->w1cmask + offset, 0, size);
2043 /* Clear cmask as device-specific registers can't be checked */
2044 memset(pdev->cmask + offset, 0, size);
2045 memset(pdev->used + offset, 0, size);
2046
2047 if (!pdev->config[PCI_CAPABILITY_LIST])
2048 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
2049 }
2050
2051 /* Reserve space for capability at a known offset (to call after load). */
2052 void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
2053 {
2054 memset(pdev->used + offset, 0xff, size);
2055 }
2056
2057 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
2058 {
2059 return pci_find_capability_list(pdev, cap_id, NULL);
2060 }
2061
2062 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
2063 {
2064 PCIDevice *d = (PCIDevice *)dev;
2065 const pci_class_desc *desc;
2066 char ctxt[64];
2067 PCIIORegion *r;
2068 int i, class;
2069
2070 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
2071 desc = pci_class_descriptions;
2072 while (desc->desc && class != desc->class)
2073 desc++;
2074 if (desc->desc) {
2075 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
2076 } else {
2077 snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
2078 }
2079
2080 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
2081 "pci id %04x:%04x (sub %04x:%04x)\n",
2082 indent, "", ctxt, pci_bus_num(d->bus),
2083 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
2084 pci_get_word(d->config + PCI_VENDOR_ID),
2085 pci_get_word(d->config + PCI_DEVICE_ID),
2086 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
2087 pci_get_word(d->config + PCI_SUBSYSTEM_ID));
2088 for (i = 0; i < PCI_NUM_REGIONS; i++) {
2089 r = &d->io_regions[i];
2090 if (!r->size)
2091 continue;
2092 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
2093 " [0x%"FMT_PCIBUS"]\n",
2094 indent, "",
2095 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
2096 r->addr, r->addr + r->size - 1);
2097 }
2098 }
2099
2100 static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len)
2101 {
2102 PCIDevice *d = (PCIDevice *)dev;
2103 const char *name = NULL;
2104 const pci_class_desc *desc = pci_class_descriptions;
2105 int class = pci_get_word(d->config + PCI_CLASS_DEVICE);
2106
2107 while (desc->desc &&
2108 (class & ~desc->fw_ign_bits) !=
2109 (desc->class & ~desc->fw_ign_bits)) {
2110 desc++;
2111 }
2112
2113 if (desc->desc) {
2114 name = desc->fw_name;
2115 }
2116
2117 if (name) {
2118 pstrcpy(buf, len, name);
2119 } else {
2120 snprintf(buf, len, "pci%04x,%04x",
2121 pci_get_word(d->config + PCI_VENDOR_ID),
2122 pci_get_word(d->config + PCI_DEVICE_ID));
2123 }
2124
2125 return buf;
2126 }
2127
2128 static char *pcibus_get_fw_dev_path(DeviceState *dev)
2129 {
2130 PCIDevice *d = (PCIDevice *)dev;
2131 char path[50], name[33];
2132 int off;
2133
2134 off = snprintf(path, sizeof(path), "%s@%x",
2135 pci_dev_fw_name(dev, name, sizeof name),
2136 PCI_SLOT(d->devfn));
2137 if (PCI_FUNC(d->devfn))
2138 snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn));
2139 return strdup(path);
2140 }
2141
2142 static char *pcibus_get_dev_path(DeviceState *dev)
2143 {
2144 PCIDevice *d = container_of(dev, PCIDevice, qdev);
2145 PCIDevice *t;
2146 int slot_depth;
2147 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function.
2148 * 00 is added here to make this format compatible with
2149 * domain:Bus:Slot.Func for systems without nested PCI bridges.
2150 * Slot.Function list specifies the slot and function numbers for all
2151 * devices on the path from root to the specific device. */
2152 char domain[] = "DDDD:00";
2153 char slot[] = ":SS.F";
2154 int domain_len = sizeof domain - 1 /* For '\0' */;
2155 int slot_len = sizeof slot - 1 /* For '\0' */;
2156 int path_len;
2157 char *path, *p;
2158 int s;
2159
2160 /* Calculate # of slots on path between device and root. */;
2161 slot_depth = 0;
2162 for (t = d; t; t = t->bus->parent_dev) {
2163 ++slot_depth;
2164 }
2165
2166 path_len = domain_len + slot_len * slot_depth;
2167
2168 /* Allocate memory, fill in the terminating null byte. */
2169 path = qemu_malloc(path_len + 1 /* For '\0' */);
2170 path[path_len] = '\0';
2171
2172 /* First field is the domain. */
2173 s = snprintf(domain, sizeof domain, "%04x:00", pci_find_domain(d->bus));
2174 assert(s == domain_len);
2175 memcpy(path, domain, domain_len);
2176
2177 /* Fill in slot numbers. We walk up from device to root, so need to print
2178 * them in the reverse order, last to first. */
2179 p = path + path_len;
2180 for (t = d; t; t = t->bus->parent_dev) {
2181 p -= slot_len;
2182 s = snprintf(slot, sizeof slot, ":%02x.%x",
2183 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn));
2184 assert(s == slot_len);
2185 memcpy(p, slot, slot_len);
2186 }
2187
2188 return path;
2189 }
2190
2191 static int pci_qdev_find_recursive(PCIBus *bus,
2192 const char *id, PCIDevice **pdev)
2193 {
2194 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id);
2195 if (!qdev) {
2196 return -ENODEV;
2197 }
2198
2199 /* roughly check if given qdev is pci device */
2200 if (qdev->info->init == &pci_qdev_init &&
2201 qdev->parent_bus->info == &pci_bus_info) {
2202 *pdev = DO_UPCAST(PCIDevice, qdev, qdev);
2203 return 0;
2204 }
2205 return -EINVAL;
2206 }
2207
2208 int pci_qdev_find_device(const char *id, PCIDevice **pdev)
2209 {
2210 struct PCIHostBus *host;
2211 int rc = -ENODEV;
2212
2213 QLIST_FOREACH(host, &host_buses, next) {
2214 int tmp = pci_qdev_find_recursive(host->bus, id, pdev);
2215 if (!tmp) {
2216 rc = 0;
2217 break;
2218 }
2219 if (tmp != -ENODEV) {
2220 rc = tmp;
2221 }
2222 }
2223
2224 return rc;
2225 }
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